A wideband reconfigurable digital ALC circuit and control method

Abstract

The application relates to the technical field of automatic level, and provides a wideband reconfigurable digital ALC circuit and a control method, which comprise an input port, an output port, and a plurality of channel conditioning modules, a coupling and multi-path detection module, a control and storage module, and a power control driving module which are connected in a closed loop; the input port distributes radio frequency signals to corresponding channel conditioning modules according to signal output frequency bands for conditioning; a directional coupler in the coupling and multi-path detection module extracts the coupling signals of the corresponding channel conditioning modules, dynamically adjusts the attenuation amount of a digital attenuator, and adjusts the coupling signals to the optimal linear region of corresponding root mean square detectors; the power control driving module comprises a DAC and a reconfigurable driving circuit; the reconfigurable driving circuit switches the working mode based on the output frequency band, outputs attenuator analog control signals to corresponding analog attenuators in the coupling and multi-path detection module, and realizes high-precision detection of the RMS power of complex modulation radio frequency signals in a 9 kHz-40 GHz super wide frequency band.

Description

Technical Field

[0001] This invention relates to the field of automatic level technology, and in particular to a wideband reconfigurable digital ALC circuit and control method. Background Technology

[0002] In existing digital ALC solutions, the voltage-controlled attenuator operates below 20GHz, which is insufficient for millimeter-wave applications. Its detection path uses a single-path diode detection structure, lacking a multi-path joint detection mechanism. In complex modulation signal scenarios such as orthogonal frequency division multiplexing, the peak-to-average power ratio (PAPR) fluctuates drastically (typically 10-12dB), leading to increased average power detection error. Furthermore, the detection link lacks adaptive gain adjustment; when the input signal dynamic range exceeds 60dB, the actual effective detection range is significantly reduced due to detector linearity limitations. Additionally, the ALC loop lacks a distributed temperature detection circuit, making it impossible to monitor temperature rise at critical nodes in real time. The DAC driver link lacks a temperature compensation algorithm and a calibration model for the relationship between control voltage and temperature. When ambient temperature changes, the DAC reference voltage drifts, causing attenuation deviations. This, combined with the temperature drift effect of the voltage-controlled attenuator, degrades power control accuracy and severely impacts the long-term stability of high-precision ALC systems. These defects collectively lead to a decrease in power control accuracy and a deterioration in EVM performance of existing digital ALCs in complex modulation and large dynamic range scenarios, severely restricting their application in 5G NR high-order modulation and high-stability RF signal output. Summary of the Invention

[0003] To address the problems existing in the prior art, the first objective of this invention is to provide a wideband reconfigurable digital ALC circuit, comprising: an input port, an output port, and a multi-channel conditioning module, a coupling and multi-path detection module, a control and storage module, and a power control drive module connected in a closed loop;

[0004] The input port distributes the radio frequency signal to the corresponding channel conditioning module for conditioning according to the signal output frequency band.

[0005] The channel conditioning module includes an amplifier, an analog attenuator, and segmented filtering and amplification components connected in sequence to condition the input radio frequency signal;

[0006] The coupling and multipath detection module includes a directional coupler, a digital attenuator, a root mean square detector, and a variable gain amplifier connected in sequence. The directional coupler extracts the coupling signal of the corresponding channel conditioning module and dynamically adjusts the attenuation of the digital attenuator to adjust the coupling signal to the optimal linear region of the corresponding root mean square detector.

[0007] The control and storage module includes an FPGA and an ADC, memory, host computer, and temperature sensor array connected to the FPGA;

[0008] The power control drive module includes a DAC and a reconfigurable drive circuit. The reconfigurable drive circuit outputs an attenuator analog control signal to the corresponding analog attenuator based on the output frequency band switching operating mode.

[0009] Specifically, the power control drive module adjusts the attenuation of the analog attenuator based on the detection voltage error value, depending on whether the actual detection voltage value collected by the FPGA is within the threshold range of the desired detection voltage value.

[0010] Specifically, the channel conditioning module includes a low-frequency channel conditioning module, a mid-frequency channel conditioning module, and a high-frequency channel conditioning module.

[0011] The low-frequency channel conditioning module includes a first amplifier, a single-voltage controlled analog attenuator, and a first segmented filtering and amplification component connected in sequence.

[0012] The intermediate frequency channel conditioning module includes a second amplifier, a dual-voltage controlled analog attenuator, and a second segmented filter and amplification component connected in sequence.

[0013] The high-frequency channel conditioning module includes a frequency multiplier, a third amplifier, a current-controlled analog attenuator, and a third segmented filtering and amplification component connected in sequence.

[0014] Specifically, the coupling and multi-path detection module includes a first path for extracting power samples from the low-frequency channel conditioning module, a second path for extracting power samples from the mid-frequency channel conditioning module, and a third path for extracting power samples from the high-frequency channel conditioning module. The first path includes a first directional coupler, a first digital attenuator, and a single-pole double-throw RF switch connected in sequence. The output ports of the RF switch are respectively equipped with a first root-mean-square detector and a second root-mean-square detector with different dynamic ranges.

[0015] Specifically, the reconfigurable drive circuit includes a second analog switch and an adjustable parameter single operational amplifier, an adjustable parameter dual operational amplifier, and an adjustable parameter VI conversion amplifier connected in sequence to the output port of the second analog switch. These are used to send dedicated analog voltage signals adapted to the single voltage controlled analog attenuator, the dual voltage controlled analog attenuator, and the current controlled analog attenuator, respectively.

[0016] Specifically, the temperature sensor array is distributed in the ALC circuit to monitor the temperature changes of the RF path and ALC loop in real time and transmit the temperature signal to the FPGA. The FPGA performs temperature compensation on the DAC value through a lookup table compensation mechanism.

[0017] Specifically, the low-frequency channel conditioning module is used to condition radio frequency signals in the 9kHz-6GHz band, the intermediate-frequency channel conditioning module is used to condition radio frequency signals in the 6GHz-20GHz band, and the high-frequency channel conditioning module is used to condition radio frequency signals in the 20GHz-40GHz band.

[0018] The second objective of this invention is to provide a wideband reconfigurable digital ALC circuit control method, comprising:

[0019] S1. Set the output signal frequency and power;

[0020] S2. Set the reconfigurable drive circuit mode according to the output frequency band: When the output frequency is in the range of 9kHz-6GHz, the reconfigurable drive circuit is set as an adjustable parameter single operational amplifier; when the output frequency is in the range of 6GHz-20GHz, the reconfigurable drive circuit is set as an adjustable parameter dual operational amplifier; when the output frequency is in the range of 20GHz-40GHz, the reconfigurable drive circuit is set as an adjustable parameter VI conversion amplifier.

[0021] S3. Set the power control word DAC value according to the output power;

[0022] S4. Set the attenuation A of the digital attenuator, where A is a variable;

[0023] S5. Select the root mean square detector;

[0024] S6. Set the gain K of the variable gain amplifier, where K is a variable;

[0025] S7. Measure the detection voltage value output by the root mean square detector using an ADC;

[0026] S8. Determine whether the input power of the root mean square detector is in the optimal linear region: If the input power is in the optimal linear region, proceed to step 9; if the input power is not in the optimal linear region, proceed to step 4.

[0027] S9. Determine whether the actual detected voltage value enters the threshold range of the expected detected voltage value: If the actual detected voltage value enters the threshold range of the expected detected voltage value, then execute step S14; if the actual detected voltage value does not enter the threshold range of the expected detected voltage value, then execute step S10.

[0028] S10. Based on the detector voltage error value, the DAC value is adjusted using a PI control algorithm;

[0029] S11. Read the temperature value from the temperature sensor;

[0030] S12. Perform temperature compensation on the DAC value based on the temperature value;

[0031] S13. Determine whether the actual detected voltage value enters the threshold range of the expected detected voltage value: If the actual detected voltage value enters the threshold range of the expected detected voltage value, then execute step S14; if the actual detected voltage value does not enter the threshold range of the expected detected voltage value, then execute step S10.

[0032] S14. Determine whether to continue power control at the current frequency: If power control at the current frequency continues, proceed to step S9; if power control at the current frequency does not continue, proceed to step S15.

[0033] S15. End the entire process.

[0034] Compared with existing data, the beneficial effects of the present invention are as follows:

[0035] 1. This invention achieves high-precision detection of the RMS power of complex modulated RF signals within the ultra-wide frequency band of 9kHz-40GHz by dynamically combining and selecting RF switches and analog switches, automatically matching a root mean square detector with optimal dynamic range and bandwidth characteristics. The system intelligently switches the detector's operating mode based on preset signal frequency and power parameters, breaking through the bandwidth limitations of traditional fixed detectors. It supports linear measurement of multiple signal standards such as QAM and OFDM within a wide dynamic range. Combined with temperature compensation and nonlinear correction algorithms, it ensures a full-band measurement accuracy better than ±0.3dB.

[0036] 2. The ALC circuit designed in this invention integrates core modules such as a digital attenuator, a broadband root mean square detector, a high sampling rate and high resolution ADC / DAC, an FPGA, and an analog attenuator to construct a closed-loop power control system. The FPGA acts as the main control unit, receiving frequency and power parameters set by the host computer, feedback voltage from the detection path, and temperature sensor data in real time. It acquires signal characteristics through a high-speed 18-bit ADC, dynamically analyzes and generates precise control signals using built-in algorithms, and drives the 16-bit DAC to output and adjust the voltage to the attenuator link. This achieves high-precision, small-step control within a dynamic range of -50dBm to +25dBm. This architecture, through multi-parameter fusion control and high-speed signal chain collaboration, effectively eliminates the influence of factors such as ambient temperature and device nonlinearity, ensuring long-term power output stability better than ±0.5dB across the entire frequency band, meeting the requirements for high-precision RF signal generation.

[0037] 3. This invention monitors the temperature changes of the RF path and ALC loop in real time through a distributed temperature sensor array, and dynamically compensates the power parameters using a lookup table method. This effectively suppresses the output power error caused by temperature drift and significantly improves the power control accuracy. At the same time, the system analyzes temperature data in real time, and automatically triggers a multi-level protection mechanism when an abnormal temperature rise is detected, including early warning prompts and graded shutdown strategies to avoid device damage. This design takes into account both power stability and equipment safety, and achieves reliable control across the entire operating temperature range through hardware and software co-optimization, enhancing the long-term operational stability and lifespan of the system.

[0038] 4. The reconfigurable drive circuit proposed in this invention integrates three modes: an adjustable single operational amplifier, a dual operational amplifier, and a VI conversion amplifier. This enables high-precision control of various types of analog attenuators across a wide frequency band. The circuit can flexibly configure parameters according to requirements, adapting to single-voltage, dual-voltage, and current-controlled attenuators. It supports high-resolution, wide dynamic range attenuation adjustment. Its modular design breaks through the limitations of traditional drive architectures, significantly improving compatibility with different attenuator control interfaces while ensuring signal linearity. This meets the multi-mode and multi-scenario application requirements of complex RF systems, providing a hardware foundation for high-precision attenuation control.

[0039] 5. The wideband reconfigurable digital ALC circuit control method proposed in this invention achieves high-precision power regulation of complex modulation signals through the synergistic effect of dual adaptive detection technology and adaptive PI power control technology. The dual adaptive detection technology dynamically adjusts the digital attenuator and variable gain amplifier, and simultaneously optimizes the operating range of the root mean square detector and ADC. The adaptive PI power control technology intelligently adjusts the proportional-integral coefficient according to the real-time detection error, and achieves rapid power convergence while ensuring system stability. This method effectively solves the dynamic range adaptation problem of wideband complex signal power measurement, takes into account both control accuracy and response speed, and significantly improves the system's adaptability and anti-interference capability to signals with different modulation formats. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of the wideband reconfigurable digital ALC circuit of the present invention;

[0041] Figure 2 This is a block diagram of the wideband reconfigurable digital ALC circuit of the present invention;

[0042] Figure 3 This is a block diagram of the reconfigurable drive circuit of the present invention;

[0043] Figure 4 This is a flowchart of the wideband reconfigurable digital ALC circuit control method of the present invention. Detailed Implementation

[0044] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0045] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0046] This invention provides a wideband reconfigurable digital ALC circuit and control method.

[0047] The wideband reconfigurable digital ALC circuit includes: a control and storage module, a first RF switch, a channel conditioning module, a coupling and multipath detection module, a power control drive module, and a second RF switch. Based on dynamic topology reconfiguration technology, the hardware links of the digital attenuator, RMS detector array, and variable gain amplifier are reconfigured using an FPGA, enabling flexible configuration of the multimode drive circuit and multipath detection architecture.

[0048] The control and storage module serves as the control and data processing hub of the system, responsible for all logic control, data processing, system calibration, and status monitoring functions. It includes a high-performance field-programmable gate array (FPGA) M30, as well as an analog-to-digital converter (ADC) M26, a memory M29, a host computer M28, and a temperature sensor array M27 connected to the FPGA M30.

[0049] The FPGA M30 serves as the core computing engine, executing the digital PI control algorithm. It compares the target power with the detector feedback value in real time, parses instructions from the host computer, detector feedback voltage and temperature data, and sends signals to each module. The memory M29 stores system calibration data such as the temperature compensation table, preset control parameters, operating status data, and fault logs. The ADC M26 acquires the analog detector voltage VDET output from the coupling and multi-path detection modules, converts it into a digital signal at high speed, and outputs it to the FPGA M30. The ADC M26 is preferably an 18-bit ADC (sampling rate ≥ 5MSPS). The FPGA M30, combined with the dynamic PI algorithm, generates a 16-bit DAC (sampling rate ≥ 5MSPS) control signal. A temperature sensor array is distributed within the ALC circuit, constructing a distributed temperature sensing network. This network monitors temperature changes in the RF path and ALC loop in real time and transmits the temperature signal to the FPGA M30. The FPGA M30, through a lookup table compensation mechanism, combined with real-time temperature monitoring and dynamic parameter calibration, effectively suppresses output power errors caused by temperature drift, significantly improving power control accuracy and ensuring power stability better than ±0.5dB over a wide temperature range. Furthermore, the system analyzes temperature data in real time and automatically triggers a multi-level protection mechanism when abnormal temperature rises are detected, including early warning prompts and tiered shutdown strategies to prevent device damage. This design balances power stability and equipment safety, achieving reliable control across the entire operating temperature range through hardware and software co-optimization, enhancing the system's long-term operational stability and lifespan. The host computer is used to set parameters such as target output power, operating frequency band, and control mode and transmit them to the FPGA M30, while simultaneously displaying real-time information such as system output power, temperature, and operating status.

[0050] The first RF switch M1 is a single-pole triple-throw RF switch. It receives the external input RF signal FIN and, driven by the control signal CTR6 sent by FPGA M30, switches the input RF signal FIN to the corresponding channel conditioning module according to the output frequency band. The output ports RF1, RF2, and RF3 output three signals F1, F2, and F3 to the low-frequency, intermediate-frequency, and high-frequency channel conditioning modules, respectively.

[0051] The channel conditioning module includes a low-frequency channel conditioning module, an intermediate-frequency channel conditioning module, and a high-frequency channel conditioning module. Based on the signal output frequency band, they respectively perform pre-amplification, controllable attenuation, segmented filtering, and power amplification to achieve standardized conditioning of signals in different frequency bands. Specifically, the low-frequency channel conditioning module conditions RF signals in the 9kHz-6GHz band, the intermediate-frequency channel conditioning module conditions RF signals in the 6GHz-20GHz band, and the high-frequency channel conditioning module conditions RF signals in the 20GHz-40GHz band.

[0052] The low-frequency channel conditioning module includes a first amplifier M3, a single-voltage controlled analog attenuator M6, and a first segmented filter and amplification component M9 connected in sequence. The first amplifier M3 receives the F1 signal input at the output port RF1 of the single-pole triple-throw RF switch M1 and outputs the FFIL1 RF signal to the first directional coupler.

[0053] The intermediate frequency channel conditioning module includes a second amplifier M4, a dual voltage controlled analog attenuator M7, and a second segmented filter and amplification component M10 connected in sequence. The second amplifier M4 receives the F2 signal input from the output port RF2 of the single-pole triple-throw RF switch M1 and outputs the FFIL2 RF signal to the second directional coupler M13.

[0054] The high-frequency channel conditioning module includes a frequency multiplier M2, a third amplifier M5, a current-controlled analog attenuator M8, and a third segmented filter and amplification component M11 connected in sequence. The frequency multiplier M2 receives the F3 signal input from the output port RF3 of the single-pole triple-throw RF switch M1 and outputs the FFIL3 RF signal to the third directional coupler M14.

[0055] The amplifiers in each channel are used to improve the signal level and compensate for the insertion loss of the RF switch and the front-end link.

[0056] The low-frequency, mid-frequency, and high-frequency conditioning modules employ single-voltage controlled analog attenuators M6, dual-voltage controlled analog attenuators M7, and current-controlled analog attenuators M8, respectively, to match the gain slope characteristics of different frequency bands. The FPGA dynamically configures the power control drive module based on parameters set by the host computer, adjusting the attenuation of each analog attenuator in real time. In the 9kHz-6GHz low-frequency band, a single-voltage controlled analog attenuator M6 is used, continuously adjusting the attenuation through a single external DC voltage signal. In the 6GHz-20GHz mid-frequency band, a dual-voltage controlled analog attenuator M7 is used, integrating two cascaded attenuation units, each controlled by two independent voltages, to meet the linearity requirements across the entire attenuation range of the mid-frequency band and improve signal flatness and phase characteristics. In the 20GHz-40GHz high-frequency band, a current-controlled analog attenuator M8 is used to meet the high-precision attenuation requirements of the millimeter-wave band.

[0057] The high-frequency channel conditioning module is equipped with a frequency multiplier to multiply the input 10GHz-20GHz signal to the 20GHz-40GHz high-frequency band, which can solve the problem of the difficulty and high cost of directly generating high-frequency signals.

[0058] The segmented filtering and amplification components include multiple sub-band filter banks and compensation amplifiers, which are used to compensate for link loss, normalize output levels, and clean up the spectrum to ensure signal purity.

[0059] The coupling and multi-path detection module includes a first path, a second path, and a third path. The three paths are connected to the variable gain amplifier M25 through the first analog switch M24. This is used to extract power samples from the main RF link and adjust the attenuation of the digital attenuator to bring the coupling signal into the optimal linear region of the root mean square detector. The root mean square detector converts the RF power into a high-precision analog detection voltage, providing accurate power feedback for closed-loop control.

[0060] First path position: The output RF signal FFIL1 of the low-frequency channel conditioning module generates a first through signal FOUT1 and a first coupling signal FCPL1 after passing through the first directional coupler M12. The first through signal FOUT1 is output through the RF1 input port of the second RF switch M18. The first coupling signal FCPL1 is output to the first digital attenuator M15. The first digital attenuator M15 performs programmable attenuation of the first coupling signal FCPL1 under the drive of the control signal CTR7 and outputs it to the input of the single-pole double-throw RF switch M19. Under the drive of the control signal CTR10, the RF switch M19 switches the signal to the first root mean square detector M20 or the second root mean square detector M21 with different dynamic ranges. The detector converts the input RF signal into a first analog detection voltage VDET1 and a second analog detection voltage VDET2 that are proportional to their true power.

[0061] The second path is as follows: the output RF signal FFIL2 of the intermediate frequency channel conditioning module is converted into a second through signal FOUT2 and a second coupled signal FCPL2 after passing through the second directional coupler M13. The second through signal FOUT2 is output through the RF2 input port of the second RF switch M18, and the second coupled signal FCPL2 is output to the second digital attenuator M16. The second digital attenuator M16 performs programmable attenuation of the second coupled signal FCPL2 under the drive of the control signal CTR8, and outputs it to the third root mean square detector M22. The detector converts the input RF signal into a third analog detection voltage VDET3 that is proportional to its true power.

[0062] The third path is as follows: The output RF signal FFIL3 of the high-frequency channel conditioning module is converted into a third through signal FOUT3 and a third coupled signal FCPL3 after passing through the third directional coupler M14. The third through signal FOUT3 is output through the RF3 input port of the second RF switch M18, and the third coupled signal FCPL3 is output to the third digital attenuator M17. The third digital attenuator M17 performs programmable attenuation of the third coupled signal FCPL3 under the drive of the control signal CTR9, and outputs it to the fourth root mean square detector M23. The detector converts the input RF signal into a fourth analog detection voltage VDET4 that is proportional to its true power.

[0063] The first analog switch M24, based on the signal output frequency band, switches to the corresponding RMS detector under the drive of the control signal CTR12, and inputs the analog detection voltage to the variable gain amplifier M25. The variable gain amplifier M25 adjusts the gain K value under the drive of the control signal CTR14, and outputs the detection voltage signal VDET to the ADCM26.

[0064] The second RF switch M18, based on the signal output frequency band, is connected to the channel conditioning module adjusted to the corresponding frequency band under the drive of FPGA M30.

[0065] The directional coupler separates the channel output signal into a through signal and a coupled signal, achieving isolation between power detection and output. A digital attenuator programmably attenuates the coupled signal to extend the detector's dynamic range, ensuring the input power of the RMS detector is within its optimal linear region. In this region, the output voltage exhibits a strictly logarithmic linear relationship with the input power, resulting in low linearity error, low temperature drift, and fast response. The FPGA M30 adjusts the attenuation A of the digital attenuator based on whether the RMS detector's input power is within the optimal linear region. When the input power is high, the coupled signal is attenuated to prevent the detector from entering the saturation region; when the input power is low, there is no attenuation or only slight attenuation to maintain detection sensitivity.

[0066] The root mean square (RMS) detector converts the RF coupled signal into an analog detection voltage proportional to its true average power. The low-frequency channel conditioning module has a frequency range approaching three orders of magnitude. A single detector has poor input VSWR and coupling flatness, making it difficult to simultaneously handle linear detection of both weak -50dBm signals and high-power +25dBm signals. Therefore, two different range RMS detectors, a first RMS detector M20 and a second RMS detector M21, are used. The FPGA M30 controls the switching of the RF switch M19 based on whether the input power of the RMS detector is within the optimal linear region, thus achieving dynamic range coverage from -50dBm to +25dBm. The intermediate frequency (IF) and high-frequency channel conditioning modules have a frequency range of only about one octave. Within this relatively narrow frequency band, a single RMS detector is sufficient to cover the dynamic range from -50dBm to +25dBm.

[0067] Driven by the control signal CTR12, the first analog switch M24 transmits the analog detection voltage output by the root mean square detector to the variable gain amplifier M25. By adjusting the gain K of the variable gain amplifier M25, the analog detection voltage VDET signal is amplified or attenuated to the optimal input voltage range of the ADC M26, thereby improving sampling accuracy and resolution.

[0068] The ADC M26 acquires the analog detection voltage VDET output from the coupling and multipath detection module, converts it into a digital signal at high speed, and outputs it to the FPGA M30. The FPGA M30 calculates the input power of the root-mean-square detector by combining the gain of the variable gain amplifier and the attenuation of the digital attenuator. The FPGA compares the calculated input power with the preset optimal linear region of the root-mean-square filter to determine whether it is within the optimal linear region.

[0069] The power control drive module includes a digital-to-analog converter (DAC) M31 and a reconfigurable drive circuit M32. The DAC M31 converts the control signal CTR5 into an analog voltage signal DRV and outputs it to the reconfigurable drive circuit M32 to adjust the output power of the channel conditioning module.

[0070] The reconfigurable drive circuit M32 includes a second analog switch M33 and an adjustable parameter single operational amplifier M34, an adjustable parameter dual operational amplifier M35, and an adjustable parameter VI conversion amplifier M36 connected sequentially to the output ports S1, S2, and S3 of the second analog switch M33. The second analog switch M33 switches the working mode of the reconfigurable drive circuit according to the output frequency band under the drive of the control signal CTR13-1. Adjustable single operational amplifier M34 processes the input analog voltage signal DRV. Driven by control signal CTR13-2, the gain of adjustable single operational amplifier M34 is adjusted to perform in-phase / out-of-phase proportional amplification and level shifting on the analog voltage signal DRV, outputting the first analog voltage signal DRV1 to single voltage-controlled analog attenuator M6. Adjustable dual operational amplifier M35 processes the input analog voltage signal DRV. Driven by control signal CTR13-3, the gain of adjustable dual operational amplifier M35 is adjusted to perform gain and biasing on the analog voltage signal DRV, outputting the second analog voltage signal DRV2 to dual voltage-controlled analog attenuator M7. Adjustable VI conversion amplifier M36 processes the input analog voltage signal DRV. Driven by control signal CTR13-4, the gain of adjustable VI conversion amplifier M36 is adjusted to linearly convert the analog voltage signal into a controllable DC current signal, outputting the DC current signal DRV3 to current-controlled analog attenuator M8.

[0071] In the open-loop phase, the FPGA M30 looks up the initial DAC value according to the target power set by the host computer M28. In the closed-loop phase, the FPGA M30, based on the dynamic PI control algorithm, compares the current digital detection value input from the ADC M26 with the target value and sends it to the dynamic PI controller. The PI controller calculates the required power increment correction value, adds the correction value to the current DAC control word to obtain a new digital control word, refreshes the register of the 16-bit high-speed DAC M31 through the digital interface, and drives the DAC M31 to output an analog voltage signal.

[0072] The second analog switch M33 is adjusted to connect with the adjustable parameter amplifier of the corresponding frequency band based on the signal output frequency band. The analog signal output by the DAC is conditioned by the reconfigurable drive circuit and converted into a dedicated analog voltage signal adapted to the single voltage control analog attenuator M6, the dual voltage control analog attenuator M7, and the current control analog attenuator M8. The reconfigurable drive circuit integrates three modes: an adjustable parameter single operational amplifier M34, an adjustable parameter dual operational amplifier M35, and an adjustable parameter VI conversion amplifier M36, to achieve high-precision control of multiple types of analog attenuators over a wide bandwidth and high-precision, small-step control within a dynamic range of -50dBm to +25dBm.

[0073] The adjustable single operational amplifier M34 amplifies the analog voltage signal DRV using in-phase / out-phase proportional amplification and level shifting, outputting a continuously varying first analog voltage signal DRV1. This output is applied to a single control pin of the single-voltage controlled analog attenuator M6, causing a linear change in the on-resistance of the internal field-effect transistor, thereby adjusting the attenuation of the RF signal. The adjustable dual operational amplifier M35 generates two second analog voltage signals DRV2 with a specific functional relationship from the DRV signal through two different gain and bias settings. These signals are simultaneously applied to the two control terminals of the dual-voltage controlled analog attenuator M7. The two cascaded attenuation units within the dual-voltage controlled analog attenuator M7 are adjusted in a segmented, coordinated manner, performing coarse and fine adjustments respectively, to achieve precise control of the signal attenuation. The adjustable parameter VI conversion amplifier M36 linearly converts the analog voltage signal DRV into a controllable DC current signal DRV3, which is then sent to the current control port of the current-controlled analog attenuator M8. The equivalent resistance of the PIN diode in the current-controlled analog attenuator M5 under radio frequency is strictly controlled by the DC current, thereby adjusting the attenuation.

[0074] The FPGA M30 uses the ADC to convert the analog detection voltage VDET into a digital signal to determine whether the actual detection voltage value falls within the threshold range of the desired detection voltage value. The FPGA M30 converts the digital signal into the actual analog voltage value and compares it with the threshold range of the desired detection voltage. If it is not within the threshold range, an adaptive PI control algorithm is used to adjust the DAC value based on the detection voltage error value. The temperature value of the ALC loop is read by a temperature sensor, and temperature compensation is performed on the DAC value based on the temperature value.

[0075] This invention also provides a control method for a wideband reconfigurable digital ALC circuit, the flowchart of which is shown below. Figure 4 As shown, the specific implementation steps of the technical solution are as follows:

[0076] S1. Set the output signal frequency and power;

[0077] S2. Set the reconfigurable drive circuit mode according to the output frequency band: When the output frequency is in the range of 9kHz-6GHz, the reconfigurable drive circuit is set as an adjustable parameter single operational amplifier; when the output frequency is in the range of 6GHz-20GHz, the reconfigurable drive circuit is set as an adjustable parameter dual operational amplifier; when the output frequency is in the range of 20GHz-40GHz, the reconfigurable drive circuit is set as an adjustable parameter VI conversion amplifier.

[0078] S3. Set the power control word DAC value according to the output power;

[0079] S4. Set the attenuation A of the digital attenuator, where A is a variable;

[0080] S5. Select the root mean square detector;

[0081] S6. Set the gain K of the variable gain amplifier, where K is a variable;

[0082] S7. Measure the detection voltage value output by the root mean square detector using an ADC;

[0083] S8. Determine whether the input power of the root mean square detector is in the optimal linear region: If the input power is in the optimal linear region, proceed to step 9; if the input power is not in the optimal linear region, proceed to step 4.

[0084] S9. Determine whether the actual detected voltage value enters the threshold range of the expected detected voltage value: If the actual detected voltage value enters the threshold range of the expected detected voltage value, then execute step S14; if the actual detected voltage value does not enter the threshold range of the expected detected voltage value, then execute step S10.

[0085] S10. Based on the detector voltage error value, the DAC value is adjusted using a PI control algorithm;

[0086] S11. Read the temperature value from the temperature sensor;

[0087] S12. Perform temperature compensation on the DAC value based on the temperature value;

[0088] S13. Determine whether the actual detected voltage value enters the threshold range of the expected detected voltage value: If the actual detected voltage value enters the threshold range of the expected detected voltage value, then execute step S14; if the actual detected voltage value does not enter the threshold range of the expected detected voltage value, then execute step S10.

[0089] S14. Determine whether to continue power control at the current frequency: If power control at the current frequency continues, proceed to step S9; if power control at the current frequency does not continue, proceed to step S15.

[0090] S15. End the entire process.

[0091] The entire process is controlled in a closed-loop iterative manner with a microsecond cycle, ultimately achieving high-precision (±0.5dB stability) and high-resolution (0.01dB level) control of output power across the entire frequency band (9kHz-40GHz) and the full dynamic range (-50dBm to +25dBm).

[0092] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention. The above are merely preferred embodiments of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the protection scope of the present invention.

Claims

1. A wideband reconfigurable digital ALC circuit, characterized in that, include: Input ports, output ports, and closed-loop connection of multi-channel conditioning modules, coupling and multi-path detection modules, control and storage modules, and power control drive modules; The input port distributes the radio frequency signal to the corresponding channel conditioning module for conditioning according to the signal output frequency band. The channel conditioning module includes an amplifier, an analog attenuator, and segmented filtering and amplification components connected in sequence to condition the input radio frequency signal; The coupling and multipath detection module includes a directional coupler, a digital attenuator, a root mean square detector, and a variable gain amplifier connected in sequence. The directional coupler extracts the coupling signal of the corresponding channel conditioning module and dynamically adjusts the attenuation of the digital attenuator to adjust the coupling signal to the optimal linear region of the corresponding root mean square detector. The control and storage module includes an FPGA and an ADC, memory, host computer, and temperature sensor array connected to the FPGA; The power control drive module includes a DAC and a reconfigurable drive circuit. The reconfigurable drive circuit outputs an attenuator analog control signal to the corresponding analog attenuator based on the output frequency band switching operating mode.

2. The wideband reconfigurable digital ALC circuit according to claim 1, characterized in that, The power control drive module adjusts the attenuation of the analog attenuator based on the detection voltage error value, depending on whether the actual detection voltage value collected by the FPGA is within the threshold range of the desired detection voltage value.

3. The wideband reconfigurable digital ALC circuit according to claim 1, characterized in that, The channel conditioning module includes a low-frequency channel conditioning module, a mid-frequency channel conditioning module, and a high-frequency channel conditioning module. The low-frequency channel conditioning module includes a first amplifier, a single-voltage controlled analog attenuator, and a first segmented filtering and amplification component connected in sequence. The intermediate frequency channel conditioning module includes a second amplifier, a dual-voltage controlled analog attenuator, and a second segmented filter and amplification component connected in sequence. The high-frequency channel conditioning module includes a frequency multiplier, a third amplifier, a current-controlled analog attenuator, and a third segmented filtering and amplification component connected in sequence.

4. The wideband reconfigurable digital ALC circuit according to claim 3, characterized in that, The coupling and multi-path detection module includes a first path for extracting power samples from the low-frequency channel conditioning module, a second path for extracting power samples from the mid-frequency channel conditioning module, and a third path for extracting power samples from the high-frequency channel conditioning module. The first path includes a first directional coupler, a first digital attenuator, and a single-pole double-throw RF switch connected in sequence. The output ports of the RF switch are respectively equipped with a first root-mean-square detector and a second root-mean-square detector with different dynamic ranges.

5. The wideband reconfigurable digital ALC circuit according to claim 3, characterized in that, The reconfigurable drive circuit includes a second analog switch and an adjustable parameter single operational amplifier, an adjustable parameter dual operational amplifier, and an adjustable parameter VI conversion amplifier connected in sequence to the output port of the second analog switch. These are used to send dedicated analog voltage signals adapted to the single voltage-controlled analog attenuator, the dual voltage-controlled analog attenuator, and the current-controlled analog attenuator, respectively.

6. The wideband reconfigurable digital ALC circuit according to claim 1, characterized in that, The temperature sensor array is distributed in the ALC circuit, which monitors the temperature changes of the RF path and ALC loop in real time and transmits the temperature signal to the FPGA. The FPGA performs temperature compensation on the DAC value through a lookup table compensation mechanism.

7. The wideband reconfigurable digital ALC circuit according to claim 3, characterized in that, The low-frequency channel conditioning module is used to condition radio frequency signals in the 9kHz-6GHz band, the intermediate-frequency channel conditioning module is used to condition radio frequency signals in the 6GHz-20GHz band, and the high-frequency channel conditioning module is used to condition radio frequency signals in the 20GHz-40GHz band.

8. A method for controlling a wideband reconfigurable digital ALC circuit, characterized in that, include: S1. Set the output signal frequency and power; S2. Set the reconfigurable drive circuit mode according to the output frequency band: When the output frequency is in the range of 9kHz-6GHz, the reconfigurable drive circuit is set as an adjustable parameter single operational amplifier; when the output frequency is in the range of 6GHz-20GHz, the reconfigurable drive circuit is set as an adjustable parameter dual operational amplifier; when the output frequency is in the range of 20GHz-40GHz, the reconfigurable drive circuit is set as an adjustable parameter VI conversion amplifier. S3. Set the power control word DAC value according to the output power; S4. Set the attenuation A of the digital attenuator, where A is a variable; S5. Select the root mean square detector; S6. Set the gain K of the variable gain amplifier, where K is a variable; S7. Measure the detection voltage value output by the root mean square detector using an ADC; S8. Determine whether the input power of the root mean square detector is in the optimal linear region: If the input power is in the optimal linear region, proceed to step 9; if the input power is not in the optimal linear region, proceed to step 4. S9. Determine whether the actual detected voltage value enters the threshold range of the expected detected voltage value: If the actual detected voltage value enters the threshold range of the expected detected voltage value, then execute step S14; if the actual detected voltage value does not enter the threshold range of the expected detected voltage value, then execute step S10. S10. Based on the detector voltage error value, the DAC value is adjusted using a PI control algorithm; S11. Read the temperature value from the temperature sensor; S12. Perform temperature compensation on the DAC value based on the temperature value; S13. Determine whether the actual detected voltage value enters the threshold range of the expected detected voltage value: If the actual detected voltage value enters the threshold range of the expected detected voltage value, then execute step S14; if the actual detected voltage value does not enter the threshold range of the expected detected voltage value, then execute step S10. S14. Determine whether to continue power control at the current frequency: If power control at the current frequency continues, proceed to step S9; if power control at the current frequency does not continue, proceed to step S15. S15. End the entire process.

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