A digital waveform generation method based on digital logic

Abstract

The application relates to the technical field of digital waveform generation, and particularly discloses a digital waveform generation method based on digital logic, which comprises the following steps: generating timing information with a main clock integer multiple as a unit based on a system main clock; for each rising edge and falling edge of a waveform, splitting a target edge time into a main clock integer part and a fine offset smaller than a single main clock period; respectively applying corresponding fine offset delays to rising edge and falling edge reference pulses to output edge trigger pulses with sub-clock period precision delays; and sending the delayed rising edge trigger pulses and falling edge trigger pulses into trigger set and reset control ends respectively, and synthesizing a target digital waveform with programmable edge positions through set and reset level jumps. The application aims to solve the problem that in traditional digital waveform generation technology, precision is limited by a system main clock period and it is difficult to generate complex waveforms with accurately programmable edge positions.

Description

Technical Field

[0001] This invention relates to the field of digital waveform generation technology, and more specifically to a digital waveform generation method based on digital logic. Background Technology

[0002] Currently, most mainstream digital signal waveform generation solutions in the industry adopt direct digital frequency synthesis (DDS) technology or waveform generation methods based on system master clock frequency division and timer counting. These traditional solutions have mature architectures and low implementation costs, and are widely used in signal generation scenarios with conventional precision. However, they have unavoidable technical defects in high-precision timing control scenarios. The core limitation of traditional solutions is that all edge nodes of their output waveform, including the jump positions of the rising and falling edges of the signal, can only be strictly aligned with the sampling edges of the system master clock. The adjustment step of waveform timing is completely limited to a single system clock cycle, making it impossible to achieve fine-tuning of timing with smaller granularity.

[0003] This fixed clock cycle step constraint directly results in extremely low time resolution for traditional waveform generation techniques. Timing control accuracy is entirely dependent on the system's main clock frequency. Even if accuracy is optimized by increasing the clock frequency, it leads to a series of derivative problems such as a surge in hardware power consumption, increased circuit design complexity, signal crosstalk interference, and decreased system stability. Hardware optimization costs are extremely high, and the accuracy improvement is limited. At the same time, this technical deficiency makes it difficult for traditional solutions to generate complex waveforms with arbitrarily precise edge positions and flexibly adjustable timing parameters. For special complex waveforms with multiple edges, narrow pulses, and high-precision timing matching, edge offset, timing error accumulation, and waveform distortion are highly likely to occur.

[0004] In high-end core fields such as high-speed serial communication timing calibration, nanometer-level precision measurement instruments, laser pulse control, high-precision timing synchronization testing, and semiconductor device testing, the edge timing accuracy of signal waveforms directly determines the measurement accuracy, control reliability, and operational stability of equipment. Timing errors at the nanosecond or even sub-nanosecond level can lead to serious problems such as equipment detection failure, data deviation, and synchronization failure. However, traditional digital waveform generation technology is limited by clock cycle barriers and cannot achieve fine-grained timing control at the sub-clock cycle level, making it difficult to meet the increasingly demanding requirements of high-precision, high-resolution, and high-flexibility waveform generation and timing control in various high-end fields. Summary of the Invention

[0005] The purpose of this invention is to provide a digital waveform generation method based on digital logic to solve the above-mentioned technical problems.

[0006] The objective of this invention can be achieved through the following technical solutions: A digital waveform generation method based on digital logic includes the following steps: Step 1: Macro-level timing: Based on the system master clock, generate timing information in units of integer multiples of the master clock, and determine the waveform period reference and the clock integer reference time corresponding to each edge; Step 2, Micro-timing decomposition: For each rising and falling edge of the waveform, the target edge time is decomposed into the integer part of the master clock and a fine offset less than a single master clock cycle, and independent fine delay control values ​​are configured for the rising and falling edges respectively. Step 3, Sub-clock cycle delay processing: Using the FPGA's built-in carry logic delay chain, apply corresponding fine offset delays to the rising and falling edge reference pulses respectively, and output edge trigger pulses with precise sub-clock cycle delay; Step 4: Waveform Synthesis and Output: The delayed rising edge trigger pulse and falling edge trigger pulse are sent to the set and reset control terminals of the trigger, respectively. The target digital waveform with programmable edge position is synthesized by the level transition of the set and reset.

[0007] As a further aspect of the present invention: in step one, the macroscopic timing uses a programmable frequency divider to count the system master clock, calculates the total number of master clocks in a single period based on the target waveform period, generates a frame start pulse as a global time reference when the count reaches a threshold, and outputs the clock count reference point corresponding to each edge.

[0008] As a further aspect of the present invention: the FPGA's built-in carry logic delay chain is a CARRY8 carry chain, with a fixed unit delay of 45ps~50ps for a single CARRY8 unit. By configuring the carry chain tap level to match the fine offset obtained in step two, a picosecond-level adjustable delay can be achieved.

[0009] As a further aspect of the present invention: the rising edge and falling edge are configured with independent CARRY8 delay chains, and the delay levels of the two are configured independently, so as to achieve micro-timing offset of the two trigger pulses without interference.

[0010] As a further aspect of the present invention: the trigger is an FDCE asynchronous clear D trigger, the rising edge pulse delayed by CARRY8 is connected to the FDCE set terminal, and the control output jumps from low level to high level; the falling edge pulse delayed by CARRY8 is connected to the FDCE reset terminal, and the control output jumps from high level to low level.

[0011] As a further aspect of the present invention: the fine offset is at the sub-nanosecond level, the overall waveform edge timing resolution is determined by the single-stage delay of the CARRY8 unit, the minimum delay step is less than or equal to 45ps, the edge timing linearity error is less than ±20ps, and the waveform output edge jitter is less than 30ps RMS.

[0012] As a further aspect of the present invention: by independently controlling the macroscopic clock reference time and microscopic fine offset of the rising and falling edges, a complex pulse sequence with arbitrary duty cycle, arbitrary pulse position, and non-periodic multi-edge is generated.

[0013] The beneficial effects of this invention are: The timing accuracy of the waveform edge is no longer limited by the system master clock cycle, but is determined by the unit delay of dedicated hardware delay chains such as CARRY8, which can achieve picosecond (ps) level time resolution, far higher than traditional digital methods. The entire solution is completed within the FPGA digital logic, eliminating the need for external analog delay lines or complex phase-locked loops (PLLs) for phase shifting, thus improving the system's reliability, reconfigurability, and integration. By controlling the macroscopic timing and microscopic offset of the rising and falling edges respectively, it is theoretically possible to generate complex pulse sequences with arbitrary duty cycles, arbitrary pulse positions, and non-periodicity, which has a wide range of applications. It makes full use of the existing fast carry chain resources in the FPGA to achieve high-performance timing functions with minimal logic and routing overhead. Attached Figure Description

[0014] The invention will now be further described with reference to the accompanying drawings.

[0015] Figure 1 This is a flowchart illustrating a digital waveform generation method based on digital logic according to the present invention. Detailed Implementation

[0016] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0017] Traditional signal generation schemes typically rely on direct digital frequency synthesis (DDS) or timers that divide / count the system clock. The edges (rising and falling edges) of the output waveform can only be aligned with the edges of the system clock, and the minimum step for time adjustment is one clock cycle. This severely limits the time resolution of the waveform and cannot meet the increasingly demanding timing control requirements of fields such as high-speed communication, precision measurement, and instrumentation.

[0018] To address the aforementioned technical problems, this invention proposes a digital waveform generation method based on digital logic. The core idea is to decompose the timing control of the waveform into two cooperating layers: a macroscopic timing layer and a microscopic timing layer. For example... Figure 1 As shown, it specifically includes: Step 1, Macro-level Timing (Frame Timing): This part is handled by the frequency generation module. This module generates timing information in integer multiples (N times) of the system master clock, based on the waveform repetition frequency or period specified by the user. It is responsible for defining the overall time frame of the waveform output, such as determining the start time of a complete waveform cycle, or controlling periodic timing nodes in the waveform that do not require high-precision positioning.

[0019] Step 2, Micro-Timing (Edge Timing): This is crucial for achieving high precision. For each rising and falling edge in the waveform, its precise triggering time is subdivided into an "integer multiple of the master clock" and a "fine offset portion less than the master clock cycle." The key to this invention lies in the processing of the latter. We set independent, fine delay control values ​​less than one master clock cycle for each rising and falling edge.

[0020] Step 3, Sub-clock Cycle Delay Chain: To achieve the aforementioned fine-grained delay, this invention creatively utilizes dedicated carry logic resources in FPGA chips, such as the CARRY8 chain in Xilinx devices. The CARRY8 chain has a fixed and extremely small gate delay, providing high-resolution, configurable delay steps. The raw pulse signal representing edge triggering is input into the CARRY8 chain, and by configuring the chain length, a precise, sub-nanosecond delay can be achieved for this pulse signal. The trigger pulses for rising and falling edges are fine-tuned by independent delay chains.

[0021] Step 4: Waveform Synthesis and Output: The rising and falling edge trigger signals, precisely delayed by the CARRY8 chain, are sent to dedicated trigger modules (such as FDCE) for processing. The FDCE module converts these asynchronous double-edge trigger pulses into single-channel arbitrary-phase digital signals. Specifically, the rising edge trigger pulse controls the output signal to transition from low to high, while the falling edge trigger pulse controls it to transition from high to low. By precisely arranging these macroscopic trigger times and microscopically delayed edge actions, a complex digital waveform defined by the user and with arbitrarily programmable edge positions is finally synthesized at the output port.

[0022] Taking the generation of 10kHz high-precision digital waveform based on Xilinx Kintex-7 series FPGA as an example, the system main clock frequency is 100MHz, the corresponding clock period is 10ns, and the repetition frequency of the target output waveform is 10kHz, that is, the waveform period is 100μs.

[0023] In step one, macro-level timing, or frame timing, is configured. The macro-level timing module uses a 32-bit programmable divider, with integer multiples of the system master clock as the smallest timing unit. Based on a target period of 100μs, a complete waveform period contains 10,000 master clock cycles. The macro-level timing module counts the master clock, generating a frame start pulse whenever the count reaches 9,999, which serves as the global time reference for the entire waveform output. Specifically, the waveform is configured to generate a rising edge reference at the 2,500th clock cycle (corresponding to 25μs) and a falling edge reference at the 7,500th clock cycle (corresponding to 75μs). This step establishes the overall time frame of the waveform but does not handle sub-nanosecond precision control.

[0024] In step two, micro-timing, or edge timing, is decomposed. Assume the user's desired actual edge times are 25.3 μs for the rising edge and 75.7 μs for the falling edge. The system decomposes these two target times into the "integer part of the main clock" and the "sub-clock offset part," respectively. For the rising edge, it is located within the 2,530th main clock cycle, with an offset of 0.3 μs (300 ps) relative to that clock's rising edge; for the falling edge, it is located within the 7,570th main clock cycle, with an offset of 0.7 μs (700 ps) relative to that clock's rising edge. The system configures independent, fine-grained delay control values ​​for these two edges, completing the fine-grained decomposition of the time dimension.

[0025] In step three, a fine delay is achieved using a sub-clock cycle delay chain. This embodiment utilizes the dedicated carry logic resource CARRY8 carry chain within the FPGA to achieve the aforementioned 300ps and 700ps delays. Actual measurements show that the delay step of a single CARRY8 unit is approximately 50ps. Therefore, the system is configured with a rising edge delay chain length of 6 stages (6 × 50ps = 300ps) and a falling edge delay chain length of 14 stages (14 × 50ps = 700ps). The original edge reference pulse is input to the corresponding CARRY8 delay chain, and the delay taps are configured via a selector, converting the originally coarse pulse aligned with the master clock into a trigger signal with a precise time delay. Actual measurement data shows that this scheme achieves a minimum delay step of 45ps, a linearity error of less than ±20ps, and a low temperature drift coefficient.

[0026] In step four, waveform synthesis and output are performed. The rising and falling edge trigger signals, precisely delayed by the CARRY8 chain, are sent to the control terminals of the FDCE (Asynchronous Clear D Flip-Flop). Specifically, the delayed rising edge pulse is connected to the set terminal of the flip-flop to control the output signal to flip from low to high; the delayed falling edge pulse is connected to the reset terminal of the flip-flop to control the output signal to flip from high to low. Through this process, the system successfully synthesizes a high-precision digital waveform at the output terminal with a duty cycle of 50.4% and edge jitter of less than 30 ps RMS.

[0027] The foregoing has provided a detailed description of one embodiment of the present invention, but this description is merely a preferred embodiment and should not be construed as limiting the scope of the invention. All equivalent variations and modifications made within the scope of the present invention should still fall within the scope of the present invention.

Claims

1. A digital waveform generation method based on digital logic, characterized in that, Includes the following steps: Step 1: Macro-level timing: Based on the system master clock, generate timing information in units of integer multiples of the master clock, and determine the waveform period reference and the clock integer reference time corresponding to each edge; Step 2, Micro-timing decomposition: For each rising and falling edge of the waveform, the target edge time is decomposed into the integer part of the master clock and a fine offset less than a single master clock cycle, and independent fine delay control values ​​are configured for the rising and falling edges respectively. Step 3, Sub-clock cycle delay processing: Using the FPGA's built-in carry logic delay chain, apply corresponding fine offset delays to the rising and falling edge reference pulses respectively, and output edge trigger pulses with precise sub-clock cycle delay; Step 4: Waveform Synthesis and Output: The delayed rising edge trigger pulse and falling edge trigger pulse are sent to the set and reset control terminals of the trigger, respectively. The target digital waveform with programmable edge position is synthesized by the level transition of the set and reset.

2. The digital waveform generation method based on digital logic according to claim 1, characterized in that, In step one, the macro timing uses a programmable frequency divider to count the system master clock. Based on the target waveform period, the total number of master clocks in a single period is calculated. When the count reaches the threshold, a frame start pulse is generated as a global time reference, and the clock count reference point corresponding to each edge is output.

3. The digital waveform generation method based on digital logic according to claim 1, characterized in that, The FPGA's built-in carry logic delay chain is a CARRY8 carry chain. The fixed unit delay of a single CARRY8 unit is 45ps~50ps. By configuring the carry chain tap level to match the fine offset obtained in step two, picosecond-level adjustable delay can be achieved.

4. The digital waveform generation method based on digital logic according to claim 1, characterized in that, The rising and falling edges are configured with independent CARRY8 delay chains, and the delay levels of the two chains are configured independently to achieve micro-timing offsets of the two trigger pulses without interference.

5. The digital waveform generation method based on digital logic according to claim 1, characterized in that, The trigger is an FDCE asynchronous reset D trigger. The rising edge pulse delayed by CARRY8 is connected to the FDCE set terminal, which controls the output to jump from low level to high level; the falling edge pulse delayed by CARRY8 is connected to the FDCE reset terminal, which controls the output to jump from high level to low level.

6. The digital waveform generation method based on digital logic according to claim 1, characterized in that, The fine offset is at the sub-nanosecond level. The overall waveform edge timing resolution is determined by the single-stage delay of the CARRY8 unit. The minimum delay step is less than or equal to 45ps, the edge timing linearity error is less than ±20ps, and the waveform output edge jitter is less than 30ps RMS.

7. The digital waveform generation method based on digital logic according to claim 1, characterized in that, By independently controlling the macroscopic clock reference time and microscopic fine offset of the rising and falling edges, a non-periodic multi-edge complex pulse sequence with arbitrary duty cycle and pulse position can be generated.

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