A comparison detection circuit for I3C protocol, chip and electronic equipment

Abstract

The application provides a comparison detection circuit, a chip and an electronic device for an I3C protocol, and relates to the technical field of communication protocols. The application comprises a power supply end, a current biasing module, a rail-to-rail input comparison module, a load module, a feedforward capacitor and an output shaping module. The current biasing module is used to provide a dynamically adjustable biasing current to a current source unit of the rail-to-rail input comparison module according to an I3C input signal. The rail-to-rail input comparison module is used to provide a level comparison signal to the load module according to the dynamically adjustable biasing current, the I3C input signal and a reference voltage. The load module is used to output a corrected level comparison signal according to a transition edge of the level comparison signal and the I3C input signal. The output shaping module is used to output a standard digital logic signal suitable for the I3C protocol. The application provides a technical solution of an I3C protocol signal comparison detection circuit which takes into account low power consumption, timing synchronization and anti-interference capability.

Description

Technical Field

[0001] This application relates to the field of communication protocol technology, and in particular to a comparison detection circuit, chip, and electronic device for the I3C protocol. Background Technology

[0002] As a new generation of high-speed serial communication protocol, the I3C bus is widely used in integrated circuit communication scenarios such as sensors and embedded chips. It places high demands on signal detection accuracy, timing synchronization, low power consumption characteristics, and timing jitter control.

[0003] Existing I3C interface receivers typically employ an architecture of low-voltage domain logic recognition, Schmitt triggers, and level shifters to match external signals with the chip's internal logic domain. This involves first stepping down the chip's internal power supply to below 2V, then using a Schmitt trigger to determine the high or low level logic of the external low-voltage digital signal, and finally using a level shifter to convert the low-voltage logic signal into a signal within the chip's internal operating voltage domain.

[0004] However, existing technical solutions have several drawbacks: First, to adapt to the operation of the Schmitt trigger, an additional auxiliary voltage of approximately 2V is required, which introduces continuous steady-state current loss. Simultaneously, if the external input digital signal voltage is too low, the Schmitt trigger will generate additional static current, significantly increasing the overall power consumption at the receiver, which is detrimental to low-power applications. Second, the Schmitt trigger relies on the hysteresis characteristics of positive and negative thresholds to determine the level. Its inherent threshold difference causes inconsistent propagation delays between the rising and falling edges, easily leading to signal setup and hold time violations in I3C high-speed communication mode. When the external I3C bus signal is affected by long-distance transmission interference or electromagnetic interference, fluctuating within the hysteresis threshold window, the Schmitt trigger output will frequently and repeatedly change, causing misjudgments of the I3C bus START and STOP signals, failing to meet the strict timing jitter constraints of the I3C protocol. Finally, the level converter needs to operate continuously to connect the low-voltage domain with the core voltage domain of the chip. Its static current and the power consumption of the Schmitt trigger are superimposed, further increasing the overall power consumption. At the same time, the level converter introduces a signal transmission delay of 2-5ns, which can easily cause significant timing deviations in high-speed I3C signal transmission and reduce communication reliability. Summary of the Invention

[0005] This application provides a comparison and detection circuit, chip, and electronic device for the I3C protocol, which provides a technical solution for an I3C protocol signal comparison and detection circuit that balances low power consumption, timing synchronization, and anti-interference capabilities.

[0006] This application provides a comparison detection circuit for the I3C protocol. The comparison detection circuit for the I3C protocol includes: a power supply terminal, a current bias module, a rail-to-rail input comparison module, a load module, a feedforward capacitor, and an output shaping module. The power supply terminal is used to supply power to the current bias module, the rail-to-rail input comparator module and the load module. The power supply terminal is the internal power supply of the I3C protocol chip. The input terminal of the current bias module is connected to the I3C signal input terminal, and the output terminal of the current bias module is connected to the current source unit of the rail-to-rail input comparison module. The current bias module is used to provide a dynamically adjustable bias current to the current source unit of the rail-to-rail input comparison module according to the I3C input signal provided by the I3C signal input terminal. The dynamically adjustable bias current increases according to the level flip of the I3C input signal. The first comparison terminal of the rail-to-rail input comparator is connected to the I3C signal input terminal, the second comparison terminal of the rail-to-rail input comparator is connected to the reference signal terminal, and the output terminal of the rail-to-rail input comparator is connected to the load module; wherein, the reference signal terminal is used to output a switchable reference voltage according to the I3C input signal; The rail-to-rail input comparator module provides a level comparison signal to the load module based on the dynamically adjustable bias current, the I3C input signal, and the reference voltage output from the reference signal terminal. The intermediate node of the load module is connected to the I3C signal input terminal through a feedforward capacitor, and the output terminal of the load module is connected to the input terminal of the output shaping module. The load module is used to amplify and correct the level comparison signal based on the transition edge of the level comparison signal and the I3C input signal to obtain the corrected level comparison signal. The output shaping module is used to shape the edges of the corrected level comparison signal and output a standard digital logic signal that is compatible with the I3C protocol.

[0007] In one alternative implementation, the current biasing module includes: Constant current source, coupling capacitor unit, bias unit, and current replication unit; The power supply terminal is connected to the constant current source, coupling capacitor unit, bias unit and current replication unit, and is used to supply power to the constant current source, coupling capacitor unit, bias unit and current replication unit; The output of the constant current source is connected to the current replication unit to provide a reference current to the current replication unit; The input terminal of the coupling capacitor unit is connected to the I3C signal input terminal, and the output terminal of the coupling capacitor unit is connected to the bias unit. The coupling capacitor unit is used to turn on the bias unit when the I3C input signal provided by the I3C signal input terminal changes. The output of the bias unit is connected to the current replication unit. The bias unit is used to generate a jumping current when the I3C input signal jumps and outputs the jumping current to the current replication unit. The current replication unit is used to generate a dynamically adjustable bias current based on the reference current, or the reference current and the jump current, and output the dynamically adjustable bias current to the current source unit of the rail-to-rail input comparison module.

[0008] In one optional embodiment, the coupling capacitor unit includes a first coupling capacitor and a second coupling capacitor; the bias unit includes a first bias switch and a second bias switch. The first plate of the first coupling capacitor and the first plate of the second coupling capacitor are both connected to the I3C signal input terminal. The second plate of the first coupling capacitor is connected to the gate of the first bias switch transistor. The source of the first bias switch transistor is connected to the power supply terminal. The drain of the first bias switch transistor is connected to the first input terminal of the current mirror replication unit. The second plate of the second coupling capacitor is connected to the gate of the second bias switch transistor, the source of the second bias switch transistor is grounded, and the drain of the second bias switch transistor is connected to the second input terminal of the current mirror replication unit; the output terminal of the constant current source is connected to the first input terminal of the current mirror replication unit. The output of the current mirror copy unit is connected to the current source unit of the rail-to-rail input comparison module, and is used to mirror and copy the dynamically adjustable bias current and output it to the current source unit of the rail-to-rail input comparison module.

[0009] In one alternative implementation, when the I3C input signal is in a steady state, both the first bias switch and the second bias switch are turned off, the current mirror replication unit replicates the reference current output by the constant current source, and outputs it to the current source unit of the rail-to-rail input comparison module. When the I3C input signal flips from high level to low level, the I3C input signal is coupled through the first coupling capacitor, turns on the first bias switch, and generates the first transition current. The current mirror copying unit mirrors the superimposed reference current and the first transition current to generate a dynamically adjustable bias current and outputs it to the current source unit of the rail-to-rail input comparison module. When the I3C input signal flips from low to high, the I3C input signal is coupled through the second coupling capacitor, turns on the second bias switch, and generates the second switching current. The current mirror copying unit mirrors the superimposed reference current and the second switching current to generate a dynamically adjustable bias current and outputs it to the current source unit of the rail-to-rail input comparison module.

[0010] In one alternative implementation, the current bias module further includes a first resistor, a second resistor, a third resistor, and a fourth resistor; The first end of the first resistor is connected to the second end of the second coupling capacitor and the control terminal of the second bias switch. The second end of the first resistor is grounded. The first resistor is used to pull down the gate potential of the second bias switch when the I3C input signal is in a steady state, so that the second bias switch is turned off. The first end of the second resistor is connected to the second end of the first coupling capacitor and the control terminal of the first bias switch transistor. The second end of the second resistor is connected to the power supply terminal. The second resistor is used to pull up the gate potential of the first bias switch transistor when the I3C input signal is in a steady state, so that the first bias switch transistor is turned off. The first end of the third resistor is connected to the drain of the first bias switch transistor, and the second end of the third resistor is connected to the output of the constant current source. The third resistor is used to reset the first bias switch transistor to the off state after the I3C input signal flips from high level to low level. The first end of the fourth resistor is connected to the current mirror replication unit, and the second end of the fourth resistor is connected to the drain of the second bias switch. The fourth resistor is used to reset the second bias switch to the off state after the I3C input signal flips from low level to high level.

[0011] In one alternative implementation, the current mirror replication unit includes a current mirror and a first current replication switch. The current mirror includes a first paired transistor and a second paired transistor; the source of the first paired transistor and the source of the second paired transistor are both connected to the power supply terminal, the gates of the first paired transistor and the second paired transistor are connected, the drain of the first paired transistor is shorted to the gate of the first paired transistor, the drain of the first paired transistor is connected to the drain of the second bias switch transistor, the drain of the second paired transistor is connected to the drain and gate of the first current replication switch transistor, and the source of the first current replication switch transistor is grounded. In this configuration, the drain of the first paired transistor is the first input terminal of the current mirror replication unit, the drain of the second paired transistor is the second input terminal of the current mirror replication unit, and the drain and gate of the first current replication switch transistor are shorted to form the output terminal of the current mirror replication unit.

[0012] In one alternative implementation, the rail-to-rail input comparison module includes a current source unit and a rail-to-rail input pair unit; the current source unit includes a second current replication switch and a current source switch. The gate of the second current replication switch is connected to the gate of the first current replication switch, the source of the second current replication switch is grounded, the drain of the second current replication switch is connected to the first terminal of the rail-to-rail input pair unit, and the gate of the second current replication switch is also connected to the first control terminal of the load module. The source of the current source switch is connected to the power supply terminal and connected to the drain of the first current replication switch through the second pairing transistor. The drain of the current source switch is connected to the second terminal of the rail-to-rail input pair unit, and the gate of the current source switch is connected to the second control terminal of the load module. The first comparison terminal of the rail-to-rail input pair unit is connected to the I3C signal input terminal, the second comparison terminal of the rail-to-rail input pair unit is connected to the reference signal terminal, and the multiple output terminals of the rail-to-rail input pair unit are all connected to the corresponding input terminals of the load module. The dynamically adjustable bias current output by the first current replication switch controls the second current replication switch and the current source switch to turn on or off, so as to realize the synchronous increase or decrease of the current and the dynamically adjustable bias current in the rail-to-rail input comparison module. The first current-replicating switch and the second current-replicating switch form a current mirror structure.

[0013] In one alternative implementation, the rail-to-rail input pair unit includes a first rail-to-rail input switch, a second rail-to-rail input switch, a third rail-to-rail input switch, and a fourth rail-to-rail input switch. The gate of the first rail-to-rail input switch is connected to the I3C signal input terminal. The source of the first rail-to-rail input switch is connected to the source of the fourth rail-to-rail input switch and the drain of the second current replication switch. The drain of the first rail-to-rail input switch is the first output terminal of the rail-to-rail input pair unit and is connected to the first input terminal of the load module. The gate of the second rail-to-rail input switch is connected to the gate of the first rail-to-rail input switch, the source of the second rail-to-rail input switch is connected to the drain of the current source switch, and the drain of the second rail-to-rail input switch is the second output terminal of the rail-to-rail input pair unit, which is connected to the second input terminal of the load module. The gate of the third rail-to-rail input switch is connected to the reference signal terminal, the source of the third rail-to-rail input switch is connected to the source of the first rail-to-rail input switch, and the drain of the third rail-to-rail input switch is the third output terminal of the rail-to-rail input pair unit, which is connected to the third input terminal of the load module. The gate of the fourth rail-to-rail input switch is connected to the gate of the third rail-to-rail input switch, the source of the fourth rail-to-rail input switch is connected to the source of the second rail-to-rail input switch, and the drain of the fourth rail-to-rail input switch is the fourth output terminal of the rail-to-rail input pair unit, which is connected to the fourth input terminal of the load module.

[0014] In one optional implementation, the load module includes a first load unit and a second load unit; The control terminal of the first load unit is connected to the control terminal of the current source switch transistor. The first input terminal of the first load unit is connected to the power supply terminal. The second input terminal of the first load unit is connected to the drain of the first rail-to-rail input switch transistor. The third input terminal of the first load unit is connected to the drain of the third rail-to-rail input switch transistor. The output terminal of the first load unit is connected to the input terminal of the output shaping module. The second input terminal of the first load unit serves as the first input terminal of the load module, and the third input terminal of the first load unit serves as the third input terminal of the load module. The control terminal of the second load unit is connected to the control terminal of the second current replication switch. The first input terminal of the second load unit is connected to the ground terminal. The second input terminal of the second load unit is connected to the drain of the second rail-to-rail input switch. The third input terminal of the second load unit is connected to the drain of the fourth rail-to-rail input switch. The output terminal of the second load unit is connected to the input terminal of the output shaping module. The second input terminal of the second load unit serves as the second input terminal of the load module, and the third input terminal of the second load unit serves as the fourth input terminal of the load module.

[0015] In one optional implementation, the first load unit includes a first switch, a second switch, a third switch, and a fourth switch. The gate of the first switch is connected to the gate of the second switch, and then connected to the gate of the current source switch; the gate of the third switch is connected to the gate of the fourth switch, and the gate of the third switch is shorted to its own drain; the sources of the first switch and the second switch are both connected to the power supply terminal. The drain of the first switching transistor is connected to the source of the fourth switching transistor. The drain of the fourth switching transistor serves as the output terminal of the first load unit and is connected to the input terminal of the output shaping module. The drain of the second switch is connected to the source of the third switch. The gate and drain of the third switch are shorted together and then connected to the I3C signal input terminal through a feedforward capacitor. The drain of the first switching transistor is the second input terminal of the load unit and is connected to the drain of the first rail-to-rail input switching transistor. The drain of the second switching transistor is the third input terminal of the load unit and is connected to the drain of the third rail-to-rail input switching transistor. And / or, the second load unit includes a fifth switch, a sixth switch, a seventh switch, and an eighth switch; After the gate of the seventh switch is connected to the gate of the eighth switch, it is connected to the gate of the second current replication switch; the gate of the fifth switch is connected to the gate of the sixth switch. The sources of the seventh and eighth switching transistors are connected to the ground terminal; the drain of the seventh switching transistor is connected to the source of the fifth switching transistor; the drain of the fifth switching transistor is connected to the I3C signal input terminal through a feedforward capacitor; the drain of the eighth switching transistor is connected to the source of the sixth switching transistor; the drain of the sixth switching transistor serves as the output terminal of the second load unit and is connected to the input terminal of the output shaping module. The source of the fifth switch is the third input terminal of the load unit and is connected to the drain of the fourth rail-to-rail input switch; the source of the sixth switch is the fourth input terminal of the load unit and is connected to the drain of the second rail-to-rail input switch.

[0016] In one alternative implementation, the output shaping module includes a cascaded inverter structure; The cascaded inverter structure is used to perform edge shaping on the corrected level comparison signal and output a standard digital logic signal that is compatible with the I3C protocol.

[0017] In one alternative implementation, the cascaded inverter structure includes an odd number of inverters connected in series. The first inverter in an odd number of inverters connected in series is connected to the output of the load module, and the last inverter in an odd number of inverters connected in series outputs a standard digital logic signal adapted to the I3C protocol.

[0018] In one alternative implementation, when the I3C input signal flips from low to high, the switchable reference voltage output from the reference signal terminal switches from a second voltage to a first voltage. When the I3C input signal flips from high level to low level, the switchable reference voltage output from the reference signal terminal switches from the first voltage to the second voltage. The second voltage is greater than the first voltage.

[0019] This application also provides a chip, including a comparison detection circuit for the I3C protocol according to any of the first aspects.

[0020] This application also provides an electronic device, including a chip from the second aspect.

[0021] Under the above technical solution, the comparison detection circuit for the I3C protocol provided in this application embodiment includes: a power supply terminal, a current bias module, a rail-to-rail input comparison module, a load module, a feedforward capacitor, and an output shaping module; the power supply terminal is used to supply power to the current bias module, the rail-to-rail input comparison module, and the load module, wherein the power supply terminal is the internal power supply of the I3C protocol chip; the input terminal of the current bias module is connected to the I3C signal input terminal, and the output terminal of the current bias module is connected to the current source unit of the rail-to-rail input comparison module; the current bias module is used to provide a dynamically adjustable bias current to the current source unit of the rail-to-rail input comparison module according to the I3C input signal provided by the I3C signal input terminal; wherein the dynamically adjustable bias current can instantaneously increase according to the level flip of the I3C input signal; the first comparison terminal of the rail-to-rail input comparison module is connected to the I3C signal input terminal. The input terminals are connected as follows: the second comparison terminal of the rail-to-rail input comparator is connected to the reference signal terminal; the output terminal of the rail-to-rail input comparator is connected to the load module. The rail-to-rail input comparator provides a level comparison signal to the load module based on the dynamically adjustable bias current, the I3C input signal provided by the I3C signal input terminal, and the reference voltage provided by the reference signal terminal. The reference signal terminal outputs a switchable reference voltage based on the I3C input signal. The intermediate node of the load module is connected to the I3C signal input terminal via a feedforward capacitor. The output terminal of the load module is connected to the input terminal of the output shaping module. The load module amplifies and corrects the level comparison signal based on the transition edges of the level comparison signal and the I3C input signal to obtain a corrected level comparison signal. The output shaping module performs edge shaping on the corrected level comparison signal and outputs a standard digital logic signal adapted to the I3C protocol.

[0022] Based on the above description, the power supply terminal used in this application embodiment is the internal power supply of the I3C protocol chip, which does not require the generation of additional auxiliary voltage, thus avoiding continuous steady-state current loss caused by the additional auxiliary voltage.

[0023] The current bias module provides a dynamically adjustable bias current to the current source unit of the rail-to-rail input comparator module based on the I3C input signal provided by the I3C signal input terminal. The dynamically adjustable bias current can be increased instantaneously according to the level flip of the I3C input signal. That is, when the rising edge and falling edge of the I3C input signal flip, the current bias module can synchronously and instantaneously increase the bias current. At this time, the feedforward capacitor can synchronously perform bidirectional acceleration regulation on the load module, so that the rising edge and falling edge propagation delay of the overall structure formed by the rail-to-rail input comparator module and the load module are consistent, eliminating the timing asymmetry problem caused by the Schmitt trigger hysteresis threshold difference, and effectively avoiding setup time and hold time violations in I3C high-speed mode.

[0024] Furthermore, the embodiments of this application set a switchable reference voltage to replace the fixed hysteresis window of the Schmitt trigger; at the same time, the setting of dynamic bias current and feedforward capacitor can quickly complete the level determination. When the I3C bus is affected by long lines or electromagnetic interference and the signal fluctuates, it can distinguish between valid signals and noise jitter, avoid repeated output jumps, eliminate misjudgment of I3C bus START and STOP signals, and meet the timing jitter constraint requirements of the I3C protocol.

[0025] Furthermore, the embodiments of this application eliminate independent level converters, directly perform signal comparison and shaping based on the internal power domain of the chip, and eliminate the 2-5ns fixed transmission delay introduced by the level converter; at the same time, the feedforward capacitor couples the I3C signal transition edge, adjusts the working state of the load module in advance, further accelerates the comparator output switching, significantly reduces the overall signal delay, and adapts to the timing requirements of I3C high-speed communication.

[0026] Finally, the output shaping module provided in this application embodiment performs edge shaping on the corrected level comparison signal and outputs a standard digital logic signal with steep edges and stable timing, ensuring the timing stability of I3C bus communication and improving communication reliability. Attached Figure Description

[0027] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0028] Figure 1 A schematic diagram of a comparison detection circuit for the I3C protocol provided in an embodiment of the present invention. Figure 1 ; Figure 2 A schematic diagram of a comparison detection circuit for the I3C protocol provided in this application embodiment. Figure 2 ; Figure 3 This is a schematic diagram of a switchable reference voltage generation module provided in an embodiment of the present invention.

[0029] Explanation of reference numerals in the attached figures: 10 - Current bias module; 101 - Coupling capacitor unit; 102 - Bias unit; 103 - Current replication unit; 20 - Rail-to-rail input comparator module; 201 - Rail-to-rail input pair unit; 30 - Load module; 301 - First load unit; 302 - Second load unit; 40 - Output shaping module; VDD - Power supply terminal; GND - Ground terminal; INN - I3C signal input terminal; REF - Reference signal terminal; I1 - Constant current source; C1 - First coupling capacitor; C2 - Second coupling capacitor; R1 - First resistor; R2 - Second resistor; R3 - Third resistor; R4 - Fourth resistor; MP0 - Current source switch transistor; MP1 - First switch; MP2 - Second switch; MP3 - Third switch; MP4 - Fourth switch; MP5 - Second rail-to-rail input switch; MP6 - Fourth rail-to-rail input switch; MP7 - First bias switch; MP8 - First paired switch; MP9 - Second paired switch; MN0 - Fifth switch; MN1 - Sixth switch; MN2 - Seventh switch; MN3 - Eighth switch; MN4 - Second current replication switch; MN5 - First current replication switch; MN6 - First rail-to-rail input switch; MN7 - Third rail-to-rail input switch; MN8 - Second bias switch; CF - Feedforward capacitor. Detailed Implementation

[0030] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to limit the application. It is understood that the terms “first,” “second,” etc., as used herein may be used to describe various information or data, but these elements are not limited by these terms. These terms are only used to distinguish the information described in the first instance from another piece of information. For example, without departing from the scope of this application, first action information may be referred to as second action information, and similarly, second action information may be referred to as first action information. Both first action information and second action information are action information, but they are not the same action information.

[0032] In this document, it should be understood that the terminology used is for convenience of understanding only and does not imply any limitation on its meaning. Furthermore, any number of elements in the accompanying drawings is for illustrative purposes only and not for limitation, and any naming is for distinction only and has no limiting meaning.

[0033] As a new generation of high-speed serial communication protocol, the I3C bus is widely used in integrated circuit communication scenarios such as sensors and embedded chips. It places high demands on signal detection accuracy, timing synchronization, low power consumption characteristics, and timing jitter control.

[0034] Existing I3C interface receivers typically employ an architecture of low-voltage domain logic recognition, Schmitt triggers, and level shifters to match external signals with the chip's internal logic domain. This involves first stepping down the chip's internal power supply to below 2V, then using a Schmitt trigger to determine the high or low level logic of the external low-voltage digital signal, and finally using a level shifter to convert the low-voltage logic signal into a signal within the chip's internal operating voltage domain.

[0035] However, existing technical solutions have several drawbacks: First, to adapt to the operation of the Schmitt trigger, an additional auxiliary voltage of approximately 2V is required, which introduces continuous steady-state current loss. Simultaneously, if the external input digital signal voltage is too low, the Schmitt trigger will generate additional static current, significantly increasing the overall power consumption at the receiver, which is detrimental to low-power applications. Second, the Schmitt trigger relies on the hysteresis characteristics of positive and negative thresholds to determine the level. Its inherent threshold difference causes inconsistent propagation delays between the rising and falling edges, easily leading to signal setup and hold time violations in I3C high-speed communication mode. When the external I3C bus signal is affected by long-distance transmission interference or electromagnetic interference, fluctuating within the hysteresis threshold window, the Schmitt trigger output will frequently and repeatedly change, causing misjudgments of the I3C bus START and STOP signals, failing to meet the strict timing jitter constraints of the I3C protocol. Finally, the level converter needs to operate continuously to connect the low-voltage domain with the core voltage domain of the chip. Its static current and the power consumption of the Schmitt trigger are superimposed, further increasing the overall power consumption. At the same time, the level converter introduces a signal transmission delay of 2-5ns, which can easily cause significant timing deviations in high-speed I3C signal transmission and reduce communication reliability.

[0036] Based on this, the technical concept of this application is as follows: The traditional Schmitt trigger hysteresis judgment and independent level conversion structure are eliminated, and a comparison architecture combining dynamic bias current regulation and feedforward capacitor CF acceleration is adopted. The current bias module instantaneously increases the current at the rising and falling edges of the I3C input signal, instantly improving the comparison speed during the flip-flop, while maintaining a small current in the steady state to reduce static power consumption. Simultaneously, the feedforward capacitor CF accelerates the load module flip-flop, eliminating the timing asymmetry problem caused by the traditional hysteresis threshold and ensuring consistent rising and falling edge propagation delays. Combined with rail-to-rail input comparison and a switchable reference voltage for level detection, no additional low-voltage power supply and level conversion circuit are required, reducing transmission delay and superimposed power consumption. Finally, the output shaping module outputs a well-defined standard logic signal, achieving low power consumption, high speed, timing symmetry, and strong anti-interference capability, meeting the timing requirements of the high-speed I3C protocol.

[0037] The technical solutions shown in this application will now be described in detail through specific embodiments. It should be noted that the following embodiments may exist independently or in combination with each other; for identical or similar content, the description will not be repeated in different embodiments.

[0038] Reference Figure 1 This application provides a comparison detection circuit for the I3C protocol. The comparison detection circuit for the I3C protocol includes: a power supply terminal VDD, a current bias module 10, a rail-to-rail input comparison module 20, a load module 30, a feedforward capacitor CF, and an output shaping module 40. The power supply terminal VDD is used to supply power to the current bias module 10, the rail-to-rail input comparator module 20 and the load module 30. The power supply terminal VDD is the internal power supply of the I3C protocol chip. The input terminal of the current bias module 10 is connected to the I3C signal input terminal INN, and the output terminal of the current bias module 10 is connected to the current source unit of the rail-to-rail input comparison module 20. The current bias module 10 is used to provide a dynamically adjustable bias current to the current source unit of the rail-to-rail input comparison module 20 according to the I3C input signal provided by the I3C signal input terminal INN. The dynamically adjustable bias current can be increased instantaneously according to the level flip of the I3C input signal. The first comparison terminal of the rail-to-rail input comparison module 20 is connected to the I3C signal input terminal INN, the second comparison terminal of the rail-to-rail input comparison module 20 is connected to the reference signal terminal REF, and the output terminal of the rail-to-rail input comparison module 20 is connected to the load module 30. The reference signal terminal REF is used to output a switchable reference voltage according to the I3C input signal. The rail-to-rail input comparison module 20 is used to provide a level comparison signal to the load module 30 based on the dynamically adjustable bias current, the I3C input signal provided by the I3C signal input terminal INN, and the reference voltage provided by the reference signal terminal REF. The intermediate node of the load module 30 is connected to the I3C signal input terminal INN through the feedforward capacitor CF. The output terminal of the load module 30 is connected to the input terminal of the output shaping module 40. The load module 30 is used to amplify and correct the level comparison signal according to the transition edge of the level comparison signal and the I3C input signal to obtain the corrected level comparison signal. The output shaping module 40 is used to perform edge shaping on the corrected level comparison signal and output a standard digital logic signal that is compatible with the I3C protocol.

[0039] In this embodiment, the power supply terminal VDD serves as the power source for the entire circuit. It adopts the internal power supply of the I3C protocol chip, eliminating the need for additional step-down circuits to generate a dedicated low-voltage power supply. This provides unified power to the current bias module 10, the rail-to-rail input comparison module 20, and the load module 30.

[0040] The input terminal of the current bias module 10 is connected to the I3C signal input terminal INN, and the output terminal is connected to the current source unit of the rail-to-rail input comparator module 20. It is used to supply a dynamically adjustable bias current to the current source unit of the rail-to-rail input comparator module 20 based on the I3C input signal input at the I3C signal input terminal INN. When the I3C input signal undergoes a level flip, this dynamically adjustable bias current instantaneously increases, thereby changing the operating current state of the subsequent comparator module.

[0041] The rail-to-rail input comparison module 20 has two comparison terminals and an output terminal: the first comparison terminal is connected to the I3C signal input terminal INN to receive the I3C input signal; the second comparison terminal is connected to the reference signal terminal REF to receive the reference voltage. The rail-to-rail input comparison module 20 operates based on the dynamically adjustable bias current output by the current bias module 10, and combines this with the I3C input signal and the reference voltage output from the reference signal terminal REF to complete the level comparison and output a level comparison signal to the load module 30. The reference signal terminal REF can output different levels of reference voltage according to the actual situation of the I3C input signal, realizing the switching of the detection reference.

[0042] The intermediate node of load module 30 is connected to the I3C signal input terminal INN via a feedforward capacitor CF, and the output terminal of load module 30 is connected to the input terminal of output shaping module 40. Load module 30 receives the level comparison signal output from rail-to-rail input comparator module 20, and simultaneously amplifies and corrects the level comparison signal by incorporating the transition edge of the I3C input signal, ultimately generating a corrected level comparison signal for transmission. The feedforward capacitor CF acts as a coupling device, establishing a signal path between the I3C input signal and load module 30, thus cooperating to complete the signal processing.

[0043] The input terminal of the output shaping module 40 receives the corrected level comparison signal output by the load module 30. Its main function is to perform edge shaping processing on the signal, filter out signal defects, normalize the waveform shape, and finally output a standard digital logic signal that conforms to the I3C protocol specification.

[0044] In this embodiment, the working logic of the comparison detection circuit for the I3C protocol is as follows: After the I3C input signal is connected to the circuit from the signal input terminal, it is split into two paths and connected to the current bias module 10 and the load module 30 respectively; the power supply terminal VDD continuously supplies power to the entire circuit. The current bias module 10 outputs a dynamic bias current according to the I3C input signal status and supplies it to the rail-to-rail input comparison module 20; the rail-to-rail input comparison module 20 combines the bias current, the I3C input signal, and the switchable reference voltage to output a level comparison signal to the load module 30. The load module 30 amplifies and corrects the level comparison signal using the I3C signal transition edge coupled by the feedforward capacitor CF, and then the output shaping module 40 completes waveform shaping, finally outputting a digital logic signal adapted to the I3C protocol. When the I3C input signal undergoes a level transition, the bias current of the current bias module 10 will increase instantaneously, working with the other modules to complete high-speed signal detection and processing.

[0045] Based on the above description, the comparison detection circuit for the I3C protocol provided in this application embodiment includes: a power supply terminal VDD, a current bias module 10, a rail-to-rail input comparison module 20, a load module 30, a feedforward capacitor CF, and an output shaping module 40; the power supply terminal VDD is used to supply power to the current bias module 10, the rail-to-rail input comparison module 20, and the load module 30, wherein the power supply terminal VDD is the internal power supply of the I3C protocol chip; the input terminal of the current bias module 10 is connected to the I3C signal input terminal INN, and the output terminal of the current bias module 10 is connected to the current source unit of the rail-to-rail input comparison module 20; the current bias module 10 is used to provide a dynamically adjustable bias current to the current source unit of the rail-to-rail input comparison module 20 according to the I3C input signal provided by the I3C signal input terminal INN; wherein the dynamically adjustable bias current can increase instantaneously according to the level flip of the I3C input signal; the first comparison terminal of the rail-to-rail input comparison module 20 is connected to the I3C signal input terminal INN. The rail-to-rail input comparison module 20 is connected to the INN terminal, and its second comparison terminal is connected to the reference signal terminal REF. The output terminal of the rail-to-rail input comparison module 20 is connected to the load module 30. The rail-to-rail input comparison module 20 provides a level comparison signal to the load module 30 based on the dynamically adjustable bias current, the I3C input signal provided by the I3C signal input terminal INN, and the reference voltage provided by the reference signal terminal REF. The reference signal terminal REF outputs a switchable reference voltage based on the I3C input signal. The intermediate node of the load module 30 is connected to the I3C signal input terminal INN via a feedforward capacitor CF. The output terminal of the load module 30 is connected to the input terminal of the output shaping module 40. The load module 30 amplifies and corrects the level comparison signal based on the transition edges of the level comparison signal and the I3C input signal to obtain a corrected level comparison signal. The output shaping module 40 performs edge shaping on the corrected level comparison signal and outputs a standard digital logic signal adapted to the I3C protocol.

[0046] Based on the above description, the power supply terminal VDD used in the embodiments of this application is the internal power supply of the I3C protocol chip, which does not require the generation of additional auxiliary voltage, thus avoiding continuous steady-state current loss caused by the additional auxiliary voltage.

[0047] The current bias module 10 provides a dynamically adjustable bias current to the current source unit of the rail-to-rail input comparison module 20 based on the I3C input signal provided by the I3C signal input terminal INN. The dynamically adjustable bias current can be increased instantaneously according to the level flip of the I3C input signal. That is, when the rising edge and falling edge of the I3C input signal flip, the current bias module 10 can synchronously and instantaneously increase the bias current. At this time, the feedforward capacitor CF can synchronously perform bidirectional acceleration regulation on the load module 30, so that the rising edge and falling edge propagation delay of the overall structure formed by the rail-to-rail input comparison module 20 and the load module 30 are consistent, eliminating the timing asymmetry problem caused by the Schmitt trigger hysteresis threshold difference, and effectively avoiding setup time and hold time violations in I3C high-speed mode.

[0048] Furthermore, the embodiments of this application set a switchable reference voltage to replace the fixed hysteresis window of the Schmitt trigger; at the same time, the setting of dynamic bias current and feedforward capacitor CF can quickly complete the level determination. When the I3C bus is affected by long lines or electromagnetic interference and the signal fluctuates, it can distinguish between valid signals and noise jitter, avoid repeated output jumps, eliminate misjudgment of I3C bus START and STOP signals, and meet the timing jitter constraint requirements of the I3C protocol.

[0049] Furthermore, the embodiments of this application eliminate independent level converters and directly complete signal comparison and shaping based on the internal power domain of the chip, eliminating the 2-5ns fixed transmission delay introduced by the level converter; at the same time, the feedforward capacitor CF couples the I3C signal transition edge, pre-regulates the working state of the load module 30, further accelerates the comparator output switching, significantly reduces the overall signal delay, and adapts to the timing requirements of I3C high-speed communication.

[0050] Finally, the output shaping module 40 provided in this embodiment performs edge shaping on the corrected level comparison signal and outputs a standard digital logic signal with steep edges and stable timing, ensuring the timing stability of I3C bus communication and improving communication reliability.

[0051] Optional, refer to Figure 2 The current bias module 10 includes: a constant current source, a coupling capacitor unit 101, a bias unit 102, and a current replication unit 103. The power supply terminal VDD is connected to the constant current source, coupling capacitor unit 101, bias unit 102 and current replication unit 103, and is used to supply power to the constant current source, coupling capacitor unit 101, bias unit 102 and current replication unit 103. The output terminal of the constant current source is connected to the current replication unit 103 to provide a reference current to the current replication unit 103; The input terminal of the coupling capacitor unit 101 is connected to the I3C signal input terminal INN, and the output terminal of the coupling capacitor unit 101 is connected to the bias unit 102. The coupling capacitor unit 101 is used to turn on the bias unit 102 when the I3C input signal provided by the I3C signal input terminal INN changes. The output terminal of the bias unit 102 is connected to the current replication unit 103. The bias unit 102 is used to generate a jump current when the I3C input signal jumps and output the jump current to the current replication unit 103. The current replication unit 103 is used to generate a dynamically adjustable bias current based on the reference current, or the reference current and the jump current, and output the dynamically adjustable bias current to the current source unit of the rail-to-rail input comparison module 20.

[0052] In this embodiment, the power supply terminal VDD is connected to the constant current source, the coupling capacitor unit 101, the bias unit 102, and the current replication unit 103, respectively, to provide working power to all the above units and ensure the overall normal operation of the current bias module 10.

[0053] The output terminal of the constant current source is connected to the current replication unit 103 to continuously supply a stable reference current to the current replication unit 103. This reference current is part of the dynamically adjustable bias current.

[0054] The input terminal of the coupling capacitor unit 101 is connected to the I3C signal input terminal INN, and the output terminal is connected to the bias unit 102. When the I3C input signal remains stable, the coupling capacitor unit 101 does not operate, and the bias unit 102 is in the off state; when the I3C input signal undergoes a level transition, the coupling capacitor unit 101 uses the capacitive coupling characteristic to trigger and turn on the bias unit 102, realizing the logic transmission from signal transition to device conduction.

[0055] The output of the bias unit 102 is connected to the current replication unit 103. It only works when the I3C input signal jumps and the coupling capacitor unit 101 is turned on. At this time, it generates a jump current and sends the current to the current replication unit 103. After the I3C input signal stabilizes, the bias unit 102 stops working and no longer outputs jump current.

[0056] When the I3C input signal is stable, the current replication unit 103 only receives the reference current output by the constant current source to generate a dynamically adjustable bias current and output it outward. When the I3C input signal changes, it simultaneously receives the reference current and the changing current output by the bias unit 102, integrates the two currents to generate a dynamically adjustable bias current, and finally outputs the generated dynamically adjustable bias current to the current source unit of the rail-to-rail input comparison module 20.

[0057] Based on the above description, in the embodiment of this application, during the period when the I3C input signal is stable, the bias unit 102 is turned off, and the current replication unit 103 generates the bias current only based on the reference current. The overall operating current of the circuit is small, which effectively reduces static power consumption.

[0058] When the I3C input signal level changes, the coupling capacitor unit 101 quickly turns on the bias unit 102, generating a jump current, which causes the bias current output by the current replication unit 103 to increase instantaneously, thereby increasing the operating speed of the subsequent rail-to-rail input comparison module 20 and accelerating the signal detection and response speed.

[0059] Furthermore, the embodiments of this application can rely on the combination of the coupling capacitor unit 101 sensing signal transitions and the bias unit 102 outputting transition current as needed to achieve automatic switching of the bias current according to the input signal state, accurately matching the current requirements of different working scenarios of the circuit.

[0060] Furthermore, refer to Figure 2 The coupling capacitor unit 101 includes a first coupling capacitor C1 and a second coupling capacitor C2; the bias unit 102 includes a first bias switch MP7 and a second bias switch MN8. The first plate of the first coupling capacitor C1 and the first plate of the second coupling capacitor C2 are both connected to the I3C signal input terminal INN. The second plate of the first coupling capacitor C1 is connected to the gate of the first bias switch MP7. The source of the first bias switch MP7 is connected to the power supply terminal VDD. The drain of the first bias switch MP7 is connected to the first input terminal of the current mirror replication unit. The second plate of the second coupling capacitor C2 is connected to the gate of the second bias switch MN8, the source of the second bias switch MN8 is grounded, and the drain of the second bias switch MN8 is connected to the second input terminal of the current mirror replication unit; the output terminal of the constant current source is connected to the first input terminal of the current mirror replication unit. The output of the current mirror copy unit is connected to the current source unit of the rail-to-rail input comparison module 20, and is used to mirror and copy the dynamically adjustable bias current and output it to the current source unit of the rail-to-rail input comparison module 20.

[0061] In this embodiment, the first plate of the first coupling capacitor C1 and the first plate of the second coupling capacitor C2 are connected to the I3C signal input terminal INN, and the two coupling capacitors synchronously acquire the level changes of the I3C input signal.

[0062] The second plate of the first coupling capacitor C1 is connected to the gate of the first bias switch MP7. The source of the first bias switch MP7 is connected to the power supply terminal VDD, and the drain is connected to the first input terminal of the current mirror replication unit. When the I3C input signal transitions from high to low, the first coupling capacitor C1 uses its capacitive coupling characteristic to pull down the gate potential of the first bias switch MP7, turning on the switch and injecting current from the power supply terminal to the first input terminal of the current mirror replication unit.

[0063] The second plate of the second coupling capacitor C2 is connected to the gate of the second bias switch MN8; the source of the second bias switch MN8 is grounded, and its drain is connected to the second input terminal of the current mirror replication unit. When the I3C input signal transitions from low to high, the second coupling capacitor C2 utilizes its capacitive coupling characteristics to raise the gate potential of the second bias switch MN8, causing the switch to conduct and discharge current to ground, thus changing the current state at the second input terminal of the current mirror replication unit.

[0064] The output of the constant current source is connected to the first input of the current mirror replication unit, continuously providing a stable reference current to this node as the basic current for the steady-state operation of the circuit.

[0065] The current mirror copying unit receives the reference current at the first input terminal, the current generated by the first bias switch MP7 being turned on, or the current generated by the second bias switch MN8 being turned on at the second input terminal, and mirrors the integrated current to generate a dynamically adjustable bias current, which is then sent from the output terminal to the current source unit of the rail-to-rail input comparison module 20.

[0066] Based on the above description, the embodiments of this application rely on two sets of independent coupling capacitors and bias switching transistors to respond to the falling edge and rising edge of the I3C input signal, respectively. The two operating conditions are independent of each other and can accurately identify signal flips in different directions.

[0067] When the I3C input signal is in a steady state, only the constant current source provides the reference current, resulting in a relatively small overall current and effectively reducing the circuit's static power consumption. When the I3C input signal experiences a level transition, the corresponding bias switch is turned on, adding an extra current and causing the bias current output by the current mirror replication unit to increase instantaneously, thus improving the response speed of the subsequent comparison module. The current mirror replication unit mirrors the integrated current, ensuring stable and consistent output current amplitude, and providing reliable bias drive for the current source unit of the rail-to-rail input comparison module 20.

[0068] Furthermore, in this embodiment, the rising and falling edges of the I3C input signal adopt a symmetrical coupling trigger structure, and the current regulation mechanism under the two transition scenarios is similar, which can keep the circuit's response characteristics to the two edges consistent and avoid timing deviations.

[0069] In one alternative implementation, refer to Figure 2 When the I3C input signal is in a steady state, both the first bias switch MP7 and the second bias switch MN8 are turned off. The current mirror copying unit copies the reference current output by the constant current source and outputs it to the current source unit of the rail-to-rail input comparison module 20. When the I3C input signal flips from high level to low level, the I3C input signal is coupled through the first coupling capacitor C1, turns on the first bias switch MP7, and generates the first jump current. The current mirror copying unit mirrors the superimposed reference current and the first jump current to generate a dynamically adjustable bias current and outputs it to the current source unit of the rail-to-rail input comparison module 20. When the I3C input signal flips from low level to high level, the I3C input signal is coupled through the second coupling capacitor C2, turns on the second bias switch MN8, and generates the second switching current; the current mirror copying unit mirrors the superimposed reference current and the second switching current to generate a dynamically adjustable bias current and outputs it to the current source unit of the rail-to-rail input comparison module 20.

[0070] In this embodiment, when the I3C input signal is in a steady state, both the first bias switch MP7 and the second bias switch MN8 remain off, and no additional current is generated. The current mirror replication unit only mirrors the reference current output by the constant current source and uses this current as the bias current to supply the current source unit of the rail-to-rail input comparison module 20. The circuit operates with a fixed reference current.

[0071] When the I3C input signal transitions from high to low, the signal transition is coupled through the first coupling capacitor C1, causing the first bias switch MP7 to switch from off to on. The on-state of the first bias switch MP7 generates a first transition current. This first transition current is superimposed on the original reference current. The current mirror replication unit performs a mirror replication of the superimposed total current to generate a dynamically adjustable bias current, which is then output to the current source unit of the rail-to-rail input comparison module 20.

[0072] When the I3C input signal flips from low to high, the signal transition is coupled through the second coupling capacitor C2, causing the second bias switch MN8 to switch from off to on. The on-state of the second bias switch MN8 generates a second transition current. This second transition current is superimposed on the original reference current. The current mirror replication unit performs a mirror replication of the superimposed total current to generate a dynamically adjustable bias current, which is then output to the current source unit of the rail-to-rail input comparison module 20.

[0073] Based on the above description, when the I3C input signal is stable, both bias switches are turned off, and the circuit only consumes the reference current without additional current loss, effectively reducing the overall static power consumption. When the I3C input signal flips at the rising or falling edge, the corresponding bias switch turns on and outputs a switching current. After being superimposed on the reference current, the overall bias current increases instantaneously, improving the operating speed of the subsequent comparator module and adapting to the high-speed communication requirements of I3C.

[0074] Optional, refer to Figure 2 The current bias module 10 also includes a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4; The first end of the first resistor R1 is connected to the second end of the second coupling capacitor C2 and the control terminal of the second bias switch MN8. The second end of the first resistor R1 is grounded. The first resistor R1 is used to pull down the gate potential of the second bias switch MN8 when the I3C input signal is in a steady state, so that the second bias switch MN8 is turned off. The first end of the second resistor R2 is connected to the second end of the first coupling capacitor C1 and the control terminal of the first bias switch MP7. The second end of the second resistor R2 is connected to the power supply terminal VDD. The second resistor R2 is used to pull up the gate potential of the first bias switch MP7 when the I3C input signal is in a steady state, so that the first bias switch MP7 is turned off. The first end of the third resistor R3 is connected to the drain of the first bias switch MP7, and the second end of the third resistor R3 is connected to the output of the constant current source. The third resistor R3 is used to reset the first bias switch MP7 to the off state after the I3C input signal flips from high level to low level. The first end of the fourth resistor R4 is connected to the current mirror replication unit, and the second end of the fourth resistor R4 is connected to the drain of the second bias switch MN8. The fourth resistor R4 is used to reset the second bias switch MN8 to the off state after the I3C input signal flips from low level to high level.

[0075] In this embodiment, one end of the first resistor R1 is connected to the second terminal of the second coupling capacitor C2 and the control terminal (gate) of the second bias switch MN8, while the other end is grounded. When the I3C input signal is in a steady state, the resistor continuously pulls down the gate potential of the second bias switch MN8, maintaining the second bias switch MN8 in a turned-off state and preventing the second bias switch from being mistakenly turned on.

[0076] One end of the second resistor R2 is connected to the second terminal of the first coupling capacitor C1 and the control terminal (gate) of the first bias switch MP7, and the other end is connected to the power supply terminal VDD. When the I3C input signal is in a steady state, the second resistor R2 continuously pulls up the gate potential of the first bias switch MP7, keeping the first bias switch MP7 off.

[0077] The third resistor R3 is connected at one end to the drain of the first bias switch MP7 and at the other end to the output of the constant current source. After the I3C input signal completes its transition from high to low, the third resistor R3, in conjunction with the circuit potential change, resets the first bias switch MP7 from the conducting state to the off state.

[0078] One end of the fourth resistor R4 is connected to the current mirror replication unit, and the other end is connected to the drain of the second bias switch MN8. After the I3C input signal completes its transition from low to high level, the fourth resistor R4 acts on the circuit loop, resetting the conducting second bias switch MN8 to the off state.

[0079] The overall working logic is as follows: Under steady state, the first resistor R1 and the second resistor R2 clamp the potential of the two biased switching transistors respectively to ensure that they are reliably turned off; when the I3C input signal level flips, the coupling capacitor changes the gate potential to turn on the corresponding switching transistor to generate a jumping current; after the flipping action is completed, the third resistor R3 and the fourth resistor R4 reset the two switching transistors respectively, so that they return to the off state.

[0080] Based on the above description, when the I3C input signal is in a steady state, the first resistor R1 pulls down and the second resistor R2 pulls up the gate potential of the two bias switches, forcing the corresponding bias switches to remain off. This can resist the misleading turn-on caused by circuit noise and voltage fluctuations, and ensure the accurate steady-state working logic of the current bias module 10.

[0081] After the I3C input signal level flips, the third resistor R3 and the fourth resistor R4 quickly restore the conducting bias switch to the off state, so that the switching current is generated only at the moment the I3C input signal flips. After the I3C input signal stabilizes, the circuit immediately returns to the low current operating mode.

[0082] Optionally, the current mirror replication unit includes a current mirror and a first current replication switch MN5; The current mirror includes a first paired transistor MP8 and a second paired transistor MP9; the source of the first paired transistor MP8 and the source of the second paired transistor MP9 are both connected to the power supply terminal VDD, the gates of the first paired transistor MP8 and the second paired transistor MP9 are connected, the drain of the first paired transistor MP8 is shorted to the gate of the first paired transistor MP8, the drain of the first paired transistor MP8 is connected to the drain of the second bias switch transistor MN8, the drain of the second paired transistor MP9 is connected to the drain and gate of the first current replication switch transistor MN5, and the source of the first current replication switch transistor MN5 is grounded; In this configuration, the drain of the first paired transistor MP8 is the first input terminal of the current mirror replication unit, the drain of the second paired transistor MP9 is the second input terminal of the current mirror replication unit, and the drain and gate of the first current replication switch transistor MN5 are short-circuited to form the output terminal of the current mirror replication unit.

[0083] In this embodiment, the sources of the first paired transistor MP8 and the second paired transistor MP9 are connected to the power supply terminal VDD; their gates are interconnected, and the drain of the first paired transistor MP8 is shorted to its own gate. The drain of the first paired transistor MP8 also serves as the first input terminal of the current mirror replication unit and is connected to the drain of the second bias switch MN8. The drain of the second paired transistor MP9 is the second input terminal of the current mirror replication unit, which is connected to the drain and gate of the first current replication switch MN5. The source of the first current replication switch MN5 is grounded, and its drain is shorted to its gate; this shorted common node serves as the output terminal of the current mirror replication unit.

[0084] The operating logic of the current mirror replication unit is as follows: the first paired transistor MP8 uses a drain-gate short-circuit connection to determine the reference branch current of the current mirror; the second paired transistor MP9 is connected to the gate of the first paired transistor MP8, and current mirror replication is achieved based on transistor matching characteristics. The input current is input from the first input terminal and the second input terminal, and after the current mirror completes the current mirroring, it is sent to the first current replication switch MN5; this switch also has a drain-gate short-circuit structure to further stabilize the current pattern, and finally outputs a dynamically adjustable bias current from the output terminal.

[0085] Based on the above description, the first paired transistor MP8 with its drain and gate shorted together forms the reference branch of the current mirror. The second paired transistor MP9 is interconnected with the gate of the first paired transistor MP8, which can mirror the input current to ensure a stable ratio between the output current and the input current. A first current replication switch MN5 with its drain and gate shorted together is added to the rear end of the current mirror to further clamp the potential, smooth the current, and enhance the output drive capability, providing a stable operating current for the current source unit of the subsequent rail-to-rail input comparator module 20.

[0086] In one alternative implementation, refer to Figure 2 The rail-to-rail input comparison module 20 includes a current source unit and a rail-to-rail input pair unit 201; the current source unit includes a second current replication switch MN4 and a current source switch MP0. The gate of the second current replication switch MN4 is connected to the gate of the first current replication switch MN5. The source of the second current replication switch MN4 is grounded. The drain of the second current replication switch MN4 is connected to the first terminal of the rail-to-rail input pair unit 201. The gate of the second current replication switch MN4 is also connected to the first control terminal of the load module 30. The source of the current source switch MP0 is connected to the power supply terminal VDD and connected to the drain of the first current replication switch MN5 through the second pairing transistor MP9. The drain of the current source switch MP0 is connected to the second terminal of the rail-to-rail input pair unit 201. The gate of the current source switch MP0 is connected to the second control terminal of the load module 30. The first comparison terminal of the rail-to-rail input pair unit 201 is connected to the I3C signal input terminal INN, the second comparison terminal of the rail-to-rail input pair unit 201 is connected to the reference signal terminal REF, and the multiple output terminals of the rail-to-rail input pair unit 201 are all connected to the corresponding input terminals of the load module 30. The dynamically adjustable bias current output by the first current replication switch MN5 controls the second current replication switch MN4 and the current source switch MP0 to turn on or off, so as to realize the synchronous increase or decrease of the current and the dynamically adjustable bias current in the rail-to-rail input comparison module 20. Among them, the first current replication switch MN5 and the second current replication switch MN4 form a current mirror structure.

[0087] In this embodiment, the gate of the second current replication switch MN4 is connected to the gate of the first current replication switch MN5, and the two form a current mirror structure; the source of the second current replication switch MN4 is grounded, and the drain of the second current replication switch MN4 is connected to the first terminal of the rail input pair unit 201.

[0088] The source of the current source switch MP0 is connected to the power supply terminal VDD and is connected to the drain of the first current replication switch MN5 via the second paired switch MP9; the drain of the current source switch MP0 is connected to the second terminal of the rail-to-rail input pair unit 201, and the gate of the current source switch MP0 is connected to the second control terminal of the load module 30.

[0089] The first comparison terminal of the rail-to-rail input pair unit 201 is connected to the I3C signal input terminal INN to receive the I3C input signal; the second comparison terminal of the rail-to-rail input pair unit 201 is connected to the reference signal terminal REF to receive the reference voltage; all output terminals of the rail-to-rail input pair unit 201 are connected to the respective input terminals of the load module 30.

[0090] The specific operating logic of the rail-to-rail input comparison module 20 is as follows: The first current replication switch MN5 outputs a dynamically adjustable bias current. This dynamically adjustable bias current synchronously controls the second current replication switch MN4 through a current mirror, and simultaneously controls the on / off state of the current source switch MP0 in conjunction with the circuit path. The internal operating current of the rail-to-rail input comparison module 20 changes synchronously with the dynamically adjustable bias current: when the bias current increases, the module's operating current increases synchronously; when the bias current decreases, the module's operating current decreases synchronously. The rail-to-rail input comparison unit 201 compares the I3C input signal with the reference voltage, generates the corresponding level signal, and sends it to the subsequent load module 30.

[0091] Based on the above description, in this embodiment of the application, the first current replication switch MN5 and the second current replication switch MN4 constitute a current mirror structure, which can mirror and replicate the dynamically adjustable bias current output from the previous stage, so that the operating current of the rail-to-rail input comparison module 20 increases or decreases synchronously with the bias current, resulting in good current tracking performance and ensuring the uniformity of current regulation logic throughout the circuit.

[0092] When the I3C input signal is in a steady state, the amplitude of the front-end dynamic bias current is small. After being mirrored by the current mirror, the output current of the current source unit is synchronously maintained at a low level, which greatly reduces the static power consumption of the rail-to-rail input comparison module 20. When the I3C input signal undergoes a level flip, the dynamic bias current increases instantaneously, the module operating current increases synchronously, and the signal comparison speed of the rail-to-rail input comparison unit 201 is accelerated, effectively improving the transient response capability of the circuit and meeting the requirements of high-speed I3C communication.

[0093] In this embodiment, the rail-to-rail input pair unit 201 connects to the I3C input signal and the reference voltage. Based on the dynamic current source drive at the front end, it can complete level identification and comparison in the entire voltage range, adapt to I3C bus signals of different amplitudes, and has a wide range of circuit applications.

[0094] In some alternative implementations, refer to Figure 2 The rail-to-rail input pair unit 201 includes a first rail-to-rail input switch MN6, a second rail-to-rail input switch MP5, a third rail-to-rail input switch MN7, and a fourth rail-to-rail input switch MP6. The gate of the first rail-to-rail input switch MN6 is connected to the I3C signal input terminal INN. The source of the first rail-to-rail input switch MN6 is connected to the source of the fourth rail-to-rail input switch MP6 and the drain of the second current replication switch MN4. The drain of the first rail-to-rail input switch MN6 is the first output terminal of the rail-to-rail input pair unit 201 and is connected to the first input terminal of the load module 30. The gate of the second rail-to-rail input switch MP5 is connected to the gate of the first rail-to-rail input switch MN6. The source of the second rail-to-rail input switch MP5 is connected to the drain of the current source switch MP0. The drain of the second rail-to-rail input switch MP5 is the second output terminal of the rail-to-rail input pair unit 201, which is connected to the second input terminal of the load module 30. The gate of the third rail-to-rail input switch MN7 is connected to the reference signal terminal REF, the source of the third rail-to-rail input switch MN7 is connected to the source of the first rail-to-rail input switch MN6, and the drain of the third rail-to-rail input switch MN7 is the third output terminal of the rail-to-rail input pair unit 201, which is connected to the third input terminal of the load module 30. The gate of the fourth rail-to-rail input switch MP6 is connected to the gate of the third rail-to-rail input switch MN7. The source of the fourth rail-to-rail input switch MP6 is connected to the source of the second rail-to-rail input switch MP5. The drain of the fourth rail-to-rail input switch MP6 is the fourth output terminal of the rail-to-rail input pair unit 201, which is connected to the fourth input terminal of the load module 30.

[0095] In this embodiment, the gate of the first rail-to-rail input switch MN6 is connected to the I3C signal input terminal INN and is controlled by the I3C input signal; the source of the first rail-to-rail input switch MN6 is simultaneously connected to the source of the fourth rail-to-rail input switch MP6 and the drain of the second current replication switch MN4, and the second current replication switch MN4 provides the operating current; the drain of the first rail-to-rail input switch MN6 serves as the first output terminal of the rail-to-rail input pair unit 201 and is connected to the first input terminal of the load module 30.

[0096] The gate of the second rail-to-rail input switch MP5 is connected to the gate of the first rail-to-rail input switch MN6, and is controlled synchronously by the I3C input signal; the source of the second rail-to-rail input switch MP5 is connected to the drain of the current source switch MP0, and the current source switch MP0 provides the operating current; the drain of the second rail-to-rail input switch MP5 serves as the second output terminal of the rail-to-rail input pair unit 201, and is connected to the second input terminal of the load module 30.

[0097] The gate of the third rail-to-rail input switch MN7 is connected to the reference signal terminal and is used to be controlled by the reference voltage; the source of the third rail-to-rail input switch MN7 is connected to the source of the first rail-to-rail input switch MN6 and shares the same current path; the drain of the third rail-to-rail input switch MN7 serves as the third output terminal of the rail-to-rail input pair unit 201 and is connected to the third input terminal of the load module 30.

[0098] The gate of the fourth rail-to-rail input switch MP6 is connected to the gate of the third rail-to-rail input switch MN7, and synchronously receives the reference voltage; the source of the fourth rail-to-rail input switch MP6 is connected to the source of the second rail-to-rail input switch MP5, and they share another current path; the drain of the fourth rail-to-rail input switch MP6 serves as the fourth output terminal of the rail-to-rail input pair unit 201, and is connected to the fourth input terminal of the load module 30.

[0099] The rail-to-rail input pair unit 201 is divided into two symmetrical branches: the first and second rail-to-rail input switches MP5 form one group, uniformly responding to the I3C input signal; the third and fourth rail-to-rail input switches MP6 form the other group, uniformly responding to the reference voltage. The two groups of devices are supplied with operating current by the second current replication switch MN4 and the current source switch MP0 of the current source unit, respectively. The devices change their conduction level according to the voltage signal connected to their respective gates, converting the voltage difference between the I3C input signal and the reference voltage into multiple level signals, which are synchronously transmitted to the load module 30 through four output terminals to complete the level comparison function.

[0100] Based on the above description, the gates of the first and second rail-to-rail input switches MP5 can be shorted to synchronously access the same input voltage, and the gates of the third and fourth rail-to-rail input switches MP6 can be shorted to synchronously access the same input voltage, ensuring that the operating states of the devices in the two branches are completely consistent; and the two branches respond independently to the I3C signal and the reference voltage, with clear voltage comparison logic, effectively improving the accuracy of level judgment.

[0101] The rail-to-rail input pair unit 201 has four independent output terminals, which are respectively connected to different input terminals of the load module 30. It can transmit the compared level signals in parallel, and the signal transmission path matching degree is high, which can stably drive the subsequent load module 30 to work.

[0102] Furthermore, the overall circuit of the rail-to-rail input pair unit 201 adopts a symmetrical topology design, which maintains a uniform response characteristic for the rising and falling edges of the I3C input signal. Combined with the front-end dynamic bias circuit, it further ensures that the propagation delay of the two edges is consistent when the signal flips, thus meeting the timing requirements of I3C high-speed communication.

[0103] Reference Figure 2The rail-to-rail input comparator module 20 and load module 30 provided in this embodiment can form a rail-to-rail input comparator. INN is the I3C signal input terminal, and REF is the comparator reference voltage terminal. MN6, MN7, MP5, and MP6 together constitute the rail-to-rail input pair of the comparator. Compared with the traditional single NMOS input pair or single PMOS input pair structure, this embodiment adopts a complementary rail-to-rail input architecture, which can completely cover the full swing input range of the I3C signal from 0V to the power supply voltage. This solves the problem that a single transistor input structure can only recognize narrow voltage ranges, low voltage ranges, or high voltage range signal failures. It can adapt to I3C bus signals with different power supply voltages and different level swings, greatly improving the voltage adaptation range and versatility of the circuit. The circuit operates in three states: steady-state operation, I3C signal high-level to low-level transition, and I3C signal low-level to high-level transition. In steady state, the I3C input signal typically remains high. The dynamic current bias circuit only copies the reference current I1 to the tail current sources MP0 and MN4, allowing the comparator to operate with a very small reference current and extremely low overall static power consumption. When the INN input signal flips from high to low, the coupling capacitor C1 pulls down the gate potential of MP7, causing MP7 to turn on instantaneously and generate an additional jump current. After being copied by the current mirror, this rapidly increases the overall bias current of the comparator. Simultaneously, the feedforward capacitor CF further pulls down the gate potential of MP3, significantly accelerating the comparator output switching speed through the feedforward acceleration mechanism. After the comparator output OUT completes its flip, the reference voltage at the REF terminal is switched synchronously, creating a dynamic threshold hysteresis effect. This effectively suppresses output erroneous switching caused by I3C bus noise. After the signal flip is complete, the corresponding resistor pulls the gate potential of MP7 up to the power supply, automatically turning off MP7, and the circuit returns to a low-power steady state. When the INN input signal flips from low to high, the coupling capacitor C2 raises the gate potential of MN8, causing MN8 to conduct instantaneously and generate a switching current, increasing the comparator's transient operating current. Simultaneously, the feedforward capacitor CF further raises the gate potential of MP3, collaboratively accelerating the comparator output flip and achieving a high-speed, symmetrical response to the bidirectional edges of the I3C signal. This embodiment combines rail-to-rail complementary input, dynamic bias current, capacitor feedforward acceleration, and adaptive reference voltage switching to ensure ultra-low static power consumption and high-speed symmetrical response while maintaining compatibility with I3C input signals across the entire voltage domain, effectively improving the adaptability and reliability of high-speed I3C bus communication.

[0104] In one alternative implementation, refer to Figure 2 The load module 30 includes a first load unit 301 and a second load unit 302; The control terminal of the first load unit 301 is connected to the control terminal of the current source switch MP0. The first input terminal of the first load unit 301 is connected to the power supply terminal VDD. The second input terminal of the first load unit 301 is connected to the drain of the first rail-to-rail input switch MN6. The third input terminal of the first load unit 301 is connected to the drain of the third rail-to-rail input switch MN7. The output terminal of the first load unit 301 is connected to the input terminal of the output shaping module 40. The second input terminal of the first load unit 301 serves as the first input terminal of the load module 30, and the third input terminal of the first load unit 301 serves as the third input terminal of the load module 30. The control terminal of the second load unit 302 is connected to the control terminal of the second current replication switch MN4. The first input terminal of the second load unit 302 is connected to the ground terminal GND. The second input terminal of the second load unit 302 is connected to the drain of the second rail-to-rail input switch MP5. The third input terminal of the second load unit 302 is connected to the drain of the fourth rail-to-rail input switch MP6. The output terminal of the second load unit 302 is connected to the input terminal of the output shaping module 40. The second input terminal of the second load unit 302 serves as the second input terminal of the load module 30, and the third input terminal of the second load unit 302 serves as the fourth input terminal of the load module 30.

[0105] In this embodiment, the load module 30 is composed of a first load unit 301 and a second load unit 302. The two load units respectively receive the comparison output signals of the rail-to-rail input pair unit 201 and are respectively controlled by the corresponding rail-to-rail input switch of the front-end current source unit. Finally, they jointly output the processed level signal to the rear-end output shaping module 40.

[0106] The control terminal of the first load unit 301 is connected to the control terminal of the current source switch MP0, and receives the synchronous control signal from the previous stage current source switch MP0; the first input terminal of the first load unit 301 is connected to the power supply terminal VDD to obtain the working power; the second input terminal of the first load unit 301 serves as the first input terminal of the load module 30 and is connected to the drain of the first rail-to-rail input switch MN6; the third input terminal of the first load unit 301 serves as the third input terminal of the load module 30 and is connected to the drain of the third rail-to-rail input switch MN7; the output terminal of the first load unit 301 is connected to the input terminal of the output shaping module 40 to output the level signal processed in this stage.

[0107] The control terminal of the second load unit 302 is connected to the control terminal of the second current replication switch MN4, and receives the synchronization control signal from the preceding second current replication switch MN4; the first input terminal of the second load unit 302 is connected to the ground terminal GND; the second input terminal of the second load unit 302 serves as the second input terminal of the load module 30 and is connected to the drain of the second rail-to-rail input switch MP6; the third input terminal of the second load unit 302 serves as the fourth input terminal of the load module 30 and is connected to the drain of the second rail-to-rail input switch MP5; the output terminal of the second load unit 302 is also connected to the input terminal of the output shaping module 40, and outputs the processed level signal to the subsequent stage.

[0108] In this embodiment, the load module 30 adopts a dual-load unit differential symmetrical architecture. The first load unit 301 is powered by a power supply and controlled by a current source switch MP0, and is specifically designed to collect two comparison output signals from the first rail-to-rail input switch MN6 and the third rail-to-rail input switch MN7. The second load unit 302 is grounded and controlled by a second current replication switch MN4, and collects two comparison output signals from the second rail-to-rail input switch MP5 and the fourth rail-to-rail input switch MP6.

[0109] Based on this, the first load unit 301 and the second load unit 302 can work synchronously with the change of the front-stage dynamic bias current: when the I3C input signal is in a steady state, the front-stage bias current is small, and the two load units stably pick up the weak comparison signal in a low-power state; when the I3C input signal undergoes a rising / falling edge flip, the front-stage dynamic bias current increases instantaneously, and the current source switch MP0 and the second current replication switch MN4 synchronously regulate the working state of the two load units, so that the load units can quickly respond to the level difference of the rail-to-rail input pair unit 201.

[0110] The first load unit 301 and the second load unit 302 synchronously receive the four rail-to-rail comparison output signals, integrate, amplify and correct the differential level signals, eliminate the weak deviations and fluctuations generated during the comparison process, and finally send the normalized correction level signals in parallel to the output shaping module 40 to complete the signal processing function of the load module 30.

[0111] In this embodiment, the first load unit 301 and the second load unit 302 are respectively matched to the output signals of the four rail-to-rail input switches. The signal pickup and amplification paths of the rising and falling edges of the I3C signal are completely symmetrical, with no structural deviation. This avoids the problem of inconsistent propagation delay caused by the difference in unilateral response of traditional circuits and meets the high-speed timing symmetry requirements of I3C.

[0112] Furthermore, the control timing of the first load unit 301 being bound to the current source switch MP0 and the second load unit 302 being bound to the second current replication switch MN4 can accurately follow the changes in dynamic bias current: maintaining a low-power operating state under steady-state conditions, reducing overall static power consumption; accelerating the operation of signal switching transient synchronization, rapidly amplifying level differences, and improving the transient switching speed of the circuit.

[0113] Furthermore, the load module 30 connects to the output terminals of the four rail-to-rail input switches via the first load unit 301 and the second load unit 302 respectively, to fully acquire the differential comparison information between the I3C input signal and the reference voltage, avoiding signal omissions and information loss, significantly improving the accuracy of level judgment and anti-interference capability, and avoiding misjudgments caused by bus jitter. The first load unit 301 and the second load unit 302 synchronously process and output the corrected level signal in parallel, amplifying the power of the weak comparison signal from the previous stage, enhancing the signal driving capability, and stably driving the subsequent output shaping module 40 to work, avoiding signal attenuation and distortion problems during high-speed I3C signal transmission.

[0114] Optional, refer to Figure 2 The first load unit 301 includes a first switch MP1, a second switch MP2, a third switch MP3 and a fourth switch MP4. The gate of the first switch MP1 is connected to the gate of the second switch MP2, and then connected to the gate of the current source switch MP0; the gate of the third switch MP3 is connected to the gate of the fourth switch MP4, and the gate of the third switch MP3 is shorted to its own drain; the sources of the first switch MP1 and the second switch MP2 are both connected to the power supply terminal VDD. The drain of the first switching transistor MP1 is connected to the source of the fourth switching transistor MP4. The drain of the fourth switching transistor MP4 serves as the output terminal of the first load unit 301 and is connected to the input terminal of the output shaping module 40. The drain of the second switch MP2 is connected to the source of the third switch MP3. After the gate and drain of the third switch MP3 are shorted, they are connected to the I3C signal input terminal INN through the feedforward capacitor CF. The drain of the first switch MP1 is the second input terminal of the load unit and is connected to the drain of the first rail-to-rail input switch MN6. The drain of the second switch MP2 is the third input terminal of the load unit and is connected to the drain of the third rail-to-rail input switch MN7. And / or, the second load unit 302 includes a fifth switch MN0, a sixth switch MN1, a seventh switch MN2 and an eighth switch MN3; After the gate of the seventh switch MN2 is connected to the gate of the eighth switch MN3, it is connected to the gate of the second current replication switch MN4; the gate of the fifth switch MN0 is connected to the gate of the sixth switch MN1. The sources of the seventh switch MN2 and the eighth switch MN3 are connected to the ground terminal GND; the drain of the seventh switch MN2 is connected to the source of the fifth switch MN0, and the drain of the fifth switch MN0 is connected to the I3C signal input terminal INN through the feedforward capacitor CF; the drain of the eighth switch MN3 is connected to the source of the sixth switch MN1; the drain of the sixth switch MN1 serves as the output terminal of the second load unit 302 and is connected to the input terminal of the output shaping module 40. Among them, the source of the fifth switch MN0 is the third input terminal of the load unit and is connected to the drain of the fourth rail-to-rail input switch MP6; the source of the sixth switch MN1 is the fourth input terminal of the load unit and is connected to the drain of the second rail-to-rail input switch MP5.

[0115] In this embodiment, the first load unit 301 is composed of a first switch MP1, a second switch MP2, a third switch MP3, and a fourth switch MP4.

[0116] The gates of the first switch MP1 and the second switch MP2 are interconnected and connected to the gate of the current source switch MP0, so that the first load unit 301 is controlled by the front-end current source switch MP0. The sources of the first switch MP1 and the second switch MP2 are both connected to the power supply terminal VDD.

[0117] The drain of the first switch MP1 serves as the second input terminal of the first load unit 301 and is connected to the drain of the first rail-to-rail input switch MN6. This drain is also connected to the source of the fourth switch MP4. The drain of the fourth switch MP4 forms the output terminal of the first load unit 301 and is connected to the input terminal of the output shaping module 40.

[0118] The drain of the second switch MP2 serves as the third input terminal of the first load unit 301 and is connected to the drain of the third rail-to-rail input switch MN7. At the same time, this drain is connected to the source of the third switch MP3.

[0119] The gate of the third switch MP3 is interconnected with the gate of the fourth switch MP4, and the gate of the third switch MP3 is shorted to its own drain, forming a diode connection structure; the shorted node between the gate and drain of the third switch MP3 is connected to the I3C signal input terminal INN through the feedforward capacitor CF.

[0120] The second load unit 302 is composed of the fifth switch MN0, the sixth switch MN1, the seventh switch MN2, and the eighth switch MN3.

[0121] After the gate of the seventh switch MN2 is interconnected with the gate of the eighth switch MN3, they are connected together to the gate of the second current replication switch MN4, so that the second load unit 302 is controlled by the preceding second current replication switch MN4; the gate of the fifth switch MN0 is interconnected with the gate of the sixth switch MN1 to form a synchronous conduction structure.

[0122] The sources of the seventh switch MN2 and the eighth switch MN3 are both grounded; the drain of the seventh switch MN2 is connected to the source of the fifth switch MN0, and the source of the fifth switch MN0 serves as the third input terminal of the second load unit 302, which is connected to the drain of the fourth rail-to-rail input switch MP6; the drain of the fifth switch MN0 is connected to the I3C signal input terminal INN through the feedforward capacitor CF.

[0123] The drain of the eighth switch MN3 is connected to the source of the sixth switch MN1. The source of the sixth switch MN1 serves as the fourth input terminal of the second load unit 302 and is connected to the drain of the second rail-to-rail input switch MP5. The drain of the sixth switch MN1 serves as the output terminal of the second load unit 302 and is connected to the input terminal of the output shaping module 40.

[0124] In this embodiment, the load module 30 adopts a symmetrical PMOS type first load unit 301 and NMOS type second load unit 302 architecture, respectively receiving four comparison output signals from the rail-to-rail input pair unit 201, and combining the edge coupling characteristics of the feedforward capacitor CF and the front-stage dynamic bias control signal to complete signal amplification and correction.

[0125] The first load unit 301 is uniformly controlled by the gate signal of the current source switch MP0. The first switch MP1, the second switch MP2, the third switch MP3, and the fourth switch MP4 are synchronously turned on or off, respectively acquiring the level states of the first rail-to-rail input switch MN6 and the third rail-to-rail input switch MN7. The third switch MP3 adopts a drain-gate short-circuit structure, which has the functions of potential clamping and current limiting. Moreover, its short-circuit node is coupled to the I3C input signal transition edge in real time through the feedforward capacitor CF, which can quickly change the potential of this stage at the moment the I3C signal flips, accelerating the output flip of the first load unit 301. The fourth switch MP4 follows the gate potential synchronously and outputs a corrected level comparison signal.

[0126] The second load unit 302 is uniformly controlled by the gate signal of the second current replication switch MN4. The fifth switch MN0, the sixth switch MN1, the seventh switch MN2, and the eighth switch MN3 are synchronously turned on or off, respectively cooperating to acquire the level signals of the fourth rail-to-rail input switch MP6 and the second rail-to-rail input switch MP5. The gates of the fifth switch MN0 and the sixth switch MN1 are interconnected, and their operating states are synchronized and unified. When the I3C input signal changes, the feedforward capacitor CF couples the edge signal to the drain of the fifth switch MN0, rapidly disturbing the lower branch potential, thereby realizing the synchronous accelerated switching of the output of the second load unit 302.

[0127] Under steady-state conditions, the control signals of the front and rear stages are stable, the operating state of each switch is constant, and the load unit outputs a stable comparison level in a low-loss state. During the signal flip-over transient, relying on the AC coupling characteristics of the feedforward capacitor CF, the flip-over of the upper and lower load units is accelerated in both directions synchronously, amplifying and correcting the weak comparison difference of the front stage. Finally, the two load units synchronously output a regular and accurate level signal to the output shaping module 40.

[0128] Based on the above description, the first load unit 301 provided in this application embodiment is a PMOS upper load structure and the second load unit 302 is an NMOS lower load structure. The circuit topology, control logic, and feedforward acceleration path are completely symmetrical, and the response speed to the rising and falling edges of the I3C input signal is consistent. This completely solves the inherent hysteresis asymmetry problem of the traditional Schmitt trigger architecture, ensures bidirectional propagation delay matching of the comparator, and meets the high-speed timing requirements of I3C.

[0129] Furthermore, the feedforward capacitor CF acts simultaneously on the first load unit 301 and the second load unit 302, directly coupling the edge disturbance potential at the instant of I3C signal transition, skipping the level-by-level transmission delay, triggering the state flip of the load unit switch in advance, significantly shortening the output rise and fall delay, and avoiding the timing deviation problem of high-speed I3C communication.

[0130] The third switch MP3 in the first load unit 301 adopts a drain-gate short-circuit diode connection, which can stabilize the branch potential, suppress the current deviation caused by power supply and process fluctuations, and limit the branch current to avoid overcurrent operation of the device. In conjunction with the rail-to-rail input pair unit 201, it can effectively suppress the output false jump caused by long bus interference and electromagnetic jitter, and avoid misjudgment of START / STOP protocol signals.

[0131] Furthermore, the first load unit 301 and the second load unit 302 are controlled by the front-end current source switch MP0 and the second current replication switch MN4, respectively, and can completely follow the dynamic bias current changes: the bias current is small when the signal is in steady state, and the power consumption of the load unit is extremely low; the bias current increases instantaneously when the signal flips, and the driving capability of the load unit is simultaneously improved, quickly completing level amplification and flipping, achieving both low power consumption and high-speed response.

[0132] In one alternative implementation, refer to Figure 2 The output shaping module 40 includes a cascaded inverter structure; The cascaded inverter structure is used to perform edge shaping on the corrected level comparison signal and output a standard digital logic signal that is compatible with the I3C protocol.

[0133] In this embodiment, the corrected level comparison signal output by the load module 30 is fed into a cascaded inverter structure. Utilizing the threshold switching characteristics of multi-stage inverters, the edges of the input signal are progressively trimmed. For level signals with slight jitter, smooth edges, and insufficiently steep waveforms, the cascaded inverter can gradually filter out signal noise, sharpen the rising and falling edges, and standardize the waveform shape. This converts the pre-processed analog level transition signal into a digital logic signal with steep edges, standard amplitude, and clear logic, making it conform to the level and timing specifications of I3C bus communication.

[0134] It should be understood that the cascaded inverter structure possesses excellent waveform shaping capabilities, capable of smoothing the gradual transition waveform of the preceding circuit output into steep digital edges, eliminating timing ambiguity caused by gradual signal changes, and improving signal integrity. The multi-stage inverters progressively filter levels, effectively shielding small voltage fluctuations and high-frequency noise remaining from the preceding stage, preventing erroneous output level flips caused by I3C bus interference, and effectively preventing misjudgment of START / STOP signals, thus meeting the timing jitter requirements of the I3C protocol. Cascaded inverters can stably output standard high and low logic levels, unifying the signal voltage domain without the need for additional level conversion circuits, achieving matching with downstream digital logic circuits, and simplifying the overall circuit architecture.

[0135] Optionally, the cascaded inverter structure includes an odd number of inverters connected in series. The first inverter in an odd number of inverters connected in series is connected to the output of the load module 30, and the last inverter in an odd number of inverters connected in series outputs a standard digital logic signal adapted to the I3C protocol.

[0136] For example, refer to Figure 2 The cascaded inverter structure consists of three inverters connected in series.

[0137] In this embodiment, the cascaded inverter structure consists of an odd number of inverters connected in series. Multiple inverters are arranged in series step-by-step according to the signal flow direction, forming a regular multi-stage signal shaping path. The input terminal of the first inverter in the series structure is connected to the output terminal of the load module 30, used to receive the corrected level comparison signal output by the load module 30; the tail inverter in the series structure serves as the final output terminal, used to output a standard digital logic signal adapted to the I3C protocol.

[0138] The correction level signal output by the load module 30 is fed into the first inverter of an odd-stage series inverter. The waveform is continuously shaped through stage-by-stage inversion and level threshold reshaping. Because the overall structure uses an odd-stage series inverter, after multiple stages of inversion, the logic level output by the final tail inverter remains consistent with the original logic level of the input shaping module, preventing logic inversion errors. During the stage-by-stage transmission, each inverter sharpens the edges and filters noise from the input waveform based on its own inversion threshold, gradually correcting residual waveform variations, minor jitter, and transitional distortions from previous stages. Finally, the tail inverter outputs a standard digital signal with steep edges, accurate logic, and a regular waveform.

[0139] In one alternative implementation, when the I3C input signal flips from low to high, the switchable reference voltage output from the reference signal terminal REF switches from a second voltage to a first voltage. When the I3C input signal flips from high level to low level, the switchable reference voltage output from the reference signal terminal REF switches from the first voltage to the second voltage. The second voltage is greater than the first voltage.

[0140] In this embodiment, the reference signal terminal REF can output two reference voltages with different amplitudes, defined as a first voltage and a second voltage, respectively. The second voltage is greater than the first voltage, and the voltage switching is completed synchronously with the level flip of the I3C input signal.

[0141] When the I3C input signal flips from low to high, the reference voltage output from the reference signal terminal REF switches from the second voltage to the first voltage. When the I3C input signal flips from high to low, the reference voltage output from the reference signal terminal REF switches from the first voltage to the second voltage.

[0142] The rail-to-rail input comparison module 20 compares the I3C input signal with the reference voltage of the reference signal terminal REF. The reference voltage switches synchronously with the edge of the input signal, which is equivalent to configuring different decision thresholds for the rising and falling edges of the signal. Together with the dynamic bias current and the feedforward capacitor CF, the level determination is completed.

[0143] Based on the above description, different threshold voltages are used for comparison of the rising and falling edges of the I3C signal. This can adapt to the level change characteristics of the two flip states, making the level judgment logic more consistent with the actual signal state and avoiding the judgment deviation caused by a single threshold.

[0144] By combining different switching thresholds for the REF signal at the reference signal terminal, it can effectively shield the small signal fluctuations caused by long-distance bus transmission and electromagnetic interference, avoid frequent signal jumps around a single threshold, avoid misjudgment of the I3C protocol START and STOP signals, and meet the protocol's constraints on timing jitter.

[0145] In a specific example, refer to Figure 3 The diagram shows a circuit schematic of a switchable reference voltage generation module.

[0146] The switchable reference voltage generation module is a 2-to-1 multiplexer (MUX); its input signals are two fixed voltage sources and the output OUT of the output shaping module.

[0147] The first voltage source has a voltage of 0.6V (corresponding to the first voltage), and the second voltage source has a voltage of 0.8V (corresponding to the second voltage). REF serves as the reference signal terminal, outputting the selected reference voltage and sending it to the second comparison terminal of the rail-to-rail input comparison module.

[0148] In one specific embodiment, refer to Figure 2This application discloses a comparison detection circuit for the I3C protocol, the structure of which is shown in the figure. INN is the I3C signal input terminal, and REF is the reference voltage terminal; MN6, MN7, MP5, and MP6 form a rail-to-rail input pair; MP0 and MN4 are the comparator tail current sources; MP1-MP4 and MN0-MN3 form the comparator output load. The circuit operates in three states: steady-state operation, I3C signal high-level to low-level transition, and I3C signal low-level to high-level transition. In steady-state operation, the I3C input signal is usually kept at a high level, and the dynamic current bias circuit only copies the reference current I1 to MP0 and MN4. The comparator operates with a very small reference current, resulting in extremely low overall static power consumption. When the INN input signal flips from high to low, the first coupling capacitor C1 pulls down the gate potential of MP7, causing MP7 to turn on instantaneously and generate an additional jump current. After being replicated by the current mirror, this rapidly increases the overall bias current of the comparator. Simultaneously, the feedforward capacitor CF further pulls down the gate potential of MP3, significantly accelerating the comparator output switching speed through the feedforward acceleration mechanism. After the comparator output OUT completes its flip, the reference voltage at the REF terminal is switched synchronously, forming a dynamic threshold hysteresis effect. This effectively suppresses output erroneous switching caused by I3C bus noise. After the signal flip is complete, the corresponding resistor pulls the gate potential of MP7 up to the power supply, MP7 automatically turns off, and the circuit returns to a low-power steady state. When the INN input signal flips from low to high, the coupling capacitor C2 raises the gate potential of MN8, causing MN8 to turn on instantaneously and generate a jump current, increasing the transient operating current of the comparator. At the same time, the feedforward capacitor CF further raises the gate potential of MP3, working together to accelerate the comparator output switching and achieving a high-speed, symmetrical response to the bidirectional edges of the I3C signal. This embodiment combines dynamic bias current, capacitor feedforward acceleration, and adaptive reference voltage switching to significantly improve the bidirectional switching speed and anti-interference capability of I3C signals while ensuring ultra-low static power consumption, thus meeting the timing and reliability requirements of high-speed I3C bus communication.

[0149] Based on the above description, refer to Figure 2 The rail-to-rail input comparison module 20 and the load module 30 provided in this application embodiment together constitute a rail-to-rail input comparator. The comparison detection circuit for the I3C protocol in this application embodiment can be specifically adapted to the mainstream 2V low-voltage operating scenario of the I3C protocol. The I3C protocol can achieve a balance between transmission rate and power consumption under 2V low-voltage conditions. Therefore, this application embodiment is specifically optimized for this low-voltage operating environment.

[0150] In this embodiment, INN is the I3C signal input terminal, and REF is the reference voltage terminal. MN6, MN7, MP5, and MP6 form a rail-to-rail input pair. Compared with the traditional single NMOS or single PMOS input structure, this embodiment adopts a complementary rail-to-rail input architecture, which can fully cover the full swing input range of the I3C signal from 0V to 2V under 2V low-voltage power supply. This solves the problems of limited detection range, failure of critical point identification, and degradation of response performance of single input structure under low-voltage conditions, and effectively ensures the integrity and accuracy of low-voltage I3C signal detection.

[0151] MP0 and MN4 are the tail current sources, and MP1-MP4 and MN0-MN3 constitute the output load. Together with the dynamic current bias circuit and the multiplexer MUX for dynamically switching the reference voltage, they achieve low-power, high-speed, and highly interference-resistant I3C signal comparison and detection functions. The circuit operates in three states: steady state, high-level to low-level transition, and low-level to high-level transition. In steady state, the I3C input signal is usually high. The dynamic current bias circuit only copies the reference current I1 to the tail current sources MP0 and MN4, allowing the comparator to operate with minimal current and extremely low static power consumption, meeting the low-power design requirements of low-voltage I3C systems. When INN transitions from high to low, the coupling capacitor C1 pulls down the gate potential of MP7, causing MP7 to instantaneously conduct and generate a jumping current. After being copied by the current mirror, this quickly increases the comparator bias current. Simultaneously, the feedforward capacitor CF further pulls down the gate potential of MP3, accelerating the output switching speed through the feedforward acceleration mechanism and improving the switching lag problem in low-voltage circuits. After the output flip is complete, the MUX synchronously switches the reference voltage at the REF terminal to form a dynamic hysteresis threshold, effectively suppressing erroneous flips caused by bus noise. Subsequently, the resistor pulls the gate potential of MP7 up to the power supply, MP7 is turned off, and the circuit returns to a low-power steady state. When INN flips from low to high, the coupling capacitor C2 raises the gate potential of MN8, causing MN8 to conduct momentarily and generate a transient current. This, together with the feedforward capacitor CF, raises the gate potential of MP3, accelerating the output flip and achieving a high-speed, symmetrical response on both the rising and falling edges of the I3C signal. This embodiment is designed for I3C 2V low-voltage scenarios, integrating rail-to-rail full voltage detection, dynamic bias energy saving, capacitor feedforward acceleration, and adaptive reference voltage switching technology. It effectively solves the shortcomings of traditional comparators in low-voltage I3C applications, such as high power consumption, slow speed, poor adaptability, and susceptibility to erroneous flips, achieving a balance between speed, power consumption, and reliability in low-voltage I3C communication.

[0152] This application also provides a chip including the comparison and detection circuit for the I3C protocol described above.

[0153] In this embodiment, the chip integrates the I3C protocol comparison and detection circuit of the present invention, which is mainly used in scenarios such as I3C bus master / slave control chips, low-power SoC, automotive electronics and industrial control, to achieve high-speed, low-power reception and decision of I3C bus signals.

[0154] Based on the description of the comparison detection circuit for the I3C protocol, this chip exhibits extremely low static power consumption when the I3C input signal is in steady state. When the I3C input signal flips, it achieves high-speed response through dynamic bias and feedforward acceleration, meeting the dual requirements of low power consumption and high-speed communication. Furthermore, it eliminates the need for additional level conversion or filtering circuits; a single chip handles signal reception and processing, simplifying peripheral design and reducing PCB layout costs. Rail-to-rail input adapts to signals of different amplitudes, flexibly accommodating various I3C peripherals and rate levels, demonstrating strong versatility.

[0155] This application also provides an electronic device including the above-described chip.

[0156] In this embodiment, the electronic device is equipped with a chip integrating an I3C protocol comparison and detection circuit. It can be used in consumer electronics such as mobile phones, smart wearables, and tablets, interfacing with various I3C interface sensors and touch components; it can also be applied to smart home devices, IoT nodes, etc., achieving long-term stable operation thanks to its low power consumption; simultaneously, it is compatible with automotive modules, industrial control terminals, and other scenarios, completing bus communication in complex electromagnetic environments; and it can also be integrated into multi-protocol master control systems to achieve high-speed interconnection of peripherals.

[0157] This electronic device significantly reduces overall power consumption, with low steady-state power consumption, effectively extending the battery life of battery-powered products. Furthermore, it eliminates the need for additional external components such as level converters and filters, simplifying hardware design.

[0158] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a cycle, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such cycle, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the cycle, method, article, or apparatus that includes said element.

[0159] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A comparison detection circuit for the I3C protocol, characterized in that, The comparison and detection circuit for the I3C protocol includes: a power supply terminal, a current bias module, a rail-to-rail input comparison module, a load module, a feedforward capacitor, and an output shaping module. The power supply terminal is used to supply power to the current bias module, the rail-to-rail input comparison module and the load module, wherein the power supply terminal is the internal power supply of the I3C protocol chip; The input terminal of the current bias module is connected to the I3C signal input terminal, and the output terminal of the current bias module is connected to the current source unit of the rail-to-rail input comparison module. The current bias module is used to provide a dynamically adjustable bias current to the current source unit of the rail-to-rail input comparison module according to the I3C input signal provided by the I3C signal input terminal. The dynamically adjustable bias current increases when the level of the I3C input signal flips. The first comparison terminal of the rail-to-rail input comparison module is connected to the I3C signal input terminal, the second comparison terminal of the rail-to-rail input comparison module is connected to the reference signal terminal, and the output terminal of the rail-to-rail input comparison module is connected to the load module; wherein, the reference signal terminal is used to output a switchable reference voltage according to the I3C input signal; The rail-to-rail input comparison module is used to provide a level comparison signal to the load module based on the dynamically adjustable bias current, the I3C input signal, and the reference voltage output from the reference signal terminal. The load module is connected to the I3C signal input terminal through the feedforward capacitor, and the output terminal of the load module is connected to the input terminal of the output shaping module. The load module is used to amplify and correct the level comparison signal according to the transition edge of the level comparison signal and the I3C input signal to obtain the corrected level comparison signal. The output shaping module is used to perform edge shaping on the corrected level comparison signal and output a standard digital logic signal adapted to the I3C protocol.

2. The comparison and detection circuit for the I3C protocol according to claim 1, characterized in that, The current biasing module includes: Constant current source, coupling capacitor unit, bias unit, and current replication unit; The power supply terminal is connected to the constant current source, the coupling capacitor unit, the bias unit, and the current replication unit; it is used to supply power to the constant current source, the coupling capacitor unit, the bias unit, and the current replication unit. The output terminal of the constant current source is connected to the current replication unit and is used to provide a reference current to the current replication unit; The input terminal of the coupling capacitor unit is connected to the I3C signal input terminal, and the output terminal of the coupling capacitor unit is connected to the bias unit; the coupling capacitor unit is used to turn on the bias unit when the I3C input signal provided by the I3C signal input terminal changes. The output terminal of the bias unit is connected to the current replication unit; the bias unit is used to generate a switching current when the I3C input signal changes, and output the switching current to the current replication unit. The current replication unit is used to generate the dynamically adjustable bias current based on the reference current, or the reference current and the switching current, and output the dynamically adjustable bias current to the current source unit of the rail-to-rail input comparison module.

3. The comparison and detection circuit for the I3C protocol according to claim 2, characterized in that, The coupling capacitor unit includes a first coupling capacitor and a second coupling capacitor; the bias unit includes a first bias switch and a second bias switch. The first plate of the first coupling capacitor and the first plate of the second coupling capacitor are both connected to the I3C signal input terminal. The second plate of the first coupling capacitor is connected to the gate of the first bias switch. The source of the first bias switch is connected to the power supply terminal. The drain of the first bias switch is connected to the first input terminal of the current mirror replication unit. The second plate of the second coupling capacitor is connected to the gate of the second bias switch transistor, the source of the second bias switch transistor is grounded, and the drain of the second bias switch transistor is connected to the second input terminal of the current mirror replication unit; the output terminal of the constant current source is connected to the first input terminal of the current mirror replication unit. The output of the current mirror copying unit is connected to the current source unit of the rail-to-rail input comparison module, and is used to mirror and copy the dynamically adjustable bias current and output it to the current source unit of the rail-to-rail input comparison module.

4. The comparison and detection circuit for the I3C protocol according to claim 3, characterized in that, When the I3C input signal is in a steady state, both the first bias switch and the second bias switch are turned off. The current mirror replication unit replicates the reference current output by the constant current source and outputs it to the current source unit of the rail-to-rail input comparison module. When the I3C input signal flips from high level to low level, the I3C input signal is coupled through the first coupling capacitor, turns on the first bias switch, and generates a first switching current. The current mirror copying unit mirrors the superimposed reference current and the first switching current to generate the dynamically adjustable bias current and outputs it to the current source unit of the rail-to-rail input comparison module. When the I3C input signal flips from low level to high level, the I3C input signal is coupled through the second coupling capacitor, turns on the second bias switch, and generates a second switching current; The current mirror replication unit mirrors the superimposed reference current and the second switching current to generate the dynamically adjustable bias current and outputs it to the current source unit of the rail-to-rail input comparison module.

5. The comparison and detection circuit for the I3C protocol according to claim 4, characterized in that, The current bias module also includes a first resistor, a second resistor, a third resistor, and a fourth resistor; The first end of the first resistor is connected to the second end of the second coupling capacitor and the control terminal of the second bias switch, and the second end of the first resistor is grounded; the first resistor is used to pull down the gate potential of the second bias switch when the I3C input signal is in a steady state, so that the second bias switch is turned off. The first end of the second resistor is connected to the second end of the first coupling capacitor and the control terminal of the first bias switch, and the second end of the second resistor is connected to the power supply terminal; the second resistor is used to pull up the gate potential of the first bias switch when the I3C input signal is in a steady state, so that the first bias switch is turned off. The first end of the third resistor is connected to the drain of the first bias switch, and the second end of the third resistor is connected to the output of the constant current source; the third resistor is used to reset the first bias switch to the off state after the I3C input signal flips from high level to low level. The first end of the fourth resistor is connected to the current mirror replication unit, and the second end of the fourth resistor is connected to the drain of the second bias switch. The fourth resistor is used to reset the second bias switch to the off state after the I3C input signal flips from low level to high level.

6. The comparison and detection circuit for the I3C protocol according to claim 4, characterized in that, The current mirror replication unit includes a current mirror and a first current replication switch transistor; The current mirror includes a first paired transistor and a second paired transistor; the source of the first paired transistor and the source of the second paired transistor are both connected to the power supply terminal, the gates of the first paired transistor and the second paired transistor are connected, the drain of the first paired transistor is shorted to the gate of the first paired transistor, the drain of the first paired transistor is connected to the drain of the second bias switch transistor, the drain of the second paired transistor is connected to the drain and gate of the first current replication switch transistor, and the source of the first current replication switch transistor is grounded. Wherein, the drain of the first paired transistor is the first input terminal of the current mirror replication unit, the drain of the second paired transistor is the second input terminal of the current mirror replication unit, and the drain and gate of the first current replication switching transistor are shorted to form the output terminal of the current mirror replication unit.

7. The comparison detection circuit for the I3C protocol according to claim 6, characterized in that, The rail-to-rail input comparison module includes a current source unit and a rail-to-rail input pair unit; the current source unit includes a second current replication switch and a current source switch. The gate of the second current replication switch is connected to the gate of the first current replication switch, the source of the second current replication switch is grounded, the drain of the second current replication switch is connected to the first terminal of the rail-to-rail input pair unit, and the gate of the second current replication switch is also connected to the first control terminal of the load module. The source of the current source switch is connected to the power supply terminal and connected to the drain of the first current replication switch through the second pairing transistor. The drain of the current source switch is connected to the second terminal of the rail-to-rail input pair unit. The gate of the current source switch is connected to the second control terminal of the load module. The first comparison terminal of the rail-to-rail input pair unit is connected to the I3C signal input terminal, the second comparison terminal of the rail-to-rail input pair unit is connected to the reference signal terminal, and the multiple output terminals of the rail-to-rail input pair unit are all connected to the corresponding input terminals of the load module. The dynamically adjustable bias current output by the first current replication switch controls the second current replication switch and the current source switch to be turned on or off, so as to realize the synchronous increase or decrease of the current in the rail-to-rail input comparison module and the dynamically adjustable bias current. The first current-replicating switch and the second current-replicating switch form a current mirror structure.

8. The comparison detection circuit for the I3C protocol according to claim 7, characterized in that, The rail-to-rail input pair unit includes a first rail-to-rail input switch, a second rail-to-rail input switch, a third rail-to-rail input switch, and a fourth rail-to-rail input switch. The gate of the first rail-to-rail input switch is connected to the I3C signal input terminal, the source of the first rail-to-rail input switch is connected to the source of the fourth rail-to-rail input switch and the drain of the second current replication switch, and the drain of the first rail-to-rail input switch is the first output terminal of the rail-to-rail input pair unit and connected to the first input terminal of the load module. The gate of the second rail-to-rail input switch is connected to the gate of the first rail-to-rail input switch, the source of the second rail-to-rail input switch is connected to the drain of the current source switch, and the drain of the second rail-to-rail input switch is the second output terminal of the rail-to-rail input pair unit, which is connected to the second input terminal of the load module. The gate of the third rail-to-rail input switch is connected to the reference signal terminal, the source of the third rail-to-rail input switch is connected to the source of the first rail-to-rail input switch, and the drain of the third rail-to-rail input switch is the third output terminal of the rail-to-rail input pair unit, which is connected to the third input terminal of the load module. The gate of the fourth rail-to-rail input switch is connected to the gate of the third rail-to-rail input switch, the source of the fourth rail-to-rail input switch is connected to the source of the second rail-to-rail input switch, and the drain of the fourth rail-to-rail input switch is the fourth output terminal of the rail-to-rail input pair unit, which is connected to the fourth input terminal of the load module.

9. The comparison and detection circuit for the I3C protocol according to claim 8, characterized in that, The load module includes a first load unit and a second load unit; The control terminal of the first load unit is connected to the control terminal of the current source switch, the first input terminal of the first load unit is connected to the power supply terminal, the second input terminal of the first load unit is connected to the drain of the first rail-to-rail input switch, the third input terminal of the first load unit is connected to the drain of the third rail-to-rail input switch, and the output terminal of the first load unit is connected to the input terminal of the output shaping module; wherein, the second input terminal of the first load unit serves as the first input terminal of the load module, and the third input terminal of the first load unit serves as the third input terminal of the load module; The control terminal of the second load unit is connected to the control terminal of the second current replication switch. The first input terminal of the second load unit is connected to the ground terminal. The second input terminal of the second load unit is connected to the drain of the second rail-to-rail input switch. The third input terminal of the second load unit is connected to the drain of the fourth rail-to-rail input switch. The output terminal of the second load unit is connected to the input terminal of the output shaping module. The second input terminal of the second load unit serves as the second input terminal of the load module, and the third input terminal of the second load unit serves as the fourth input terminal of the load module.

10. The comparison detection circuit for the I3C protocol according to claim 9, characterized in that, The first load unit includes a first switch, a second switch, a third switch, and a fourth switch; The gate of the first switch is connected to the gate of the second switch, and then connected to the gate of the current source switch; the gate of the third switch is connected to the gate of the fourth switch, and the gate of the third switch is shorted to its own drain; the sources of the first switch and the second switch are both connected to the power supply terminal. The drain of the first switching transistor is connected to the source of the fourth switching transistor, and the drain of the fourth switching transistor serves as the output terminal of the first load unit and is connected to the input terminal of the output shaping module. The drain of the second switch is connected to the source of the third switch. The gate and drain of the third switch are shorted together and then connected to the I3C signal input terminal through the feedforward capacitor. Wherein, the drain of the first switching transistor is the second input terminal of the load unit and is connected to the drain of the first rail-to-rail input switching transistor, and the drain of the second switching transistor is the third input terminal of the load unit and is connected to the drain of the third rail-to-rail input switching transistor. And / or, the second load unit includes a fifth switch, a sixth switch, a seventh switch, and an eighth switch; The gate of the seventh switch is connected to the gate of the eighth switch, and then connected to the gate of the second current replication switch; the gate of the fifth switch is connected to the gate of the sixth switch. The sources of the seventh and eighth switching transistors are connected to the ground terminal; the drain of the seventh switching transistor is connected to the source of the fifth switching transistor, the drain of the fifth switching transistor is connected to the I3C signal input terminal through the feedforward capacitor, and the drain of the eighth switching transistor is connected to the source of the sixth switching transistor; the drain of the sixth switching transistor serves as the output terminal of the second load unit and is connected to the input terminal of the output shaping module. The source of the fifth switch is the third input terminal of the load unit and is connected to the drain of the fourth rail-to-rail input switch; the source of the sixth switch is the fourth input terminal of the load unit and is connected to the drain of the second rail-to-rail input switch.

11. The comparison detection circuit for the I3C protocol according to any one of claims 1-10, characterized in that, The output shaping module includes a cascaded inverter structure; The cascaded inverter structure is used to perform edge shaping on the corrected level comparison signal and output a standard digital logic signal adapted to the I3C protocol.

12. The comparison detection circuit for the I3C protocol according to claim 11, characterized in that, The cascaded inverter structure includes an odd number of inverters connected in series. The first inverter in the odd number of inverters connected in series is connected to the output terminal of the load module, and the last inverter in the odd number of inverters connected in series outputs a standard digital logic signal adapted to the I3C protocol.

13. The comparison detection circuit for the I3C protocol according to any one of claims 1-10, characterized in that: When the I3C input signal flips from low level to high level, the switchable reference voltage output by the reference signal terminal switches from the second voltage to the first voltage; When the I3C input signal flips from high level to low level, the switchable reference voltage output by the reference signal terminal switches from the first voltage to the second voltage. Wherein, the second voltage is greater than the first voltage.

14. A chip, characterized in that, Includes the comparison detection circuit for the I3C protocol as described in any one of claims 1 to 13.

15. An electronic device, characterized in that, Includes the chip described in claim 14.

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