IGBT turn-on gate drive continuous regulation circuit and control method

Abstract

The application discloses an IGBT opening gate drive continuous regulation and control circuit and a control method, and belongs to the technical field of power semiconductor drive. The front-end detection comparison unit in the drive circuit is used for receiving detection signals and reference signals and outputting primary analog control quantities; the current mirror transmission unit is used for mirror copying and interstage transmission of the primary analog control quantities; the intermediate regulation and control unit is used for adjusting the opening drive capability under the action of a first control signal; and the output shaping unit is used for dynamically shaping a rear-stage control signal under the action of a second control signal and a second dynamic shaping network, and outputting an opening drive voltage to drive the IGBT gate. In the application, the second resistance and the second capacitor in the second dynamic shaping network act on an output shaping node, and the feedback path in which the resistance R3 is located influences the conversion state of the front-end control quantity, so that the continuous regulation and control of the IGBT gate voltage and the power side voltage and current response are realized, and the opening speed, overshoot suppression and electromagnetic interference control can be considered.

Description

Technical Field

[0001] This invention relates to a continuous control circuit and method for IGBT gate drive, belonging to the field of power semiconductor drive technology. Background Technology

[0002] Insulated-gate bipolar transistors (IGBTs) are widely used in motor drives, new energy power generation, rail transportation, power electronic converters, and high-voltage high-power switching power supplies because they combine the gate drive characteristics of MOS and bipolar conductivity. During the turn-on process, the gate drive method of an IGBT directly affects the device's turn-on speed, voltage and current overshoot, transient losses, and electromagnetic interference level.

[0003] In existing technologies, common IGBT driving methods typically employ fixed gate resistors or simple segmented driving structures. While these solutions are structurally simple, their driving capability is often a pre-set fixed value. When bus voltage, load current, device junction temperature, and parasitic parameters change, fixed driving parameters often struggle to balance multiple performance indicators. On one hand, excessively strong driving capability, while beneficial for shortening turn-on time and reducing some turn-on losses, can easily lead to significant voltage overshoot, current overshoot, and higher electromagnetic interference. On the other hand, insufficiently weak driving capability, while suppressing oscillations and overshoot, may result in decreased turn-on speed, increased losses, and negatively impact system efficiency and thermal stability.

[0004] To address the shortcomings of fixed-drive methods, some existing solutions have introduced adaptive drive methods such as staged gate drive, discrete level switching, or feedback triggering. However, these solutions typically rely on specific threshold judgments, discrete timing switching, or predefined segmented logic, resulting in significantly discrete control behavior that is highly sensitive to detection thresholds, delay parameters, and device parasitic parameters. When actual operating conditions deviate from design conditions, segment boundaries and stage durations are prone to deviation, leading to decreased gate waveform control accuracy and making it difficult to achieve continuous, smooth, and multi-degree-of-freedom adjustment of the IGBT turn-on process.

[0005] Furthermore, in actual driving processes, the gate drive waveform is not only affected by the output drive parameters, but also by factors such as changes in the detection signal, inter-stage transmission characteristics, and the load state of the subsequent stage. If the drive circuit's ability to coordinate and adjust these factors is insufficient, the adaptability of the turn-on waveform may decrease when the bus voltage, load current, or device parameters change, thereby affecting the overall control effect of voltage and current change rate and electromagnetic interference level during the turn-on process.

[0006] Therefore, there is an urgent need to provide a new IGBT gate drive continuous control circuit and control method, which can perform multi-level continuous control and dynamic shaping of the gate drive during the turn-on process under different operating conditions, thereby improving the overall balance performance between turn-on loss, overshoot, oscillation and electromagnetic interference. Summary of the Invention

[0007] The purpose of this invention is to solve the problems of fixed gate resistor drive or discrete segmented drive in the prior art, which make it difficult to control turn-on loss, turn-on stress and electromagnetic interference. Therefore, this invention provides an IGBT turn-on gate drive continuous control circuit and control method, which has multi-level analog control and dynamic shaping functions.

[0008] The objective of this invention is achieved through the following technical solution:

[0009] An IGBT gate-on driving continuous control circuit includes: a front-end detection and comparison unit, a current mirror transmission unit, an intermediate control unit, and an output shaping unit; the input terminal of the current mirror transmission unit is connected to the output terminal of the front-end detection and comparison unit, the input terminal of the intermediate control unit is connected to the output terminal of the current mirror transmission unit, and the input terminal of the output shaping unit is connected to the output terminal of the intermediate control unit.

[0010] The front-end detection and comparison unit is used to receive a detection signal and a reference signal, compare the detection signal and the reference signal, and output a primary analog control quantity;

[0011] The current mirror transmission unit is used to mirror and transmit the primary analog control quantity output by the front-end detection and comparison unit to form an intermediate control signal.

[0012] The intermediate control unit is used to adjust the turn-on drive capability corresponding to the intermediate control signal under the action of the first control signal, and output the subsequent control signal.

[0013] The output shaping unit is used to dynamically shape the subsequent control signal and output a turn-on driving voltage under the action of the second control signal to drive the gate of the IGBT.

[0014] Preferably, the front-end detection and comparison unit includes: a bias enable branch, a comparison input branch, a first dynamic compensation and control quantity conversion branch, and a front-end mirror output branch;

[0015] A bias enable branch is used to provide operating bias current for the front-end detection and comparison unit;

[0016] The comparison input branch is used to compare the detection signal VP with the reference signal VREF. Based on the difference between the detection signal VP and the reference signal VREF, a primary analog control quantity representing the driving requirement is generated in the internal node of the front-end detection comparison unit.

[0017] The first dynamic compensation and control quantity conversion branch is used to smooth the primary analog control quantity formed by comparing the detection signal VP with the reference signal VREF, and then convert the smoothed control quantity into a voltage or current signal suitable for transmission to the current mirror transmission unit via the front-end mirror output branch.

[0018] The front-end mirror output branch is used to receive the smoothed and converted control quantity output from the first dynamic compensation and control quantity conversion branch, and output it to the current mirror transmission unit.

[0019] Preferably, the bias enable branch includes: PMOS transistors MP1, MP2, MP3 and MP4; the comparator input branch includes: PMOS transistors MP5 and MP6 and NMOS transistors MN1 and MN2; the first dynamic compensation and control quantity conversion branch includes: a first resistor R1, a first capacitor C1, NMOS transistors MN3 and MN4 and resistors R2 and R3; the front-end mirror output branch includes: PMOS transistors MP7 and MP8;

[0020] In this configuration, the sources of PMOS transistors MP1 and MP3, as well as the source of PMOS transistor MP7, are all connected to the power supply terminal VDD. The gate of PMOS transistor MP1 receives the first bias control signal VPVBO1, the gate of PMOS transistor MP2 receives the second bias control signal VPVBO2, the gate of PMOS transistor MP1 is connected to the gate of PMOS transistor MP3, the drain of PMOS transistor MP1 is connected to the source of PMOS transistor MP2, the gate of PMOS transistor MP2 is connected to the gate of PMOS transistor MP4, and the drain of PMOS transistor MP3 is connected to the source of PMOS transistor MP4.

[0021] The drain of PMOS transistor MP2 is connected to the source of PMOS transistors MP5 and MP6, respectively. The gate of PMOS transistor MP5 receives the detection signal VP, and the gate of PMOS transistor MP6 receives the reference signal VREF. The drain of PMOS transistor MP5 is connected to the drain of NMOS transistor MN1, the gate of NMOS transistor MN1, and the gate of NMOS transistor MN2, respectively. The sources of NMOS transistors MN1 and MN2 are grounded. The drain of NMOS transistor MN2 is connected to the drain of PMOS transistor MP6, one end of the first resistor R1, and the gate of NMOS transistor MN3, respectively. The source of NMOS transistor MN3 is grounded. The other end of the first resistor R1 is connected to one end of the first capacitor C1, and the other end of the first capacitor C1 is connected to the drain of NMOS transistor MN3, the gate of NMOS transistor MN4, and the drain of PMOS transistor MP4, respectively. The source of NMOS transistor MN4 is connected to the feedback node where the detection signal VP is located, and is connected to one end of resistor R3 to form a closed-loop feedback path. The other end of resistor R3 is grounded. The drain of NMOS transistor MN4 is connected to one end of resistor R2. The other end of resistor R2 is connected to the drain and gate of PMOS transistor MP8, respectively. The source of PMOS transistor MP8 is connected to the drain and gate of PMOS transistor MP7, respectively.

[0022] Preferably, the current mirror transmission unit includes: multi-stage current mirror branches and intermediate transmission branches;

[0023] A multi-stage current mirror branch is used to mirror and copy the control quantity output by the front-end detection and comparison unit, and form a mirror current.

[0024] An intermediate transmission branch is used to receive the mirror current and form an intermediate control signal, and then transmit the intermediate control signal to the intermediate control unit.

[0025] Preferably, the multi-stage current mirror branch includes PMOS transistors MP9 and MP10; the intermediate transmission branch includes NMOS transistors MN5 and MN6.

[0026] In this configuration, the source of PMOS transistor MP9 is connected to the power supply terminal VDD, the gate of PMOS transistor MP9 is connected to the gate of PMOS transistor MP7, the drain of PMOS transistor MP9 is connected to the source of PMOS transistor MP10, the gate of PMOS transistor MP10 is connected to the gate of PMOS transistor MP8, the drain of PMOS transistor MP10 is connected to the drain and gate of NMOS transistor MN5, the source of NMOS transistor MN5 is connected to the drain and gate of NMOS transistor MN6, the source of NMOS transistor MN6 is grounded, and the gate nodes of NMOS transistor MN5 and NMOS transistor MN6 serve as intermediate control signal output nodes of the current mirror transmission unit.

[0027] Preferably, the intermediate control unit includes: an active load branch, a main pull-down branch, a first control branch, and a first feedback resistor R4;

[0028] An active load branch is used to form a pull-up active load between the power supply terminal VDD and the first feedback resistor R4, and to form a subsequent control signal based on the pull-down current change of the main pull-down branch.

[0029] The main pull-down branch is used to receive the intermediate control signal generated by the current mirror transmission unit and generate a pull-down current corresponding to the intermediate control signal.

[0030] The first control branch is used to adjust the conduction capability of the main pull-down branch under the action of the first control signal VCTR1, thereby changing the rate of change and the turn-on drive strength of the subsequent control signal formed by the active load branch according to the change of the pull-down current.

[0031] The first feedback resistor R4 is used to feed back the change in pull-down current of the main pull-down branch to the active load branch, so as to improve the dynamic response stability of the intermediate control unit.

[0032] Preferably, the active load branch includes PMOS transistors MP11 and MP12; the main pull-down branch includes NMOS transistors MN7 and MN8; and the first control branch includes NMOS transistor MN9.

[0033] In this configuration, the gate of NMOS transistor MN5 is connected to the gate of NMOS transistor MN7 and the drain of NMOS transistor MN9, the gate of NMOS transistor MN6 is connected to the gate of NMOS transistor MN8, the source of NMOS transistor MN8 is grounded, the drain of NMOS transistor MN8 is connected to the source of NMOS transistor MN7, the gate of NMOS transistor MN9 receives the first control signal VCTR1, and the source of NMOS transistor MN9 is grounded; the drain of NMOS transistor MN7 is connected to one end of the first feedback resistor R4, the other end of the first feedback resistor R4 is connected to the drain and gate of PMOS transistor MP12, the source of PMOS transistor MP12 is connected to the drain and gate of PMOS transistor MP11, and the source of PMOS transistor MP11 is connected to the power supply terminal VDD.

[0034] Preferably, the output shaping unit includes: an output stage PMOS branch, an output execution transistor, a second control branch, and a second dynamic shaping network;

[0035] The output stage PMOS branch is used to provide pull-up drive current to the output shaping node VRC according to the subsequent control signal.

[0036] The output execution transistor is used to output an enable drive voltage to the output terminal VOUT according to the potential change of the output shaping node VRC;

[0037] The second control branch is used to adjust the pull-down capability of the output shaping node VRC under the action of the second control signal VCTR2;

[0038] The second dynamic shaping network is used together with the second control branch to adjust the dynamic response of the output shaping node VRC and control the slope of the turn-on drive voltage VOUT to reduce voltage overshoot, current overshoot and electromagnetic interference during IGBT turn-on.

[0039] Preferably, the output stage PMOS branch includes PMOS transistors MP13 and MP14; the output execution transistor includes NMOS transistor MNLD1; the second control branch includes NMOS transistor MN10; and the second dynamic shaping network includes a second resistor R5 and a second capacitor C2.

[0040] In this configuration, the source of PMOS transistor MP13 is connected to the power supply terminal VDD and the drain of NMOS transistor MNLD1, the gate of PMOS transistor MP13 is connected to the gate of PMOS transistor MP11, the drain of PMOS transistor MP13 is connected to the source of PMOS transistor MP14, the gate of PMOS transistor MP14 is connected to the gate of PMOS transistor MP12, the drain of PMOS transistor MP14 is connected to the gate of NMOS transistor MNLD1, the drain of NMOS transistor MN10, and one end of the second resistor R5, and the connection node of the drain of PMOS transistor MP14, the gate of NMOS transistor MNLD1, the drain of NMOS transistor MN10, and one end of the second resistor R5 is the output shaping node VRC, the other end of the second resistor R5 is connected to one end of the second capacitor C2, the other end of the second capacitor C2 is grounded, the source of NMOS transistor MN10 is grounded, the gate of NMOS transistor MN10 receives the second control signal VCTR2, and the source of NMOS transistor MNLD1 is connected to the output terminal VOUT.

[0041] A control method based on an IGBT gate drive continuous control circuit includes the following steps:

[0042] S1. Input the detection signal VP and the reference signal VREF to the front-end detection and comparison unit, and establish the working state of the bias enable branch.

[0043] S2. The front-end detection and comparison unit compares the detection signal VP with the reference signal VREF to generate a primary analog control quantity;

[0044] S3. The primary analog control quantity is dynamically smoothed using the first dynamic compensation and control quantity conversion branch, and the dynamically smoothed control quantity is converted into a voltage or current signal suitable for subsequent transmission.

[0045] S4. The current mirror transmission unit is used to mirror and transmit the control quantity after dynamic smoothing and conversion to form an intermediate control signal.

[0046] S5. The intermediate control unit adjusts the turn-on drive capability corresponding to the intermediate control signal under the action of the first control signal VCTR1 to form the subsequent control signal.

[0047] S6. The output shaping unit dynamically shapes the subsequent control signal under the action of the second control signal VCTR2 and the second dynamic shaping network, and outputs the turn-on drive voltage VOUT to drive the IGBT gate.

[0048] In step S5, the conduction capability of the main pull-down branch in the intermediate control unit is changed by adjusting the first control signal VCTR1, thereby changing the establishment speed and amplitude of the subsequent control signal; in step S6, the dynamic response of the output shaping node VRC is adjusted by adjusting the second control signal VCTR2 and the time constant formed by the second resistor R5 and the second capacitor C2 in the second dynamic shaping network, so as to control the slope of the change of the turn-on drive voltage VOUT.

[0049] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0050] 1. The present invention adopts a multi-stage analog control structure of front-end detection and comparison, intermediate current mirror transmission, intermediate regulation and output shaping, which can realize continuous adjustment of gate drive during IGBT turn-on process, rather than relying solely on fixed resistance value or discrete segmented switching.

[0051] 2. This invention achieves dual dynamic shaping of the front-end comparison control quantity and the rear-end drive output quantity by setting up a first dynamic compensation and control quantity conversion branch at the front end and a second dynamic shaping network at the output end, which helps to reduce abrupt changes in control quantity and improve the smoothness of output waveform;

[0052] 3. The present invention sets up independent first and second control signals, which can adjust the intermediate stage driving capability and the output stage waveform characteristics respectively, thereby improving the adaptability to different working conditions;

[0053] 4. This invention achieves inter-stage replication and isolation of control quantities through a multi-stage current mirror transmission structure, which helps to reduce the impact of front-end coupling on the comparison accuracy and system stability of the front end;

[0054] 5. This invention is beneficial for continuously and adjustable control of the gate drive waveform during the IGBT turn-on process under different bus voltage, load current, parasitic parameters and junction temperature conditions, thereby reducing turn-on losses, suppressing voltage and current overshoot stress and reducing electromagnetic interference.

[0055] 6. The present invention can perform hierarchical coordinated adjustment of the gate drive during the IGBT turn-on process. Through a multi-stage structure including front-end detection and comparison, intermediate current mirror transmission, intermediate regulation and output shaping, it can realize continuous adjustment and dynamic shaping of the turn-on drive waveform.

[0056] 7. This invention dynamically shapes the output shaping node VRC through the second resistor R5 and the second capacitor C2 in the second dynamic shaping network, and influences the front-end control quantity conversion state and subsequent drive strength through the feedback path where resistor R3 is located. This allows the second capacitor C2, the second resistor R5, and the resistor R3 to adjust the IGBT gate voltage and power side voltage and current response from three aspects: the dynamic establishment process of the output shaping node, the output damping state, and the front-end feedback adjustment strength. This achieves continuous control of the IGBT gate voltage and power side voltage and current response, which is beneficial for balancing turn-on speed, overshoot suppression, and electromagnetic interference control. Attached Figure Description

[0057] Figure 1 This is a schematic diagram of the structure of an IGBT gate-on drive continuous control circuit according to an embodiment of the present invention.

[0058] Figure 2 The waveform diagram shows how the second capacitor C2 affects the gate voltage of the IGBT in the IGBT gate drive continuous control circuit of the present invention.

[0059] Figure 3 The waveform diagram shows how the second resistor R5 affects the gate voltage of the IGBT in the IGBT gate drive continuous control circuit of the present invention.

[0060] Figure 4 The waveform diagram shows the effect of resistor R3 on the IGBT gate voltage in the IGBT turn-on gate drive continuous control circuit of this invention.

[0061] Figure 5 The waveform diagram shows the effect of the second capacitor C2 on the collector-emitter voltage and collector current of the IGBT in the IGBT gate drive continuous control circuit of the present invention.

[0062] Figure 6 The waveform diagram shows the effect of the second resistor R5 in the IGBT gate drive continuous control circuit of the present invention on the collector-emitter voltage and collector current of the IGBT.

[0063] Figure 7 The waveform diagram shows how resistor R3 affects the collector-emitter voltage and collector current of the IGBT in the IGBT gate drive continuous control circuit of this invention.

[0064] In the figure, the reference numerals are as follows: 01 is the front-end detection and comparison unit; 011 is the bias enable branch; 012 is the comparison input branch; 013 is the first dynamic compensation and control quantity conversion branch; 014 is the front-end mirror output branch; 02 is the current mirror transmission unit; 021 is the multi-stage current mirror branch; 022 is the intermediate transmission branch; 03 is the intermediate control unit; 031 is the active load branch; 032 is the main pull-down branch; 033 is the first control branch; 04 is the output shaping unit; 041 is the output stage PMOS branch; 042 is the output execution transistor; 043 is the second control branch; 044 is the second dynamic shaping network. Detailed Implementation

[0065] The present invention will be further described in detail below with reference to the accompanying drawings: This embodiment is implemented under the premise of the technical solution of the present invention, and detailed implementation methods are given, but the protection scope of the present invention is not limited to the following embodiments.

[0066] Example 1: Circuit Structure Example

[0067] like Figure 1 As shown, the IGBT gate drive continuous control circuit involved in this embodiment includes: a front-end detection and comparison unit 01, a current mirror transmission unit 02, an intermediate control unit 03, and an output shaping unit 04.

[0068] The front-end detection and comparison unit 01 is used to receive a detection signal and a reference signal, compare the detection signal and the reference signal, and output a primary analog control quantity. The front-end detection and comparison unit 01 includes a bias enable branch 011, a comparison input branch 012, a first dynamic compensation and control quantity conversion branch 013, and a front-end mirror output branch 014. The first dynamic compensation and control quantity conversion branch 013 includes a first resistor R1, a first capacitor C1, NMOS transistors MN3 and MN4, and resistors R2 and R3, which are used to smooth the primary analog control quantity formed after comparing the detection signal and the reference signal, and then convert the smoothed control quantity into a voltage or current signal suitable for subsequent transmission.

[0069] The current mirror transmission unit 02 is connected to the front-end detection and comparison unit 01 and is used to mirror and transmit the primary analog control quantity between stages to form an intermediate control signal. By setting the current mirror transmission unit 02, the control quantity can be transmitted to the next stage without significantly disrupting the operating point of the front-end detection and comparison unit 01, thereby improving the inter-stage isolation capability and control stability.

[0070] The intermediate control unit 03 is connected to the current mirror transmission unit 02 and is used to adjust the driving capability corresponding to the intermediate control signal under the action of the first control signal to form the subsequent control signal. The intermediate control unit 03 includes an active load branch 031, a main pull-down branch 032, a first control branch 033, and a first feedback resistor R4; by setting the first control signal, the conduction capability and control quantity establishment speed of this stage can be changed.

[0071] The output shaping unit 04 is connected to the intermediate control unit 03 and is used to dynamically shape the subsequent control signal and output a turn-on drive voltage under the action of the second control signal and the second dynamic shaping network 044 to drive the gate of the IGBT to complete the turn-on process. The output shaping unit 04 includes an output stage PMOS branch 041, an output execution transistor 042, a second control branch 043, and a second dynamic shaping network 044. The second dynamic shaping network 044 includes a second resistor R5 and a second capacitor C2, which are used to control the dynamic response of the output shaping node VRC and the slope of the output turn-on drive voltage.

[0072] The front-end detection and comparison unit 01 includes: a bias enable branch 011 composed of PMOS transistors MP1, MP2, MP3, and MP4. The bias enable branch 011 includes a first PMOS branch controlled by a first bias control signal and a second PMOS branch controlled by a second bias control signal, used to provide bias current to the front-end detection and comparison unit 01 and the subsequent branches. It also includes a comparison input branch 012 composed of PMOS transistors MP5 and MP6 and NMOS transistors MN1 and MN2, and a first dynamic compensation and control quantity conversion branch 013 composed of a first resistor R1, a first capacitor C1, NMOS transistors MN3 and MN4, and resistors R2 and R3. Specifically, PMOS transistors MP1 and MP2 receive the first bias control signal VPVBO1 and the second bias control signal VPVBO2, respectively; PMOS transistor MP5 receives the detection signal VP, and PMOS transistor MP6 receives the reference signal VREF. The front-end detection and comparison unit 01 utilizes a differential comparison structure composed of PMOS and NMOS transistors. By comparing the difference between VP and VREF, it converts the difference between the detected signal VP and the reference signal VREF into the primary analog control quantity. The front-end detection and comparison unit 01 generates a primary analog control quantity representing the drive requirement within its internal nodes. This control quantity is further smoothed by a first dynamic compensation and control quantity conversion branch 013, composed of a first resistor R1 and a first capacitor C1, to avoid overly steep transient changes in the comparison output. MN3, MN4, and R2, R3 are used to convert the smoothed control quantity into a voltage or current signal suitable for subsequent transmission.

[0073] In this circuit, the source of NMOS transistor MN4 is connected to the feedback node where the detection signal VP is located, and grounded through resistor R3. This introduces the node where the detection signal VP is located into the first dynamic compensation and control quantity conversion branch 013, forming a closed-loop feedback path. This allows the front-end detection and comparison unit 01 to continuously adjust the subsequent control quantity according to the change of the detection signal VP. This closed-loop feedback path ensures that the output of the first dynamic compensation and control quantity conversion branch 013 is affected by both the comparison result of VP and VREF and the state of the feedback node where the detection signal VP is located, thereby improving the stability of the front-end control quantity.

[0074] The current mirror transmission unit 02 includes a multi-stage current mirror branch 021 composed of PMOS transistors MP9 and MP10, and an intermediate transmission branch 022 composed of NMOS transistors MN5 and MN6. The multi-stage current mirror branch 021 is used to mirror the control quantity output by the front-end detection and comparison unit 01 and form a mirror current; the intermediate transmission branch 022 is used to receive the mirror current and form an intermediate control signal, and transmit the intermediate control signal to the intermediate control unit 03.

[0075] The intermediate control unit 03 includes: an active load branch 031, a main pull-down branch 032, a first control branch 033, and a first feedback resistor R4. The active load branch 031 includes PMOS transistors MP11 and MP12, the main pull-down branch 032 includes NMOS transistors MN7 and MN8, and the first control branch 033 includes an NMOS transistor MN9. The first control branch 033 receives a first control signal VCTR1, used to adjust the conduction capability of the main pull-down branch 032, thereby changing the rate of change and turn-on drive strength of the subsequent control signal. The first feedback resistor R4 provides local feedback to improve the stability and dynamic response characteristics of this stage.

[0076] The output shaping unit 04 includes: an output stage PMOS branch 041, an output execution transistor 042, a second control branch 043, and a second dynamic shaping network 044. The output stage PMOS branch 041 includes PMOS transistors MP13 and MP14; the output execution transistor 042 includes an NMOS transistor MNLD1; the second control branch 043 includes an NMOS transistor MN10; and the second dynamic shaping network 044 includes a second resistor R5 and a second capacitor C2. The second control branch 043 receives a second control signal VCTR2 and, together with the second dynamic shaping network 044, acts on the output shaping node VRC to adjust the rising or plateau characteristics of the output turn-on drive voltage VOUT.

[0077] In this embodiment, the second resistor R5 and the second capacitor C2 in the second dynamic shaping network 044 directly act on the output shaping node VRC to change the dynamic setup process and damping state of the output shaping node VRC; resistor R3 is located between the feedback node where the detection signal VP is located and the ground terminal, and is used to affect the feedback state and front-end control quantity conversion process of the first dynamic compensation and control quantity conversion branch 013. The parameter changes of the second capacitor C2, the second resistor R5, and the resistor R3 are reflected in the IGBT gate voltage and power side response waveforms through the output shaping node VRC, the output execution transistor 042, and the output terminal VOUT.

[0078] In this embodiment, VOUT can be directly connected to the gate terminal of the IGBT, or connected to the gate terminal of the IGBT through external circuits such as an isolation driver stage and a gate current limiting network.

[0079] The first control signal VCTR1 and the second control signal VCTR2 are independently set analog control signals. They act on the intermediate regulation unit 03 and the output shaping unit 04 respectively to achieve hierarchical coordinated regulation of the gate drive during the IGBT turn-on process.

[0080] The detection signal VP is a voltage signal characterizing the IGBT's turn-on process operating state. It can be generated by an external sampling network and may correspond to the IGBT's collector-emitter voltage sampling signal, current sampling signal, gate voltage feedback signal, or other detection signals characterizing the turn-on process state. In this embodiment, the voltage signal is any one or a combination of the following: IGBT collector voltage related signal, collector-emitter voltage related signal, collector current sampling related signal, emitter current sampling related signal, gate voltage related signal, and desaturation detection related signal.

[0081] Example 2: Working Process Example

[0082] This embodiment illustrates a typical working process of the above circuit during the IGBT turn-on process.

[0083] In the initial state, the bias enable control terminals VPVBO1 and VPVBO2 turn on the bias enable branch 011, and the front-end detection and comparison unit 01, the current mirror transmission unit 02, the intermediate control unit 03, and the output shaping unit 04 establish their respective static operating points. At this time, the output terminal VOUT is at the initial drive level.

[0084] When the IGBT needs to enter the turn-on process, the detection signal VP, which characterizes the IGBT state, changes relative to the reference signal VREF. The comparison input branch 012 in the front-end detection and comparison unit 01 compares VP and VREF and internally generates the corresponding primary analog control quantity. Due to the inclusion of the first dynamic compensation and control quantity conversion branch 013, composed of the first resistor R1 and the first capacitor C1, this primary analog control quantity does not abruptly change in an ideal step manner, but rather transitions smoothly within a predetermined time constant. This reduces the impact on subsequent stages caused by sudden changes in the preceding control signal.

[0085] The smoothed control signal is transmitted to the intermediate control unit 03 via the front-end mirror output branch 014 and the current mirror transmission unit 02. Under the action of the first control signal VCTR1, the intermediate control unit 03 further adjusts the intermediate control signal transmitted to this stage. Specifically, VCTR1 can change the conduction level of MN9, thereby changing the overall conduction capability of the main pull-down path where MN7 and MN8 are located, so that the subsequent control signals output by this stage have different setup speeds and drive strengths.

[0086] After the subsequent control signal enters the output shaping unit 04, it drives the output terminal VOUT through the output stage PMOS branch 041 and the output execution transistor 042. Simultaneously, it adjusts the rate of change of the output shaping node VRC through the second resistor R5 and the second capacitor C2 in the second dynamic shaping network 044. The second control signal VCTR2 can further change the conduction state of MN10, thus jointly determining the dynamic response characteristics of the VRC node with the second resistor R5 and the second capacitor C2. Finally, MNLD1 converts the shaped control result into the output drive voltage VOUT. Since this output voltage is not a simple fixed-slope change, but is simultaneously affected by the comparison result of the preceding stage, the intermediate stage control capability, and the output stage shaping network, a smoother, more continuous, and adjustable gate drive waveform can be formed during the IGBT turn-on process.

[0087] In the above process, the second capacitor C2 mainly affects the dynamic establishment and smoothness of the output shaping node VRC, the second resistor R5 mainly affects the damping characteristics of the dynamic shaping branch related to the output shaping node VRC, and the resistor R3 mainly affects the conversion state of the front-end control quantity by detecting the feedback node where the signal VP is located. The three together change the establishment process of the output VOUT, causing the IGBT gate voltage, power side collector-emitter voltage, and collector current waveforms to exhibit different trends.

[0088] When actual operating conditions change, such as increased bus voltage, increased load current, changes in device junction temperature, or changes in parasitic parameters, the intermediate stage drive capability and output stage shaping can be altered by adjusting VCTR1 and VCTR2, thereby keeping the VOUT waveform within a range more suitable for the current operating conditions. This allows for more flexible trade-off control of turn-on speed, overshoot suppression, and electromagnetic interference under different operating conditions.

[0089] In other embodiments, the detection signal VP can also be selected as a voltage or current feedback quantity that better reflects the transient characteristics of IGBT turn-on. The reference signal VREF and the first control signal VCTR1 and the second control signal VCTR2 can be set according to the target turn-on slope, the allowable overshoot amplitude and the desired turn-on loss level to further optimize the gate drive waveform during the turn-on process.

[0090] Example 3: Control Method Example

[0091] This embodiment provides a control method based on the above-described IGBT gate drive continuous control circuit, including the following steps:

[0092] Step 1: Establish operating bias. By enabling the bias control terminals VPVBO1 and VPVBO2, the front-end detection and comparison unit 01 and all subsequent units are brought into normal operating state, forming a static operating point.

[0093] Step two: Acquire the detection signal VP, which characterizes the operating state of the IGBT, and input the reference signal VREF to the front-end detection and comparison unit 01. This reference signal can be a fixed reference voltage or a reference signal that is adjusted according to changes in operating conditions.

[0094] Step three: The front-end detection and comparison unit 01 compares the detection signal VP with the reference signal VREF to form a primary analog control quantity. This control quantity reflects the deviation information of the current IGBT state relative to the target state.

[0095] Step four: The primary analog control quantity is smoothed using the first dynamic compensation and control quantity conversion branch 013 to avoid excessive current or voltage jumps caused by the control quantity during inter-stage transmission.

[0096] Step 5: The smoothed control quantity is mirrored and transmitted between stages using the current mirror transmission unit 02 to form an intermediate control signal.

[0097] Step six: Adjust the driving capability of the intermediate control unit 03 by setting the first control signal VCTR1, so that the intermediate control signal can obtain a suitable change speed and driving amplitude before entering the output stage.

[0098] Step 7: By setting the second control signal VCTR2 and combining it with the second resistor R5 and the second capacitor C2 in the second dynamic shaping network 044, the output shaping node VRC is shaped and controlled, and then the output execution transistor 042 outputs the target drive voltage VOUT. Among them, the second capacitor C2 is used to adjust the dynamic establishment process of the output shaping node VRC, the second resistor R5 is used to adjust the damping state of the dynamic shaping branch corresponding to the output shaping node VRC, and the resistor R3 is used to adjust the front-end control quantity conversion state by detecting the feedback node where the signal VP is located, so that the output terminal VOUT forms different turn-on drive waveforms, and further adjusts the change process of the collector-emitter voltage and collector current on the IGBT power side.

[0099] Step 8: Apply the driving voltage VOUT to the IGBT gate to achieve continuous control of the IGBT turn-on process.

[0100] In this embodiment, VCTR1 and VCTR2 can be generated by an external controller or by an on-chip adaptive adjustment module. Depending on the application scenario, the gate waveform of the IGBT can be adjusted with multiple degrees of freedom by changing the magnitude, timing, or variation pattern of VCTR1 and VCTR2, so as to take into account multiple indicators such as turn-on loss, overshoot, voltage oscillation, and electromagnetic interference.

[0101] Example 4: Driving Waveform Modulation Example

[0102] In this embodiment, combined with Figures 2 to 7 The regulation mechanism of the gate drive waveform and power side response waveform during the turn-on process of this invention will be further explained.

[0103] Figures 2 to 4 This is used to represent the influence of the second capacitor C2, the second resistor R5, and the resistor R3 on the IGBT gate voltage. Figure 2 This represents the waveform showing how the second capacitor C2 affects the IGBT gate voltage. Figure 3 This represents the waveform showing how the second resistor R5 affects the IGBT gate voltage. Figure 4 This represents the waveform showing the effect of resistor R3 on the IGBT gate voltage. The IGBT gate voltage is the actual gate drive voltage formed after the output terminal VOUT is applied to the IGBT gate.

[0104] like Figure 2As shown, with the parameters of the second resistor R5 and resistor R3 kept at their corresponding settings, the change in the value of the second capacitor C2 will affect the IGBT gate voltage waveform. Specifically, when the second capacitor C2 gradually decreases along the direction marked in the figure, the dynamic establishment process of the output shaping node VRC changes. After the output execution transistor 042 acts on the output terminal VOUT, the overall establishment process of the IGBT gate voltage tends to be smoother, and the Miller plateau-related stage and the process of approaching the target drive voltage after the plateau are correspondingly delayed. Therefore, the second capacitor C2 is mainly used to adjust the overall dynamic smoothness of the IGBT gate voltage.

[0105] like Figure 3 As shown, with the parameters of the second capacitor C2 and resistor R3 kept at their corresponding settings, the change in the value of the second resistor R5 affects the IGBT gate voltage waveform. Specifically, as the second resistor R5 gradually increases along the direction indicated in the figure, the damping effect of the second dynamic shaping network 044 is enhanced, making the changes in the output shaping node VRC and the IGBT gate voltage near the threshold, near the Miller plateau, and in the rising phase after the plateau more gradual. Therefore, the second resistor R5 is mainly used to adjust the response position and slope of the IGBT gate voltage within the main switching range.

[0106] like Figure 4 As shown, with the parameters of the second capacitor C2 and the second resistor R5 kept at their corresponding settings, the change in the value of resistor R3 affects the IGBT gate voltage waveform. Specifically, when resistor R3 gradually increases along the direction indicated in the figure, the state of the feedback node where the detection signal VP is located and the transition state of the front-end control quantity change, causing the establishment process of the subsequent control quantity transmitted to the intermediate control unit 03 and the output shaping unit 04 to slow down, thereby delaying and smoothing out the later stage rise of the IGBT gate voltage. Therefore, resistor R3 is mainly used to adjust the front-end feedback state, the subsequent drive strength, and the output shaping response speed.

[0107] Depend on Figures 2 to 4 It can be seen that the second capacitor C2, the second resistor R5, and the resistor R3 can all affect the IGBT gate voltage waveform, but their effects have different focuses: Figure 2 This mainly reflects the influence of the second capacitor C2 on the overall gate voltage establishment process and the degree of dynamic smoothness; Figure 3 This mainly reflects the damping effect of the second resistor R5 on the transition process near the threshold, near the Miller plateau, and after the plateau; Figure 4 This mainly reflects the regulating effect of resistor R3 on the front-end feedback state, the driving strength of the subsequent stage, and the output shaping response speed.

[0108] During the Miller plateau phase, the output shaping unit 04 adjusts the output shaping node VRC via the second control signal VCTR2 and the second resistor R5 and second capacitor C2 in the second dynamic shaping network 044. This prevents the output VOUT from exhibiting a simple fixed plateau near the plateau, instead forming a controlled plateau holding, gradual rise, or smooth transition. By adjusting the waveform in this phase, the rate of decrease of the IGBT collector-emitter voltage and the establishment process of the collector current can be further influenced, thereby improving voltage overshoot, current overshoot, and oscillation performance.

[0109] In the later stage after the plateau, once the IGBT has essentially established its dominant pass channel, the output shaping unit 04 continues to regulate the rising trajectory of VOUT, ensuring the gate voltage smoothly approaches the target drive potential. By appropriately setting the second resistor R5, the second capacitor C2, and VCTR2, excessively rapid rises at the output in the later stage after the plateau can be avoided, thereby reducing unnecessary high-frequency disturbances caused by excessive drive in the later stage.

[0110] Figures 5 to 7 This is used to represent the influence of the second capacitor C2, the second resistor R5, and the resistor R3 on the collector-emitter voltage and collector current on the power side of the IGBT. Among them, Figure 5 This represents the waveform showing how the second capacitor C2 affects the collector-emitter voltage and collector current of the IGBT. Figure 6 This indicates the waveforms showing how the second resistor R5 affects the IGBT collector-emitter voltage and collector current. Figure 7 This represents the waveforms showing how resistor R3 affects the IGBT collector-emitter voltage and collector current.

[0111] like Figure 5 As shown, with the parameters of the second resistors R5 and R3 kept at their corresponding settings, the change in the value of the second capacitor C2 will affect the collector-emitter voltage and collector current waveforms on the IGBT power side. Specifically, as the second capacitor C2 gradually decreases along the direction indicated in the figure, the IGBT collector-emitter voltage drop process shifts later and becomes smoother, with a smaller voltage slope; simultaneously, the IGBT collector current build-up process also shifts later and the current slope decreases. Therefore, the second capacitor C2 mainly affects the overall time unfolding and smoothness of the power side response.

[0112] like Figure 6As shown, with the parameters of the second capacitor C2 and resistor R3 kept at their corresponding settings, the change in the value of the second resistor R5 will affect the collector-emitter voltage and collector current waveforms on the IGBT power side. Specifically, as the second resistor R5 gradually increases along the direction indicated in the figure, the damping effect of the second dynamic shaping network 044 is enhanced, reducing the slope of the collector-emitter voltage drop and the slope of the collector current rise within the main switching range of the IGBT turn-on. Therefore, the second resistor R5 is mainly used to adjust the voltage and current change rates within the main switching range on the power side.

[0113] like Figure 7 As shown, with the parameters of the second capacitor C2 and the second resistor R5 kept at their corresponding settings, the change in the value of resistor R3 will affect the collector-emitter voltage and collector current waveforms on the IGBT power side. Specifically, as resistor R3 gradually increases along the direction indicated in the figure, the front-end feedback state and the subsequent drive strength change, slowing down the establishment process of the output shaping node VRC and the output terminal VOUT, thus making the overall collector-emitter voltage drop process and collector current establishment process smoother. Therefore, resistor R3 is mainly used to adjust the front-end feedback state and the subsequent drive strength, which on the power side is mainly reflected in changes in the overall establishment speed of voltage and current response and the drive strength.

[0114] Depend on Figures 5 to 7 It can be seen that the second capacitor C2, the second resistor R5, and the resistor R3 can all affect the rate of change of voltage and current on the power side of the IGBT, but their mechanisms of action are different: Figure 5 This mainly reflects the adjustment of the overall response time and overall smoothness of the power side by the second capacitor C2; Figure 6 It mainly reflects the regulation of the voltage and current change rates in the main switch section on the power side by the second resistor R5; Figure 7 It mainly reflects the adjustment of the front-end feedback status, the driving strength of the subsequent stage, and the overall set-up speed of the power side by resistor R3.

[0115] Furthermore, Figure 2 and Figure 5 Correspondingly, this is used to explain the combined effect of the second capacitor C2 on the IGBT gate voltage and power-side response; Figure 3 and Figure 6 Correspondingly, this is used to illustrate the combined effect of the second resistor R5 on the IGBT gate voltage and power-side response; Figure 4 and Figure 7 Correspondingly, this is used to explain the combined effect of resistor R3 on the IGBT gate voltage and power-side response.

[0116] Because the gate voltage first rises to near the threshold voltage during IGBT turn-on, followed by the collector current establishing up, and causing a drop in the collector-emitter voltage during the Miller plateau phase, the power-side waveform is not completely synchronized with the gate voltage. Instead, it exhibits a dynamic process where the collector current establishes up first, followed by a drop in the collector-emitter voltage. The second capacitor C2, the second resistor R5, and the resistor R3 affect the power-side waveform through front-end feedback, inter-stage mirror transmission, intermediate regulation, and output shaping, all of which influence the IGBT gate voltage establishment process and further affect the power-side collector-emitter voltage drop process and the collector current establishment process.

[0117] In this embodiment, Figures 2 to 4 The gate drive waveform shown may include at least the following stages:

[0118] The first stage is the initial setup stage, during which the output VOUT starts to rise from the initial potential.

[0119] The second stage is the threshold transition stage, where the gate voltage approaches or reaches the threshold voltage Vth, and the driving capability begins to affect the establishment of the dominant pass channel.

[0120] The third stage is the Miller platform-related stage, where the rate of change of the gate drive waveform determines the power-side voltage and current trajectory.

[0121] The fourth stage is the post-platform approximation stage, where the output VOUT continues to rise and gradually approaches the target driving potential.

[0122] The transitions between the aforementioned stages are not strictly discrete, but rather a continuous transition achieved through the combined effects of front-end dynamic compensation, intermediate drive adjustment, and output shaping.

[0123] It should be noted that, Figures 2 to 7 The waveforms shown are merely illustrative, used to illustrate that the turn-on drive waveform and power-side response waveform of this invention can change accordingly with variations in the first control signal VCTR1, the second control signal VCTR2, the parameters of the first dynamic compensation and control quantity conversion branch 013, and the parameters of the second dynamic shaping network 044. They are not intended to limit the specific waveform shape, slope value, or stage duration of this invention. Under different IGBT device models, different bus voltages, different load currents, and different parasitic parameters, the specific shape of the waveform can be adjusted accordingly. As long as continuous adjustment of the gate drive waveform during the turn-on process can be achieved through multi-level analog control and dynamic shaping, it should fall within the protection scope of this invention.

[0124] Example 5: Application Example

[0125] The IGBT turn-on gate drive continuous control circuit provided by this invention can be applied to power electronic devices that require fine control of the IGBT turn-on process, such as inverters, DC / DC converters, rectifiers, motor drivers, new energy storage conversion systems, rail transit traction converters, and industrial power supplies.

[0126] In practical applications, the detection signal VP can be provided by a current sampling resistor, a voltage divider network, a desaturation detection branch, or other detection modules; the reference signal VREF can be preset according to the target turn-on characteristics; VCTR1 and VCTR2 can be generated by a digital controller via digital-to-analog conversion, or by an analog adaptive adjustment circuit. By integrating the driving circuit of this invention into a dedicated driving chip, the system integration and control consistency can be further improved.

[0127] In summary, this invention achieves continuous control and dynamic shaping of the gate drive during the IGBT turn-on process through the multi-level synergistic action of the front-end detection and comparison unit 01, the current mirror transmission unit 02, the intermediate control unit 03, and the output shaping unit 04. This scheme can flexibly adjust the turn-on drive capability and output waveform under different operating conditions, which is beneficial for reducing turn-on losses, suppressing overshoot, and reducing electromagnetic interference, and has good engineering application value. Furthermore, this invention, through the parameter adjustment of the second capacitor C2, the second resistor R5, and the resistor R3, changes the establishment process of the output shaping node VRC, the damping state of the dynamic shaping branch, and the front-end feedback state, thereby forming a multi-parameter synergistic adjustment of the IGBT gate voltage and power side response waveform.

[0128] The above description is merely a preferred embodiment of the present invention. These specific embodiments are different implementations based on the overall concept of the present invention, and the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A continuously adjustable circuit for driving the gate of an IGBT, characterized in that, include: The unit comprises a front-end detection and comparison unit (01), a current mirror transmission unit (02), an intermediate control unit (03), and an output shaping unit (04); the input terminal of the current mirror transmission unit (02) is connected to the output terminal of the front-end detection and comparison unit (01), the input terminal of the intermediate control unit (03) is connected to the output terminal of the current mirror transmission unit (02), and the input terminal of the output shaping unit (04) is connected to the output terminal of the intermediate control unit (03). The front-end detection and comparison unit (01) is used to receive the detection signal and the reference signal, compare the detection signal and the reference signal, and output the primary analog control quantity; The current mirror transmission unit (02) is used to mirror and transmit the primary analog control quantity output by the front-end detection and comparison unit (01) to form an intermediate control signal. The intermediate control unit (03) is used to adjust the turn-on drive capability corresponding to the intermediate control signal under the action of the first control signal and output the subsequent control signal. The output shaping unit (04) is used to dynamically shape the subsequent control signal and output the turn-on driving voltage under the action of the second control signal to drive the gate of the IGBT.

2. The IGBT gate turn-on driving continuous control circuit according to claim 1, characterized in that, The front-end detection comparison unit (01) includes: bias enable branch (011), comparison input branch (012), first dynamic compensation and control quantity conversion branch (013), and front-end mirror output branch (014). The bias enable branch (011) is used to provide operating bias current for the front-end detection and comparison unit (01); The comparison input branch (012) is used to compare the detection signal VP with the reference signal VREF. The difference between the detection signal VP and the reference signal VREF is used to generate a primary analog control quantity representing the driving demand in the internal node of the front-end detection comparison unit (01). The first dynamic compensation and control quantity conversion branch (013) is used to smooth the primary analog control quantity formed by comparing the detection signal VP with the reference signal VREF, and then convert the smoothed control quantity into a voltage or current signal suitable for transmission to the current mirror transmission unit (02) via the front-end mirror output branch (014). The front-end mirror output branch (014) is used to receive the smoothed and converted control quantity output by the first dynamic compensation and control quantity conversion branch (013) and output it to the current mirror transmission unit (02).

3. The IGBT gate turn-on drive continuous control circuit according to claim 2, characterized in that, The bias enable branch (011) includes: PMOS transistors MP1, MP2, MP3 and MP4; the comparator input branch (012) includes: PMOS transistors MP5 and MP6 and NMOS transistors MN1 and MN2; the first dynamic compensation and control quantity conversion branch (013) includes: a first resistor R1, a first capacitor C1, NMOS transistors MN3 and MN4 and resistors R2 and R3; the front-end mirror output branch (014) includes: PMOS transistors MP7 and MP8; In this configuration, the sources of PMOS transistors MP1 and MP3, as well as the source of PMOS transistor MP7, are all connected to the power supply terminal VDD. The gate of PMOS transistor MP1 receives the first bias control signal VPVBO1, the gate of PMOS transistor MP2 receives the second bias control signal VPVBO2, the gate of PMOS transistor MP1 is connected to the gate of PMOS transistor MP3, the drain of PMOS transistor MP1 is connected to the source of PMOS transistor MP2, the gate of PMOS transistor MP2 is connected to the gate of PMOS transistor MP4, and the drain of PMOS transistor MP3 is connected to the source of PMOS transistor MP4. The drain of PMOS transistor MP2 is connected to the source of PMOS transistors MP5 and MP6, respectively. The gate of PMOS transistor MP5 receives the detection signal VP, and the gate of PMOS transistor MP6 receives the reference signal VREF. The drain of PMOS transistor MP5 is connected to the drain of NMOS transistor MN1, the gate of NMOS transistor MN1, and the gate of NMOS transistor MN2, respectively. The sources of NMOS transistors MN1 and MN2 are grounded. The drain of NMOS transistor MN2 is connected to the drain of PMOS transistor MP6, one end of the first resistor R1, and the gate of NMOS transistor MN3, respectively. The source of NMOS transistor MN3 is grounded. The other end of the first resistor R1 is connected to one end of the first capacitor C1, and the other end of the first capacitor C1 is connected to the drain of NMOS transistor MN3, the gate of NMOS transistor MN4, and the drain of PMOS transistor MP4, respectively. The source of NMOS transistor MN4 is connected to the feedback node where the detection signal VP is located, and is connected to one end of resistor R3 to form a closed-loop feedback path. The other end of resistor R3 is grounded. The drain of NMOS transistor MN4 is connected to one end of resistor R2. The other end of resistor R2 is connected to the drain and gate of PMOS transistor MP8, respectively. The source of PMOS transistor MP8 is connected to the drain and gate of PMOS transistor MP7, respectively.

4. The IGBT gate drive continuous control circuit according to claim 3, characterized in that, The current mirror transmission unit (02) includes: a multi-stage current mirror branch (021) and an intermediate transmission branch (022). The multi-stage current mirror branch (021) is used to mirror and copy the control quantity output by the front-end detection and comparison unit (01) and form a mirror current; The intermediate transmission branch (022) is used to receive the mirror current and form an intermediate control signal, and transmit the intermediate control signal to the intermediate control unit (03).

5. The IGBT gate drive continuous control circuit according to claim 4, characterized in that, The multi-stage current mirror branch (021) includes PMOS transistors MP9 and MP10; the intermediate transmission branch (022) includes NMOS transistors MN5 and MN6; Among them, the source of PMOS transistor MP9 is connected to the power supply terminal VDD, the gate of PMOS transistor MP9 is connected to the gate of PMOS transistor MP7, the drain of PMOS transistor MP9 is connected to the source of PMOS transistor MP10, the gate of PMOS transistor MP10 is connected to the gate of PMOS transistor MP8, the drain of PMOS transistor MP10 is connected to the drain and gate of NMOS transistor MN5, the source of NMOS transistor MN5 is connected to the drain and gate of NMOS transistor MN6, the source of NMOS transistor MN6 is grounded, and the gate nodes of NMOS transistor MN5 and NMOS transistor MN6 serve as the intermediate control signal output nodes of the current mirror transmission unit (02).

6. The IGBT gate drive continuous control circuit according to claim 5, characterized in that, The intermediate control unit (03) includes: an active load branch (031), a main pull-down branch (032), a first control branch (033), and a first feedback resistor R4; The active load branch (031) is used to form a pull-up active load between the power supply terminal VDD and the first feedback resistor R4, and to form a subsequent control signal according to the pull-down current change of the main pull-down branch (032). The main pull-down branch (032) is used to receive the intermediate control signal generated by the current mirror transmission unit (02) and generate a pull-down current corresponding to the intermediate control signal; The first control branch (033) is used to adjust the conduction capability of the main pull-down branch (032) under the action of the first control signal VCTR1, thereby changing the rate of change and the turn-on drive strength of the subsequent control signal formed by the active load branch (031) according to the change of the pull-down current. The first feedback resistor R4 is used to feed back the pull-down current change of the main pull-down branch (032) to the active load branch (031) to improve the dynamic response stability of the intermediate control unit.

7. The IGBT gate drive continuous control circuit according to claim 6, characterized in that, The active load branch (031) includes PMOS transistors MP11 and MP12; the main pull-down branch (032) includes NMOS transistors MN7 and MN8; the first control branch (033) includes NMOS transistor MN9; In this configuration, the gate of NMOS transistor MN5 is connected to the gate of NMOS transistor MN7 and the drain of NMOS transistor MN9, the gate of NMOS transistor MN6 is connected to the gate of NMOS transistor MN8, the source of NMOS transistor MN8 is grounded, the drain of NMOS transistor MN8 is connected to the source of NMOS transistor MN7, the gate of NMOS transistor MN9 receives the first control signal VCTR1, and the source of NMOS transistor MN9 is grounded; the drain of NMOS transistor MN7 is connected to one end of the first feedback resistor R4, the other end of the first feedback resistor R4 is connected to the drain and gate of PMOS transistor MP12, the source of PMOS transistor MP12 is connected to the drain and gate of PMOS transistor MP11, and the source of PMOS transistor MP11 is connected to the power supply terminal VDD.

8. The IGBT gate drive continuous control circuit according to claim 7, characterized in that, The output shaping unit (04) includes: an output stage PMOS branch (041), an output execution transistor (042), a second control branch (043), and a second dynamic shaping network (044). The output stage PMOS branch (041) is used to provide pull-up drive current to the output shaping node VRC according to the subsequent control signal; The output execution transistor (042) is used to output an on-drive voltage to the output terminal VOUT according to the potential change of the output shaping node VRC; The second control branch (043) is used to adjust the pull-down capability of the output shaping node VRC under the action of the second control signal VCTR2; The second dynamic shaping network (044) is used together with the second control branch (043) to adjust the dynamic response of the output shaping node VRC and control the slope of the turn-on drive voltage VOUT to reduce voltage overshoot, current overshoot and electromagnetic interference during IGBT turn-on.

9. The IGBT gate drive continuous control circuit according to claim 8, characterized in that, The output stage PMOS branch (041) includes: PMOS transistors MP13 and MP14; the output execution transistor (042) includes: NMOS transistor MNLD1; the second control branch (043) includes: NMOS transistor MN10; the second dynamic shaping network (044) includes: second resistor R5 and second capacitor C2; In this configuration, the source of PMOS transistor MP13 is connected to the power supply terminal VDD and the drain of NMOS transistor MNLD1, the gate of PMOS transistor MP13 is connected to the gate of PMOS transistor MP11, the drain of PMOS transistor MP13 is connected to the source of PMOS transistor MP14, the gate of PMOS transistor MP14 is connected to the gate of PMOS transistor MP12, the drain of PMOS transistor MP14 is connected to the gate of NMOS transistor MNLD1, the drain of NMOS transistor MN10, and one end of the second resistor R5, and the connection node of the drain of PMOS transistor MP14, the gate of NMOS transistor MNLD1, the drain of NMOS transistor MN10, and one end of the second resistor R5 is the output shaping node VRC, the other end of the second resistor R5 is connected to one end of the second capacitor C2, the other end of the second capacitor C2 is grounded, the source of NMOS transistor MN10 is grounded, the gate of NMOS transistor MN10 receives the second control signal VCTR2, and the source of NMOS transistor MNLD1 is connected to the output terminal VOUT.

10. A control method based on the IGBT gate drive continuous control circuit according to claim 9, characterized in that, Includes the following steps: S1. Input the detection signal VP and the reference signal VREF to the front-end detection comparison unit (01) and establish the working state of the bias enable branch (011); S2. The front-end detection and comparison unit (01) compares the detection signal VP with the reference signal VREF to generate a primary analog control quantity; S3. The primary analog control quantity is dynamically smoothed using the first dynamic compensation and control quantity conversion branch (013), and the control quantity after dynamic smoothing is converted into a voltage or current signal suitable for subsequent transmission. S4. The current mirror transmission unit (02) is used to mirror and transmit the control quantity after dynamic smoothing and conversion to form an intermediate control signal. S5. Using the intermediate control unit (03) under the action of the first control signal VCTR1, the turn-on drive capability corresponding to the intermediate control signal is adjusted to form the subsequent control signal; S6. Using the output shaping unit (04) under the action of the second control signal VCTR2 and the second dynamic shaping network (044), the subsequent control signal is dynamically shaped, and the turn-on drive voltage VOUT is output to drive the IGBT gate. In step S5, the conduction capability of the main pull-down branch (032) in the intermediate control unit (03) is changed by adjusting the first control signal VCTR1, thereby changing the establishment speed and amplitude of the subsequent control signal; in step S6, the dynamic response of the output shaping node VRC is adjusted by adjusting the time constant formed by the second resistor R5 and the second capacitor C2 in the second dynamic shaping network (044) and the second control signal VCTR2, so as to control the slope of the change of the turn-on drive voltage VOUT.

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