Delay circuit and electrostatic discharge method
Patent Information
- Application Number
- CN202610851302.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-06-12
- Publication Date
- 2026-10-09
AI Technical Summary
[0005]本发明的目的在于提供一种延时电路及静电泄放方法，以解决现有技术的阻容钳位电路中由于RC时间常数固定导致泄放管导通时间较短、无法将大能量静电电荷充分泄放而易损伤内部核心电路的技术问题
[0027]本发明通过在电阻元件和电容元件之间引入受控的第一晶体管，并将主泄放管（第二晶体管）栅极的电位反馈至第一晶体管的控制端。在静电放电信号到来时，利用节点电位的升高使第一晶体管关断并呈现高阻态，相当于动态放大了RC电路的电阻，从而降低了电容元件的充电速度。该结构能够延长主泄放管的导通时间，提高栅极感应电压的幅值并保持更长的高电平状态，使得主泄放管深度导通，从而确保静电电荷得到充分泄放，提高了芯片整体抵御静电冲击的安全性和可靠性。
Smart Images
Figure CN122891035A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit manufacturing, and in particular to a delay circuit and an electrostatic discharge method. Background Technology
[0002] In integrated circuits, RC coupling circuits are commonly used for electrostatic discharge (ESD) protection. For example... Figure 1 As shown, a traditional RC coupling circuit mainly consists of a resistor R, a capacitor C, an inverter INV, and a large-size bleeder diode (BIG NMOS). Among them, the resistor R and the capacitor C are connected in series between the power supply and ground, and their common terminal node 1 (NODE1) is connected to the gate node 2 (NODE2) of the bleeder diode via the inverter.
[0003] When an electrostatic pulse arrives, since the voltage across capacitor C cannot change abruptly, node 1 is initially at a low level. After being inverted by the inverter, it outputs a high level at node 2, causing the discharge tube to quickly conduct and discharge the electrostatic current.
[0004] However, the RC time constant of this structure is fixed. During an electrostatic pulse, the capacitor is continuously charged, causing the potential of node 1 to rise rapidly. Once the inverter's switching threshold is reached, node 2 switches to a low level, causing the bleeder to turn off quickly. This fixed delay mechanism results in a short conduction time for the bleeder and a limited duration of high gate potential maintenance, often failing to fully discharge large amounts of electrostatic charge, posing a risk of damaging the internal core circuitry. Summary of the Invention
[0005] The purpose of this invention is to provide a delay circuit and an electrostatic discharge method to solve the technical problem in the prior art RC clamp circuit that the fixed RC time constant results in a short conduction time of the discharge tube, which cannot fully discharge large energy electrostatic charges and is prone to damage to the internal core circuit.
[0006] To achieve the above objectives, the present invention provides the following technical solution:
[0007] This invention provides a delay circuit, comprising:
[0008] Power supply terminal and ground terminal;
[0009] A resistor, a first transistor, and a capacitor are connected in series between the power supply terminal and the ground terminal; wherein the first transistor is located between the resistor and the capacitor, and the common connection terminal of the first transistor and the capacitor is a first node;
[0010] The inverting unit has its input connected to the first node and its output connected to the second node.
[0011] The second transistor has a first terminal connected to the power supply terminal, a second terminal connected to the ground terminal, and a control terminal connected to the second node;
[0012] The control terminal of the first transistor is connected to the second node; when an input signal is received, the inverting unit inverts the level signal of the first node and outputs it to the second node to turn on the second transistor; as the level of the second node changes, the first transistor turns off to slow down the charging rate of the capacitor element.
[0013] Preferably, the first transistor is a P-type metal-oxide-semiconductor field-effect transistor.
[0014] Preferably, the source of the P-type metal-oxide-semiconductor field-effect transistor is connected to the resistive element, the drain is connected to the first node, and the gate is connected to the second node.
[0015] Preferably, the second transistor is an N-type metal-oxide-semiconductor field-effect transistor.
[0016] Preferably, the drain of the N-type metal-oxide-semiconductor field-effect transistor is connected to the power supply terminal, the source is connected to the ground terminal, and the gate is connected to the second node.
[0017] Preferably, the first end of the resistive element is connected to the power supply terminal, and the second end of the resistive element is connected to the first transistor; the first end of the capacitor element is connected to the first node, and the second end of the capacitor element is connected to the ground terminal.
[0018] Preferably, the delay circuit is an electrostatic discharge protection circuit, used to discharge electrostatic charge when an electrostatic discharge event occurs.
[0019] The present invention also provides an electrostatic discharge method, applied to the delay circuit described in any of the above claims, comprising:
[0020] Step 1: When an electrostatic discharge signal is received at the power supply terminal, the capacitor element is charged through the resistor element and the first transistor that is turned on.
[0021] Step 2: During the initial charging phase of the capacitor element, the first node remains at a low level, and the inverting unit inverts the low level to a high level and outputs it to the second node.
[0022] Step 3: The high level of the second node drives the second transistor to conduct, so as to discharge the charge of the electrostatic discharge signal;
[0023] Step 4: The high level of the second node is fed back to the control terminal of the first transistor, causing the first transistor to turn off, thereby slowing down the charging rate of the capacitor element and extending the conduction time of the second transistor.
[0024] Preferably, in step one, the electrostatic discharge signal is a transmission line pulse signal.
[0025] Preferably, in step four, after the first transistor is turned off, it is in a high-impedance state, which is equivalent to amplifying the resistance of the delay circuit, so that the voltage at the second node is maintained at the high level.
[0026] As described above, the delay circuit and electrostatic discharge method of the present invention have the following beneficial effects:
[0027] This invention introduces a controlled first transistor between the resistive and capacitive elements, and feeds back the gate potential of the main discharge transistor (second transistor) to the control terminal of the first transistor. When an electrostatic discharge signal arrives, the rise in node potential causes the first transistor to turn off and enter a high-resistance state, effectively amplifying the resistance of the RC circuit and thus reducing the charging speed of the capacitor. This structure extends the conduction time of the main discharge transistor, increases the amplitude of the gate-induced voltage, and maintains a longer high-level state, allowing the main discharge transistor to conduct deeply. This ensures sufficient discharge of electrostatic charge, improving the overall safety and reliability of the chip against electrostatic shocks. Attached Figure Description
[0028] Figure 1 The diagram shown is a schematic representation of a prior art resistor-capacitor delay circuit.
[0029] Figure 2 The diagram shown is a schematic representation of the delay circuit of the present invention.
[0030] Figure 3 The diagram shown is a flowchart of the electrostatic discharge method of the present invention.
[0031] Figure 4 The diagram shows a comparison of node voltage waveforms between the present invention and existing technologies. Detailed Implementation
[0032] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0033] A delay circuit, comprising:
[0034] Power supply terminal and ground terminal;
[0035] A resistor R, a first transistor PMOS, and a capacitor C are connected in series between the power supply terminal and the ground terminal;
[0036] The first transistor PMOS is located between the resistor element R and the capacitor element C, and the common connection terminal of the first transistor PMOS and the capacitor element C is the first node NODE1.
[0037] The inverting unit INV has its input connected to the first node NODE1 and its output connected to the second node NODE2.
[0038] The second transistor, BIG NMOS, has its first terminal connected to the power supply terminal, its second terminal connected to the ground terminal, and its control terminal connected to the second node, NODE2.
[0039] In this configuration, the control terminal of the first transistor PMOS is connected to the second node NODE2. When an input signal is received, the inverting unit INV inverts the level signal of the first node NODE1 and outputs it to the second node NODE2 to turn on the second transistor BIGNMOS. As the level of the second node NODE2 changes, the first transistor PMOS turns off to slow down the charging rate of the capacitor C.
[0040] Please refer to Figure 2 , Figure 2 A schematic diagram of the circuit structure of a delay circuit provided in an embodiment of this application is illustrated. In semiconductor integrated circuits, the power supply terminal is typically used to receive the external supply voltage, and the ground terminal is typically connected to the reference ground potential inside the chip. The aforementioned delay circuit can be designed and integrated into various logic chips or memory chips to protect the internal core functional circuits from damage caused by external abnormal transient voltages. By introducing a first transistor PMOS as a dynamic adjustment structure, the delay circuit can dynamically change the rate of change of the node level when a transient input signal arrives, thereby extending the on-time of the subsequent discharge path.
[0041] In some embodiments, the first transistor PMOS is a P-type metal-oxide-semiconductor field-effect transistor.
[0042] In some embodiments, the source of a P-type metal-oxide-semiconductor field-effect transistor is connected to a resistive element R, the drain is connected to a first node NODE1, and the gate is connected to a second node NODE2.
[0043] like Figure 2As shown, in the specific circuit connection, the first transistor PMOS, besides using a P-type metal-oxide-semiconductor field-effect transistor, can also employ other suitable types of semiconductor switching devices such as fin field-effect transistors and all-around gate transistors, depending on the specific process platform or overall layout requirements. Using a P-type device allows for good conduction characteristics when the control terminal is low, and a rapid transition to a high-impedance state when the control terminal potential rises. This setting can delay the decay process of the relevant node potential, enabling the entire circuit to exhibit better response capability when facing abnormal pulses of long duration.
[0044] In some embodiments, the second transistor BIG NMOS is an N-type metal-oxide-semiconductor field-effect transistor.
[0045] In some embodiments, the drain of the N-type metal-oxide-semiconductor field-effect transistor is connected to the power supply terminal, the source is connected to the ground terminal, and the gate is connected to the second node NODE2.
[0046] Combination Figure 2 As can be seen, the second transistor, BIG NMOS, typically serves as the primary charge discharge channel, and its channel size can be adjusted according to the maximum current required to discharge for the target electrostatic discharge (ESD) level. In different application scenarios, high-current-carrying devices such as bipolar junction transistors (BJTs) or laterally diffused metal-oxide-semiconductor (MODS) transistors can also be used to replace conventional N-type MODS MOSFETs. The design of the second transistor, BIG NMOS, enables it to withstand large current densities. When triggered by a high level at the second node NODE2, it can quickly establish a low-impedance path between the power supply and ground terminals, thereby safely guiding excess harmful charges to the ground terminal.
[0047] In some embodiments, the first end of the resistor element R is connected to the power supply terminal, and the second end of the resistor element R is connected to the first transistor PMOS; the first end of the capacitor element C is connected to the first node NODE1, and the second end of the capacitor element C is connected to the ground terminal.
[0048] like Figure 2 As shown, the resistive element R and the capacitor element C together constitute the front-end sensing network. Their specific physical structure and size parameters can be flexibly configured based on the target time constant. The resistive element R can be a polysilicon resistor, a diffusion region resistor, a metal thin-film resistor, or a combination of these structures. The capacitor element C can be a metal-insulator-metal capacitor, a metal-oxide-semiconductor capacitor, or a metal-oxide-metal capacitor. The inverting unit INV typically includes logic gate circuits composed of transistors, used to logically invert the level of the first node NODE1 at the input terminal and provide the corresponding driving capability. The number of stages and size configuration of the inverting unit INV affects the level switching speed of the second node NODE2.
[0049] In some embodiments, the delay circuit is an electrostatic discharge protection circuit used to discharge electrostatic charge when an electrostatic discharge event occurs.
[0050] Electrostatic discharge (ESD) events are typically accompanied by a large transfer of charge within a very short time. This delay circuit, through an internal feedback mechanism, increases the amplitude of the gate-induced voltage of the second transistor (BIG NMOS) when an ESD signal arrives, causing the BIG NMOS to enter a deep conduction state, thus allowing the ESD charge to be fully discharged. This structural improvement enhances the overall chip's resistance to ESD without increasing the integrated circuit layout area.
[0051] Please refer to Figure 3 , Figure 3 A flowchart illustrating an embodiment of the present application provides a method for discharging static electricity.
[0052] An electrostatic discharge method, applied to the delay circuit described above, includes:
[0053] Step 1: When an electrostatic discharge signal is received at the power supply terminal, the capacitor C is charged through the resistor R and the first conducting transistor PMOS.
[0054] In some embodiments, in step one, the electrostatic discharge signal is a transmission line pulse signal.
[0055] like Figure 3 As shown in step one, besides the transmission line pulse signal, the electrostatic discharge signal can also be a transient discharge pulse generated by the human body model, machine model, or component charging model. When such an abnormal level signal enters the power supply terminal, the source of the first transistor PMOS is usually at a high potential, while the drain and control terminal are initially close to ground potential. Therefore, the first transistor PMOS is deeply turned on, which is equivalent to a transmission line with a certain parasitic resistance value in the circuit, allowing the initial charging current to pass smoothly and act on the capacitor element C.
[0056] Step 2: In the initial stage of charging of capacitor element C, the first node NODE1 remains at a low level, and the inverting unit INV inverts the low level to a high level and outputs it to the second node NODE2.
[0057] like Figure 3 As shown in step two, due to the physical characteristic that the voltage across capacitor C cannot change abruptly, the first node NODE1 maintains a low level state for a short time window. Upon receiving a low-level input, the inverting unit INV flips its state, generating a high-level output at the second node NODE2. This provides the necessary drive potential for subsequently starting the main discharge path.
[0058] Step 3: The high level of the second node NODE2 drives the second transistor BIG NMOS to turn on, so as to discharge the charge of the electrostatic discharge signal.
[0059] like Figure 3 As shown in step three, in response to the high-level signal output by the second node NODE2, the conductive channel of the second transistor BIG NMOS is quickly turned on. With the intervention of the feedback mechanism, the high level of the second node NODE2 is effectively maintained, ensuring that the second transistor BIG NMOS can remain in a deeply conductive state, establishing a stable current discharge path, and quickly dissipating the accumulated electrostatic charge.
[0060] Step 4: The high level of the second node NODE2 is fed back to the control terminal of the first transistor PMOS, causing the first transistor PMOS to turn off, thereby slowing down the charging rate of the capacitor C and extending the conduction time of the second transistor BIG NMOS.
[0061] In some embodiments, in step four, after the first transistor PMOS is turned off, it is in a high-resistance state and is equivalent to amplifying the resistance of the delay circuit so that the voltage at the second node NODE2 is maintained at a high level.
[0062] like Figure 3 As shown in step four, when the control terminal of the first transistor PMOS senses a high level at the second node NODE2, the first transistor PMOS turns off due to the change in bias conditions, exhibiting a high-resistance state. This physical process is equivalent to dynamically increasing the effective impedance of the original network, amplifying the overall equivalent resistance, thereby significantly reducing the charging speed of the capacitor element C, and slowing down the rate at which the voltage of the first node NODE1 rises. Correspondingly, the inverting unit INV can maintain the voltage of the second node NODE2 at a high level for a longer period of time.
[0063] Please refer to the reference. Figure 4 , Figure 4 The diagram shows a comparison of the node voltage over time between the prior art and the embodiments of this application. This is further supported by simulation results based on the EE 95nm platform. Figure 4 As can be seen from the curve comparison, after introducing the feedback mechanism of the first transistor PMOS, the voltage at the second node NODE2 in the RC coupling circuit of this embodiment can be maintained at a high level for a significantly longer period of time. The figure clearly shows an increased RC delay window. This method can effectively extend the turn-on time window of the second transistor BIG NMOS, allowing the electrostatic charge to be fully discharged over a longer period, preventing residual charge from causing secondary damage to internal devices due to premature closure of the discharge path.
[0064] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0065] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A delay circuit, characterized in that, include: Power supply terminal and ground terminal; A resistor, a first transistor, and a capacitor are connected in series between the power supply terminal and the ground terminal; wherein the first transistor is located between the resistor and the capacitor, and the common connection terminal of the first transistor and the capacitor is a first node; The inverting unit has its input connected to the first node and its output connected to the second node. The second transistor has a first terminal connected to the power supply terminal, a second terminal connected to the ground terminal, and a control terminal connected to the second node; The control terminal of the first transistor is connected to the second node; when an input signal is received, the inverting unit inverts the level signal of the first node and outputs it to the second node to turn on the second transistor; as the level of the second node changes, the first transistor turns off to slow down the charging rate of the capacitor element.
2. The delay circuit according to claim 1, characterized in that: The first transistor is a P-type metal-oxide-semiconductor field-effect transistor.
3. The delay circuit according to claim 2, characterized in that: The source of the P-type metal-oxide-semiconductor field-effect transistor is connected to the resistive element, the drain is connected to the first node, and the gate is connected to the second node.
4. The delay circuit according to claim 1, characterized in that: The second transistor is an N-type metal-oxide-semiconductor field-effect transistor.
5. The delay circuit according to claim 4, characterized in that: The drain of the N-type metal-oxide-semiconductor field-effect transistor is connected to the power supply terminal, the source is connected to the ground terminal, and the gate is connected to the second node.
6. The delay circuit according to claim 1, characterized in that: The first end of the resistor is connected to the power supply terminal, and the second end of the resistor is connected to the first transistor; the first end of the capacitor is connected to the first node, and the second end of the capacitor is connected to the ground terminal.
7. The delay circuit according to claim 1, characterized in that: The delay circuit is an electrostatic discharge protection circuit, used to discharge electrostatic charge when an electrostatic discharge event occurs.
8. A method for electrostatic discharge, applied to a delay circuit as described in any one of claims 1 to 7, characterized in that, include: Step 1: When an electrostatic discharge signal is received at the power supply terminal, the capacitor element is charged through the resistor element and the first transistor that is turned on. Step 2: During the initial charging phase of the capacitor element, the first node remains at a low level, and the inverting unit inverts the low level to a high level and outputs it to the second node. Step 3: The high level of the second node drives the second transistor to conduct, so as to discharge the charge of the electrostatic discharge signal; Step 4: The high level of the second node is fed back to the control terminal of the first transistor, causing the first transistor to turn off, thereby slowing down the charging rate of the capacitor element and extending the conduction time of the second transistor.
9. The electrostatic discharge method according to claim 8, characterized in that: In step one, the electrostatic discharge signal is a transmission line pulse signal.
10. The electrostatic discharge method according to claim 8, characterized in that: In step four, after the first transistor is turned off, it is in a high-impedance state, which is equivalent to amplifying the resistance of the delay circuit, so that the voltage at the second node is maintained at the high level.