A clock data recovery circuit dynamic bandwidth extension and lock acceleration circuit and method

Abstract

The application discloses a clock data recovery circuit dynamic bandwidth expansion and locking acceleration circuit and method, which comprises the following steps: frequency detection is performed on non-periodic data and a first clock signal CLK90 output by a voltage-controlled oscillator by using a frequency detection circuit FD to generate a frequency detection pulse signal; phase detection is performed on the non-periodic data and a second clock signal CLK0 output by the voltage-controlled oscillator by using a phase detection circuit PD to generate a phase advance pulse signal UP and a phase lag pulse signal DN; logical operation is performed on the frequency detection pulse signal, the phase advance pulse signal UP and the phase lag pulse signal DN to generate a bandwidth expansion tuning signal VTF_AUX; and the VTF_AUX is superimposed on a proportional path control signal VTF_MAIN of the clock data recovery circuit to dynamically expand the loop bandwidth in the effective period of the frequency detection pulse signal. The application can accelerate the frequency capture process, maintain the narrow-band jitter suppression capability after locking, and improve the jitter tolerance.

Description

Technical Field

[0001] This invention relates to microelectronics technology, and in particular to a clock data recovery circuit with dynamic bandwidth expansion and locking acceleration circuit and method. Background Technology

[0002] The core function of a clock data recovery (CDR) circuit is to accurately extract a periodic clock signal from received noisy and jittery non-periodic data, and then resample the data to ensure correct data parsing. CDR operation typically involves two key stages: frequency acquisition and phase locking. The goal of frequency acquisition is to quickly converge the output frequency of the CDR's internal voltage-controlled oscillator (VCO) to near the input data rate. This requires the frequency difference to fall within the acquisition range of the subsequent phase-locked loop (PLL). Finally, the PLL aligns the clock edge with the midpoint of the data bits, achieving optimal sampling. In traditional PLL-based CDR schemes, to achieve better jitter filtering performance and stability after locking, the loop bandwidth is usually set relatively narrow. However, a narrow loop bandwidth becomes a significant bottleneck in the frequency acquisition stage, indicating a weaker ability to correct the initial frequency difference, a slower response speed, and a longer acquisition time.

[0003] Dynamically expanding the CDR loop bandwidth during the frequency acquisition phase effectively resolves this contradiction and brings three benefits: First, it improves the loop's response speed to frequency differences during the frequency acquisition phase, allowing the VCO frequency to approach the target frequency with a greater slope; second, once the frequency error is detected to have decreased to within a preset threshold, the loop bandwidth is switched back to its initial narrower state, effectively suppressing high-frequency data jitter and noise; third, after CDR lock-up, when the jitter of the input random data increases, bandwidth expansion can also be dynamically triggered, reducing the risk of lock-up loss under high input jitter and improving the jitter tolerance performance of CDR.

[0004] Therefore, adding dynamic bandwidth expansion during CDR frequency acquisition is a design strategy of "rapid convergence first, then stable suppression," which is a design balance between acquisition speed and locking performance. With the practical application of high-speed interfaces and other application fields, more effective bandwidth adaptive expansion technology may drive the further development of CDR performance. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to address the shortcomings of the prior art by providing a dynamic bandwidth expansion and locking acceleration circuit and method for clock data recovery circuit. This dynamic bandwidth expansion and locking acceleration circuit and method utilizes specific logic operations between the output signals of frequency detection (FD) and phase detection (PD) to expand the loop bandwidth in real time and dynamically within each frequency detection pulse cycle. This can accelerate the frequency acquisition process, maintain narrowband jitter suppression capability after locking, and improve jitter tolerance.

[0006] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0007] A method for dynamic bandwidth expansion and locking acceleration of a clock data recovery circuit includes the following steps.

[0008] The frequency detection circuit FD is used to detect the frequency of the input non-periodic data and the first clock signal CLK90 output by the voltage-controlled oscillator, generating a frequency detection pulse signal.

[0009] The phase detection circuit PD is used to perform phase detection between the input aperiodic data and the second clock signal CLK0 output by the voltage-controlled oscillator, generating a phase-leading pulse signal UP and a phase-lagging pulse signal DN.

[0010] The frequency detection pulse signal is logically operated with the phase lead pulse signal UP and the phase lag pulse signal DN to generate the bandwidth extension tuning signal VTF_AUX.

[0011] The bandwidth extension tuning signal VTF_AUX is superimposed on the proportional path control signal VTF_MAIN of the clock data recovery circuit to dynamically extend the loop bandwidth during the effective period of the frequency detection pulse signal.

[0012] The frequency detection pulse signal is obtained by sampling the first clock signal CLK90 at the rising edge of the non-periodic data. The frequency detection pulse signal includes two complementary pulse signals, namely the first pulse signal Q1 and the second pulse signal Q1B.

[0013] Methods for generating the bandwidth-extended tuned signal VTF_AUX include:

[0014] The first auxiliary pulse UP_AUX is generated by latching the phase-leading pulse signal UP with the first pulse signal Q1.

[0015] The phase lag pulse signal DN is latched using the second pulse signal Q1B to generate the second auxiliary pulse DN_AUX.

[0016] The bandwidth-extended tuning signal VTF_AUX is obtained by differentially amplifying the first auxiliary pulse UP_AUX and the second auxiliary pulse DN_AUX.

[0017] When the clock data recovery circuit enters the locked state, the effective width of the frequency detection pulse signal decreases or disappears, the bandwidth extension tuning signal VTF_AUX automatically returns to zero, and the loop bandwidth is restored to the initial narrowband state.

[0018] Once the clock data recovery circuit is locked, if the jitter amplitude of the input non-periodic data exceeds the preset threshold, the frequency detection pulse signal will regenerate an effective width, triggering the bandwidth expansion tuning signal VTF_AUX to be superimposed again, dynamically widening the loop bandwidth.

[0019] The bandwidth extension tuning signal VTF_AUX and the proportional path control signal VTF_MAIN are superimposed to form the synthesized proportional control signal VTF. The synthesized proportional control signal VTF is then superimposed with the integral path signal VTC to form the input signal VT of the voltage-controlled oscillator. Among them, the proportional path control signal VTF_MAIN is obtained by proportionally amplifying the phase lead pulse signal UP; the integral path signal VTC is obtained by controlling the voltage-to-current circuit VIC to charge and discharge the external capacitor through the phase lead pulse signal UP and the phase lag pulse signal DN.

[0020] A clock data recovery circuit with dynamic bandwidth expansion and locking acceleration includes:

[0021] A voltage-controlled oscillator (VCO) is used to generate a first clock signal CLK90, a second clock signal CLK0, and a third clock signal CLK180.

[0022] The frequency detection circuit FD has a first clock signal CLK90 connected to its first input terminal and non-periodic data connected to its second input terminal, which is used to output a frequency detection pulse signal.

[0023] The phase detection circuit PD has a first clock input terminal connected to a second clock signal CLK0, a second clock input terminal connected to a third clock signal CLK180, and a data input terminal connected to non-periodic data. It is used to output a phase-leading pulse signal UP and a phase-lagging pulse signal DN.

[0024] The dynamic bandwidth expansion circuit has its first input terminal connected to the output terminal of the frequency detection circuit FD, and its second input terminal connected to the output terminal of the phase detection circuit PD. It is used to perform logical operations on the frequency detection pulse signal, the phase lead pulse position signal UP, and the phase lag pulse signal DN, and output the bandwidth expansion tuning signal VTF_AUX.

[0025] The proportional amplifier has its input connected to the output of the phase detection circuit PD, and is used to output the proportional path control signal VTF_MAIN.

[0026] The first adder has its first input connected to the output of the proportional amplifier and its second input connected to the output of the dynamic bandwidth expansion circuit. It is used to add the proportional path control signal VTF_MAIN and the bandwidth expansion tuning signal VTF_AUX to output the synthesized proportional control signal VTF.

[0027] The frequency detection circuit is a first D flip-flop. Its data input terminal is connected to the first clock signal CLK90, its clock terminal is connected to the rising edge of non-periodic data, its non-inverting output terminal outputs the first pulse signal Q1, and its inverting output terminal outputs the second pulse signal Q1B.

[0028] The dynamic bandwidth expansion circuit includes:

[0029] The high-level active latch has a data input terminal connected to the phase advance pulse signal UP, a clock terminal connected to the first pulse signal Q1, and outputs the first auxiliary pulse UP_AUX.

[0030] The low-level active latch has a data input terminal connected to the phase lag pulse signal DN, a clock terminal connected to the second pulse signal Q1B, and outputs a second auxiliary pulse DN_AUX.

[0031] Differential amplifier K1 has its positive input connected to the output of a high-level active latch, its negative input connected to the output of a low-level active latch, and its output is the bandwidth extension tuning signal VTF_AUX.

[0032] The phase detection circuit is a Bang-bang phase detector, including:

[0033] The second D flip-flop has a clock input to the second clock signal CLK0 and a data input to non-periodic data, outputting an early sampling signal Q4.

[0034] The third D flip-flop has a clock input to the third clock signal CLK180 and a data input to non-periodic data, outputting a late-sampled signal Q5.

[0035] The fourth D flip-flop has a late sampling signal Q5 connected to its clock terminal and an early sampling signal Q4 connected to its data terminal, outputting a phase-leading pulse signal UP and a phase-lagging pulse signal DN.

[0036] The present invention has the following beneficial effects:

[0037] 1. This invention utilizes the Q1 / Q1B pulse signals output by the frequency detection circuit FD to conditionally select / latch the UP / DN pulse signals output by the phase detection circuit PD (the high-level active latch uses Q1 to latch UP, and the low-level active latch uses Q1B to latch DN), generating auxiliary tuning pulses UP_AUX and DN_AUX. This logic structure ensures that the bandwidth expansion operation is synchronized with the frequency detection pulse period, rather than being continuously or randomly triggered, thereby achieving precise and controllable dynamic bandwidth adjustment.

[0038] 2. This invention, by means of dynamic bandwidth expansion and accelerated locking circuit, can realize dynamic expansion of CDR loop bandwidth during frequency acquisition, thereby accelerating clock locking speed and improving jitter tolerance performance after locking.

[0039] 3. When the CDR is not locked or the input jitter is large, this invention generates UP_AUX / DN_AUX in each FD output pulse cycle. This UP_AUX is generated through differential amplifier K1 to produce a bandwidth extension tuning signal VTF_AUX, which is then superimposed on the proportional path control signal VTF_MAIN. This "cycle-by-cycle" bandwidth extension method significantly improves the response speed during the frequency acquisition stage, enabling the VCO frequency to converge faster.

[0040] 4. When the frequency error shrinks to within the threshold (CDR is close to lock), the duty cycle of Q1 / Q1B decreases, and the effective pulse width of UP_AUX / DN_AUX naturally narrows, automatically restoring the bandwidth to its initial narrowband state. Even after locking, if the input jitter exceeds the threshold, this bandwidth expansion mechanism can still be triggered, improving jitter tolerance and reducing the risk of lock-up failure. In other words, this invention possesses dual-mode operating characteristics: automatically restoring narrowband after CDR lock and triggering bandwidth expansion again under high jitter input. Attached Figure Description

[0041] Figure 1 The block diagram of the CDR circuit with dynamic bandwidth expansion function of the present invention is shown.

[0042] Figure 2 The diagram shows the dynamic bandwidth expansion circuit of the present invention applied to a CDR circuit.

[0043] Figure 3 The circuit diagram of the Bang-bang PD of the present invention is shown.

[0044] Figure 4 The timing waveform diagram of the dynamic bandwidth expansion circuit of the present invention is shown.

[0045] Figure 5 The diagram shows a comparison of the VT waveforms before and after the addition of the dynamic bandwidth extension circuit in this invention. Detailed Implementation

[0046] The present invention will now be described in further detail with reference to the accompanying drawings and specific preferred embodiments.

[0047] In the description of this invention, it should be understood that the terms "left side," "right side," "upper part," "lower part," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. "First," "second," etc., do not indicate the importance of the components, and therefore should not be construed as a limitation of this invention. The specific dimensions used in this embodiment are only for illustrating the technical solution and do not limit the scope of protection of this invention.

[0048] like Figure 1 As shown, a clock data recovery circuit with dynamic bandwidth expansion and locking acceleration includes a voltage-controlled oscillator (VCO), a frequency detection circuit (FD), a phase detection circuit (PD), a dynamic bandwidth expansion circuit, a proportional amplification path, and an integral path.

[0049] A voltage-controlled oscillator (VCO) is used to generate a first clock signal CLK90, a second clock signal CLK0, and a third clock signal CLK180. The phase difference between the first clock signal CLK90 and the second clock signal CLK0 is 90 degrees, and the phase difference between the second clock signal CLK0 and the third clock signal CLK180 is 180 degrees.

[0050] The frequency detection circuit FD has a first clock signal CLK90 connected to its first input terminal and non-periodic data connected to its second input terminal, which is used to output a frequency detection pulse signal.

[0051] like Figure 2 As shown, the frequency detection circuit described above is preferably a first D flip-flop (also called D flip-flop 1), whose data input terminal is connected to the first clock signal CLK90, whose clock terminal is connected to the rising edge of non-periodic data, whose non-inverting output terminal outputs the first pulse signal Q1, and whose inverting output terminal outputs the second pulse signal Q1B.

[0052] The phase detection circuit PD has a first clock input terminal connected to a second clock signal CLK0, a second clock input terminal connected to a third clock signal CLK180, and a data input terminal connected to non-periodic data. It is used to output a phase-leading pulse signal UP and a phase-lagging pulse signal DN.

[0053] like Figure 3 As shown, the phase detection circuit is a Bang-bang phase detector, which includes the following components.

[0054] The second D flip-flop has a clock input to the second clock signal CLK0 and a data input to non-periodic data, outputting an early sampling signal Q4.

[0055] The third D flip-flop has a clock input to the third clock signal CLK180 and a data input to non-periodic data, outputting a late-sampled signal Q5.

[0056] The fourth D flip-flop has a late sampling signal Q5 connected to its clock terminal and an early sampling signal Q4 connected to its data terminal, outputting a phase-leading pulse signal UP and a phase-lagging pulse signal DN.

[0057] The aforementioned dynamic bandwidth expansion circuit has its first input terminal connected to the output terminal of the frequency detection circuit FD, and its second input terminal connected to the output terminal of the phase detection circuit PD. It is used to perform logical operations on the frequency detection pulse signal, the phase lead pulse position signal UP, and the phase lag pulse signal DN, and output the bandwidth expansion tuning signal VTF_AUX.

[0058] like Figure 2 As shown, the dynamic bandwidth extension circuit includes the following components.

[0059] The high-level active latch has a data input terminal connected to the phase advance pulse signal UP, a clock terminal connected to the first pulse signal Q1, and outputs the first auxiliary pulse UP_AUX.

[0060] The low-level active latch has a data input terminal connected to the phase lag pulse signal DN, a clock terminal connected to the second pulse signal Q1B, and outputs a second auxiliary pulse DN_AUX.

[0061] Differential amplifier K1 has its positive input connected to the output of a high-level active latch, its negative input connected to the output of a low-level active latch, and its output is the bandwidth extension tuning signal VTF_AUX.

[0062] like Figure 1 As shown, the proportional amplification path includes a proportional amplifier K0 and a first adder (also called adder 1); wherein, the input terminal of the proportional amplifier K0 is connected to the phase lead pulse signal UP of the phase detection circuit PD output terminal, which is used to output the proportional path control signal VTF_MAIN.

[0063] The first input terminal of the aforementioned first adder is connected to the output terminal of the proportional amplifier, and its second input terminal is connected to the output terminal of the dynamic bandwidth expansion circuit. It is used to add the proportional path control signal VTF_MAIN and the bandwidth expansion tuning signal VTF_AUX to output the synthesized proportional control signal VTF.

[0064] like Figure 1As shown, the integration path includes a voltage-to-current circuit VIC, an external capacitor, and a second adder (also called adder 2). The input of the voltage-to-current circuit VIC is connected to the phase detection circuit PD. The voltage-to-current circuit VIC controls the charging and discharging of the external capacitor and generates an integration path signal VTC, which is input to the second adder. The second adder superimposes the integration path signal VTC and the synthesized proportional control signal VTF to form the input signal VT of the voltage-controlled oscillator, which is then input to the voltage-controlled oscillator VCO.

[0065] A method for dynamic bandwidth expansion and locking acceleration of a clock data recovery circuit includes the following steps.

[0066] S1. The frequency detection circuit FD is used to detect the frequency of the input non-periodic data and the first clock signal CLK90 output by the voltage-controlled oscillator, and a frequency detection pulse signal is generated.

[0067] In this embodiment, the frequency detection pulse signal is preferably obtained by sampling the first clock signal CLK90 by the rising edge of the non-periodic data. The frequency detection pulse signal includes two complementary pulse signals, namely the first pulse signal Q1 and the second pulse signal Q1B.

[0068] S2. The phase detection circuit PD is used to perform phase detection between the input aperiodic data and the second clock signal CLK0 output by the voltage-controlled oscillator, generating a phase-leading pulse signal UP and a phase-lag pulse signal DN. UP and DN represent the phase lag and phase-lead information of the second clock signal CLK0, respectively.

[0069] S3. Perform logical operations on the frequency detection pulse signal, the phase lead pulse signal UP, and the phase lag pulse signal DN to generate the bandwidth extension tuning signal VTF_AUX.

[0070] The logical operation method for the aforementioned bandwidth extended tuning signal VTF_AUX preferably includes the following steps.

[0071] The first auxiliary pulse UP_AUX is generated by latching the phase-leading pulse signal UP with the first pulse signal Q1.

[0072] The phase lag pulse signal DN is latched using the second pulse signal Q1B to generate the second auxiliary pulse DN_AUX.

[0073] The first auxiliary pulse UP_AUX and the second auxiliary pulse DN_AUX are differentially amplified by differential amplifier K1 to obtain the bandwidth extended tuning signal VTF_AUX.

[0074] S4. The bandwidth expansion tuning signal VTF_AUX is superimposed on the proportional path control signal VTF_MAIN of the clock data recovery circuit to output the synthesized proportional control signal VTF, thereby dynamically expanding the loop bandwidth during the effective period of the frequency detection pulse signal. The proportional path control signal VTF_MAIN is obtained by proportionally amplifying the phase-leading pulse signal UP.

[0075] S5. The synthesized proportional control signal VTF and the integral path signal VTC are superimposed to form the input signal VT of the voltage-controlled oscillator, which serves as the control signal for the VCO voltage control terminal to achieve frequency adjustment of the VCO output clock signal.

[0076] The aforementioned integral path signal VTC is obtained by charging and discharging the external capacitor through the control voltage-to-current circuit VIC of the phase-leading pulse signal UP and the phase-lag pulse signal DN. The VTC voltage waveform is the frequency approximation process of the CDR integral path.

[0077] The timing waveform of the dynamic bandwidth extension circuit is as follows: Figure 4 As shown. When CDR is unlocked, the pulse frequencies of the outputs Q1 and Q1B of D flip-flop 1 are close to the frequency difference. During CDR locking, the duty cycle of Q1 gradually decreases. The pulse frequencies of the outputs UP and DN of the Bang-bang PD are also close to the frequency difference when unlocked. Since the sampling clock CLK0 leads CLK90 by 90 degrees, UP and DN also lead Q1 and Q1B by phase. The high-level active latch uses Q1 to latch UP, and the low-level active latch uses Q1B to latch DN, outputting dynamic bandwidth extension pulses UP_AUX and DN_AUX.

[0078] Compare the VT waveforms before and after adding the dynamic bandwidth extension circuit, as follows: Figure 5 As shown, VT serves as the control signal for the VCO voltage-controlled terminal, and its swing amplitude is positively correlated with the CDR loop bandwidth. When the CDR is not locked, the dynamic bandwidth expansion circuit can dynamically widen the bandwidth in each frequency detection pulse cycle, accelerating CDR locking during frequency acquisition. It can be seen that when the VT terminal starts frequency acquisition from the same initial voltage state, the dynamic bandwidth expansion circuit can speed up the acquisition process. When the CDR is locked, the loop bandwidth is switched to the same narrower state as the CDR without bandwidth expansion function, thus suppressing high-frequency data jitter and noise. When periodic jitter is injected into the input data and the CDR is locked, if the amplitude of the injected jitter exceeds the jitter tolerance when the bandwidth expansion function is not enabled, the loop bandwidth expansion function can also be triggered. That is, the CDR can cope with larger jitter amplitudes at the injected jitter frequency without losing lock, thus improving the jitter tolerance performance. Figure 5In the diagram, the red line represents the VT waveform without dynamic bandwidth extension; the blue line represents the VT waveform with dynamic bandwidth extension.

[0079] The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the specific details in the above embodiments. Within the scope of the technical concept of the present invention, various equivalent transformations can be made to the technical solutions of the present invention, and all such equivalent transformations fall within the protection scope of the present invention.

Claims

1. A method for dynamic bandwidth expansion and locking acceleration of a clock data recovery circuit, characterized in that: include: The frequency detection circuit FD is used to detect the frequency of the input aperiodic data and the first clock signal CLK90 output by the voltage-controlled oscillator, and a frequency detection pulse signal is generated. The phase detection circuit PD is used to perform phase detection between the input aperiodic data and the second clock signal CLK0 output by the voltage-controlled oscillator, generating a phase-leading pulse signal UP and a phase-lag pulse signal DN. The frequency detection pulse signal is logically operated with the phase lead pulse signal UP and the phase lag pulse signal DN to generate the bandwidth extended tuning signal VTF_AUX. The bandwidth extension tuning signal VTF_AUX is superimposed on the proportional path control signal VTF_MAIN of the clock data recovery circuit to dynamically extend the loop bandwidth during the effective period of the frequency detection pulse signal.

2. The method for dynamic bandwidth expansion and locking acceleration of clock data recovery circuit according to claim 1, characterized in that: The frequency detection pulse signal is obtained by sampling the first clock signal CLK90 at the rising edge of the non-periodic data. The frequency detection pulse signal includes two complementary pulse signals, namely the first pulse signal Q1 and the second pulse signal Q1B.

3. The clock data recovery circuit dynamic bandwidth expansion and locking acceleration circuit and method according to claim 2, characterized in that: Methods for generating the bandwidth-extended tuned signal VTF_AUX include: The phase-leading pulse signal UP is latched using the first pulse signal Q1 to generate the first auxiliary pulse UP_AUX; The phase lag pulse signal DN is latched using the second pulse signal Q1B to generate the second auxiliary pulse DN_AUX; The bandwidth-extended tuning signal VTF_AUX is obtained by differentially amplifying the first auxiliary pulse UP_AUX and the second auxiliary pulse DN_AUX.

4. The method for dynamic bandwidth expansion and locking acceleration of clock data recovery circuit according to claim 1, characterized in that: When the clock data recovery circuit enters the locked state, the effective width of the frequency detection pulse signal decreases or disappears, the bandwidth extension tuning signal VTF_AUX automatically returns to zero, and the loop bandwidth is restored to the initial narrowband state.

5. The method for dynamic bandwidth expansion and locking acceleration of clock data recovery circuit according to claim 1, characterized in that: Once the clock data recovery circuit is locked, if the jitter amplitude of the input non-periodic data exceeds the preset threshold, the frequency detection pulse signal will regenerate an effective width, triggering the bandwidth expansion tuning signal VTF_AUX to be superimposed again, dynamically widening the loop bandwidth.

6. The method for dynamic bandwidth expansion and locking acceleration of the clock data recovery circuit according to claim 1, characterized in that: The bandwidth extension tuning signal VTF_AUX and the proportional path control signal VTF_MAIN are superimposed to form the synthesized proportional control signal VTF. The synthesized proportional control signal VTF is then superimposed with the integral path signal VTC to form the input signal VT of the voltage-controlled oscillator. Among them, the proportional path control signal VTF_MAIN is obtained by proportionally amplifying the phase lead pulse signal UP; the integral path signal VTC is obtained by controlling the voltage-to-current circuit VIC to charge and discharge the external capacitor through the phase lead pulse signal UP and the phase lag pulse signal DN.

7. A clock data recovery circuit with dynamic bandwidth expansion and locking acceleration, characterized in that: include: A voltage-controlled oscillator (VCO) is used to generate a first clock signal CLK90, a second clock signal CLK0, and a third clock signal CLK180. The frequency detection circuit FD has a first clock signal CLK90 connected to its first input terminal and non-periodic data connected to its second input terminal, which is used to output a frequency detection pulse signal. The phase detection circuit PD has a first clock input terminal connected to a second clock signal CLK0, a second clock input terminal connected to a third clock signal CLK180, and a data input terminal connected to non-periodic data, used to output a phase lead pulse position pulse signal UP and a phase lag pulse signal DN. The dynamic bandwidth expansion circuit has its first input terminal connected to the output terminal of the frequency detection circuit FD, and its second input terminal connected to the output terminal of the phase detection circuit PD. It is used to perform logical operations on the frequency detection pulse signal, the phase lead pulse position signal UP, and the phase lag pulse signal DN, and output the bandwidth expansion tuning signal VTF_AUX. The proportional amplifier has its input connected to the output of the phase detection circuit PD, and is used to output the proportional path control signal VTF_MAIN. The first adder has its first input connected to the output of the proportional amplifier and its second input connected to the output of the dynamic bandwidth expansion circuit. It is used to add the proportional path control signal VTF_MAIN and the bandwidth expansion tuning signal VTF_AUX to output the synthesized proportional control signal VTF.

8. The clock data recovery circuit dynamic bandwidth expansion and locking acceleration circuit according to claim 7, characterized in that: The frequency detection circuit is a first D flip-flop. Its data input terminal is connected to the first clock signal CLK90, its clock terminal is connected to the rising edge of non-periodic data, its non-inverting output terminal outputs the first pulse signal Q1, and its inverting output terminal outputs the second pulse signal Q1B.

9. The clock data recovery circuit dynamic bandwidth expansion and locking acceleration circuit according to claim 8, characterized in that: The dynamic bandwidth expansion circuit includes: A high-level active latch has a data input terminal connected to a phase advance pulse signal UP, a clock terminal connected to a first pulse signal Q1, and outputs a first auxiliary pulse UP_AUX. A low-level active latch has a data input terminal connected to a phase hysteresis pulse signal DN, a clock terminal connected to a second pulse signal Q1B, and an output second auxiliary pulse DN_AUX. Differential amplifier K1 has its positive input connected to the output of a high-level active latch, its negative input connected to the output of a low-level active latch, and its output output is the bandwidth extension tuning signal VTF_AUX.

10. The clock data recovery circuit dynamic bandwidth expansion and locking acceleration circuit according to claim 7, characterized in that: The phase detection circuit is a Bang-bang phase detector, including: The second D flip-flop has a clock input to the second clock signal CLK0 and a data input to non-periodic data, and outputs an early sampling signal Q4. The third D flip-flop has a clock input to the third clock signal CLK180 and a data input to non-periodic data, and outputs a late-sampling signal Q5. The fourth D flip-flop has a late sampling signal Q5 connected to its clock terminal and an early sampling signal Q4 connected to its data terminal, outputting a phase-leading pulse signal UP and a phase-lagging pulse signal DN.

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