Sturdy-mash modulator for single-bit feedback dac and its coefficient optimization method

Abstract

The application provides a Sturdy-MASH modulator suitable for a single-bit feedback DAC and a coefficient optimization method thereof, which is different from a scheme of reducing the amplitude of inter-stage quantization noise by using a multi-bit quantizer or a multi-bit feedback DAC, and the injection path of the first-stage quantization noise into the second-stage CIFF loop is constrained in the modulator; in the circuit implementation, the positive and negative feedback capacitors of the first stage and the second stage are multiplexed by using Double Phase timing, and the switch control logic is simplified in combination with the MASH structure, so that the number of feedback capacitors and logic units is reduced, and the integration and efficiency of the circuit are improved; while ensuring high precision, the system complexity and the saturation risk of the second stage are reduced, and the application is suitable for the design of a Sigma-Delta modulator loaded with a high-performance single-bit DAC; the hierarchical search coefficient optimization method is used, each coefficient is searched in a hierarchical manner from high to low according to the influence degree, and the coefficient optimization complexity is reduced.

Description

Technical Field

[0001] This invention relates to the field of analog-to-digital converters and mixed-signal integrated circuits, specifically to a Sturdy-MASH modulator suitable for single-bit feedback DACs and its coefficient optimization method. Background Technology

[0002] Sigma-Delta modulators are widely used in high-precision analog-to-digital converters (ADCs) and digital signal processing due to their high resolution and excellent noise immunity. To further improve the dynamic range and accuracy of the system, multi-stage cascaded (MASH) structures are often employed. Among them, the Sturdy-MASH structure, as an improved MASH architecture, aims to solve the stability problem caused by improper zero-point placement of the quantization noise transfer function (NTF) in traditional MASH structures, especially in higher-order loops. Traditional Sturdy-MASH modulators typically consist of a first-stage and a second-stage modulation loop. Their core principle is to combine the outputs of the two stages using a specific digital synthesis algorithm to cancel the quantization noise of the first stage while preserving the quantization noise characteristics of the second stage. In existing typical implementations, to achieve this noise cancellation, the output noise of the first-stage quantizer is often injected into the second-stage modulation loop through multiple paths: one path passes through the integrator chain of the second stage, while another path may be directly fed forward to the adder node at the input of the second-stage quantizer.

[0003] However, in practical applications with single-bit DACs or one-bit quantizers, this traditional noise injection method has significant technical drawbacks. Because the first-stage quantization noise is directly superimposed on the input of the second-stage quantizer, it causes a sharp increase in the input signal swing of the second-stage quantizer. When the system is under large signal input or specific frequency excitation, excessive input swing can easily lead to saturation of the second-stage integrator and nonlinear distortion of the quantizer, severely limiting the modulator's dynamic range. Furthermore, to maintain system stability and compensate for the effects of these direct feedforwards, existing techniques often impose strict limitations on coefficient design, making it difficult to optimize circuit linearity and signal-to-noise ratio while ensuring stability. Summary of the Invention

[0004] This invention aims to provide a Sturdy-MASH modulator suitable for single-bit feedback DACs and its coefficient optimization method, which can effectively suppress the input swing of the second-stage quantizer and prevent integrator saturation while maintaining its inherent stability, thereby improving the overall performance and robustness of the system.

[0005] To achieve the above objectives, the technical solution adopted in this invention is as follows: a Sturdy-MASH modulator suitable for a single-bit feedback DAC, comprising a first-stage modulation loop, a second-stage modulation loop, and a digital output synthesis unit connected to the first-stage modulation loop and the second-stage modulation loop; while maintaining the noise processing relationship between Sturdy-MASH stages, the analog injection path of the first-stage quantization noise is limited to entering the second-stage modulation loop only through the input terminal of the first-order integrator of the second stage, and the direct feedforward path from the first-stage quantization noise to the addition node at the input terminal of the second-stage quantizer is disconnected, so as to suppress the direct superposition of the first-stage quantization noise at the input node of the second-stage quantizer and reduce the input swing and saturation risk of the second-stage quantizer.

[0006] To achieve the above objectives, the technical solution adopted in this invention is as follows: a Sturdy-MASH modulator suitable for a single-bit feedback DAC, comprising a first-stage modulation loop, a second-stage modulation loop, and a digital output synthesis unit connected to the first-stage modulation loop and the second-stage modulation loop; while maintaining the noise processing relationship between Sturdy-MASH stages, the analog injection path of the first-stage quantization noise is limited to entering the second-stage modulation loop only through the input terminal of the first-order integrator of the second stage, and the direct feedforward path from the first-stage quantization noise to the addition node at the input terminal of the second-stage quantizer is disconnected, so as to suppress the direct superposition of the first-stage quantization noise at the input node of the second-stage quantizer and reduce the input swing and saturation risk of the second-stage quantizer.

[0007] Preferably, the second-stage modulation loop adopts a second-order CIFF structure; when the first-stage quantization noise is used as the input signal of the second-stage CIFF loop, it is applied to the input terminal of the second-stage first integrator only through the second-stage first-order input coefficient b1_2.

[0008] Preferably, the digital output synthesis unit performs first-level quantization output. Second-level quantization output Combined, the modulator output signal is generated. : ;in, This is the digital synthesis scaling factor for the second-stage output; depending on the requirements of the subsequent interface, the output normalization factor can also be set; the second-stage quantization output signal satisfies: in This is the second-order signal transfer function. This is the second-order noise transfer function. This is the second level of quantization noise. For inter-stage injection coefficients, This represents the first level of quantization noise.

[0009] Preferably, in a single-bit feedback DAC or a one-bit quantizer implementation, the and Take the integer value; in the implementation of a multi-bit quantizer or multi-code-value quantizer, the... It can be set to a decimal value.

[0010] Preferably, the first-stage quantization noise is obtained by subtracting the first-stage input signal, the first-stage first-order integrator output signal, and the first-stage second-order integrator output signal from the first-stage quantizer output signal.

[0011] Preferably, the first-stage modulation loop and the second-stage modulation loop use Double Phase timing for feedback capacitor reuse.

[0012] Preferably, the feedback capacitor reuses the positive and negative feedback capacitors of the first and second stages, and combines the corresponding switching control logic to reduce the number of feedback capacitors and the number of switching logic control units.

[0013] Preferably, the feedback capacitor reuse is combined with the noise injection path between restricted stages to realize positive and negative feedback capacitor reuse and switching logic merging in the first-stage quantization noise extraction and the second-stage noise injection link, thereby reducing the complexity of circuit implementation.

[0014] On the other hand, this invention proposes a coefficient optimization method for Sturdy-MASH modulators suitable for single-bit DACs, including the following steps: establishing a modulator behavior-level model containing inter-stage noise injection paths; analyzing the impact of each loop coefficient on the swing of the second-stage integrator, the input swing of the quantizer, stability, and output accuracy; Establish coefficient priorities based on the degree of impact, and distinguish between key coefficients that dominate saturation risk and auxiliary adjustment coefficients; perform hierarchical step traversal according to priority, with higher priority coefficients using smaller steps and lower priority coefficients using larger steps; apply integrator swing, quantizer input swing, stability and in-band noise constraints during the traversal process. The output coefficients combine anti-saturation performance and high precision performance.

[0015] Preferably, the coefficient priority includes c2_1, a1_1, a2_1, a1_2, and a2_2; among which c2_1 has the greatest impact on the second-stage swing amplitude and stability, a1_1 and a2_1 have the next greatest impact on the first-stage noise transfer function, dynamic range, and inter-stage noise amplitude, and a1_2 and a2_2 are used for second-stage performance fine-tuning; each coefficient is searched in a hierarchical manner according to its degree of influence from high to low.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: (1) By reconstructing the noise processing relationship between stages, this invention strictly limits the analog injection path of the first-stage quantization noise to only enter the second-stage modulation loop through the input terminal of the first-order integrator of the second stage, and completely disconnects the direct feedforward path from the first-stage quantization noise to the addition node at the input terminal of the second-stage quantizer. This improvement directly eliminates the direct superposition effect of the first-stage quantization noise at the input node of the second-stage quantizer, significantly reduces the input swing of the second-stage quantizer, effectively avoids the saturation risk of the integrator and quantizer under large signals, and thus greatly improves the dynamic range and linearity of the modulator. (2) Combining the priority-based hierarchical step traversal coefficient optimization method, the coefficients of each loop can be accurately determined. This method performs hierarchical search based on the degree of influence of the coefficients on the integrator swing, stability and output accuracy. Under the premise of ensuring anti-saturation performance, it further optimizes the in-band noise characteristics and system stability, and achieves the best balance between high accuracy and high robustness. (3) By introducing feedback capacitor reuse technology under Double Phase timing and combining it with a limited noise injection path, the number of feedback capacitors and the number of switching logic control units in the circuit are further reduced, reducing the complexity and power consumption of the circuit implementation. It is particularly suitable for single-bit DAC application scenarios that are sensitive to area and power consumption. On the basis of ensuring the stability of the Sturdy-MASH structure, it solves the technical bottleneck of easy saturation of the second stage in single-bit applications and significantly improves the overall performance of the modulator. Attached Figure Description

[0017] Figure 1 This is a MATLAB model diagram of the Sturdy-MASH 2-2 single-bit feedback DAC modulator of this invention; Figure 2 This is a circuit diagram of the Sturdy-MASH 2-2 single-bit feedback DAC modulator of the present invention; Figure 3 This is a schematic diagram of the power spectral density (PSD) of the modulator of the Sturdy-MASH 2-2 single-bit feedback DAC of the present invention. Detailed Implementation

[0018] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used herein in the specification of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the terms "comprising" and "having," and any variations thereof, in the specification, claims, and foregoing drawings of this application are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or foregoing drawings of this application are used to distinguish different objects, not to describe a particular order.

[0019] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0020] The following description is intended to disclose the invention and enable those skilled in the art to implement it. The preferred embodiments described below are merely examples, and other obvious variations will occur to those skilled in the art.

[0021] like Figure 1 and Figure 3 As shown, this invention proposes a Sturdy-MASH modulator suitable for a single-bit feedback DAC, including a first-stage modulation loop, a second-stage modulation loop, and a digital output synthesis unit connected to the first-stage modulation loop and the second-stage modulation loop; While maintaining the noise processing relationship between Sturdy-MASH levels, the analog injection path of the first-stage quantization noise is limited to entering the second-stage modulation loop only through the input terminal of the first-order integrator of the second stage. Furthermore, the direct feedforward path from the first-stage quantization noise to the addition node at the input terminal of the second-stage quantizer is disconnected to suppress the direct superposition of the first-stage quantization noise at the input node of the second-stage quantizer and reduce the input swing and saturation risk of the second-stage quantizer.

[0022] The second-stage modulation loop employs a second-order CIFF structure, comprising a two-stage integrator, a first-stage quantizer Q1, a feedforward / feedback coefficient branch, and a single-bit feedback DAC. Input signal After being filtered by the first-stage modulation loop, the signal enters Q1 to obtain the first-stage quantization output. When the first-stage quantization noise is used as the input signal for the second-stage CIFF loop, it only affects the input of the first integrator of the second stage through the first-order input coefficient b1_2 of the second stage.

[0023] The second-stage modulation loop can also employ a second-order CIFF structure, including two-stage integrators, a second-stage quantizer Q2, and feedforward / feedback branches. Its input is the first-stage quantization noise. rather than the original input signal .

[0024] This embodiment is limited by the interstage noise processing relationship of the Sturdy-MASH 2-2 single-bit DAC. Simulated injection path: Only the first input coefficient b1_2 of the second stage is injected into the input terminal of the first integrator of the second stage; at the same time, its direct feedforward path to the input adder of the second stage quantizer is canceled, that is, b3_2=0.

[0025] The above-mentioned restricted injection paths can be avoided The input node of the second-stage quantizer is directly superimposed with the signal inside the loop, thereby reducing the input swing of the second-stage quantizer. This is particularly suitable for situations where the quantization noise amplitude is large under single-bit feedback DAC or one-bit quantizer.

[0026] The digital output synthesis unit outputs the first-level quantization output V1z and the second-level quantization output. Combined, the modulator output signal is generated. : ;in, This is the scaling factor for the digital synthesis of the second-stage output; depending on the requirements of the subsequent interface, it can also be... The output normalization coefficient can be set.

[0027] Specifically, the first-stage quantization noise extraction and restricted injection method is as follows: The input of the first-stage quantizer Q1 is denoted as... The first-level quantization output is denoted as ,but: ;in, This represents the first level of quantization noise.

[0028] The first-level quantization noise can be obtained by adding or subtracting the output of the first-level quantizer, the first-level input, and the outputs of each integrator. In one specific implementation, the relationship is as follows: In circuit implementation, the result can be obtained by subtracting the weighted sum of the input signal and the outputs of the two integrators from the output signal of the first-stage quantizer. This signal is sent to the input of the first integrator of the second stage only through the b1_2 path, and is not sent to the input adder node of the second stage quantizer separately.

[0029] coefficient After scaling, the signal is fed into the second-stage modulation loop. The output of the second stage can be expressed as: ;in, This is the second-order signal transfer function. This is the second-order noise transfer function. This is the second level of quantization noise. This represents the interstage injection coefficient.

[0030] In a single-bit feedback DAC or a one-bit quantizer implementation, the and Take the integer value; in the implementation of a multi-bit quantizer or multi-code-value quantizer, the... It can be set to a decimal value. The total output of the modulator can be expressed as: in, and These are the first-level signal transfer function and the noise transfer function, respectively.

[0031] In a preferred embodiment, the second level is configured as a unit signal transfer function (USTF) structure, such that: And order: The first-order quantization noise term then satisfies: therefore, It can be canceled out in digital output synthesis, and the output mainly retains the waveform. The shaped second-stage quantization noise component. A constrained injection path, combined with digital cancellation, can reduce the second-stage input swing without using a multi-bit feedback DAC. For single-bit feedback DACs or one-bit quantizers, this is to avoid introducing fractional noise through the main feedback path. Coefficients, preferably selected as follows: This simplifies the digital synthesis relationship and feedback DAC implementation. When using a dual-code or multi-code quantizer, The value can be set to a small value according to the system noise shaping target, for example... However, in a single-bit feedback DAC, it is preferable to use integer coefficients to keep the implementation simple.

[0032] Specifically, the transfer function of the second-order CIFF loop is configured as follows: For the second-order CIFF Sigma-Delta loop in this embodiment, its transfer function can be expressed as: Where a1 and a2 are feedforward coefficients, b1 and b3 are input feedforward coefficients, and c1 and c2 are feedback or integrator scaling correlation coefficients. For the second-stage modulation loop, this embodiment omits... The input to the second-stage quantizer is fed forward directly into the second-stage quantizer's input adder. Therefore, b3_2 = 0, and the coefficients b1_2, a1_2, a2_2, c1_2, and c2_2 are adjusted to ensure that the second stage satisfies unit or approximate conditions within the target bandwidth. Unit signal transfer function, and avoid It is directly superimposed onto the input of the second-stage quantizer.

[0033] Therefore, this embodiment achieves the robust noise shaping effect of Sturdy-MASH under a single-bit feedback DAC, while avoiding the matching, DEM and calibration complexity of multi-bit DACs, and providing path-level suppression for the second-stage large swing.

[0034] This embodiment also provides a method for determining coefficients. This method first analyzes the impact of each coefficient on saturation and accuracy, then performs a hierarchical search according to priority, avoiding indiscriminate global traversal.

[0035] In one specific implementation, the method includes establishing a modulator behavior-level model containing inter-stage noise injection paths; analyzing the impact of each loop coefficient on the swing of the second-stage integrator, the input swing of the quantizer, stability, and output accuracy; establishing coefficient priorities based on the degree of impact, distinguishing between key coefficients that dominate saturation risk and auxiliary adjustment coefficients; performing a graded step traversal according to priority, where high-priority coefficients use smaller steps and low-priority coefficients use larger steps; applying integrator swing, quantizer input swing, stability, and in-band noise constraints during the traversal; and outputting a coefficient set that balances anti-saturation performance and high accuracy, as follows: Step S1: Establish a behavioral-level model; Establish a Sturdy-MASH behavioral-level model of a single-bit feedback DAC, which includes a two-stage CIFF loop, a quantization noise extraction path, an inter-stage injection path, and a digital output synthesis path, and disable the direct feedforward path at the input of the second-stage quantizer; Step S2: Generate initial coefficients; generate a combination of initial coefficients based on the target sampling rate, oversampling rate, signal bandwidth, target signal-to-noise ratio, and loop order; Step S3: Fix the restricted injection structure; in the second stage The path directly feedforward to the input of the second-stage quantizer is closed, i.e., b3_2 = 0; and reserved. The path injected into the input terminal of the second-stage first integrator via b1_2; Step S4: Establish a coefficient priority graph; analyze the impact of each coefficient on the second-stage swing and stability through simulation. The priority can be set as: c2_1 → a1_1 → a2_1 → a1_2 → a2_2; among them, c2_1 has the greatest impact on the second-stage swing and stability; a1_1 and a2_1 have the next greatest impact on the first-stage NTF, output swing, and inter-stage noise amplitude; a1_2 and a2_2 are used for fine-tuning the second-stage performance. Step S5: Perform a hierarchical step-by-step traversal according to priority; set different step values ​​according to the degree of influence: high priority coefficients use small steps for fine-grained search, and low priority coefficients use larger steps for coarse-grained search. In one implementation: Δc2_1 < Δa1_1 < Δa2_1 < Δa1_2 < Δa2_2; that is, the lower the degree of influence, the larger the search step. Step S6: Apply swing and stability constraints; in each search stage, determine whether the integrator output swing, the second-stage quantizer input swing, stability, output spectrum, and in-band noise meet the preset conditions; for single-bit Sturdy-MASH, the peak value or peak-to-peak value of the second-stage quantizer input can be used as the priority constraint index. Step S7: Proceed through the effective coefficient intervals level by level; if the current coefficient satisfies the constraints, its candidate interval is passed to the next priority search; otherwise, discard or narrow the interval until the coefficients c2_1, a1_1, a2_1, a1_2, and a2_2 awaiting optimization are determined; this method can narrow the search space and prioritize the coefficients most sensitive to the second-level saturation. By combining the noise injection path between restricted stages, a coefficient combination that balances saturation prevention and high accuracy can be obtained more quickly.

[0036] Furthermore, a positive and negative feedback capacitor multiplexing and merging control circuit based on Double Phase timing is implemented, as shown in Figure 2. This embodiment can be implemented using a fully differential switched capacitor circuit, including a two-stage integrator group, comparators Comp_1 / Comp_2, a single-bit DAC, sampling capacitors, integrating capacitors, and a feedforward / feedback capacitor array. The first stage includes A1_1, A2_1, integrating capacitors Ci1_1 / Ci2_1, sampling capacitor Cs1_1, feedback capacitor Cf_1, and feedforward capacitors Cff0_1, Cff1_1, and Cff2_1. The second stage includes A1_2, A2_2, integrating capacitors Ci1_2 / Ci2_2, sampling capacitor Cs1_2, feedback capacitor Cf_2, and feedforward capacitors Cff1_2 and Cff2_2.

[0037] Comp_1 and Comp_2 generate quantized outputs M1 and M2, respectively. The feedback DAC switching logic generates control signals such as C1 and C2 based on M1, M2, and timing signals to switch the connection of the feedback capacitor with VREFP, VREFN, or VCM. The Double Phase timing includes P1, P2, and delayed phases P1D and P2D, used for implementation... The sampling, integration, feedback update, and comparator output delay are coordinated. In phase P1, the sampling capacitor samples the input, reference, or common-mode voltage; in phase P2, the sampled charge is transferred to the integrator input. Phases P1D and P2D are used to control the connection timing of the feedback capacitor and the inter-stage noise extraction capacitor, ensuring that the comparator output and the DAC decoding signal operate in the correct timing. The first-stage modulation loop and the second-stage modulation loop use double-phase timing for feedback capacitor reuse; the positive and negative feedback capacitors of the first and second stages are reused, and the corresponding switching control logic is combined to reduce the number of feedback capacitors and the number of switching logic control units. The feedback capacitor reuse is combined with the restricted inter-stage noise injection path to achieve positive and negative feedback capacitor reuse and switching logic merging in the first-stage quantization noise extraction and second-stage noise injection links, thereby reducing the circuit implementation complexity.

[0038] Because this embodiment uses a restricted inter-stage noise injection path. Only the input terminal of the first integrator of the second stage needs to be injected, and there is no need to set a feedforward capacitor path that directly enters the input terminal of the second stage quantizer. Therefore, the feedforward capacitor and switching control corresponding to the b3_2 path can be reduced.

[0039] In Double Phase timing, the positive and negative feedback capacitors of the first and second stages can be multiplexed in different phases: one phase is used for feedback DAC, and the other phase is used for noise injection, thereby reducing the number of capacitor arrays.

[0040] For single-bit feedback DACs, the positive and negative feedback control signals are typically complementary. This embodiment combines the positive and negative feedback switching control logic, eliminating the need for completely independent control units for the positive and negative feedback paths in the feedback DAC decoding logic, thus reducing the related switching logic by approximately half.

[0041] With the reduction of feedback capacitors and switching logic, the load on the sampling node, parasitic capacitance, and switching coupling are reduced accordingly, which helps to reduce the operational amplifier drive burden, improve the setup speed, and mitigate the risk of saturation at the input of the second-stage quantizer.

[0042] Furthermore, the preferred operating mode of the single-bit feedback DAC is as follows: In this embodiment, the feedback DAC adopts a single-bit or one-bit feedback structure, and its output switches between VREFP, VREFN, and VCM related states. Compared with multi-bit feedback DACs, this structure does not require complex cell matching and DEM circuits, has high linearity, and is simple to implement; however, due to the large quantization error of the single-bit feedback DAC, and the Sturdy-MASH... and To mitigate the risk of second-stage saturation in the output synthesis, this embodiment employs the following methods: First, E1z is restricted to being injected into the input of the first integrator of the second stage only through b1_2; second, b3_2 is set to 0 to prevent E1z from being directly superimposed onto the input of the second-stage quantizer; third, key coefficients such as c2_1, a1_1, a2_1, a1_2, and a2_2 are optimized through hierarchical coefficient search to ensure that the output swing of the second-stage integrator and the input swing of the quantizer satisfy the constraints.

[0043] Therefore, this embodiment maintains the high linearity advantage of a single-bit feedback DAC while improving the problem of easy saturation in the second stage of a single-bit Sturdy-MASH.

[0044] The above embodiment uses a 2-2 Sturdy-MASH as an example, but the core of this invention is not limited to the loop order. As long as the first-stage quantization noise is injected only through the second-stage front-end integration path and not directly fed forward to the input of the second-stage quantizer, other orders of Sigma-Delta loops are also equivalently implemented.

[0045] The second-stage modulation loop preferably adopts a CIFF structure, but a CIFB or CIFF / CIFB hybrid structure can also be used. As long as the first-stage quantization noise can be prevented from being directly superimposed on the input of the second-stage quantizer, and noise shaping, digital cancellation, and swing suppression can be achieved through coefficient configuration, it falls within the scope of protection of this invention.

[0046] The feedback DAC is preferably a single-bit or one-bit feedback DAC. Other dual- or multi-code-value quantizers can be used, and the correlation coefficient can be adjusted according to the code value range without affecting the core concept of this invention regarding inter-stage noise injection and low saturation risk.

[0047] Double Phase timing is not used alone as a conventional capacitor reuse, but is combined with inter-stage noise injection path and positive and negative feedback merging control; by reusing positive and negative feedback capacitors and merging switching logic, the positive and negative feedback switching control logic can be reduced by about half.

[0048] In summary, this invention presents a Sturdy-MASH Sigma-Delta modulator for single-bit feedback DACs. It reduces the input swing and saturation risk of the second-stage quantizer by limiting the inter-stage noise injection path; improves optimization efficiency by hierarchical coefficient search; and reduces feedback capacitance and switching logic by using double-phase capacitor reuse and positive and negative feedback combined control, thereby achieving a balance between high precision, low saturation risk, and circuit simplification.

[0049] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claimed invention. The scope of protection claimed by the appended claims and their equivalents is defined.

Claims

1. A Sturdy-MASH modulator suitable for a single-bit feedback DAC, comprising a first-stage modulation loop, a second-stage modulation loop, and a digital output synthesis unit connected to the first-stage modulation loop and the second-stage modulation loop, characterized in that: While maintaining the noise processing relationship between Sturdy-MASH levels, the analog injection path of the first-stage quantization noise is limited to entering the second-stage modulation loop only through the input terminal of the first-order integrator of the second stage. Furthermore, the direct feedforward path from the first-stage quantization noise to the addition node at the input terminal of the second-stage quantizer is disconnected to suppress the direct superposition of the first-stage quantization noise at the input node of the second-stage quantizer and reduce the input swing and saturation risk of the second-stage quantizer.

2. The Sturdy-MASH modulator for a single-bit feedback DAC according to claim 1, characterized in that, The second-stage modulation loop adopts a second-order CIFF structure; when the first-stage quantization noise is used as the input signal of the second-stage CIFF loop, it is applied to the input terminal of the first integrator of the second stage only through the first-order input coefficient b1_2 of the second stage.

3. The Sturdy-MASH modulator for a single-bit feedback DAC according to claim 2, characterized in that, The digital output synthesis unit outputs the first-level quantization. Second-level quantization output Combined, the modulator output signal is generated. : ;in, This is the digital synthesis scaling factor for the second-stage output; depending on the requirements of the subsequent interface, the output normalization factor can also be set; the second-stage quantization output signal satisfies: ;in, This is the second-order signal transfer function. This is the second-order noise transfer function. This is the second level of quantization noise. For inter-stage injection coefficients, This represents the first level of quantization noise.

4. The Sturdy-MASH modulator for a single-bit feedback DAC according to claim 3, characterized in that, In a single-bit feedback DAC or a one-bit quantizer implementation, the and Take the integer value; in the implementation of a multi-bit quantizer or multi-code-value quantizer, the... It can be set to a decimal value.

5. The Sturdy-MASH modulator for a single-bit feedback DAC according to claim 1, characterized in that, The first-stage quantization noise is obtained by subtracting the first-stage input signal, the first-stage first-order integrator output signal, and the first-stage second-order integrator output signal from the first-stage quantizer output signal.

6. The Sturdy-MASH modulator for a single-bit feedback DAC according to claim 5, characterized in that, The first-stage modulation loop and the second-stage modulation loop use Double Phase timing for feedback capacitor reuse.

7. The Sturdy-MASH modulator for a single-bit feedback DAC according to claim 6, characterized in that, The feedback capacitors reuse the positive and negative feedback capacitors of the first and second stages, and combine the corresponding switching control logic to reduce the number of feedback capacitors and the number of switching logic control units.

8. The Sturdy-MASH modulator for a single-bit feedback DAC according to claim 6, characterized in that, The combination of feedback capacitor reuse and inter-stage noise injection path enables positive and negative feedback capacitor reuse and switching logic merging in the first-stage quantization noise extraction and second-stage noise injection links, thereby reducing the complexity of circuit implementation.

9. A coefficient optimization method for a Sturdy-MASH modulator suitable for a single-bit feedback DAC as described in any one of claims 1-8, characterized in that, The process includes the following steps: establishing a modulator behavior-level model that includes inter-stage noise injection paths; analyzing the impact of each loop coefficient on the swing of the second-stage integrator, the input swing of the quantizer, stability, and output accuracy; establishing coefficient priorities based on the degree of impact, distinguishing between key coefficients that dominate saturation risk and auxiliary adjustment coefficients; performing a graded step traversal according to priority, with higher priority coefficients using smaller steps and lower priority coefficients using larger steps; applying constraints on integrator swing, quantizer input swing, stability, and in-band noise during the traversal; and outputting a coefficient combination that balances anti-saturation performance and high accuracy.

10. The coefficient optimization method according to claim 9, characterized in that, The coefficient priorities include c2_1, a1_1, a2_1, a1_2, and a2_2; among them, c2_1 has the greatest impact on the second-stage swing amplitude and stability, a1_1 and a2_1 have the next greatest impact on the first-stage noise transfer function, dynamic range, and inter-stage noise amplitude, and a1_2 and a2_2 are used for fine-tuning the second-stage performance; each coefficient is searched in a hierarchical manner according to its degree of influence from high to low.

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