Sigma-delta sampling and integrating circuit and system

Abstract

The application discloses a Sigma-Delta sampling and calculation integrated system and belongs to the field of sampling and calculation integrated chip design. The sampling and calculation circuit comprises an integrator, a quantizer, a digital-to-analog converter and a subtractor and works through a closed loop feedback loop; a feedback coefficient is introduced before a feedback signal is input into the subtractor after the analog signal is multiplied by a multiplication coefficient as input; the subtractor subtracts the input analog signal from the feedback signal of the digital-to-analog converter to obtain an error signal; the integrator sends the integrated error signal to the quantizer to convert the analog domain error signal into a digital domain pulse frequency signal; the digital-to-analog converter takes the digital domain pulse frequency signal as input, generates an analog domain feedback signal, sends the feedback signal to the input end of the subtractor through the closed loop feedback loop and forms cyclic modulation. The application realizes accurate conversion from an analog voltage to a pulse frequency and mixed signal domain multiplication calculation, thereby realizing a high-robustness sampling and calculation integrated mechanism based on Sigma-Delta modulation.

Description

Technical Field

[0001] This invention belongs to the field of integrated sensing and computing chip design, and more specifically, relates to a Sigma-Delta sensing circuit and an integrated sensing and computing system. Background Technology

[0002] With the rapid development of technologies such as Artificial Intelligence (AI), Big Data, and the Internet of Things (IoT), machine vision systems are widely used in fields such as intelligent security, autonomous driving, medical imaging, and industrial inspection. As a core component of machine vision systems, image sensors possess advantages such as small size, high integration, and low cost. They can efficiently convert captured light signals into electrical signals, making them one of the mainstream image acquisition solutions. However, traditional image sensors only handle image perception tasks, and the entire vision system function is achieved through a serial architecture of "sampling-transmission-processing" between the sensor and the backend image processing unit. This "perception-computation" separation mechanism under the von Neumann architecture has exposed a series of latency and energy efficiency bottlenecks in the context of the current explosive growth of IoT data, highly computationally intensive AI tasks, and limited hardware computing resources.

[0003] First, traditional image sensors output unprocessed raw image data, which is large in volume and contains a lot of redundant information. This data must be transmitted to the backend AI computing chip via a high-speed analog front-end signal link for preprocessing and inference. This high-bandwidth transmission not only leads to significant energy consumption and latency but also increases the complexity of hardware interface design, hindering the miniaturization and low-power requirements of terminal devices. Second, the pixel array inside the image sensor is read out row by row using a row-column scanning method, which limits the frame rate and cannot meet the real-time requirements of high-throughput scenarios. Furthermore, the direct transmission of raw image data also poses a certain risk of data leakage and makes it difficult to protect user privacy.

[0004] To address the aforementioned issues, academia and industry have begun exploring the integration of image processing capabilities at the sensing end, embedding computer vision image processing and even AI image inference functions within image sensors, proposing a "perception-computation integration" (perception-computation integration) chip architecture. This type of architecture deeply integrates image perception and computational processing functions, typically integrating perception processing logic directly into pixel arrays, analog front-end signal circuits, or analog-to-digital converters (ADCs). Among these, the ADC-based approach is referred to as a "sampling-computation integration" (sampling-computation integration) circuit. This type of architecture can complete basic operations such as motion detection and feature extraction during the image generation stage, significantly reducing data transmission volume and effectively improving the system's energy efficiency and response speed, thus becoming an important development direction for edge AI perception systems. In particular, convolution or multiply-accumulate operations, as key operators in computer vision processing, possess strong expressive power in feature extraction due to their local connectivity and weight sharing characteristics. Integrating convolutional computation capabilities into image sensors allows for primary visual perception to be completed simultaneously with image sampling, simplifying the back-end network structure and improving system real-time performance.

[0005] However, most existing integrated sensing and computing architectures employ analog computing schemes based on switched capacitors, which are severely affected by switching noise and capacitor mismatch, resulting in large calculation errors and low linearity. Furthermore, the computing principles remain based on traditional charge sharing or charge redistribution mechanisms, failing to achieve new breakthroughs. In addition, existing integrated sensing and computing circuits are not designed in conjunction with AI algorithms; the computing circuits are merely simple implementations and functionalities of a small portion of the algorithms. Complete system functionality still primarily relies on backend digital AI computing chips, limiting the scope of application and practical implementation.

[0006] Therefore, there is an urgent need to propose a sampling and calculation circuit that can perform signal calculations while sampling and quantizing analog signals. Summary of the Invention

[0007] In view of the shortcomings of related technologies, the purpose of this invention is to provide a Sigma-Delta acquisition circuit and an integrated sensing and computing system, which aims to solve the problem that existing acquisition circuits cannot perform signal calculations while sampling and quantizing analog signals.

[0008] To achieve the above objectives, in a first aspect, the present invention provides a Sigma-Delta acquisition circuit, comprising: an input multiplier circuit, an integrator, a quantizer, a digital-to-analog converter, a feedback multiplier circuit, and a subtractor, which operates through a closed-loop feedback loop; The input multiplier circuit is used to multiply the input analog signal. With multiplication factor After multiplication, the adjusted analog signal is obtained and output to the subtractor; The subtractor is used to subtract the adjusted analog signal from the feedback signal of the digital-to-analog converter to obtain the error signal; The integrator is used to integrate the error signal and then send it to the quantizer; The quantizer is used to convert the integrated error signal into a pulse frequency signal in the digital domain, and serves as the input of the digital-to-analog converter and the output of the Sigma-Delta acquisition circuit, respectively. The digital-to-analog converter is used to receive pulse frequency signals in the digital domain, convert them to the analog domain, obtain feedback signals, and output them to the feedback multiplier circuit. The feedback multiplier circuit is used to combine the feedback signal with the feedback coefficient. After multiplication, the result is output to the subtractor to form a cyclic modulation.

[0009] Optionally, the Sigma-Delta computing circuit includes two operating modes: analog-to-digital conversion mode and computing mode. In analog-to-digital conversion mode, the multiplication factor and feedback coefficient The values ​​are equal; In calculation mode, adjust the coefficients. The value is adjustable, and the mean expression of the output pulse frequency signal of the Sigma-Delta acquisition circuit is:

[0010] in, The average value of the pulse frequency signal. , ,and It is an integer; For adjustable numerical weights, This is the power supply voltage for the Sigma-Delta acquisition circuit.

[0011] Optionally, the integrator includes a set of mirror-symmetric switched capacitor networks and an operational amplifier.

[0012] Optionally, when the quantizer outputs a high level, the voltage of the feedback signal of the digital-to-analog converter is equal to the power supply level; When the quantizer outputs a low level, the voltage of the feedback signal of the digital-to-analog converter is equal to the ground level.

[0013] In a second aspect, the present invention also provides an event-driven sensing and computing integrated system for target detection, including the Sigma-Delta acquisition circuit as described in any one of the first aspects.

[0014] Optional components also include: a pixel array, a background subtraction circuit, a threshold comparator, a region of interest extraction circuit, a spiking neural network recognition circuit, and a counter; The pixel array is used to convert the light signal corresponding to the input scene image under test into an unprocessed analog pixel signal under the action of the control signal; The background subtraction circuit is used to suppress noise in the unprocessed analog pixel signal, and in imaging mode, the noise-suppressed analog pixel signal is used as the signal to be processed and output to the Sigma-Delta acquisition circuit; in calculation mode, the pixel signal of the moving target is extracted from the noise-suppressed analog pixel signal as the signal to be processed and the background-subtracted pixel signal is output. The threshold comparator is used to perform binarization on the signal to be processed and extract event pixels; The region of interest extraction circuit is used to perform connectivity analysis on the event pixels, generate a minimum motion region window, and output the region of interest image. The Sigma-Delta acquisition circuit is used to perform Sigma-Delta modulation on the pixel signals in the image of interest to obtain the pulse frequency signal corresponding to the event stream information. The pulse neural network recognition circuit is used to receive the pulse frequency signal, perform moving target recognition, and after successful recognition, control the Sigma-Delta acquisition circuit to work in analog-to-digital conversion mode to convert the pixel voltage of the original image into a pulse frequency signal and output it to the counter. The counter is used to count the pulse frequency signal output by the Sigma-Delta acquisition circuit to generate the original image.

[0015] Optionally, a digital accelerator for object detection may also be included; The target detection digital accelerator is used to receive the original image output by the counter and to perform target detection, localization and tracking of target objects in the region of interest.

[0016] Optionally, the background subtraction circuit includes a pixel input VPX, a sampling capacitor CS, a reset capacitor CR, a differential amplifier, and a background voltage input terminal VBG; The first output of the pixel input is connected to the upper plate of the sampling capacitor CS through the first switch under the control of the sampling enable signal S, and the second output is connected to the upper plate of the reset capacitor CR through the second switch under the control of the sampling enable signal R. The lower plate of the CS capacitor is grounded; the lower plate of the CR capacitor is connected to VBG and ground respectively through two parallel switches at different timing stages; and the upper plates of the sampling capacitor CS and the reset capacitor CR are connected to the positive and negative input terminals of the differential amplifier respectively through corresponding switches under the control of the output enable signal Y. When CDS is high: the upper plate of the reset capacitor CR is connected to the reset signal, and the lower plate of the reset capacitor CR is connected to GND; the background subtraction circuit operates in imaging mode. When CDS is low: when the reset enable signal R is high, the upper plate of the reset capacitor CR is connected to the reset signal, and the lower plate of the reset capacitor CR is connected to the background voltage signal. When the output enable signal Y is high, the upper plate of the reset capacitor CR is connected to the negative input terminal of the differential amplifier, and the lower plate of the reset capacitor CR is connected to GND; the background subtraction circuit operates in calculation mode.

[0017] Compared with the prior art, the above-described technical solutions conceived in this invention can achieve the following beneficial effects: 1. The Sigma-Delta acquisition circuit provided in this embodiment of the invention multiplies the analog signal by using an input multiplier circuit when the analog signal is input. With multiplication factor Multiplication is performed by multiplying the feedback signal with the feedback coefficient through a feedback multiplier circuit. Multiplication maps the input signal to the desired value in the mixed-signal domain according to a set ratio. The modulator circuit of the Sigma-Delta analog-to-digital converter in the Sigma-Delta acquisition circuit achieves accurate conversion from analog voltage to pulse frequency and mixed-signal domain multiplication calculation, replacing the traditional charge-sharing calculation scheme which is susceptible to process fluctuations, and offering both high accuracy and high stability. Simultaneously, pulse encoding is completed using the modulator's built-in Sigma-Delta signal modulation, directly providing pulse signal input for subsequent pulse neural network recognition without the overhead of additional pulse encoding circuitry. This realizes a highly robust integrated acquisition and processing mechanism based on Sigma-Delta modulation.

[0018] 2. The event-driven sensing and computing integrated system for target detection provided in this embodiment of the invention adopts an event-driven sensing and computing integrated system architecture. It integrates multi-stage processing modules such as image sampling, motion detection, region of interest extraction, and target recognition at the sensor level, constructing a closed-loop path from image generation to target detection. This effectively breaks the traditional serial "sampling-transmission-processing" mechanism. Through algorithm-circuit-architecture co-design, it achieves a closed-loop target detection function at the system level, reducing data transmission bandwidth and latency, and improving the overall system energy efficiency and real-time performance. It is suitable for deployment in power-sensitive edge vision systems with high response requirements, and has broad application prospects and industrial value. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of a Sigma-Delta acquisition circuit provided in an embodiment of the present invention; Figure 2 This is a circuit diagram of an integrator in a Sigma-Delta acquisition circuit provided in an embodiment of the present invention; Figure 3 This is an architecture diagram of an event-driven sensing and computing integrated system for target detection provided in an embodiment of the present invention; Figure 4 This is a circuit diagram of background subtraction in the event-driven sensing and computing integrated system for target detection provided in an embodiment of the present invention. Figure 5 This is a flowchart of the event-driven sensing and computing integrated system for target detection provided in an embodiment of the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0021] The following description, in conjunction with a preferred embodiment, illustrates the content involved in the above embodiments.

[0022] Example 1 Traditional image sensors only perform image sampling during the sensing phase, requiring the transmission of large amounts of raw image data to backend AI chips for processing. This results in high bandwidth demands and reduced system energy efficiency. While existing integrated sensing and computing solutions integrate some computing modules at the sensing end, they often employ noise-sensitive analog computing methods such as switched capacitors, which have limited accuracy, poor robustness, and lack co-design with AI recognition algorithms. Consequently, the system lacks closed-loop integrity and struggles to independently complete target detection tasks in various application scenarios.

[0023] Existing integrated sensing and computing circuits fail to be designed in tandem with AI algorithms. The computing circuits are merely simple implementations and functionalities of a small portion of the algorithms, while the complete system functionality still relies primarily on the backend digital AI computing chip, limiting the scope of application and practical implementation. To address the problem that existing sensing and computing circuits cannot perform signal calculations while sampling and quantizing analog signals, this invention provides a Sigma-Delta integrated sensing and computing circuit.

[0024] like Figure 1As shown, a Sigma-Delta acquisition circuit includes: an input multiplier circuit, an integrator, a 1-bit quantizer, a 1-bit digital-to-analog converter, a feedback multiplier circuit, and a subtractor, which operates through a closed-loop feedback loop; The input multiplier circuit is used to multiply the input analog signal. With multiplication factor After multiplication, input the result into the subtractor; The subtractor is used to subtract the adjusted analog signal from the feedback signal of the digital-to-analog converter to obtain the error signal; The integrator is used to integrate the error signal and then send it to the quantizer; The quantizer is used to convert the integrated error signal into a pulse frequency signal in the digital domain, and serves as the input of the digital-to-analog converter and the output of the Sigma-Delta acquisition circuit, respectively. The digital-to-analog converter is used to receive pulse frequency signals in the digital domain, generate feedback signals in the analog domain, and output them to the feedback multiplier circuit. The feedback multiplier circuit is used to combine the feedback signal with the feedback coefficient. After multiplication, the result is output to the subtractor to form a cyclic modulation.

[0025] During the cyclic modulation process, based on the modulation principle, the following is obtained: (1) After inequality transformation, we get: (2) Then by Mapped to ,Will Mapped to digital input signal After simplification, the mean expression of the pulse frequency signal is obtained as follows: (3) in, The average value of the pulse frequency signal. ,and It is an integer. For adjustable numerical weights, For the number of samples, This is the power supply voltage.

[0026] like Figure 1As shown, in the Sigma-Delta acquisition and calculation integrated circuit provided in this embodiment, the input signal and the feedback signal from the digital-to-analog converter (DAC) are processed by a subtractor to generate an error signal. The integrator integrates the error signal and sends it to a quantizer to convert it into a digital signal. This signal is then fed back to the input terminal by the DAC, forming a cyclic modulation. When the quantizer outputs "1", the voltage of the DAC feedback signal is equal to the power supply level; when the quantizer outputs "0", the voltage of the DAC feedback signal is equal to ground level. This modulation process, through oversampling and noise shaping, pushes the quantization noise to a high frequency, maintaining high accuracy for low-frequency signals.

[0027] Wherein, the multiplication factor Adjustable; by adjusting the multiplication factor, the input analog signal is weighted according to an adjustable value. Perform calculations.

[0028] Figure 1 This diagram illustrates the principle of the sampling and processing circuit based on a Sigma-Delta modulator proposed in this invention. Based on Sigma-Delta modulation technology, this circuit integrates mixed-signal computation capabilities while performing analog-to-digital conversion of analog signals, embodying the design concept of "sampling as computation." The structure employs a closed-loop path of integration-quantization-feedback to achieve high-precision frequency encoding output of the input analog signal. It can also perform specific numerical transformations through the mathematical mapping relationship between pulse frequency and input signal intensity. In a traditional Sigma-Delta modulator, the input analog voltage signal is first compared with the feedback signal, and the difference signal is fed into an integrator for time accumulation. The integration result is then fed into a 1-bit quantizer, which outputs binary pulses based on the integration level, representing either a higher or lower signal amplitude. Subsequently, this digital output is converted back to an analog quantity by a 1-bit digital-to-analog converter and fed back to the input for the next round of modulation. This closed-loop modulation mechanism effectively suppresses low-frequency quantization noise while maintaining the signal's dynamic response. By using oversampling and noise shaping techniques, it pushes error energy to higher frequencies, thereby improving the quantization accuracy of low-frequency signals. Specifically, this solution introduces a multiplication factor and a feedback factor into the traditional Sigma-Delta modulator, which can map the input signal to the desired value in the mixed signal domain according to a set ratio, realizing the function of sampling and computing simultaneously. The pulse output frequency not only reflects the magnitude of the input voltage but also carries adjustable numerical weights, providing hardware-level support for subsequent neural network pulse coding and parallel computing. Furthermore, the system incorporating the sampling and computing circuit based on the Sigma-Delta modulator proposed in this invention can complete the dual tasks of analog-to-digital conversion and data preprocessing while reusing the traditional ADC circuit without requiring an additional independent computing module, providing a compact and efficient new paradigm for the design of integrated sensing and computing chips.

[0029] Furthermore, the Sigma-Delta computing circuit has two operating modes: analog-to-digital conversion mode and computing mode.

[0030] In analog-to-digital conversion mode, the input analog signal is modulated using traditional Sigma-Delta modulation, and the output pulse frequency signal is output. If the Sigma-Delta acquisition circuit is applied to an image recognition scenario, the analog-to-digital conversion mode becomes the imaging mode, the input analog signal is the pixel voltage, and the frequency of the output pulse frequency signal is positively correlated with the pixel voltage amplitude.

[0031] In calculation mode, it supports weighted multiplication of analog input signals by adjusting the multiplication factor. The Sigma-Delta acquisition circuit performs weighted multiplication on the input analog signal and outputs the pulse frequency code of the weighted analog signal. When applied in image recognition scenarios, combined with peripheral control circuitry, it enables scaling of image data within the region of interest, normalizing it to a uniform image size, and simultaneously encoding the pulse frequency of the pixel voltages in the scaled image.

[0032] Optional, such as Figure 2 As shown, the integrator circuit, through switched capacitor technology and operational amplifier, constitutes a high-efficiency differential-integral mixed-signal calculation module. It possesses high linearity and programmable weighting capabilities, and is one of the core components for realizing the "sampling-as-calculation" function. The circuit employs a differential input structure, receiving the positive input signal Vinp and the negative input signal Vinn respectively, utilizing its superior common-mode rejection characteristics to improve the signal-to-noise ratio.

[0033] The integrator includes a set of mirror-symmetric switched capacitor networks and an operational amplifier; The switched capacitor network comprises multiple positive-phase branches Csp and multiple negative-phase branches Csn. The multiple positive-phase branches Csp are connected in parallel to the non-inverting input of the operational amplifier, and each positive-phase branch Csp receives a positive input signal Vinp. The multiple negative-phase branches Csn are connected in parallel to the inverting input of the operational amplifier, and each inverting branch Csn receives a negative input signal Vinn. Each branch includes a switch and a unit capacitor connected in series. The switch in each branch is controlled by different weighted signals, and the unit capacitor has the same capacitance value. As shown in the figure, this embodiment includes... A total of branch roads Each weight signal and unit capacitance is controlled by corresponding digital signals W1~W1. and complementary signals ~ Controlling the opening and closing of the sampling switch thereby regulates the operation of each branch; The operational amplifier adopts an operational transconductance amplifier structure. Its input terminal is connected to the output terminal of the switched capacitor network. It is used to transfer and amplify the charge / weighted charge signal output by the switched capacitor network in analog-to-digital conversion / computation mode. The charge signal is superimposed on the accumulated charge at the output terminal as a new accumulated charge.

[0034] In this embodiment, n Take 4, capacitor unit as follows Figure 2 As shown in Csp1~Csp16 and Csn1~Csn16, the capacitor unit consists of the corresponding digital control signals W1~W16 and their complementary signals. ~ Control the opening and closing of the sampling switch.

[0035] This weighted structure allows for flexible adjustment of the participation level of each sampling branch, enabling multiplication and weighting of the input signal during the sampling phase. It is a key implementation method for sampling-calculation fusion. (Formula) Then it becomes Each switched capacitor unit samples the input signal under the control of Clk1d. With the coordinated action of multiple clock phases (such as Clk1 and Clk2), the sampled charge is transferred to the integration nodes Cintp and Cintn, driving the operational amplifier on the right side of the circuit to perform integration. This amplifier is configured as a differential structure, with outputs Voutp and Voutn, generating a differential output reflecting the multiplication of the input analog quantity and the digital weighted signal, which is then further processed by the quantizer in the modulator stage. This integrator circuit not only performs the traditional error signal accumulation function but also dynamically selects the sampling capacitor array through control signals, realizing a mixed-signal domain multiplication mapping between the input signal and the digital weights. This simplifies the front-end data path, effectively reduces hardware resource consumption, and provides support for efficient analog-to-digital mixed-signal calculation and pulse-code output.

[0036] In this embodiment, multiplication factors are introduced during analog signal sampling and digital-to-analog converter feedback signals, respectively. and feedback coefficient The input signal is mapped to the desired value in the mixed-signal domain according to a set ratio. The modulator circuit of the Sigma-Delta analog-to-digital converter in the Sigma-Delta acquisition circuit achieves accurate conversion from analog voltage to pulse frequency and mixed-signal domain multiplication calculation, replacing the traditional charge-sharing calculation scheme which is susceptible to process fluctuations, and offering both high accuracy and high stability. Simultaneously, pulse encoding is completed using the modulator's built-in Sigma-Delta signal modulation, directly providing pulse signal input for subsequent pulse neural network recognition without the overhead of additional pulse encoding circuitry. This solves the problem that existing acquisition circuits cannot perform signal calculations while sampling and quantizing analog signals, realizing a highly robust integrated acquisition and calculation mechanism based on Sigma-Delta modulation.

[0037] Example 2 Based on the Sigma-Delta sampling circuit provided in Example 1, a novel image sensing and computing integrated circuit system is proposed. This system can improve the responsiveness and energy efficiency of AI computing while maintaining image sampling accuracy, and reduce the amount of data transmitted and converted. It truly achieves deep integration of "perception and computing" and provides a more competitive solution for smart terminals and edge computing scenarios.

[0038] like Figure 3 As shown, this invention provides an event-driven sensing and computing integrated system for target detection, comprising: a pixel array, a background subtraction circuit, a threshold comparator, a region of interest extraction circuit, a Sigma-Delta acquisition circuit as described in any one of embodiments, a spiking neural network recognition circuit, and a counter; wherein, Figure 3 The CDS in the middle is a CDS circuit with background subtraction.

[0039] The pixel array is used to perform row gating, reset and exposure operations under the action of control signals, and convert the light signal corresponding to the input scene under test into an unprocessed analog pixel signal to realize column parallel image signal readout; The background subtraction circuit is used to suppress noise in the unprocessed analog pixel signal based on correlation double sampling and background difference technology. In imaging mode, the noise-suppressed analog pixel signal is used as the signal to be processed and output to the Sigma-Delta acquisition circuit. In calculation mode, the pixel signal of the moving target is extracted from the noise-suppressed analog pixel signal as the signal to be processed and the background-subtracted pixel signal is output. The threshold comparator is used to perform a binarization operation on the pixel signal after background subtraction to extract the event pixel; The region of interest extraction circuit is used to generate a minimum motion region window based on the connectivity analysis of the event pixels and output the region of interest in the image. The Sigma-Delta acquisition circuit is used to perform size normalization and pulse code conversion on the pixel signals in the image of interest to obtain the pulse frequency signal corresponding to the event stream information. The spiking neural network recognition circuit is used to receive the pulse frequency signal, perform preliminary moving target recognition through a multi-layer fully connected spiking neural network composed of spiking neurons, and enable the Sigma-Delta acquisition circuit after successful recognition, so that it works in analog-to-digital conversion mode to convert the pixel voltage of the original image into a pulse frequency signal and output it to the counter. The counter is used to count the pulse frequency signal output by the Sigma-Delta acquisition circuit to generate the original image.

[0040] Optionally, a digital accelerator for object detection may also be included; The target detection digital accelerator is used to receive the original image output by the counter and to perform target detection, localization and tracking of target objects in the region of interest.

[0041] like Figure 3 As shown, specifically, this system, based on an event-driven mechanism, integrates functional modules such as image perception, motion detection, region extraction, pulse coding, spiking neural network recognition, and target detection, realizing an on-chip closed-loop processing flow from image sampling to target detection. The system employs a highly integrated pixel array and a front-end circuit with switchable operating modes. It dynamically extracts regions of interest based on event pixels, combines Sigma-Delta sampling with spiking neural networks to achieve lightweight recognition, and utilizes a target detection digital accelerator to fully meet the multiple requirements for energy efficiency, real-time performance, and accuracy in complex dynamic scenes. This architecture emphasizes the overall optimization of sensing-computing collaboration and computing resource scheduling, making it suitable for efficient perception and intelligent processing of moving targets at the edge.

[0042] like Figure 3 As shown, the pixel array uses photosensitive units based on infrared or visible light and pixel circuits based on a four-transistor active pixel sensor structure, arranged in an array form. Each row of pixels shares a row gating control signal, a row reset control signal and a row exposure control signal, and each column shares a column output signal.

[0043] Furthermore, such as Figure 4 As shown, optionally, the background subtraction circuit includes a pixel input signal VPX, two sets of sampling / reset capacitors, a differential amplifier, a background voltage input terminal VBG, and multiple switches; the switches are in pairs and controlled by a control signal. The pixel input signal is connected to the sampling capacitor or the reset capacitor via a switch. The outputs of the two sets of capacitors are respectively connected to the positive and negative input terminals of the differential amplifier. The background voltage input VBG is connected to the lower plate of the reset capacitor. The pixel input signal is connected to the upper plate of the sampling capacitor CS or the reset capacitor CR respectively through two switches under the control of the sampling enable signal S and the reset enable signal R. The lower plate of the CS capacitor is grounded, and the lower plate of the CR capacitor is connected to VBG and ground respectively through two parallel switches at different timing stages. The upper plates of the two capacitors are connected to the positive and negative input terminals of the differential amplifier respectively through two switches under the control of the output enable signal Y.

[0044] The background subtraction circuit has two operating modes: imaging mode and calculation mode, which are switched via the CDS signal (CDS = 1 for imaging mode, CDS = 0 for calculation mode). When CDS is high, the upper plate of the reset capacitor CR is connected to the reset signal, and the lower plate of the reset capacitor CR is connected to GND. This circuit operates in imaging mode. In imaging mode, correlated double sampling technology is used to sample and amplify the pixel charge, effectively suppressing shot noise, reset noise, and fixed pattern noise. When CDS is low, if R is high, the upper plate of the reset capacitor CR is connected to the reset signal, and the lower plate of the reset capacitor CR is connected to the background voltage signal; if Y is high, the upper plate of the reset capacitor CR is connected to the negative inverting input of the differential amplifier, and the lower plate of the reset capacitor CR is connected to GND. This circuit operates in calculation mode. In calculation mode, the charge signal of the current pixel is sampled and amplified, then subtracted from the background voltage to obtain a difference signal reflecting the dynamic changes of the pixel.

[0045] Further reference Figure 4 As shown, when CDS is low and R is high, the amount of charge stored on the upper plate of CR is: (4) When Y is set to high, the upper plate of capacitor CR is connected to the negative inverting input of the differential amplifier, and the lower plate of CR is connected to GND. Therefore, the charge stored on the upper plate of CR is: (5) Since the upper plate of CR remains suspended during the process from when switch R is closed to when switch Y is opened, there is no charge transfer path (the input impedance of an ideal amplifier is infinite). Therefore, the charge on the upper plate of CR remains unchanged, resulting in: (6) Right now: (7) Similarly, the following can also be obtained at the sampling end: (8) The output voltage of the differential amplifier is: (9) The background subtraction circuit performs differential amplification of the pixel voltage and the background voltage. In actual operation, the pixel row strobe signal SEL is kept high to ensure that the row is in readout mode.

[0046] The background subtraction circuit operates as follows: by setting the reset control signal RST high, the floating diffusion region FD is reset, and then set it low to exit the reset state; then, R is set high to start the sampling process, completing the steps shown in formula (4), and then R is set low. Then, by setting the exposure control signal TG high, the accumulated charge in the pixel area is transferred to FD; S is set high to start signal sampling, and the transferred signal is held on capacitor CS, completing the steps shown in formula (8), and then set low. Finally, the amplification control signal Y is set high to start the differential calculation process. The non-inverting input terminal is shown in formula (8), the inverting input terminal is shown in formula (7), and the output terminal is shown in formula (9), reflecting the difference signal of pixel changes. Through the above design, this circuit achieves dynamic subtraction of background pixel voltage while retaining the advantages of CDS noise suppression, effectively improving the detection sensitivity and stability of moving target pixels in complex scenes, and providing high-quality event information input for subsequent ROI extraction and recognition inference.

[0047] The background subtraction circuit performs dynamic differential processing on pixel charge through a switchable correlation dual sampling mode and a background subtraction mode, effectively suppressing fixed-mode noise and environmental interference, improving the detection sensitivity of moving targets, and supporting stable event extraction in complex dynamic scenes.

[0048] like Figure 3 As shown, the threshold comparator binarizes the pixel signal after background subtraction, filtering out event pixels with significant changes. The region of interest extraction circuit dynamically generates a region of interest window based on the spatial connectivity analysis of event pixels, thereby reducing redundant computational load. It is worth noting that after this circuit completes the framing of the moving target region in the current frame image, it generates a corresponding control signal. This signal, through switch control, allows the original pixel voltage within the region of interest to be directly output to the Sigma-Delta acquisition circuit. At this time, the background subtraction circuit only operates in imaging mode.

[0049] The spiking neural network recognition circuit receives event stream information from the region of interest (ROI) after image size normalization and pulse coding. Through inference using a multi-layer fully connected spiking neural network composed of spiking neurons, it achieves low-latency and highly robust preliminary image recognition. Notably, when the spiking neural network recognition circuit identifies a specified target within the ROI, it generates a corresponding control signal. This signal controls the conversion of the pixel voltages of the original image into pulse signals, which are then directly output to a counter. At this time, the Sigma-Delta acquisition circuit operates only in imaging mode.

[0050] This system embeds a three-layer SNN circuit composed of spiking neurons, which can complete the initial target recognition of the ROI region on the chip with extremely low power consumption, greatly reducing the burden of back-end inference. The imaging mode is dynamically triggered only after successful recognition, further improving the system's processing efficiency.

[0051] The counter is used to count the signal pulses output by the Sigma-Delta acquisition circuit operating in imaging mode after the target is identified, and to complete the analog-to-digital conversion of the image pixel values. The resulting multi-bit digital signal is positively correlated with the original pixel voltage.

[0052] The target detection digital accelerator is suitable for target recognition, detection and tracking scenarios that emphasize real-time performance and high energy efficiency. By using a digital hardware accelerator equipped with a deep learning neural network model, it can accurately identify, locate and track candidate targets with different proportions, poses, low lighting conditions, and occlusion and overlap.

[0053] Through the collaborative design of the above modules, this system realizes an integrated system-level closed loop from perception, motion detection, region of interest extraction, target recognition to detection, effectively improving the performance and efficiency of target detection tasks in resource-constrained environments, and effectively reducing the target detection latency and power consumption of the hardware system.

[0054] like Figure 5 As shown, the workflow of the event-driven sensing and computing integrated system for target detection provided in this embodiment of the invention includes: the pixel array completes row selection, reset, and exposure operations under the action of control signals to achieve column-parallel image signal readout; the background subtraction circuit performs noise suppression and dynamic change extraction on the pixel signal based on correlation double sampling and background difference technology; the threshold comparator performs binarization operation on the pixel signal after background subtraction to extract event pixels; the region of interest extraction circuit generates a minimum motion region window based on pixel connectivity analysis and triggers ROI signal output; the Sigma-Delta acquisition circuit performs size normalization and pulse code conversion on the ROI region image for use by the subsequent recognition module; the spiking neural network recognition circuit completes preliminary moving target recognition based on a network constructed from spiking neurons, and after successful recognition, enables the analog-to-digital conversion circuit, uses a counter to count the original pulse stream, and generates the original image; finally, the target detection digital accelerator achieves high-efficiency and strong real-time target detection and tracking.

[0055] The system dynamically adjusts its working mode through control signals such as SW, EN, and MD, enabling precise control over ROI extraction, data output path, and target detection. It supports on-demand sensing and on-demand computation, significantly improving system resource utilization and intelligent adaptive capabilities.

[0056] The event-driven sensing and computing integrated system for target detection provided in this invention adopts an event-driven sensing and computing integrated system architecture. It integrates multi-stage processing modules such as image sampling, motion detection, region of interest extraction, and target recognition at the sensor level, constructing a closed-loop path from image generation to target detection. This effectively breaks the traditional serial "sampling-transmission-processing" mechanism. Through algorithm-circuit-architecture co-design, it achieves a closed-loop target detection function at the system level, reducing data transmission bandwidth and latency, and improving the overall system energy efficiency and real-time performance. It represents a low-power, compact target detection system architecture with adaptive sensing computing capabilities. This solution not only overcomes the bottlenecks of traditional image sensing architectures in terms of energy efficiency and bandwidth but also achieves a closed-loop target detection function at the system level through algorithm-circuit-architecture co-design. It is particularly suitable for deployment in power-sensitive and high-response edge vision systems, and has broad application prospects and industrial value.

[0057] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A Sigma-Delta acquisition circuit, characterized in that, include: The input multiplier circuit, integrator, quantizer, digital-to-analog converter, feedback multiplier circuit, and subtractor operate through a closed-loop feedback circuit. The input multiplier circuit is used to multiply the input analog signal. With multiplication factor After multiplication, the adjusted analog signal is obtained and output to the subtractor; The subtractor is used to subtract the adjusted analog signal from the feedback signal of the digital-to-analog converter to obtain the error signal; The integrator is used to integrate the error signal and then send it to the quantizer; The quantizer is used to convert the integrated error signal into a pulse frequency signal in the digital domain, and serves as the input of the digital-to-analog converter and the output of the Sigma-Delta acquisition circuit, respectively. The digital-to-analog converter is used to receive pulse frequency signals in the digital domain, convert them to the analog domain, obtain feedback signals, and output them to the feedback multiplier circuit. The feedback multiplier circuit is used to combine the feedback signal with the feedback coefficient. After multiplication, the result is output to the subtractor to form a cyclic modulation.

2. The circuit as described in claim 1, characterized in that, The Sigma-Delta computing circuit includes two operating modes: analog-to-digital conversion mode and computing mode. In analog-to-digital conversion mode, the multiplication factor and feedback coefficient The values ​​are equal; In calculation mode, adjust the coefficient. The value is adjustable, and the mean expression of the output pulse frequency signal of the Sigma-Delta acquisition circuit is: in, The average value of the pulse frequency signal. , ,and It is an integer; For adjustable numerical weights, This is the power supply voltage for the Sigma-Delta computing circuit.

3. The circuit as described in claim 1, characterized in that, The integrator includes a set of mirror-symmetric switched capacitor networks and an operational amplifier.

4. The circuit as described in claim 1, characterized in that, When the quantizer outputs a high level, the voltage of the feedback signal of the digital-to-analog converter is equal to the power supply level; When the quantizer outputs a low level, the voltage of the feedback signal of the digital-to-analog converter is equal to the ground level.

5. An event-driven sensing and computing integrated system for target detection, characterized in that, Includes the Sigma-Delta acquisition circuit as described in any one of claims 1-4.

6. The system as described in claim 5, characterized in that, Also includes: Pixel array, background subtraction circuit, threshold comparator, region of interest extraction circuit, spiking neural network recognition circuit, and counter; The pixel array is used to convert the light signal corresponding to the input scene image under test into an unprocessed analog pixel signal under the action of the control signal; The background subtraction circuit is used to suppress noise in the unprocessed analog pixel signal, and in imaging mode, the noise-suppressed analog pixel signal is used as the signal to be processed and output to the Sigma-Delta acquisition circuit; in calculation mode, the pixel signal of the moving target is extracted from the noise-suppressed analog pixel signal as the signal to be processed and the background-subtracted pixel signal is output. The threshold comparator is used to perform binarization on the signal to be processed and extract event pixels; The region of interest extraction circuit is used to perform connectivity analysis on the event pixels, generate a minimum motion region window, and output the region of interest image. The Sigma-Delta acquisition circuit is used to perform Sigma-Delta modulation on the pixel signals in the image of interest to obtain the pulse frequency signal corresponding to the event stream information. The pulse neural network recognition circuit is used to receive the pulse frequency signal, perform moving target recognition, and after successful recognition, control the Sigma-Delta acquisition circuit to work in analog-to-digital conversion mode to convert the pixel voltage of the original image into a pulse frequency signal and output it to the counter. The counter is used to count the pulse frequency signal output by the Sigma-Delta acquisition circuit to generate the original image.

7. The system as described in claim 6, characterized in that, It also includes a digital accelerator for object detection; The target detection digital accelerator is used to receive the original image output by the counter and to perform target detection, localization and tracking of target objects in the region of interest.

8. The system as described in claim 7, characterized in that, The background subtraction circuit includes a pixel input VPX, a sampling capacitor CS, a reset capacitor CR, a differential amplifier, and a background voltage input terminal VBG; The first output of the pixel input is connected to the upper plate of the sampling capacitor CS through the first switch under the control of the sampling enable signal S, and the second output is connected to the upper plate of the reset capacitor CR through the second switch under the control of the reset enable signal R. The lower plate of the CS capacitor is grounded; the lower plate of the CR capacitor is connected to VBG and ground respectively through two parallel switches at different timing stages; and the upper plates of the sampling capacitor CS and the reset capacitor CR are connected to the positive and negative input terminals of the differential amplifier respectively through corresponding switches under the control of the output enable signal Y. When CDS is high: the upper plate of the reset capacitor CR is connected to the reset signal, and the lower plate of the reset capacitor CR is connected to GND; the background subtraction circuit operates in imaging mode. When CDS is low: when the reset enable signal R is high, the upper plate of the reset capacitor CR is connected to the reset signal, and the lower plate of the reset capacitor CR is connected to the background voltage signal. When the output enable signal Y is high, the upper plate of the reset capacitor CR is connected to the negative input terminal of the differential amplifier, and the lower plate of the reset capacitor CR is connected to GND; the background subtraction circuit operates in calculation mode.

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