Fpga real-time truncation method, device, medium and system for symbol bit redundancy dynamic detection

Abstract

The application discloses a kind of symbol bit redundancy dynamic detection FPGA real-time truncation method, device, medium and system, belong to communication system signal processing technical field, including steps: first, symbol bit detection module dynamically identifies the symbol bit quantity of input Din signal, and outputs symbol bit detection encoding signal Sign_code;Then, data truncation module is according to Sign_code numerical input Din signal is adaptively intercepted, and exports the Dout signal after truncation etc.This application adopts pipeline processing, delay only needs 1 clock cycle, effectively reduce the quantization error in symbol bit interception process, applicable to the communication system of large dynamic range.

Description

Technical Field

[0001] This invention relates to the field of signal processing technology for communication systems, and more specifically, to a method, apparatus, medium, and system for real-time truncation of FPGA for dynamic detection of symbol bit redundancy. Background Technology

[0002] In existing communication system signal processing, after the input analog signal is sampled by an ADC, it usually needs to undergo preprocessing such as digital down-conversion, decimation, and filtering before being sent to the subsequent signal processing module for further processing.

[0003] After the above preprocessing steps, the bit width of the original ADC sampled data will increase significantly. For example, the bit width of the Din signal sampled by one channel ADC is 16 bits. After digital downconversion (with a spurious-free dynamic range of 96dB as an example), the bit width of the output Din_dds signal will increase to 32 bits; after decimation (with a decimation factor of 20 as an example), the bit width of the output Din_dec signal will increase to 56 bits; and after FIR low-pass filtering (with a 31st order as an example), the bit width of the output Din_fir signal will increase to 80 bits.

[0004] Subsequent processing, storage, and timing closure of the aforementioned 80-bit Din_fir signal will present significant challenges. Bit width truncation is necessary to accommodate the requirements of subsequent processing and storage.

[0005] Traditional truncation methods mainly include three types: direct high-level truncation, compensated truncation, and statistical average truncation.

[0006] Direct truncation: Directly discards low-order data, but introduces a large truncation error, especially when the dynamic range of the signal amplitude is large. The effective low-order bits of small-amplitude signals are truncated, resulting in a significant decrease in the signal-to-noise ratio.

[0007] Compensation truncation: This method reduces errors by adding a pre-compensation value (such as rounding). However, this method uses a fixed compensation rule and cannot adapt to dynamic changes in signal amplitude. Statistical average truncation: This method dynamically adjusts the truncation strategy based on the statistical characteristics of the signal, but it requires a large amount of historical data, has poor real-time performance, and is complex to implement in hardware.

[0008] Furthermore, existing sign bit processing techniques typically retain all sign bits or simply truncate the most significant bits, failing to fully utilize the redundancy of sign bits. For example, in an FPGA-based PWM control signal generation system, the sign bit is determined by judging the most significant bit of the sampled signal, but the redundancy problem caused by the consistency of multiple sign bits is not considered. In low signal-to-noise ratio signal detection, although sliding window averaging filtering is used to reduce signal jitter, the sign bit processing strategy is not optimized. Summary of the Invention

[0009] The purpose of this invention is to overcome the shortcomings of the prior art and provide a method, device, medium and system for real-time truncation of FPGA for dynamic detection of symbol bit redundancy. This invention solves the problems of poor real-time performance, large quantization error of small amplitude signals and high software resource overhead in the existing FPGA signal bit width compression method in communication systems without significantly increasing software complexity.

[0010] The objective of this invention is achieved through the following solution: A real-time truncation method for dynamic detection of sign bit redundancy on an FPGA includes the following steps: First, the Din signal is input to the sign bit detection module. The sign bit detection module determines the number of redundant sign bits based on the pre-designed judgment conditions and the sign bit consistency detection principle, identifies the sign bit of the Din signal, and outputs the sign bit detection code signal Sign_code. Then, the Sign_code is input to the data truncation module. Based on the Sign_code value, the Din signal is truncated, and the truncated Dout signal is output.

[0011] Furthermore, the step of identifying the sign bit of the Din signal and outputting the sign bit detection encoding signal Sign_code specifically includes: When performing sign bit identification on the Din signal, the high-order bits of the input signal are dynamically detected to determine the number of consecutive sign bits and output the code Sign_code.

[0012] Furthermore, the step of truncating the Din signal and outputting the truncated Dout signal specifically includes the following sub-steps: Based on the value of Sign_code, the valid bits of the signal are adaptively truncated, while the sign bit and data bits are retained, and the compressed signal is output.

[0013] Furthermore, the consecutive sign bits are specifically 0 or 1.

[0014] A real-time truncation device for dynamic detection of sign bit redundancy in an FPGA includes a sign bit detection module and a data truncation module; a Din signal is input to the sign bit detection module and the data truncation module; the sign bit detection module outputs a sign bit code (Sign_code) signal to the data truncation module; the data truncation module sorts the input Din signal according to the Sign_code value, performs sign bit and data valid bit truncation processing, and outputs a Dout signal; and is used to execute the real-time truncation method for dynamic detection of sign bit redundancy in an FPGA as described in claim 1.

[0015] Furthermore, the sign bit detection module and the data truncation module are set in the FPGA.

[0016] A computer-readable storage medium storing a computer program therein, the computer program being loaded by a processor and executing the method as described in any of the preceding claims.

[0017] A real-time truncation system for dynamic detection of sign bit redundancy in an FPGA includes the real-time truncation device for dynamic detection of sign bit redundancy in an FPGA as described in any of the preceding claims.

[0018] The beneficial effects of this invention include: This invention addresses the issue that in FPGAs, signals undergo multi-stage processing, introducing multiple sign bits and significantly increasing the signal width, leading to excessive resource consumption in subsequent processing stages. It proposes a signal truncation method and apparatus for dynamic detection of sign bit redundancy, offering the following advantages: (1) The software implementation of this invention is simple and realizes real-time truncation of the sign bit. Specifically, by comparing the numerical consistency of consecutive high bits, redundant sign bits are dynamically identified, and the sign bit of the input signal is truncated in real time. The signal is processed in a pipeline from input to detection and then to truncated output, with a delay of only 1 clock cycle and no cumulative delay is introduced, making it suitable for high-speed signal processing scenarios.

[0019] (2) The present invention has strong adaptability and reduces the quantization error of small amplitude signals. Specifically, the bit width truncation method is adaptively adjusted according to the signal amplitude. When truncating, redundant sign bits are discarded first, rather than directly truncating low bits, which significantly reduces the quantization error of small amplitude signals and meets the needs of large dynamic range signal processing. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the FPGA signal truncation method for dynamic detection of the sign bit according to an embodiment of the present invention; Figure 2 for Figure 1 Flowchart of sign bit detection and processing; Figure 3 for Figure 1 Flowchart of data truncation processing. Detailed Implementation

[0022] All features disclosed in all embodiments of this specification, or steps in all methods or processes implied in the disclosure, may be combined and / or extended or replaced in any way, except for mutually exclusive features and / or steps.

[0023] In view of the problems in the background, the inventors of this invention believe that: There is an urgent need for a new technical solution that can dynamically optimize the symbol bit retention strategy and reduce the signal-to-noise ratio loss during bit width conversion without significantly increasing hardware and software overhead. In this invention, a symbol bit redundancy dynamic detection mechanism is used to detect the input signal in real time, truncate redundant symbol bits, compress the signal bit width, and facilitate signal processing, transmission, and storage.

[0024] More specifically, a real-time truncation method for dynamic detection of sign bit redundancy in FPGA is provided, comprising the following steps: First, the Din signal is input to the sign bit detection module. The sign bit detection module identifies the sign bit of the signal Din according to the pre-designed judgment conditions and outputs the sign bit detection code signal Sign_code. Then, the Sign_code is input to the data truncation module. Based on the Sign_code value, the Din signal is truncated, and the truncated Dout signal is output.

[0025] Specifically, the sign bit detection module utilizes the sign bit consistency detection principle to determine the number of redundant sign bits and outputs the encoded signal after sign bit count recognition in real time. When identifying the sign bit of the Din signal, the module dynamically detects the high-order bits of the input signal to determine the number of consecutive sign bits (0 or 1) and outputs the code Sign_code.

[0026] Specifically, the data truncation module incorporates sign bit detection results to achieve intelligent bit-width compression and reduce quantization errors. The truncation process for the Din signal adaptively extracts the valid bits based on the Sign_code value, retaining only the necessary sign and data bits, and outputs the compressed signal.

[0027] In other embodiments, based on the above embodiments, see [reference needed]. Figure 1 A real-time truncation device for dynamic detection of sign redundancy bits in an FPGA is provided, comprising a sign bit detection module and a data truncation module. The Din signal is input to both the sign bit detection module and the data truncation module in the FPGA; the sign bit detection module outputs a sign bit code (Sign_code) signal to the data truncation module; the data truncation module sorts the input Din signal according to the Sign_code value, truncating the sign bit and valid data bits, and outputs a Dout signal.

[0028] Figure 1 In this example, sign bit detection is performed using a maximum of 10 sign bits. The input Din signal has a bit width of 56 bits, the sign bit encoding (Sign_code) signal has a bit width of 6 bits, and the output Dout signal has a bit width of 32 bits. Specifically, when Dout has two or more sign bits, two sign bits are reserved (reserving two sign bits as "protection bits" to achieve a better balance between preventing arithmetic overflow and maintaining signal quality); when Dout has only one sign bit, one sign bit is reserved.

[0029] See Figure 2 The sign bit detection process enters the initial state after power-on reset, and then transitions to the state to determine whether Din[55:46] is 0x0 or 0x3FF (i.e., Din[55:46] is a sign bit with 10 zeros or 10 ones). In the process of determining whether Din[55:46] is 0x0 or 0x3FF, if yes, it transitions to the state of setting Sign_code=0x1, and then returns to the initial state. Otherwise, it transitions to the state to determine whether Din[55:47] is 0x0 or 0x1FF (i.e., Din[55:47] is a sign bit with 9 zeros or 9 ones).

[0030] Figure 2 In the process of determining whether Din[55:47] is 0x0 or 0x1FF, if it is, the process switches to the state of setting Sign_code=0x2 and then returns to the initial state. Otherwise, the process switches to the state of determining whether Din[55:48] is 0x0 or 0xFF (i.e., Din[55:48] is the sign bit of 8 0s or 8 1s).

[0031] Figure 2 In the process of determining whether Din[55:48] is 0x0 or 0xFF, if it is, the process switches to the state of setting Sign_code=0x3 and then returns to the initial state. Otherwise, the process switches to the state of determining whether Din[55:49] is 0x0 or 0x7F (i.e., Din[55:49] is a sign bit with 7 zeros or 7 ones).

[0032] Figure 2 In the process of determining whether Din[55:49] is 0x0 or 0x7F, if it is, the process switches to the state of setting Sign_code=0x4 and then returns to the initial state. Otherwise, the process switches to the state of determining whether Din[55:50] is 0x0 or 0x3F (i.e., Din[55:50] is a sign bit with 6 zeros or 6 ones).

[0033] Figure 2In the process of determining whether Din[55:50] is 0x0 or 0x3F, if it is, the process switches to the state of setting Sign_code=0x5 and then returns to the initial state. Otherwise, the process switches to the state of determining whether Din[55:51] is 0x0 or 0x1F (i.e., Din[55:51] is a sign bit of 5 0s or 5 1s).

[0034] Figure 2 In the process of determining whether Din[55:51] is 0x0 or 0x1F, if it is, the process switches to the state of setting Sign_code=0x6 and then returns to the initial state. Otherwise, the process switches to the state of determining whether Din[55:52] is 0x0 or 0xF (i.e., Din[55:52] is a sign bit with 4 zeros or 4 ones).

[0035] Figure 2 In the process of determining whether Din[55:52] is 0x0 or 0xF, if it is, the process switches to the state of setting Sign_code=0x7 and then returns to the initial state. Otherwise, the process switches to the state of determining whether Din[55:53] is 0x0 or 0x7 (i.e., Din[55:53] is a sign bit with 3 0s or 3 1s).

[0036] Figure 2 In the process of determining whether Din[55:53] is 0x0 or 0x7, if it is, the process switches to the state of setting Sign_code=0x8 and then returns to the initial state. Otherwise, the process switches to the state of setting Sign_code=0x9 (that is, Din[55:54] is the sign bit of 1~2 0s or 1~2 1s) and then returns to the initial state.

[0037] See Figure 3 The data truncation processing flow enters the initial state after power-on reset, and then transitions to the sorting state based on the Sign_code value. In the sorting state process based on the Sign_code value, if Sign_code=0x1, it transitions to the state of setting Dout=Din[39:8], and then returns to the initial state.

[0038] Figure 3 In the process of sorting the Sign_code value, if Sign_code=0x2, it will switch to the state of setting Dout=Din[40:9] and then return to the initial state.

[0039] Figure 3 In the process of sorting the Sign_code value, if Sign_code=0x3, then the process will switch to setting Dout=Din[41:10] and then return to the initial state.

[0040] Figure 3In the process of sorting the Sign_code value, if Sign_code=0x4, then the process will switch to setting Dout=Din[42:11] and then return to the initial state.

[0041] Figure 3 In the process of sorting the Sign_code value, if Sign_code=0x5, then the process will switch to setting Dout=Din[43:12] and then return to the initial state.

[0042] Figure 3 In the process of sorting the Sign_code value, if Sign_code=0x6, then it will switch to the state of setting Dout=Din[44:13] and then return to the initial state.

[0043] Figure 3 In the process of sorting the Sign_code value, if Sign_code=0x7, then the process will switch to setting Dout=Din[45:14] and then return to the initial state.

[0044] Figure 3 In the process of sorting the Sign_code value, if Sign_code=0x8, it will switch to the state of setting Dout=Din[46:15] and then return to the initial state.

[0045] Figure 3 In the process of sorting the Sign_code value, if Sign_code=0x9, it will switch to the state of setting Dout=Din[47:16] and then return to the initial state.

[0046] It should be noted that, within the scope of protection defined in the claims of this invention, the following embodiments can be combined and / or extended or replaced in any logical manner from the above specific embodiments, such as the disclosed technical principles, disclosed technical features or implicitly disclosed technical features.

[0047] Example 1 A real-time truncation method for dynamic detection of sign bit redundancy on an FPGA includes the following steps: First, the Din signal is input to the sign bit detection module. The sign bit detection module determines the number of redundant sign bits based on the pre-designed judgment conditions and the sign bit consistency detection principle, identifies the sign bit of the Din signal, and outputs the sign bit detection code signal Sign_code. Then, the Sign_code is input to the data truncation module. Based on the Sign_code value, the Din signal is truncated, and the truncated Dout signal is output.

[0048] Example 2 Based on Example 1, the identification of the sign bit of the Din signal and the output of the sign bit detection encoding signal Sign_code specifically includes: When performing sign bit identification on the Din signal, the high-order bits of the input signal are dynamically detected to determine the number of consecutive sign bits and output the code Sign_code.

[0049] Example 3 Based on Example 1, the step of truncating the Din signal and outputting the truncated Dout signal specifically includes the following sub-steps: Based on the value of Sign_code, the valid bits of the signal are adaptively truncated, while the sign bit and data bits are retained, and the compressed signal is output.

[0050] Example 4 Based on Example 2, the continuous sign bits are specifically 0 or 1.

[0051] Example 5 A real-time truncation device for dynamic detection of sign bit redundancy in an FPGA includes a sign bit detection module and a data truncation module; a Din signal is input to the sign bit detection module and the data truncation module; the sign bit detection module outputs a sign bit code (Sign_code) signal to the data truncation module; the data truncation module sorts the input Din signal according to the Sign_code value, performs sign bit and data valid bit truncation processing, and outputs a Dout signal; and is used to execute the real-time truncation method for dynamic detection of sign bit redundancy in an FPGA as described in Embodiment 1.

[0052] Example 6 Based on Embodiment 5, the sign bit detection module and the data truncation module are set in the FPGA.

[0053] Example 7 A computer-readable storage medium storing a computer program, the computer program being loaded by a processor and executed as described in any one of Embodiments 1 to 4.

[0054] Example 8 A real-time truncation system for dynamic detection of sign bit redundancy in FPGA includes the real-time truncation device for dynamic detection of sign bit redundancy in FPGA as described in any one of Embodiments 5-6.

[0055] The units described in the embodiments of the present invention can be implemented in software or hardware, and the described units can also be located in a processor. The names of these units do not necessarily limit the specific unit itself.

[0056] According to one aspect of the present invention, a computer program product or computer program is provided, the computer program product or computer program including computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, and executes the computer instructions, causing the computer device to perform the methods provided in the various optional implementations described above.

[0057] In another aspect, embodiments of the present invention also provide a computer-readable medium, which may be included in the electronic device described in the above embodiments; or it may exist independently and not assembled into the electronic device. The computer-readable medium carries one or more programs, which, when executed by the electronic device, cause the electronic device to perform the methods described in the above embodiments.

Claims

1. A real-time truncation method for dynamic detection of sign bit redundancy in FPGA, characterized in that, Includes the following steps: First, the Din signal is input to the sign bit detection module. The sign bit detection module determines the number of redundant sign bits based on the pre-designed judgment conditions and the sign bit consistency detection principle, identifies the sign bit of the Din signal, and outputs the sign bit detection code signal Sign_code. Then, the Sign_code is input to the data truncation module. Based on the Sign_code value, the Din signal is truncated, and the truncated Dout signal is output.

2. The FPGA real-time truncation method for dynamic detection of sign bit redundancy according to claim 1, characterized in that, The process of identifying the sign bit of the Din signal and outputting the sign bit detection code signal Sign_code specifically includes: When performing sign bit identification on the Din signal, the high-order bits of the input signal are dynamically detected to determine the number of consecutive sign bits and output the code Sign_code.

3. The FPGA real-time truncation method for dynamic detection of sign bit redundancy according to claim 1, characterized in that, The step of truncating the Din signal and outputting the truncated Dout signal specifically includes the following sub-steps: Based on the value of Sign_code, the valid bits of the signal are adaptively truncated, while the sign bit and data bits are retained, and the compressed signal is output.

4. The FPGA real-time truncation method for dynamic detection of sign bit redundancy according to claim 2, characterized in that, The consecutive sign bits are specifically 0 or 1.

5. An FPGA real-time truncation device for dynamic detection of sign bit redundancy, characterized in that, It includes a sign bit detection module and a data truncation module; the Din signal is input to the sign bit detection module and the data truncation module; the sign bit detection module outputs a sign bit code (Sign_code) signal to the data truncation module; the data truncation module sorts the input Din signal according to the Sign_code value, performs sign bit and data valid bit truncation processing, and outputs a Dout signal; and is used to execute the FPGA real-time truncation method for dynamic detection of sign bit redundancy as described in claim 1.

6. The FPGA real-time truncation device for dynamic detection of sign bit redundancy according to claim 5, characterized in that, The sign bit detection module and the data truncation module are set in the FPGA.

7. A computer-readable storage medium, characterized in that, A computer program is stored in a readable storage medium, the computer program being loaded by a processor and executing the method as described in any one of claims 1 to 4.

8. An FPGA real-time truncation system for dynamic detection of sign bit redundancy, characterized in that, The FPGA real-time truncation device includes the sign bit redundancy dynamic detection according to any one of claims 5-6.

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