Method for frame synchronization and carrier synchronization of a parallel radio communication receiver

Abstract

The application relates to a frame synchronization and carrier synchronization method of a parallel wireless communication receiver, which comprises the following steps: performing parallel timing synchronization on parallel sampling points obtained through frequency down-conversion to obtain parallel symbols; performing parallel frame header detection through differential conjugate correlation between a local frame header sequence and the parallel symbols, outputting a frame header locking flag and an intra-frame offset when the correlation value meets frame header judgment conditions, and performing coarse frequency offset estimation according to the correlation value and feeding back the coarse frequency offset to a frequency down-conversion numerical control oscillator; after the frame header locking flag is valid, performing joint loop processing of carrier synchronization and automatic gain control on the parallel symbols, simultaneously performing carrier phase error detection and carrier amplitude error detection on the same parallel symbols, and feeding back the obtained frequency control word and amplitude control word to the frequency down-conversion numerical control oscillator and a matched filter output end respectively. The application has the advantages that the frame header can be locked when the frequency offset is not corrected, and the frame synchronization result can be reused to establish carrier locking.

Description

Technical Field

[0001] This application relates to the field of signal synchronization in wireless communication receivers, and in particular to a method for joint frame synchronization and carrier synchronization in a parallel wireless communication receiver. Background Technology

[0002] Wireless communication plays a crucial role in real-time transmission of large amounts of data in scenarios such as satellite communication, data link transmission, and broadband access. Before demodulating valid data, the receiver must first complete timing synchronization, frame synchronization, and carrier synchronization. Timing synchronization determines the optimal sampling time for each symbol, frame synchronization determines the starting position of a data frame, and carrier synchronization eliminates frequency and phase deviations between the local oscillators at the transmitting and receiving ends. Inaccuracy in any of these three stages will lead to systematic errors in subsequent symbol decisions, resulting in increased bit error rate or even link interruption. Therefore, synchronization performance directly determines whether the receiver can operate stably under actual channel conditions.

[0003] As symbol rates increase to gigabits per second, the clock frequencies of digital processing devices such as field-programmable gate arrays (FPGAs) can no longer keep up with the sampling rates. Receivers can no longer process samples one by one per clock cycle; instead, they must divide high-speed sampling points into blocks for parallel processing, handling multiple sampling points simultaneously within a single clock cycle. Meanwhile, real-world channels exhibit Doppler shift, local oscillator drift, multipath fading, and noise interference. Receivers need to quickly establish synchronization under conditions of both frequency offset and noise, and maintain lock-on throughout the entire reception process.

[0004] Existing receiver synchronization schemes reveal a fundamental contradiction under the aforementioned parallel processing conditions: parallel block processing disrupts the mutual support relationships between synchronization stages that were originally established through symbol-by-symbol serial feedback. Because the control quantity of the timing loop is still accumulated based on the quantity of a single sampling point, when multiple sampling points are simultaneously absorbed in one clock cycle, the loop gain decreases exponentially with the degree of parallelism, and timing convergence slows down. Furthermore, because the timing, frame, and carrier stages are independently parallelized and do not share intermediate computation results, the frequency offset information generated during frame synchronization is discarded. The carrier stage can only re-insert pilots or training sequences to re-estimate the frequency offset, incurring additional bandwidth and hardware overhead. If frame synchronization adopts a method where the local frame header sequence is directly correlated with the received symbol, the phase of each correlation term accumulates with the symbol sequence number before the carrier frequency offset is corrected, and the correlation peak attenuates, making it difficult to determine the frame header position. Carrier synchronization can only start the loop after the frame header is locked and the symbol position is determined, relying on the correct symbol decision. This leads to a circular dependency where timing alignment depends on frequency offset correction, frequency offset correction depends on frame header locking, and frame header locking depends on timing alignment. If any stage fails first, the receiver will be unable to establish a reliable synchronization lock. Summary of the Invention

[0005] To address the problem that parallel block processing disrupts the mutual support relationships between synchronization stages, leading to a circular dependency between timing alignment, frequency offset correction, and frame header locking, thus preventing the establishment of reliable synchronization lock, this application provides a frame synchronization and carrier joint synchronization method for a parallel wireless communication receiver.

[0006] This application provides a method for joint frame synchronization and carrier synchronization of a parallel wireless communication receiver, which adopts the following technical solution:

[0007] A method for joint frame synchronization and carrier synchronization of a parallel wireless communication receiver includes the following steps:

[0008] S1. Perform parallel timing synchronization on the parallel sampling points obtained by downconversion to obtain parallel symbols with symbol rate alignment;

[0009] S2. Parallel frame header detection is performed on the parallel symbols. Parallel frame header detection is achieved through differential conjugate correlation between the local frame header sequence and the parallel symbols. In response to the correlation value of differential conjugate correlation satisfying the frame header determination condition, the frame header locking flag and the intra-frame offset of the frame header in the parallel block are output. Coarse frequency offset estimation is performed based on the correlation value to obtain the coarse frequency offset. The coarse frequency offset is fed back to the down-conversion numerically controlled oscillator for frequency offset compensation.

[0010] S3. In response to the frame header lock flag being valid, perform joint loop processing of carrier synchronization and automatic gain control on the parallel symbols. The joint loop processing simultaneously performs carrier phase error detection and carrier amplitude error detection on the same parallel symbol, obtaining the carrier phase error and carrier amplitude error respectively. The carrier phase error is filtered by the carrier loop to obtain the frequency control word, which is fed back to the down-conversion digitally controlled oscillator. The carrier amplitude error is filtered by the carrier loop to obtain the amplitude control word, which is fed back to the matched filter output.

[0011] By adopting the above technical solution, differential conjugate correlation enables the frequency offset phases between adjacent symbols to cancel each other out in the correlation operation. Frame header locking no longer requires that the carrier frequency offset has been corrected, thus cutting off the dependence of frame header locking on frequency offset correction. The phase angle of the correlation value generated during the frame header locking process is directly used for coarse frequency offset estimation and fed forward to the down-conversion CNC oscillator, so that the frequency offset is pushed into the acquisition range before the carrier loop starts, without the need to insert a separate training sequence. Carrier synchronization and automatic gain control use the frame header locking flag as a common start condition and the same parallel symbol as a common error source. The two error channels are fed back to the down-conversion CNC oscillator and the matched filter output, respectively, so that even in the parallel architecture where the receiver processes multiple sampling points in one clock cycle, it can still establish and maintain synchronization lock when frequency offset and noise coexist.

[0012] Optionally, the joint loop processing of S3 operates in four states driven by the frame header reference, where the frame header reference is the local frame header sequence located in parallel frame header detection. The four states include soft-start state, tracking state, gap maintenance state, and recapture state.

[0013] In the soft-start state, the frame header reference is used as the reference symbol for carrier phase error detection. In response to the mean value of the carrier phase error being lower than the convergence threshold for several consecutive clock cycles, the system enters the tracking state.

[0014] In tracking mode, the hard decision result of parallel symbols is used as a reference for carrier phase error detection, and the carrier phase is periodically checked with the frame header reference. In response to the check deviation exceeding the mislock threshold or the frame header lock flag failing for multiple consecutive frames, the system enters reacquisition mode. In response to entering a known pilot gap, the system enters gap maintenance mode.

[0015] In the gap-maintaining state, the missing pilot symbols are replaced with frame header references to maintain the updates of the joint loop processing, and the tracking state is returned in response to leaving the pilot gap.

[0016] In the reacquisition state, parallel frame header detection is re-executed and coarse frequency offset is re-estimated. In response to successful reacquisition, the system returns to the soft-start state.

[0017] By adopting the above technical solution, the carrier loop uses the already located frame header as a single known reference in three scenarios: startup transient, pilot gap, and mislocking. No additional training sequence or independent locking detector is required, so that carrier locking can still be maintained and automatically recovered when the reference symbol is missing or the symbol decision is distorted.

[0018] Optionally, S1 includes sub-steps S11 to S14:

[0019] S11. Write the parallel sampling points into the parallel shift storage space.

[0020] S12. Read sampling points from the parallel shift memory space starting from the read start pointer, divide them into multiple groups according to a step size of half a symbol period, and input them into the parallel Farrow filter bank at fractional intervals to obtain parallel interpolation results with alternating sign points and zero crossing points. The number of parallel interpolation results is twice the ratio of the number of parallel sampling points to the oversampling factor plus one.

[0021] S13. Group adjacent sign points, zero crossings and sign points in the parallel interpolation results into a group, and calculate the timing error using a parallel Gardner timing error detector.

[0022] S14. The timing error is filtered by the timing loop filter and output to the timing numerically controlled oscillator.

[0023] By adopting the above technical solution, the grouping with a step size of half a symbol period makes the interpolation results naturally form a sequence of alternating sign points and zero crossing points. The parallel Gardner timing error detector can directly take three adjacent points to calculate the timing error without additional rearrangement.

[0024] Optionally, the update amount of the fractional interval is the product of the timing control word output by the timing loop filter and the number of parallel paths corresponding to the parallel sampling points. The fractional interval is obtained by taking the modulus of the sum of the previous fractional interval and the update amount over a sampling interval.

[0025] By adopting the above technical solution, the timing control word is accumulated proportionally to the number of parallel paths, so that the loop gain of the timing loop does not decrease with the degree of parallelism when it swallows multiple sampling points in one clock cycle, thus avoiding the slowing down of timing convergence due to parallel processing.

[0026] Optionally, in response to an overflow of the accumulated result of the fractional interval, the read start pointer is decremented by one; in response to an underflow of the accumulated result of the fractional interval, the read start pointer is incremented by one; the initial value of the read start pointer is the oversampling factor; after the frame header lock flag is valid, the read start pointer is continuously updated, and the intra-frame offset is synchronously and inversely corrected according to the adjustment amount of the read start pointer.

[0027] By adopting the above technical solution, the starting pointer is dynamically shifted ahead or behind the sampling clock to track the optimal sampling point. Furthermore, when the timing loop continues to run after the frame header is locked, the intra-frame offset is synchronously corrected in the reverse direction with the pointer adjustment amount, thus avoiding symbol boundary drift from eroding the locked frame position.

[0028] Optionally, in S2, differential conjugate correlation simultaneously calculates correlation values ​​for multiple candidate start positions of the local frame header sequence and parallel symbols within one clock cycle. The number of candidate start positions is equal to the number of symbols in a parallel block. The intra-frame offset is determined by the candidate start positions whose correlation values ​​satisfy the frame header determination conditions.

[0029] By adopting the above technical solution, the positions of all candidate frame headers within a parallel block are simultaneously probed within the same clock cycle, so that frame header search does not need to proceed step by step according to symbol in the parallel architecture, and the frame header position and the offset within the block can be determined within a single clock cycle.

[0030] Optionally, the frame header determination condition is that the modulus of the correlation value exceeds the adaptive threshold, which is the product of the cumulative average of the correlation value over multiple consecutive parallel blocks and a preset multiplier coefficient.

[0031] By adopting the above technical solution, the threshold is automatically raised and lowered according to the received signal power and noise level, so that frame header detection can balance detection sensitivity and false alarm suppression without manual readjustment of the threshold in channels with varying signal-to-noise ratios.

[0032] Optionally, in S2, the coarse frequency offset is calculated from the phase angle of the correlation value of the differential conjugate correlation, and in the same locking process, the coarse frequency offset estimation is only performed once when the frame header locking flag is first effective.

[0033] By adopting the above technical solution, the phase angle of the correlation value generated during the frame synchronization process is directly converted into frequency offset without the need to perform frequency sweep or spectrum calculation. Moreover, the correlation peak at the first frame lock is the most reliable, and one estimation is sufficient to push the frequency offset into the acquisition range of the carrier loop.

[0034] Optionally, in S3, the carrier phase error is obtained by cross product operation between parallel symbols and hard decision results of parallel symbols. The cross product operation is implemented by taking the sign, multiplying and subtracting, without division and inverse trigonometric function operations.

[0035] By adopting the above technical solution, the phase error is approximated by the cross product of the received symbol and the decision symbol, and is linearly related to the phase deviation within a small angle range. Moreover, the operation consists only of sign taking, multiplication and subtraction, which is convenient to implement with a fixed time delay in a parallel pipeline.

[0036] Optionally, the coarse frequency offset estimated in the previous frame can be feedforwarded to the parallel sampling point before the parallel Gardner timing error detector performs timing error detection, in order to suppress the influence of the frequency offset on the zero-crossing point determination.

[0037] By adopting the above technical solution, the timing error detection works under near-zero frequency offset conditions, avoiding the residual frequency offset from rotating the sign phase and contaminating the amplitude determination of the zero-crossing point.

[0038] Optionally, after carrier synchronization is locked, the mapping relationship between the decision quadrant of the pilot symbol and the local pilot quadrant is taken to determine the rotation factor corresponding to the quadruple phase ambiguity. The data block is then rotated inversely to eliminate the phase ambiguity caused by carrier synchronization, and differential coding is not used.

[0039] By adopting the above technical solution, the inherent quadruple phase ambiguity of carrier synchronization is directly determined and compensated by the quadrant relationship of the known pilots, thus avoiding demodulation loss caused by differential coding.

[0040] Optionally, the correlation values ​​of differential conjugate correlations are calculated in parallel at multiple differential intervals, and the correlation values ​​of each differential interval are dynamically weighted and fused according to the coarse frequency offset.

[0041] By adopting the above technical solution, the large differential interval is favored when the frequency offset is small to obtain the accumulated gain, and the small differential interval is favored when the frequency offset is large to avoid phase cancellation. The frame header detection can adaptively make trade-offs between anti-frequency offset and anti-noise.

[0042] Optionally, based on the magnitude of the correlation value when the frame header lock flag is first valid, the method for determining the coarse frequency offset can be selected as either performing a single coarse frequency offset estimation or averaging the phase angles of the correlation values ​​of subsequent frames.

[0043] By adopting the above technical solutions, single estimation can be used to avoid additional delay when the signal-to-noise ratio is high, and multi-frame weighted averaging can be used to reduce the variance of frequency offset estimation when the signal-to-noise ratio is low.

[0044] Optionally, the carrier phase error and carrier amplitude error can be weighted according to the distance between the parallel symbols and the hard decision result, and then the average value can be calculated separately.

[0045] By adopting the above technical solution, low-confidence symbols close to the decision boundary are given smaller weights in error aggregation, reducing the pollution of the loop error signal by erroneous decisions.

[0046] Optionally, the rate of change of the frequency control word can be used as the criterion for frequency offset jump. When the rate of change exceeds a preset threshold, parallel frame header detection and coarse frequency offset estimation can be re-executed.

[0047] By adopting the above technical solution, the slowly drifting frequency offset is continuously tracked by the carrier loop without interrupting the lock, and reacquisition is only triggered when the frequency offset changes.

[0048] Optionally, phase dewinding is performed on the phase angle of the correlation values ​​of multiple consecutive frames to compensate for phase winding when the frequency offset is close to half of the symbol rate.

[0049] By adopting the above technical solution, the winding of the phase angle when the frequency offset is close to half of the symbol rate is de-wound and corrected, thus avoiding symbol flipping caused by coarse frequency offset estimation.

[0050] Optionally, the soft-start state has higher priority than the gap maintenance state, and if the recapture state fails to recapture within a preset number of frames, the state of the joint loop processing is frozen and a lockout flag is output.

[0051] By adopting the above technical solution, state competition during the startup phase is resolved by priority arbitration, and the loop state is frozen when continuous recapture fails, thus avoiding the state machine from repeatedly recapturing indefinitely under extreme conditions.

[0052] In summary, this application includes at least one of the following beneficial technical effects:

[0053] 1. Differential conjugate correlation enables frame header locking to be independent of pre-correction of frequency offset. The phase angle of the correlation value is directly converted into coarse frequency offset and fed forward to the down-conversion digitally controlled oscillator, cutting off the cyclic dependency between timing alignment, frequency offset correction and frame header locking, so that the receiver can establish synchronization lock in parallel architecture.

[0054] 2. The timing control word is accumulated according to the number of parallel paths so that the loop gain does not decrease with the degree of parallelism. The half-symbol step size grouping makes the interpolation result directly form an alternating sequence of symbol points and zero crossing points. The carrier synchronization and automatic gain control share the same error source of parallel symbols, and the parallel tracking of phase and amplitude is completed without increasing the pilot overhead.

[0055] 3. The frame header that has been located by frame synchronization is used as a single known reference for the four states of soft start, false lock check, gap maintenance and recapture, without the need for additional training sequences and independent lock detectors; the intra-frame offset is synchronously reversed with the adjustment of the timing pointer, so that the locked frame boundary is not eroded by the continuously running timing loop. Attached Figure Description

[0056] Figure 1 This is a schematic diagram of the overall process of the frame synchronization and carrier joint synchronization method of a parallel wireless communication receiver in one embodiment of this application.

[0057] Figure 2 This is a schematic diagram of the structure of a parallel timing synchronization loop in one embodiment of this application.

[0058] Figure 3 This is a schematic diagram of the parallel frame header detection and coarse frequency offset estimation in one embodiment of this application.

[0059] Figure 4 This is a schematic diagram of the combined carrier synchronization and automatic gain control loop in one embodiment of this application.

[0060] Figure 5 This is a schematic diagram of the four-state carrier ring state transition of the frame header reference drive in one embodiment of this application. Detailed Implementation

[0061] The present application will be further described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the application and are not intended to limit the scope of the application.

[0062] This application discloses a method for joint frame synchronization and carrier synchronization in a parallel wireless communication receiver. This application uses differential conjugate correlation to eliminate the dependence on carrier frequency offset correction for frame header locking, and reuses the correlation values ​​generated during frame header locking as coarse frequency offset observations and reference symbols for the carrier loop, reconstructing the mutual support between synchronization stages under a parallel block architecture. First, parallel timing synchronization is performed on the parallel sampling points obtained after down-conversion to obtain parallel symbols with symbol rate alignment. Then, parallel frame header detection is performed on the parallel symbols, outputting a frame header locking flag and intra-frame offset. The coarse frequency offset is calculated from the correlation values ​​and fed back to the down-conversion CNC oscillator. Finally, after frame header locking, a joint loop of carrier synchronization and automatic gain control is started, simultaneously generating carrier phase error and carrier amplitude error from the same parallel symbol. After being filtered by the carrier loop, these errors are fed back to the down-conversion CNC oscillator and the matched filter output, respectively. Thus, the receiver, in a parallel architecture processing multiple sampling points within one clock cycle, can establish and maintain synchronization lock even when frequency offset and noise coexist.

[0063] The following sections will provide a detailed explanation of the terminology, main methodology, specific implementation of parallel timing synchronization, specific implementation of parallel frame header detection and coarse frequency offset estimation, and specific implementation of the combined loop of carrier synchronization and automatic gain control.

[0064] The following section will first explain some of the technical terms involved in the embodiments of this application.

[0065] Parallel processing architecture refers to a receiver processing method that simultaneously processes multiple sampling points or symbols within a single system clock cycle. When the baseband symbol rate or analog-to-digital conversion sampling rate exceeds the system clock frequency achievable by a field-programmable gate array (FPGA), serial point-by-point processing can no longer process a single sampling point within one clock cycle; the insufficiency of the clock frequency must be compensated for by increasing the degree of parallelism. The cost of parallel processing architecture is that timing synchronization, frame synchronization, and carrier synchronization algorithms designed for serial processing cannot be directly applied; the error quantities, decision quantities, and state quantities they rely on are all divided into parallel blocks.

[0066] Parallel path number This refers to the number of sampling points that a parallel processing architecture can simultaneously input within one clock cycle. The following constraints must be met: a single shift input must have at least two symbols and the number of symbols must be even; the oversampling factor must be at least 4. .

[0067] Oversampling factor , refers to the number of sampling points contained within one symbol period. This determines the interval between the sign point and the zero-crossing point in the sampling sequence, that is, half a sign period corresponds to... The interval between sampling points is the basis for determining the subsequent Farrow interpolation grouping step size.

[0068] Parallel blocks refer to inputs that are parallel within one clock cycle. The set of symbols corresponding to each sampling point after timed synchronization. The number of symbols contained in each parallel block is denoted as . ,and The specific position of the frame header within a parallel block is denoted as the intra-frame offset, which ranges from 1 to... Integers between [a certain range].

[0069] fractional interval , is the phase state quantity maintained by the timed numerically controlled oscillator, and its value range is . Normalized to a sampling interval between two adjacent sampling points, it represents the fractional position of the interpolation point relative to the read sampling point. Overflow indicates that the interpolation point has crossed a complete sampling interval, and its overflow state directly drives the integer shift of the read start pointer. The update amount is determined by the timing control word output by the timing loop filter.

[0070] The read start pointer marks the starting point for reading data from the parallel shift memory space. The timed numerically controlled oscillator increments or decrements this pointer by one to ensure the Farrow filter bank always reads data near the optimal sampling point. The initial value of the pointer is the oversampling factor. .

[0071] Symbol points and zero-crossing points are the two types of sampling locations required for Gardner's timing error detection. Symbol points are located at the optimal decision time for a symbol, while zero-crossing points are located at the midpoint between two adjacent symbol points. Under ideal timing synchronization conditions, the signal amplitude at a zero-crossing point should be zero, and the amplitudes of the two symbol points before and after it should be equal. Timing deviations will cause the amplitude at the zero-crossing point to no longer be zero, and its value is proportional to the difference between the two symbol points. This proportional relationship is the error criterion of Gardner's algorithm.

[0072] The frame header lock flag is a status signal output by the frame header detection module when the relevant value meets the frame header determination condition. This flag serves as both the activation condition for the carrier synchronization and automatic gain control joint loop and the trigger condition for coarse frequency offset estimation to be executed only once.

[0073] The timing control word is the output of the timing loop filter. The timing control word is accumulated in the fractional interval register of the timing numerically controlled oscillator, and its value determines the step size of the fractional interval in each clock cycle.

[0074] The frequency control word is the output of the phase branch of the carrier loop. The frequency control word is accumulated to the phase accumulator of the down-converter digitally controlled oscillator, and its function is to correct the frequency and phase of the carrier.

[0075] The amplitude control word is the output of the amplitude branch of the carrier loop. It operates on the multiplier at the output of the matched filter to correct the signal gain.

[0076] The following concrete example illustrates why serial synchronization schemes fail simultaneously in a parallel block architecture. Assume the modulation scheme is QPSK, and the number of parallel paths... Oversampling factor Each parallel block contains One symbol; length of the local frame header sequence symbols, symbol period is . All subsequent numerical examples in this application follow this baseline scenario; all calculated results are rounded to three decimal places and expressed with an approximate equality sign.

[0077] Assume the received signal has a carrier frequency offset. ,and If the frame header is detected using the conventional direct correlation method, that is, by multiplying each received symbol and the local frame header symbol by their conjugates and then summing them, each product term will have a phase rotation that increases linearly with the symbol sequence number. When 32 terms are summed, the phase rotates exactly over the entire frame header length. The arc is a full circle, and the product terms are evenly distributed on the complex plane at 32 equally divided points of the unit circle. The vector sum is zero, the correlation peaks completely disappear, and the frame header cannot be detected.

[0078] The failure to detect the frame header establishes a closed dependency chain: timing error detection uses the amplitude of the zero-crossing point as the criterion, while residual frequency offset rotates the symbol phase and contaminates the amplitude of the zero-crossing point; therefore, timing alignment depends on the frequency offset being corrected. Frequency offset correction depends on the carrier loop, and the decision-oriented phase detector of the carrier loop requires a known reference symbol; therefore, frequency offset correction depends on the frame header being locked. Frame header locking depends on correlation operations, and correlation operations require a symbol stream aligned to the symbol rate; therefore, frame header locking depends on timing alignment. These three are interconnected, forming a circular dependency. In a serial architecture, these three stages can be captured sequentially and provide intermediate results to each other. However, after parallel block processing separates the three stages and makes them run independently in parallel, no single stage can proceed independently. This application addresses this dependency chain by breaking it.

[0079] The overall process of this method is described in detail below, using the benchmark scenario described above. (Refer to...) Figure 1 This method includes steps S1 to S3.

[0080] S1. Perform parallel timing synchronization on the parallel sampling points obtained by downconversion to obtain parallel symbols with symbol rate alignment.

[0081] In the specific implementation, S1 is... The parallel input sampling points undergo parallel Farrow interpolation filtering and parallel Gardner timing error detection. The interpolation read position is dynamically adjusted through timing loop feedback to complete symbol timing synchronization. The input of S1 is the parallel sampling points after down-conversion and matched filtering, which are not yet aligned with the symbol clock. The output is the parallel symbols aligned with the symbol rate. Subsequent frame header detection performs related operations on this symbol stream. Therefore, S1 provides a symbol-level time reference for the entire synchronization chain.

[0082] Specifically, refer to Figure 2 S1 includes sub-steps S11 to S14.

[0083] S11. Write the parallel sampling points into the parallel shift memory space. In the specific implementation, the parallel shift memory space consists of a register array with a depth of [missing information]. Shift in every clock cycle Each sampling point is used to consistently store a total of three consecutive clock cycles. One sampling point. The reason for saving three clock cycles instead of just the current cycle is... The number of sampling points is because the start pointer shifts back and forth as the timing loop overflows, and the number of sampling points read per clock cycle is [number missing]. One, more than one move-in per beat Each sampling point across cycles must remain accessible. For example, in a baseline scenario, the storage depth is 48 sampling points, with 16 shifted in and 20 read out per clock cycle. The storage space can be implemented using shift registers or a combination of registers and address pointers, the latter using pointer increments and decrements instead of physical data movement.

[0084] S12. Read sampling points from the parallel shift memory space starting from the read start pointer, divide them into multiple groups according to a step size of half a symbol period, and input them into the parallel Farrow filter bank at fractional intervals to obtain parallel interpolation results with alternating sign points and zero crossing points. The number of parallel interpolation results is twice the ratio of the number of parallel sampling points to the oversampling factor plus one.

[0085] In the specific implementation, each clock cycle selects a sample point from the parallel shift memory space, starting from the point pointed to by the read start pointer. Each sampling point is grouped into sets of four. That is, the grouping is based on a step size of half a symbol period, and is divided into a total of 10 groups. Groups, each input Each basic Farrow filter unit is computed in parallel. For example, in a baseline scenario, 20 sample points are read out with a step size of 2 sample points, divided into 9 groups: Group 1 contains sample points 1 to 4, Group 2 contains sample points 3 to 6, Group 3 contains sample points 5 to 8, and so on, with Group 9 containing sample points 17 to 20. The starting points of adjacent groups differ by half a symbol period, so the interpolation outputs of adjacent groups also differ by half a symbol period in time, which is exactly the interval between the sign point and the zero-crossing point. This grouping strategy naturally results in an interpolation output that forms a sequence of alternating sign points, zero-crossing points, sign points, and zero-crossing points, where odd-numbered outputs correspond to sign points and even-numbered outputs correspond to zero-crossing points. This provides the necessary signal structure for subsequent Gardner timing error detection without any additional rearrangement or buffering.

[0086] Each basic Farrow filter unit is interpolated using a four-tap second-order polynomial as follows:

[0087]

[0088] in, , , , To input the four consecutive sampling points of this unit, The fractional intervals used for Farrow interpolation. This is for interpolation output. The expression is in... Time output ,exist Time output That is, the interpolation point is at and Continuous movement between, the position of movement is from Decision. For example, let the four sampling points be... , , , , Then the coefficient of the quadratic term is The coefficient of the linear term is Substituting into Just for and The midpoint.

[0089] The coefficients of this interpolation filter are designed as a four-tap second-order polynomial structure. Item and The coefficients of each term are all integer multiples of 0.5, which can be achieved through shifting and addition / subtraction. Therefore, each basic Farrow filter unit requires only two multipliers, one for each term. Multiplication with coefficients and Multiplication with coefficients. In the baseline scenario, 18 multipliers are required for the 9 basic units, and all units are computed in parallel within a single clock cycle. As an alternative implementation, for modulation schemes such as BPSK that only take values ​​on the real axis, interpolation can be performed only on the real part, and the imaginary part channel can be pruned.

[0090] S13. Group adjacent sign points, zero crossings and sign points in the parallel interpolation results into a group, and calculate the timing error using a parallel Gardner timing error detector.

[0091] In a practical implementation, the Farrow filter bank output The interpolation result is denoted as . to Odd indices correspond to sign points, and even indices correspond to zero-crossing points. The parallel Gardner timing error detector groups three adjacent outputs together, with each group containing one zero-crossing point and two sign points before and after it, for a total of... Groups. For example, in the baseline scenario, the nine interpolation results are divided into four groups: Group 1 is... , , Group 2 is , , Group 3 is , , Group 4 is , , Each pair of adjacent groups shares a symbol point, so the nine interpolation results exactly support four sets of error detections, corresponding one-to-one with the four symbols in the parallel block.

[0092] The timing error for each group is calculated using the following formula:

[0093]

[0094] in, These are the zero-crossing sampled values ​​for this group. and These are the sampled values ​​of the two symbol points before and after this group, respectively. This represents the timing error of the group. The physical meaning of this formula is: in ideal timing synchronization, the signal amplitude at the zero-crossing point should be zero, and the amplitudes of the two consecutive symbol points should be equal. This holds true for constant envelope modulation such as QPSK. Therefore... When a timing deviation exists, the zero-crossing amplitude is no longer zero, and the polarity of the product of its value and the difference between the preceding and following sign points reflects the direction of the timing error. For example, suppose the preceding and following sign points of a certain set are respectively... and If there is no deviation in timing, then Substituting into If the sampling time is ahead of schedule... Substituting into If the error is negative, the sampling time of the indicator loop needs to be shifted backward. For BPSK modulation, only the real part can be used for calculation, i.e. .

[0095] S14. The timing error is filtered by the timing loop filter and output to the timing numerically controlled oscillator.

[0096] In the specific implementation, an accumulator first averages the k / sps timing errors to obtain the mean timing error, and then inputs the mean timing error into the timing loop filter. The purpose of averaging is to smooth the error fluctuations between parallel branches: within the parallel block... Group error refers to multiple observations of the timing phase at the same time, whose noise components are independent. Calculating the mean value reduces the noise variance by increasing the number of groups, thus improving the stability of the error estimate. The timing loop filter employs a second-order structure, consisting of a proportional branch and an integral branch. The proportional branch responds instantly to the current error for rapid tracking, while the integral branch accumulates historical errors to eliminate steady-state bias. Both branches are multiplied by coefficients. , Accumulate and output timing control word Feedback is sent to the timing numerically controlled oscillator to form a closed timing synchronization loop. The coefficients of the timing loop filter... , The coefficients of the carrier loop filter are independent of each other and are individually tuned according to the bandwidth requirements of their respective loops.

[0097] As an optional reinforcement, the interpolation units, multipliers and quantization paths of each parallel branch are not completely consistent in implementation, which may introduce fixed mismatch between branches. In this case, before averaging, the timing error of each branch can be statistically analyzed over a long period of time, and the long-term average of the error of each branch can be used as the fixed bias of that branch and then subtracted before entering the mean aggregation, thereby avoiding the accumulation of branch mismatch into steady-state timing deviation by the integrated branches.

[0098] As described above, the grouping with a step size of half a symbol period makes the interpolation result naturally form a sequence of alternating sign points and zero crossing points. The parallel Gardner timing error detector can directly take three adjacent points to calculate the timing error without additional rearrangement. Thus, S11 to S14 complete a complete loop update from writing the sampling point to the timing control word output within a single clock cycle.

[0099] The update amount of the fractional interval can optionally be the product of the timing control word output by the timing loop filter and the number of parallel paths corresponding to the parallel sampling points. The fractional interval is obtained by taking the modulus of the sum of the previous fractional interval and the update amount over a sampling interval.

[0100] In the specific implementation, the reading of the parallel shift memory space is controlled by a timed numerically controlled oscillator. The timed numerically controlled oscillator maintains a fractional interval register. , The range is Normalized to a sampling interval, it represents the fractional position of the interpolation point between two adjacent sampling points. Each clock cycle, Update as follows:

[0101]

[0102] in, and These are the fractional intervals between the current clock cycle and the previous clock cycle. This is the timing control word output by the timing loop filter. For the number of parallel paths, Indicates modulo 1. Control word Multiply by the number of parallel paths The physical meaning of accumulation is: The parallel inputs from multiple paths collectively generate a cumulative timing error, which needs to be amortized across... At each sampling point, that is, the corresponding single loop update Total phase accumulation of each sampling point. If no addition... If the loop gain is multiplied by the sum, it will increase. Increase and decrease This doubles the speed, resulting in a slower loop convergence.

[0103] For example, in the baseline scenario, a previous score interval is set. Timed control word The update amount after multiplying by the number of parallel paths is The cumulative result is After taking the modulus of 1 This will trigger an overflow; if the number of parallel paths is not multiplied, the accumulated result will only be... This method neither triggers overflow, nor does it advance the phase by more than one-sixteenth of the former. The loop requires sixteen times the clock cycle to complete the same phase journey. The bandwidth of the timing loop is thus set: the wider the bandwidth... The larger the magnitude and the faster the acquisition, the greater the steady-state jitter. In engineering, a trade-off between acquisition time and steady-state jitter is taken. The quantization bit width must ensure that the phase step corresponding to its minimum resolution is less than the required steady-state timing accuracy.

[0104] Fractional intervals used for Farrow interpolation Depend on The following formula is used for calibration:

[0105]

[0106] in, This is the ratio of the interval between two adjacent taps in the basic Farrow filter unit to a sampling interval. In the above embodiment where four taps take adjacent sampling points, the effective interpolation interval of the interpolation unit is one sampling interval. Therefore The fractional intervals are directly fed into the parallel Farrow filter bank. It should be understood that when the taps of the basic Farrow filter units are sampled at larger intervals, such as taps sampling at half-symbol-period intervals... It must be adjusted according to this ratio. Perform geometric calibration so that the calibrated Still falls within the effective range of the interpolation unit Within that range, the interpolation point can be and They move continuously without extrapolation. Continuing from the previous example, hour As an equivalent implementation, the control word can be multiplied by the number of parallel paths instead of being multiplied, while the timing error is... The sum of group errors is directly input into the loop filter without normalization by dividing by the number of groups, or the accumulated phase is calculated according to... Each sampling point is distributed and then sent to the fractional interval register; the three have equivalent effects on the open-loop gain of the loop, the only difference being on which side of the loop the multiplication and accumulation occur.

[0107] In some embodiments, the read start pointer is decremented by one in response to an overflow of the accumulated result of the fractional interval; the read start pointer is incremented by one in response to an underflow of the accumulated result of the fractional interval; the initial value of the read start pointer is the oversampling factor.

[0108] In the specific implementation, The update direction reflects the lead or lag relationship between the sampling clock and the symbol phase. When An overflow occurs, that is When an interpolation point is ahead of the current read start pointer by one sampling interval, the read start pointer needs to be decremented by 1; when an underflow occurs, i.e. When this happens, it indicates that the interpolation point is lagging behind the current read start pointer by one sampling interval, and the read start pointer needs to be incremented by 1. By dynamically adjusting the read start pointer, the Farrow filter bank always reads data near the optimal sampling point. Continuing from the previous example, An overflow is triggered, the read start pointer is decremented from its initial value of 4 to 3, and the read window for the next clock cycle shifts forward by one sampling point. The initial value of the read start pointer is taken as an oversampling factor. The rationale is that the pointer needs to be shifted bidirectionally without exceeding the storage boundary during subsequent increments and decrements, and the initial value is taken as... A space can be reserved in front of the readout window The backoff margin for each sampling point, and the margin thereafter is determined by... The storage depth is guaranteed. The read start pointer is thus dynamically shifted ahead or behind the sampling clock to track the optimal sampling point.

[0109] The aforementioned timing chain uses the zero-crossing amplitude as the criterion, but this criterion becomes inaccurate under residual frequency offset. The received symbol will be affected by the presence of carrier frequency offset. At that time, its phase changes with time. As the angular rate continues to rotate, the real and imaginary parts of the interpolated output are redistributed by the rotation component; at the zero-crossing point that should be zero in ideal timing, the real and imaginary parts are no longer simultaneously zero. Substituting this into the timing error formula yields... It is no longer zero. Even if the timing is already aligned, the loop will still read a non-zero timing error and adjust accordingly, eventually converging to a timing phase with a bias.

[0110] As an optional implementation, the coarse frequency offset estimated in the previous frame is feedforward compensated to the parallel sampling points before the parallel Gardner timing error detector performs timing error detection, in order to suppress the influence of the frequency offset on the zero-crossing point determination. In the specific implementation, the estimated coarse frequency offset is taken... Read out for each beat Each sampling point is multiplied by the phase inversion factor. ,in, The imaginary unit, This represents the time sequence number of the sampling point; alternatively, the step increment corresponding to the coarse frequency offset can be superimposed on the phase accumulator of the down-conversion CNC oscillator, and the sampling point after deducting the coarse frequency offset can be directly output by the down-conversion stage. The former acts on the front end of the timing loop and only serves timing error detection, while the latter acts on the front end of the down-conversion stage and benefits all subsequent stages; the two can coexist.

[0111] Here, "previous frame" refers to the fact that the coarse frequency offset estimate must be taken from a previously locked frame, because the coarse frequency offset is estimated only at the same moment the frame header is locked, and cannot be used for the currently locked frame. Therefore, the first frame of a cold start has no usable coarse frequency offset, the feedforward channel is not yet active, and the timing loop operates on uncompensated sampling points. At this time, although the timing phase carries a deviation caused by the frequency offset, it can still converge to an accuracy sufficient to support symbol decision. The reason the frame header can still be detected under these conditions is precisely because the magnitude of the differential conjugate correlation does not decay with the frequency offset. This anti-frequency offset characteristic allows the system to obtain the frame header first under unknown frequency offset conditions, thus escaping the aforementioned circular dependency. After the first frame locking, the coarse frequency offset is estimated and registered, and thereafter, inverse rotation compensation is continuously performed on the parallel sampling points entering timing error detection. The frequency deviation of the crystal oscillators at both the transmitting and receiving ends depends on the nominal accuracy and operating temperature of the crystal. It can be considered constant over a time scale of several frame periods. Therefore, this registered value remains valid between frames and does not need to be re-estimated frame by frame. Its residual slow drift is continued to be tracked by the carrier synchronization and automatic gain control combined loop.

[0112] The feedforward compensation process suffers from pipeline delay: from the estimation of the coarse frequency offset to the actual application of the inverse rotation factor to the sampling point, several register stages of timing occur. Symbols that have entered the pipeline but not yet been compensated during this period are called in-transit symbols. In practical implementation, in-transit symbols can be marked as uncompensated, and the integrator branch state of the timing loop filter can be aligned with the compensation state of the in-transit symbols at the boundary of compensation activation. This avoids loop jitter caused by a step change in the error signal at the moment of compensation switching. Timing error detection thus operates under near-zero frequency offset conditions, avoiding residual frequency offset rotating the symbol phase and contaminating the amplitude determination at the zero-crossing point.

[0113] S2. Perform parallel frame header detection on parallel symbols. Parallel frame header detection is achieved through differential conjugate correlation between the local frame header sequence and the parallel symbols. In response to the correlation value of differential conjugate correlation satisfying the frame header determination condition, output the frame header locking flag and the intra-frame offset of the frame header within the parallel block. Perform coarse frequency offset estimation based on the correlation value to obtain the coarse frequency offset. Feed the coarse frequency offset back to the down-conversion numerically controlled oscillator for frequency offset compensation.

[0114] In its implementation, S2 performs differential conjugate correlation on the parallel symbol stream after timing synchronization, detects the frame header position, and outputs a frame header lock flag. Simultaneously, it uses the phase of the differential correlation value to estimate the carrier frequency offset and feeds it back to the down-conversion stage. The input to S2 is the parallel symbols with symbol rate aligned to the output of S1. It outputs three terms, each with a different destination: the frame header lock flag is sent to the carrier synchronization and automatic gain control joint loop as its activation condition; the intra-frame offset is sent to frame structure analysis to determine the starting point of the valid data symbols; and the coarse frequency offset is fed back to the down-conversion CNC oscillator at the front end for pre-compensation.

[0115] All three outputs are derived from the same correlation value, which is precisely the role that S2 plays in the entire synchronization chain: the magnitude of the correlation value is used to determine whether the frame header appears, the candidate position of the correlation value is used to determine the intra-frame offset, and the phase angle of the correlation value is used to calculate the coarse frequency offset. The correlation operation is performed once, and its result is reused three times, without the need to insert a separate training sequence for frequency offset estimation, nor is it necessary to perform frequency sweep or spectrum calculation separately.

[0116] The behavior of S2 is illustrated through three progressive scenarios. The first scenario is the normal case with zero frequency offset and high signal-to-noise ratio: when the frame header arrives, the correlation magnitude of the candidate position aligned with the local frame header sequence is much higher than that of the other candidate positions, the decision condition is met, the frame header lock flag is set, and the intra-frame offset is taken from this candidate position. The second scenario adds a carrier frequency offset: because differential conjugate correlation involves conjugate multiplication between adjacent symbols, the phase rotation caused by the frequency offset cancels out between adjacent terms, the magnitude of the correlation value does not decrease with the frequency offset, and the frame header is still detected at the same candidate position; simultaneously, the canceled constant phase difference is not lost but remains in the phase angle of the correlation value, becoming an observation of the coarse frequency offset. The third scenario is the boundary case with low signal-to-noise ratio: noise raises the correlation value of the misaligned candidate positions and lowers the correlation value of the aligned positions. In this case, the fixed threshold will face the risk of both missed detections and false alarms, and the decision threshold must adaptively rise and fall with the noise level.

[0117] Once the coarse frequency offset is estimated, it is fed back to the phase accumulator of the down-conversion CNC oscillator for pre-compensation. Therefore, before the carrier loop starts, the residual frequency offset has been pushed into the capture band of the carrier loop. The carrier loop does not need to perform a large-scale frequency pulling on its own, and its bandwidth can be designed to be narrower, thereby achieving lower phase jitter in steady state.

[0118] In one optional implementation, the differential conjugate correlation in S2 simultaneously calculates correlation values ​​for multiple candidate start positions of the local frame header sequence and parallel symbols within one clock cycle. The number of candidate start positions is equal to the number of symbols in a parallel block. The intra-frame offset is determined by the candidate start positions whose correlation values ​​satisfy the frame header determination conditions.

[0119] In the specific implementation, refer to Figure 3 After timing synchronization is complete, the parallel symbol stream enters the frame header detection module. Each clock cycle inputs... A symbol, The frame header detection module maintains a length of... The shift register, in which This represents the number of frame header symbols; each clock cycle will increment the current number of symbols. One symbol is shifted into the shift register, and the last symbol at the end of the shift register is... One symbol is removed. For example, in the baseline scenario. , The shift register has a length of 35 symbols, and shifts in 4 symbols and out 4 symbols per clock cycle.

[0120] Register length Instead This is because the frame header within a parallel block may begin at... Any one of the symbols: starting with the first symbol, its The first to second symbols occupy the register's first to second positions. Position; starting from the first When a symbol is used, its The symbol occupies the first position. To the The union of the two is exactly one. Each sign bit. Therefore, even if a frame header crosses the boundary of two adjacent parallel blocks, its entirety... The symbols also remain in the register at the same time, and there is no need to set up additional concatenation logic between blocks. The cross-block overwriting of the register itself completes the concatenation.

[0121] For each possible starting position in the shift register ,common indivual, Take the value starting from that position. Differential conjugate correlation is performed between each symbol and the local frame header sequence. The calculation method for differential conjugate correlation is as follows: The received symbols are... With local frame header symbols Multiply to get ,in, For symbolic serial numbers, This indicates taking the complex conjugate; then for adjacent... and Perform conjugate multiplication and summation:

[0122]

[0123] in, For the first The relevant values ​​of each candidate starting position The total number of frame header symbols, accumulated. In the baseline scenario, the relevance value for each candidate position is obtained by summing 31 items.

[0124] The reason for using differential correlation instead of direct correlation is as follows. Under the condition that the frame header arrives and the candidate positions are aligned, the received symbol can be written as the product of the ideal frame header symbol and the frequency offset phase, i.e. ,in The imaginary unit, Let the symbol be the ordinal number. Substituting it, we get... The frame header sequence takes the value of , Therefore Multiplying adjacent conjugates together, we get... The symbol serial number is no longer included. That is, the frequency offset phase term of adjacent symbols is the same constant for each term, and can be extracted as a whole from the summation. Items accumulated Its modulus ,and Completely unrelated.

[0125] On the contrary, directly related The phase of each of its product terms Follow Linear changes, during accumulation, phase cancellation occurs, leading to peak attenuation, and its magnitude is adjusted accordingly. Fluctuations with frequency offset. Continuing from the aforementioned benchmark scenario, let... At this point, the 32 directly correlated product terms are evenly distributed across the 32 equally divided points of the unit circle in the complex plane, with a vector sum of zero, and the correlation peaks completely disappear. Meanwhile, the 31 terms of the differential correlation all point in the same direction, and the sum of their magnitudes is 31, exactly the same as in the case of no frequency offset. Therefore, differential correlation can maintain stable frame header detection performance under frequency offset conditions.

[0126] this Each candidate position is calculated simultaneously within the current clock cycle, which requires [further processing] in serial processing. A frame header position search that would normally take several clock cycles can be completed in just one clock cycle in a parallel architecture. In the baseline scenario, the four differential conjugate correlators in the differential conjugate correlator group are connected in parallel to four different tap positions of the shift register array. Each correlator receives the symbol and its value... The local frame header sequence is multiplied symbol by symbol; since the local frame header sequence takes values ​​of The multiplication degenerates into adjusting the polarity of the register data based on the local frame header sequence, without occupying the actual multiplier. After multiplication, adjacent product results are multiplied by conjugate and accumulated. The four relevant values ​​are given simultaneously within the same clock cycle, and the frame header position and intra-frame offset are determined within a single clock cycle.

[0127] The aforementioned differential conjugate correlation involves conjugate multiplication between adjacent symbols, meaning the difference interval is one symbol. The value of the difference interval itself can also be considered a degree of freedom: in some embodiments, the correlation values ​​of the differential conjugate correlation are calculated in parallel across multiple difference intervals, and the correlation values ​​of each difference interval are dynamically weighted and fused based on the coarse frequency offset.

[0128] In the specific implementation, the sign-by-sign product is first... According to the difference interval Divide the data into segments and coherently accumulate them within each segment to obtain the segment accumulation value:

[0129]

[0130] Then multiply the sums of the two adjacent segments by their conjugates and sum them up:

[0131]

[0132] in, For the first The cumulative value of the segment, For the difference interval, For the first The candidate starting positions are in the difference interval The relevant values ​​below. When each segment contains only one term, the expression degenerates into the aforementioned adjacent sign difference conjugate correlation. The coherent accumulation within each segment... The term has a frequency offset phase that increases linearly with the sign index, and the magnitude of its accumulation result is calculated according to... Change: When the frequency deviation is small, the modulus value is close to The coherent accumulation within the segment yields approximately The cumulative gain is multiplied by a factor of two; during periods of large frequency offset, the terms cancel each other out in the complex plane, causing a sharp drop in magnitude. Meanwhile, the phase carried by the inter-segment conjugate multiplication... The same constant applies to each segment and does not change with the segment number, therefore the inter-segment difference is always immune to frequency deviation.

[0133] thus, The value of represents a pair of mutually constraining quantities between accumulated gain and frequency offset resistance: The larger the value, the higher the coherent gain within the segment and the stronger the noise immunity, but the smaller the tolerable frequency offset. The smaller the value, the stronger the resistance to frequency offset, but the lower the intra-segment coherent gain. The basis of weighted fusion is precisely this constraint: the degree of intra-segment phase cancellation in each differential interval is determined based on the estimated coarse frequency offset, with smaller cancellation degrees assigned a larger weight. In practical implementation, the weights can be taken as the theoretical values ​​of the intra-segment cumulative modulus of each interval and normalized. The value range is generally from 1 to 4, when Below In this interval, intra-segment cancellation is negligible, and its weight is dominant. As a simplified fusion path, weighting can also be omitted, and the maximum value is taken after modulo the correlation values ​​of each differential interval, with the interval with the largest modulus value being the determining factor. With small frequency offsets, larger differential intervals are favored to obtain accumulated gain, while with large frequency offsets, smaller differential intervals are favored to avoid phase cancellation, allowing frame header detection to adaptively balance frequency offset resistance and noise resistance.

[0134] The correlation values ​​for each candidate position have been calculated. The next step is to determine which one corresponds to the actual frame header. The frame header determination condition can optionally be that the magnitude of the correlation value exceeds an adaptive threshold, which is the product of the cumulative average of the correlation values ​​over multiple consecutive parallel blocks and a preset multiplier coefficient.

[0135] In the specific implementation, the comparator array measures the amplitude of the differential correlation values ​​at the M candidate positions. The threshold is compared with an adaptive threshold. The adaptive threshold is generated by averaging the accumulated correlation values ​​of N consecutive parallel blocks using a cyclic cumulative filter. The threshold is equal to the product of the multiplication factor and the mean. When the correlation value amplitude at a candidate position exceeds the threshold, the position is determined to be the frame header position, a frame header lock flag is output, and the intra-frame offset of the frame header within the parallel block is recorded.

[0136] The adaptive threshold automatically adjusts based on signal power and noise level. Its tuning is based on the following: during clock cycles without a frame header, the correlation value at each candidate position is contributed only by noise, and its cumulative mean represents the current noise floor; upon the arrival of the frame header, the magnitude of the correlation value at the alignment position jumps to a coherent cumulative value determined by the frame header length. The ratio of these two values ​​gives the upper bound of the scaling factor. When no frame header arrives, the correlation value... The phases of the product terms are independent, and the magnitude of their vector sum approximately follows a Rayleigh distribution with a mean of 1 / 2. When the frame header is aligned, When terms are added together, the modulus is 1. The ratio between the two is therefore... In the baseline scenario The mean of the noise floor is The relevant peak value is The ratio is .

[0137] The multiplier factor must be less than this ratio; otherwise, the decision threshold will be higher than the correlation peak when the frame header is aligned, and the frame header will never be detected. Within this upper bound, the selection of the multiplier factor is a trade-off between false alarms and missed detections: a larger factor decreases the false alarm rate but increases the false alarm rate, and a smaller factor has the opposite effect; in engineering, values ​​of 2 to 4 are commonly used, with 3 being typical. Continuing the previous example, when the multiplier factor is 3, the decision threshold is... It is approximately half the peak value of the relevant peak value of 31, leaving about twice the margin of missed detections while exceeding most fluctuations of the noise floor. Cumulative window length The choice is also a compromise: Taking a larger value results in a smaller variance and a more stable threshold for the mean estimate, but it also leads to a slower response to sudden changes in channel power. Setting a small threshold results in faster tracking, but the jitter of the threshold itself can introduce additional false alarms. In engineering practice, tens to hundreds of parallel blocks can be used to make the cumulative duration cover the slow fading time constant of the channel but shorter than the coherence time of fast fading.

[0138] As an alternative or complementary decision path, the periodicity of the frame structure itself can be used for multi-frame confirmation. The frame length is usually known and fixed within a link, so once a candidate position is determined to be a frame header, the time when the next frame header will appear can be predicted. A narrow time window can be opened near the prediction time, accepting frame header decisions only within the window; any out-of-threshold events outside the window are considered false alarms and discarded. Only when several consecutive frames are confirmed within the prediction window is the frame header lock flag finally set. This path trades a slight increase in acquisition delay for a significant decrease in the false alarm rate, and can be used in conjunction with adaptive thresholding in low signal-to-noise ratio scenarios. The decision threshold thus automatically rises and falls with the received signal power and noise level, allowing frame header detection to balance detection sensitivity and false alarm suppression in channels with varying signal-to-noise ratios without manual threshold readjustment.

[0139] Once the frame header position is locked, the correlation value previously used to determine the frame header is no longer just a determination value; its phase angle also carries all the information about the carrier frequency offset. In some embodiments, the coarse frequency offset in S2 is calculated from the phase angle of the correlation value of the differential conjugate correlation, and in the same acquisition process, the coarse frequency offset estimation is only performed once when the frame header locking flag is first valid.

[0140] In its implementation, the coarse frequency offset estimation module is triggered by the initial lock-on enable signal and starts when the frame header is first detected. The phase extraction unit takes the differential correlation value R corresponding to the frame header position, i.e., the one exceeding the aforementioned threshold, and calculates the frequency offset estimate using the following formula:

[0141]

[0142] in, For symbol period, Differential correlation value The phase angle. The physical meaning of this frequency offset estimate is: differential correlation value. The phase angle contains two parts of information: the modulation phase difference between adjacent symbols, which is known for the frame header sequence; and the phase rotation caused by the carrier frequency offset. Since the modulation scheme of the frame header sequence is known, the modulation phase difference can be subtracted from the phase angle to obtain the pure frequency offset information. For a BPSK modulated frame header, the modulation phase difference between adjacent symbols is 0 or... The above formula can be calculated directly. Following the previous derivation, under the condition of frame header alignment... Its phase angle is Substituting into the above formula will accurately restore the original result. For example, suppose the frequency offset is 10% of the symbol rate, that is... Then the phase angle is Radius, substituting into the above formula, we get It matches the set value.

[0143] The frequency offset estimate is converted into the step size increment of the numerically controlled oscillator (CNC) and fed back to the phase accumulator of the down-conversion CNC oscillator for pre-compensation. The coarse frequency offset estimation is performed only once during the first frame header detection in the same acquisition process, followed by fine compensation by the carrier tracking loop in S3. Upon entering the reacquisition state, this count is reset, and the coarse frequency offset is re-estimated synchronously during the re-execution of parallel frame header detection. The reason for performing this only once is that the signal-to-noise ratio is highest and the correlation peak is most reliable during the first frame header detection, resulting in the highest estimation accuracy. Subsequent frame headers can also be used for estimation, but the initial estimation can already compress the frequency offset within the loop acquisition band, which is sufficient to ensure normal carrier loop locking.

[0144] The phase angle of the correlation value already generated during frame synchronization is directly converted into frequency offset, without the need for separate frequency sweeping or spectrum calculation. Alternatively, the down-converted local oscillator can be scanned frame by frame, with the correlation re-run for each frame, or the received symbols can be subjected to a Fast Fourier Transform (FFT) before searching for spectral peaks. The former's acquisition delay is proportional to the number of scan frames, while the latter requires additional transformation hardware and storage. Both require computational resources independent of frame synchronization and are suitable for scenarios where the frame header sequence is unavailable or the frame structure is unknown. In this embodiment, the correlation value is an existing product of frame header detection, and phase extraction requires only one arctangent operation; acquisition is completed at the same moment the frame header is locked.

[0145] Performing an estimation only once is sufficient at high signal-to-noise ratios (SNR), but at low SNRs, the phase angle of a single correlation value itself carries a large estimation variance. As an alternative implementation, based on the magnitude of the correlation value when the frame header lock flag is first enabled, the method for determining the coarse frequency offset can be selected as either performing a single coarse frequency offset estimation or weighted averaging of the phase angles of the correlation values ​​from subsequent frames.

[0146] In specific implementations, the ratio of the magnitude of the correlation peak at the time of the first frame header lock to the cumulative mean in the adaptive threshold is used as the surrogate quantity for the peak signal-to-noise ratio (PSNR). The larger this ratio, the more the correlation peak exceeds the noise floor, and the more reliable its phase angle estimation. Comparing this ratio with a preset confidence threshold allows selection between two modes. In some embodiments, if the ratio is higher than the confidence threshold, it is considered a high SNR, and the coarse frequency offset is calculated only once using the correlation value phase angle of the first frame; the carrier loop is then activated without introducing additional acquisition delay. In other embodiments, if the ratio is lower than the confidence threshold, it is considered a low SNR, and the coarse frequency offset is changed to a continuous... The phase angle of the correlation values ​​of the frames is obtained by weighted averaging. The weight of each frame is the magnitude of the correlation peak of that frame, which is then normalized. The larger the magnitude, the more reliable the phase angle estimate and the higher the weight. Multi-frame weighted averaging makes the variance of the frequency offset estimate decrease approximately inversely proportional to the number of participating frames, at the cost of the acquisition process spanning K frame periods. The value of is generally between 2 and 8: When the value is 2, the variance is reduced by about half while the latency increases by only one frame. Taking 8 reduces the variance to about one-eighth, but the acquisition latency reaches eight frame cycles, which must be balanced with the link's acquisition time requirements. The two modes are mutually exclusive, and only one mode is executed in the same acquisition process.

[0147] Another boundary for frequency offset estimation comes from the range of the phase angle itself. The range of phase angle values ​​given by the arctangent operation is... And based on the aforementioned deduction, the true phase is The condition for a one-to-one correspondence between the two is... ,Right now This means the absolute value of the frequency offset is less than half the symbol rate. Once the frequency offset crosses this boundary, the true phase deviates from the target value. After being folded back into the interval, the phase angle given by the arctangent, along with its sign, is flipped. Substituting it into the conversion formula, the obtained frequency offset estimate will point in the opposite direction, and the loop will be pulled in the wrong direction and will never be able to lock.

[0148] In other embodiments, phase dewinding is performed on the phase angles of correlation values ​​across multiple consecutive frames to compensate for phase winding when the frequency offset is close to half the symbol rate. Specifically, the phase angles of multiple consecutive frames are compared frame-by-frame: if the absolute value of the difference between the phase angles of two adjacent frames exceeds... If this occurs, it is determined that a wrapping has occurred at that point, and the phase angle of the subsequent frame is added to or subtracted from it. The correction is made so that the corrected phase difference falls back to its original state. Within this range, by accumulating the correction amount frame by frame, the unwound continuous phase trajectory can be reconstructed. Substituting this into the conversion formula, a frequency offset estimate that is not limited by the value range can be obtained. When the initial estimate falls within the safe zone, dewinding is not triggered. Phase angle comparison is only required frame by frame when multi-frame estimation mode is enabled.

[0149] As an alternative approach, instead of unwinding, the capture range of the coarse frequency offset can be directly constrained within a safety margin: the capture range is pre-declared as... Any frequency offset estimate that approaches this boundary is disregarded and awaits re-estimation in the next frame. Frequency offsets exceeding this range are handled by frequency presetting at the RF front-end or a coarser frequency sweep acquisition process. This approach sacrifices acquisition range for simplification and is suitable for links where the crystal oscillator accuracy at the transceiver end is known and the upper limit of the frequency offset is controllable. The phase angle winding that occurs when the frequency offset is close to half the symbol rate is thus corrected, preventing symbol flipping from occurring in the coarse frequency offset estimate.

[0150] Frame header locking does not mean the timing loop can stop working. The crystal oscillators at both ends of the receiver have frequency deviations, causing the sampling clock to drift slowly relative to the symbol clock, requiring the timing loop to continuously track it. Each time the timing loop tracks a step, the read start pointer may be incremented or decremented by one. This adjustment introduces a side effect that doesn't exist in a serial architecture: shifting the read start pointer by one sampling point means that the subsequent reading sampling window shifts forward or backward, and the parallel symbol stream obtained after interpolation and decision also shifts by one symbol position relative to the original symbol stream. The intra-frame offset is measured on the symbol stream before the shift; after the shift, it no longer points to the original physical frame header. Without correction, each adjustment of the read start pointer erodes the locked frame boundary by one symbol. After several such adjustments, the frame header locking flag becomes disconnected from the actual frame structure, the start point of valid data symbols is incorrectly determined, and the frame structure collapses.

[0151] In one alternative implementation, after the frame header lock flag is enabled, the read start pointer is continuously updated, and the intra-frame offset is synchronously corrected in the reverse direction according to the adjustment amount of the read start pointer.

[0152] In the specific implementation, the correction rule is in the opposite direction to the adjustment of the read start pointer: when the read start pointer is decremented, the read window moves forward by one sampling point, and the symbol stream as a whole moves forward, so the intra-frame offset increases by one; when the read start pointer is incremented, the intra-frame offset decreases by one. The reason for taking the opposite direction is that the pointer and the offset are readings of the same physical frame header in two coordinate systems. The pointer moves the origin of the coordinate system, and the offset is the position of the frame header relative to that origin. Moving the origin forward means moving the relative position backward, and the sum of the two remains unchanged, always pointing to the same physical symbol.

[0153] The corrected intra-frame offset may extend beyond the boundaries of parallel blocks. The intra-frame offset ranges from 1 to... When the correction result is greater than When the frame header has fallen into the next parallel block, a carry is performed on the frame counter and the intra-frame offset is subtracted. When the correction result is less than 1, it indicates that the frame header has reverted to the previous parallel block, the frame counter has been borrowed, and the intra-frame offset has been added. For example, in the baseline scenario Assume the intra-frame offset is 4 when the frame header is locked; after that, the read start pointer is decremented once, the intra-frame offset is corrected to 5, which exceeds the upper limit, so the frame counter is carried over and the intra-frame offset falls back to 1. The absolute position of the frame header on the symbol stream has not changed, but its representation in the parallel block coordinates has been rewritten from the 4th symbol of the previous block to the 1st symbol of the current block.

[0154] As a fallback measure, the correction amount for the intra-frame offset can be cross-checked with the position of the relevant peak in the subsequent frame header. The frame length is known in the link, so the next frame header should appear at the position predicted by the frame counter and the corrected intra-frame offset. If the measured position of the relevant peak does not match the predicted position, it indicates an error in a link of the correction chain, such as an overflow signal being missed in the pipeline, or a timing misalignment between pointer adjustment and offset correction. In this case, a rollback is performed to re-execute the frame header detection and re-establish the reference for the intra-frame offset. Alternatively, instead of reverse correction, an absolute symbol counter independent of the parallel block coordinates can be maintained: its absolute symbol number is recorded when the frame header is locked, and each subsequent adjustment of the start pointer directly reflects the increment or decrement of this counter. The frame position is directly deduced from the absolute symbol number and frame length, no longer relying on successive corrections of the intra-block offset. This implementation trades the hardware cost of a wide-bit counter for the omission of correction logic. A simpler approach is to re-perform frame header detection and re-measure intra-frame offset for each frame, sacrificing tracking continuity to avoid correction. This approach is suitable for links with short frame lengths and acceptable re-detection overhead. While the timing loop continues to run after frame header locking, the intra-frame offset is synchronously corrected in the reverse direction along with the pointer adjustment, thereby preventing symbol boundary drift from eroding the locked frame position.

[0155] S3. In response to the frame header lock flag being valid, perform joint loop processing of carrier synchronization and automatic gain control on the parallel symbols. The joint loop processing simultaneously performs carrier phase error detection and carrier amplitude error detection on the same parallel symbol, obtaining the carrier phase error and carrier amplitude error respectively. The carrier phase error is filtered by the carrier loop to obtain the frequency control word, which is fed back to the down-conversion digitally controlled oscillator. The carrier amplitude error is filtered by the carrier loop to obtain the amplitude control word, which is fed back to the matched filter output.

[0156] The coarse frequency offset output by S2 is a one-time open-loop estimate, and its accuracy is limited by the phase angle resolution of a single correlation value. Furthermore, the frequency drift of the crystal oscillator, the phase noise of the channel, and the amplitude fading will continue to change over time, and open-loop compensation cannot keep up with them. Therefore, a closed loop is still required after frame header locking to continuously track the residual phase and amplitude errors.

[0157] In its implementation, S3 initiates a joint loop after frame header locking, performing decision-oriented carrier phase error detection and magnitude-based amplitude error detection for each symbol. After loop filtering, it generates carrier frequency control words and amplitude control words, which are then fed back to the down-conversion stage and the matched filter stage. There are two error channels and two feedback points: the phase channel detects the angle between the received symbol and its decision result, outputs a frequency control word after carrier loop filtering, and feeds it back to the phase accumulator of the down-conversion digitally controlled oscillator, correcting the carrier frequency and phase; the amplitude channel detects the deviation between the magnitude of the received symbol and the ideal magnitude, outputs an amplitude control word after carrier loop filtering, and feeds it back to the multiplier at the output of the matched filter, correcting the signal gain. Although the two channels are independent, they share the same set of inputs, namely the inputs of the same parallel symbol. , The value, and the result of the same hard decision.

[0158] The reason why two channels can share the same set of inputs without interfering with each other lies in the fact that phase and amplitude are two orthogonal degrees of freedom in the complex plane: the phase error is given by the cross product of the received and decision symbols, which is only sensitive to the angle between the two vectors and is independent of the common scaling of the vector lengths; the amplitude error is given by the magnitude of the received symbol, which is only sensitive to the vector length and is independent of the rotation of the vector. A single amplitude correction does not change the phase of the symbol, thus not contaminating the phase error; a single phase correction does not change the magnitude of the symbol, thus not contaminating the amplitude error. Therefore, the same set of symbols can be used by two loops simultaneously, without the need to insert dedicated pilots or training sequences for automatic gain control.

[0159] Specifically, refer to Figure 4 S3 includes sub-steps S31 to S36.

[0160] S31. In response to the frame header lock flag being valid, the carrier synchronization and automatic gain control joint loop is initiated. The frame header lock flag is the sole activation condition for this loop. The reason for initiating the joint loop only after frame header lock is that before frame header lock, the receiver has not yet determined the frame position of the symbol, while the phase detector of the carrier loop relies on correct symbol decision. Decision-oriented phase detectors need to determine the received symbol to the correct constellation point. If initiated before frame header lock, the error rate of symbol decision is high due to the unknown frame position. Incorrect decision results, when sent to the phase detector as reference symbols, will provide error signals that are unrelated to or even opposite in direction to the true phase error, thus causing mislocking of the carrier loop. After frame header lock, the symbol position is known, and the loop can start working from the correct initial state. The output of this step is the loop enable signal, which is used by the various operational units from S32 to S36.

[0161] S32. For each symbol within the parallel block, a hard decision is performed to obtain its ideal constellation point, and the carrier phase error is detected by the deviation between the received symbol and the hard decision result. This step is completed by a symbol decision unit and a carrier phase error detector connected in series: the symbol decision unit makes a hard decision on the parallel symbols and outputs the hard decision result; the carrier phase error detector then calculates the carrier phase error based on the deviation between the received symbol and the hard decision result. Hard decision maps continuously taking values ​​of the received symbols to a finite set of constellation points, thus making "how far the received symbol has deviated" a calculable quantity. This is the basic mechanism of decision-guided phase detection, where the decision result acts as a known reference symbol, and the angle between the received symbol and this reference symbol is the carrier phase error. Taking QPSK modulation as an example, let the received symbol be... The symbol after the judgment is ,in, The imaginary unit, and These are the in-phase and quadrature components of the received symbol, respectively. and These are the in-phase and quadrature components of the post-decision symbol, respectively, with values ​​of [value]. After normalization, it becomes The output of this step is within a parallel block. Each symbol's carrier phase error This is used for S34 aggregation; the specific formula is explained in the following section on the implementation of the phase detector.

[0162] S33. For each symbol within the parallel block, the carrier amplitude error is calculated by the carrier amplitude error detector using the following formula:

[0163]

[0164] in, This represents the carrier amplitude error. For QPSK modulation, the ideal symbol has a magnitude of 1 under normalization conditions. Therefore, this formula gives the deviation of the magnitude of the currently received symbol from the ideal magnitude: when the magnitude is greater than 1, the error is negative, indicating that the signal amplitude is too large; when the magnitude is less than 1, the error is positive, indicating that the signal amplitude is too small. For example, when the magnitude of the received symbol is 1.1, substituting it into the formula yields... This negative value, after being filtered by the subsequent loop, causes the gain to adjust downwards, pulling the magnitude back to near 1, thus forming negative feedback. This error detection does not depend on a specific symbol position; therefore, the amplitude error can be calculated independently for each symbol. The amplitude error of each symbol is given in parallel within the same clock cycle and aggregated by S34.

[0165] In some embodiments, to avoid square root operations, the absolute values ​​of the in-phase and quadrature components are used to approximate the magnitude. It should be understood that the absolute values ​​and the magnitude have a coefficient related to the symbol phase, which takes a fixed value at the constellation points: for QPSK, the in-phase and quadrature components of an ideal symbol have equal amplitudes, and their sum of absolute values ​​equals the magnitude. Therefore, when using absolute values ​​and approximations, the absolute values ​​and sums must first be multiplied by a factor of 1. The scaling factor is then subtracted from 1, i.e.:

[0166]

[0167] The value of this expression is exactly zero at the ideal sign, and the loop still converges to a modulus of 1. As an equivalent notation, scaling can be omitted, and the reference constant in the expression can be taken as the sum of the absolute values ​​of the ideal signs under this approximation, i.e. The two differ by only one. The open-loop gain factor can be absorbed in the coefficients of the loop filter.

[0168] S34. Move the current parallel block within... The average carrier phase error for that clock cycle is obtained by averaging the carrier phase error and carrier amplitude error for each symbol. and average carrier amplitude error The purpose of aggregation is to leverage the cumulative effect of multiple symbols to smooth out noise and improve the reliability of error estimation: within parallel blocks Each error is a set of multiple observations of the carrier phase and gain at the same time, whose noise components are uncorrelated. Averaging these observations reduces the noise variance by the number of signs. Since the symbols arrive simultaneously within the parallel block, the averaging operation can be completed within a single clock cycle. In the implementation, each branch (phase and amplitude) has an accumulator-average unit. The M error values ​​are first summed within the accumulator-average unit, and then shifted right as a whole. The division by M is performed bitwise without a divider. For example, in the baseline scenario, M = 4, and the sum is right-shifted by 2 bits to obtain the mean error. The output of this step is two mean errors, which are used by the phase branch and amplitude branch of S35, respectively.

[0169] S35. The average carrier phase error and average carrier amplitude error are respectively filtered through a second-order loop to generate the frequency control word and amplitude control word. The carrier loop filter consists of two branches: a phase loop filter and an amplitude loop filter. Both branches are second-order structures, filtering the average carrier phase error and average carrier amplitude error respectively. The transfer function of the phase loop is:

[0170]

[0171] in, The clock cycle number. For the first Frequency control word per clock cycle, For the first Average carrier phase error over one clock cycle This is the proportionality coefficient. The integral coefficients are summed from the first clock cycle since the loop started to the current clock cycle. Each clock cycle. The proportional branch responds instantly to the current error for fast tracking, while the integral branch accumulates historical errors to eliminate steady-state phase deviation; the frequency control word is the sum of the outputs of the two branches. In the specific implementation, the integral branch is implemented using an accumulator, which adds the current average carrier phase error to its registered value in each clock cycle, and multiplies the registered value by... The summation is then added to the output of the proportional branch, therefore the summation in the above equation does not require saving the historical error sequence. The parameter design of the loop filter follows the general principles of a second-order loop, and the damping factor is taken as... To achieve good convergence characteristics, this value represents a trade-off between the overshoot and convergence speed of the second-order loop step response. The frequency control word is accumulated to the phase accumulator of the down-conversion digitally controlled oscillator to achieve continuous carrier phase tracking.

[0172] The transfer function of the amplitude loop is:

[0173]

[0174] in, For the first Amplitude control word per clock cycle, For the first Average carrier amplitude error over one clock cycle This is the proportionality coefficient. The integral coefficient is also implemented by a cycle-by-cycle accumulator. The amplitude loop uses a second-order loop instead of a first-order loop because the signal amplitude may simultaneously exhibit rapidly changing fading and slowly changing bias. The second-order loop tracks the rapidly changing bias through the proportional branch and eliminates steady-state deviation through the integral branch, achieving better steady-state performance than the first-order loop. The amplitude control word is fed back to the multiplier at the output of the matched filter for amplitude weighting correction: the current signal amplitude is multiplied by... To achieve closed-loop gain adjustment, the received symbol amplitude is ultimately converged to near the ideal value of 1. Continuing from the values ​​in S33, when the received symbol magnitude is 1.1, the carrier amplitude error is... After loop filtering, the amplitude control word accumulates in the negative direction, and the gain factor... If the value is less than 1, the modulus is pushed back to around 1.

[0175] As an alternative implementation, the amplitude loop can also adopt a first-order structure, that is, omitting the integral branch and only retaining the proportional branch, which has lower hardware overhead. However, for slowly varying amplitude bias, it can only retain a steady-state error proportional to the bias, which is suitable for links where gain drift is negligible. Similarly, amplitude error detection can also retain the square root operation instead of the absolute value and approximation, in exchange for the accuracy of the error, at the cost of the square root's resources and pipeline stages.

[0176] S36. Configure the filter coefficients for the phase loop and amplitude loop respectively. The phase loop and amplitude loop share the same set of error signal sources, i.e., for each symbol... , The values ​​are independent, but sharing an input does not mean sharing parameters. Phase loop filter coefficients. , With amplitude loop filter coefficients , These are configured independently to adapt to the different dynamic characteristics of phase and amplitude changes. Typically, the phase loop bandwidth is designed to be larger than the amplitude loop bandwidth to meet the higher dynamic performance requirements of carrier phase tracking: the carrier phase is driven by frequency drift and phase noise, and its rate of change is fast, requiring a sufficiently wide loop bandwidth to keep up. The amplitude loop bandwidth is designed to be narrower to suppress the impact of noise on amplitude estimation: gain drift and slow fading change at slow rates, and a narrow bandwidth is sufficient for tracking while keeping noise out of the loop. The output of this step is two sets of filter coefficients, which are backfilled into the two branches of S35.

[0177] The aforementioned activation conditions only answer "when to start," but fail to address three other questions: what reference symbol is used when the loop has just started and the decision is not yet reliable; what sustains the loop when pilot gaps or missing reference symbols appear in the frame structure; and how is a false lock detected and recovered? These three questions are typically addressed by independent methods: activation relies on specially inserted training sequences, gaps on encrypted pilots, and false locks on independent lock detectors. However, in this embodiment, S2 has already located a frame header sequence with a completely known phase, which is sufficient to serve as a reference for all three scenarios simultaneously.

[0178] In some embodiments, the joint loop processing of S3 operates in four states driven by a frame header reference, where the frame header reference is the local frame header sequence located in parallel frame header detection. The four states include soft-start state, tracking state, gap maintenance state, and recapture state.

[0179] In the soft-start state, the frame header reference is used as the reference symbol for carrier phase error detection. In response to the mean value of the carrier phase error being lower than the convergence threshold for several consecutive clock cycles, the system enters the tracking state.

[0180] In tracking mode, the hard decision result of parallel symbols is used as a reference for carrier phase error detection, and the carrier phase is periodically checked with the frame header reference. In response to the check deviation exceeding the mislock threshold or the frame header lock flag failing for multiple consecutive frames, the system enters reacquisition mode. In response to entering a known pilot gap, the system enters gap maintenance mode.

[0181] In the gap-maintaining state, the missing pilot symbols are replaced with frame header references to maintain the updates of the joint loop processing, and the tracking state is returned in response to leaving the pilot gap.

[0182] In the reacquisition state, parallel frame header detection is re-executed and coarse frequency offset is re-estimated. In response to successful reacquisition, the system returns to the soft-start state.

[0183] Reference Figure 5 The difference between the four states lies in the source of the reference symbols used for carrier phase error detection. In the soft-start state, the reference symbol is taken from the frame header because the decision is not yet reliable. In the tracking state, the reference symbol is taken from the hard decision result of the parallel symbols because the decision is already reliable, and the number of data symbols is much greater than that of the frame header symbols, providing more frequent error updates for the loop. In the gap-maintaining state, the frame header reference is retrieved again when the pilot is missing to prevent the loop from opening. In the reacquisition state, tracking is stopped, and the system returns to S2 to re-establish the frame position and coarse frequency offset. All four states share the same located frame header sequence as the only known reference, eliminating the need to insert any dedicated sequences into the frame structure.

[0184] The soft-start state uses frame header reference for phase detection instead of hard decision-making based directly on data symbols; its inevitability can be deduced from the decision boundaries. When the carrier loop is first started, the residual phase is random and will inevitably sweep across the entire phase interval during convergence. For a QPSK constellation, the decision boundary between two adjacent constellation points lies at... When the residual phase approaches this boundary, the probability of the received symbol landing on either side of the boundary is nearly equal. The hard decision result jumps back and forth between two adjacent constellation points, resulting in a phase error that fluctuates wildly between positive and negative values. Its mean may even point in the wrong direction, potentially causing the loop to lock into the phase difference. The phase error occurs at integer multiples of the original phase, or lingers near the boundary for an extended period without convergence. However, the phase of the frame header symbol is known a priori, and its "decision result" does not depend on the current residual phase. As a result, the phase detector bypasses the entire decision boundary region, and the error signal always points to the true phase deviation.

[0185] The switching criteria between states are all derived from the state variables already calculated within the loop, without introducing any additional detectors. The criterion for transitioning from the soft-start state to the tracking state is the convergence criterion: the average carrier phase error output by S34. When its absolute value is continuous When the clock cycle count is below the convergence threshold, the loop is considered to have converged, and the system switches to tracking mode. Continuous judgments, rather than single judgments, are used to avoid premature switching caused by occasional drops in single-shot errors due to noise. There are two criteria for switching from tracking mode to reacquisition mode: one is the false lock criterion, where a frame header reference is periodically taken in tracking mode for re-phase detection. If the resulting phase deviation exceeds the false lock threshold, it indicates that the loop has locked onto the wrong phase. The other is the loss of lock criterion, where if the frame header lock flag fails for multiple consecutive frames, it indicates that the signal has been interrupted or the channel has deteriorated, making continued tracking meaningless. The switching between tracking mode and gap maintenance mode is driven by a pilot counter, the criterion being whether the current symbol falls within a known pilot gap.

[0186] The tuning criteria for each threshold are as follows. The convergence threshold is set based on the steady-state phase jitter of the loop. Its value should be higher than the order of magnitude of the steady-state jitter but lower than the phase error corresponding to the decision boundary, ensuring that the convergence decision is neither repeatedly triggered due to jitter nor misjudged as convergence before leaving the decision boundary region. For QPSK, the decision boundary corresponds to... The convergence threshold is usually taken as a fraction of this threshold. The false locking threshold is also referenced to the decision boundary: if the loop locks to a different phase... At the erroneous phase, the phase detection deviation of the frame header reference will reach [a certain value]. The magnitude is so high that the false locking threshold should be set significantly lower than that of the false locking threshold. A value significantly higher than the median steady-state jitter value is sufficient for reliable differentiation. The number of frames lost is taken on the order of frames; if the value is too small, instantaneous deep fading of the channel will trigger unnecessary reacquisition; if the value is too large, recovery after actual loss of lock will be delayed. The number of consecutive cycles for convergence determination... It is related to the loop bandwidth and is generally taken as a multiple of the number of clock cycles corresponding to the loop time constant.

[0187] The frame header sequence reused by the four-state machine is an overhead inherent in the frame structure for frame synchronization, and its phase is fully determined when S2 completes the correlation operation. Since the four states reuse the same sequence, the following occurs: the loop startup transient does not require a dedicated training sequence with a length covering the loop acquisition time; the pilot gap does not require an encrypted pilot; and neither consumes payload bandwidth. Lock-up detection does not require a separate lock-up detector or its internal error statistics and threshold logic; and lock-up re-acquisition does not require a separate acquisition channel; neither consumes additional hardware resources. In the startup transient, pilot gap, and lock-up scenarios, the carrier loop uses the located frame header as a single known reference, ensuring that carrier lock can be maintained and automatically recovered even when reference symbols are missing or symbol decision is distorted.

[0188] As a simplified alternative arrangement, the gap maintenance state can be incorporated into the tracking state, with the reference symbol source switched internally by a pilot counter within the tracking state. This compresses the four states into three: soft start, tracking, and reacquisition. This arrangement has simpler state transition logic, but at the cost of coupling the timing of reference symbol switching with state transitions within the same state, reducing the observability of debugging and verification. Another alternative arrangement is to retain the conventional independent lock detector to drive the entry into the reacquisition state. This means that the frame header reference is not reused for false lock checking; instead, the lock detector independently calculates the error variance and provides a lock indication. This arrangement has better compatibility with existing carrier recovery modules, but at the cost of an additional statistical logic path and a set of independently tuned thresholds.

[0189] After the four states coexist, there are still two boundaries that need to be closed. As an optional implementation, the soft-start state has higher priority than the gap maintenance state, and if the recapture state fails to recapture within a preset number of frames, the state of the joint loop processing is frozen and a lock-out flag is output.

[0190] The first boundary is state contention. Before the soft-start state has converged, the pilot counter might have just advanced into the pilot gap, at which point the entry conditions for both the soft-start and gap-maintaining states are met simultaneously. Priority arbitration resolves this by prioritizing the soft-start: the soft-start state uses the frame header as a reference for phase detection, so the presence or absence of the pilot has no impact on its operation. Switching into the gap-maintaining state neither changes the source of the reference symbol nor the loop update method; the switch itself offers no benefit and instead introduces an unnecessary state jump during convergence. The second boundary is the frequent back-and-forth between the tracking state and the gap-maintaining state: if the pilot gap criterion uses only one threshold, near the start and end boundaries of the gap, the quantization error of the counter or the jitter of the symbol will cause the criterion to repeatedly flip on both sides, causing the state machine to jitter. In practical implementations, different thresholds are set for entry and exit, creating hysteresis: the threshold for entering the gap-maintaining state is slightly earlier than the nominal start point of the gap, and the threshold for exiting is slightly later than the nominal end point, thus absorbing the jitter near the boundaries.

[0191] In the reacquisition state, a frame counter is set. Each time parallel frame header detection is re-executed and the frame header lock flag is still invalid, the counter is incremented. If the counter exceeds the preset frame count without successful reacquisition, the frequency control word and amplitude control word are frozen at their current values, error updates in both loops are stopped, and a loss-of-lock flag is output, awaiting upper-layer reset or RF front-end reacquisition. The reason for freezing rather than clearing is that the most common cause of continuous reacquisition failure is prolonged deep fading or brief signal interruption, during which the frequency deviation of the transceiver crystal oscillator does not change significantly. The frozen frequency control word is usually still close to the true frequency deviation, and when the signal recovers, the loop can continue to pull in from this value, with a convergence speed much faster than reacquisition from zero. The preset frame count depends on the longest fading duration the link will experience: if the value is too small, a normal deep fading will be misjudged as a permanent loss of lock; if the value is too large, a true link interruption will be delayed in reporting. State contention during the startup phase is resolved by priority arbitration, and the loop state is frozen when continuous recapture fails, thereby preventing the state machine from infinitely recapturing under extreme conditions.

[0192] The state machine determines the source of the reference symbols used for phase detection, followed by the formulas for the phase detector itself. The carrier phase error can optionally be obtained through the cross product operation between the hard decision results of parallel symbols. The cross product operation is implemented by taking the sign, multiplying, and subtracting, without division or inverse trigonometric function operations.

[0193] In a practical implementation, taking QPSK as an example, the phase error is calculated using the following formula:

[0194]

[0195] in, For carrier phase error, This indicates the sign operation. The physical meaning of this phase detector is: to perform a cross product operation between the received symbol vector and the decision symbol vector. The magnitude of the cross product is proportional to the sine of the angle between the two vectors, and within a small angular error range, it has a linear relationship with the phase deviation. For example, suppose the received symbol falls in the first quadrant, and its decision result is... Then both symbolic functions take If the received symbol is rotated by +1 relative to the ideal constellation point. That is, its phase is ,but , Substituting into the above formula, we get This value is related to Consistent. Within a small angular range, the ratio of error to phase deviation is approximately constant. The phase detection curve is linear, and therefore the open-loop gain of the circuit does not change with the magnitude of the phase error. For BPSK modulation, the phase error simplifies to... .

[0196] This calculation only involves sign extraction, multiplication, and subtraction, without requiring division or arctangent operations, making it suitable for hardware implementation: sign extraction only requires taking the highest bit, and multiplication with the decision sign degenerates into either inverting or not inverting the sign bit. The entire phase detector consists of three levels of combinational logic: sign extraction, inversion, and addition, which can be implemented in a parallel pipeline with a fixed latency. Phase detection for each symbol is performed in parallel within the same clock cycle. As an alternative implementation, the phase angles of the received and decision symbols can be directly arctangented and subtracted to obtain a strictly linear phase detection curve. This results in a wider detection range and better linearity under large errors. The trade-off is that each symbol requires an arctangent operation, which, in a parallel architecture, requires... Using lookup tables or coordinate rotation digital computation units, resource overhead increases linearly with parallelism.

[0197] The above aggregation pairs within parallel blocks The average of all errors is calculated equally, but this The reliability of the decision for each symbol is not the same: symbols falling near constellation points are almost always correctly decided; symbols falling near decision boundaries may be incorrectly decided, and once incorrectly decided, the reference symbol used by the phase detector is wrong. The resulting error signal is not only useless, but also a random interference. In other embodiments, the carrier phase error and carrier amplitude error are weighted according to the distance between parallel symbols and hard decision results, and then the average value is calculated separately.

[0198] In practical implementation, the distance from the received symbol to its hard decision constellation point is used as the surrogate quantity for decision confidence: the smaller the distance, the closer the symbol is to the constellation point and the more reliable the decision; the larger the distance, the closer the symbol is to the decision boundary and the higher the probability of error. This distance can be in the form of the sum of absolute values. This allows for the reuse of the existing absolute value circuit in amplitude error detection, eliminating the need for a square root extractor; its required... , and , These are all quantities already calculated in phase detection and amplitude detection, without adding new input. The weights are taken as a monotonically decreasing function of the distance: in the specific implementation, a piecewise form can be adopted, with the weight of those below the preset threshold being 1, and the weight of those above the threshold being halved or directly set to zero. Setting it to zero degenerates into soft rejection.

[0199] The weighted mean is obtained by dividing the weighted sum by the sum of the weights. The weights are quantized to powers of 2; division can still be achieved by bit shifting. Quantizing the weights to 2 or 3 bits is sufficient to cover the required number of segments. The distance threshold is generally taken as a fraction of the normalized constellation point spacing. If the value is too large, the weighting loses its discriminative power and degenerates into equal weighting; if the value is too small, a large number of symbols are eliminated, and the density of error updates decreases. As a simplification approach, weighting can also be omitted, directly eliminating symbols whose distance exceeds the threshold and only calculating the average of the remaining symbols with equal weights. Low-confidence symbols near the decision boundary are thus assigned smaller weights in error aggregation, reducing the contamination of the loop error signal by erroneous decisions.

[0200] Even after carrier loop convergence, a layer of ambiguity remains. The error of a decision-guided phase detector is taken from the angle between the received symbol and its hard decision result, while the QPSK constellation rotates... After multiples of itself, it completely overlaps with itself, the set of constellation points remains unchanged, and the judgment result is only a change in the overall label. The error given by the phase detector is exactly the same as when it is not rotated. Therefore, the phase detector has no ability to distinguish this fourfold rotational symmetry, and the loop can be stably locked on. , , , At any phase, after locking, the entire constellation diagram of the data block is rotated relative to the origin. If the result is an integer multiple of the original value, the demodulation result will be completely corrupted.

[0201] In one alternative implementation, after carrier synchronization is locked, the mapping relationship between the decision quadrant of the pilot symbol and the local pilot quadrant is used to determine the rotation factor corresponding to the quadruple phase ambiguity. The data block is then rotated inversely to eliminate the phase ambiguity caused by carrier synchronization, and differential coding is not used.

[0202] In the specific implementation, the fuzzy judgment and compensation are divided into four steps. First, the known pilot symbols within the frame are taken, and the quadrant in which their hard decision result after carrier synchronization falls is read. Second, this quadrant is subtracted from the true quadrant of the pilot symbol stored locally to obtain the quadrant difference. , The value can be one of 0, 1, 2, or 3; since the entire data block is rotated by the same fuzzy phase, the quadrant difference has the same value for all symbols within the block. Furthermore, the quadrant difference is mapped to a rotation factor. Its set of values ​​is The four elements correspond in sequence. , , , Finally, by multiplying all the symbols in the data block by the rotation factor and performing an inverse rotation, the constellation diagram is restored to its original orientation. For example, quadrant difference... When the rotation factor is The entire data block was rotated in reverse. If a received symbol falls in the second quadrant after carrier synchronization, it will return to the first quadrant after reverse rotation, and its decision result will be recovered from the symbol actually sent by the transmitting end.

[0203] Quadrant determination for a single pilot symbol can also be corrupted by noise. Therefore, when a frame contains multiple pilot symbols, the quadrant difference for each pilot is determined separately, and the mode is taken as the quadrant difference for the data block. Since all pilots bear the same ambiguous phase, their quadrant differences should be consistent. The deviation values ​​given by individual pilots due to noise are filtered out by the mode vote.

[0204] Another technical approach to eliminate this ambiguity is differential coding. Differential coding carries information in the phase difference between adjacent symbols. The receiver only needs to perform differential demodulation of adjacent symbols, and the overall rotation naturally cancels out the phase difference, thus being naturally immune to phase ambiguity without any judgment or compensation logic. The cost is that differential demodulation brings noise from both symbols into the same decision, resulting in an error rate loss of about 3dB compared to coherent demodulation at the same signal-to-noise ratio. This embodiment does not use differential coding, but directly determines and compensates for ambiguity based on the known quadrant relationship of the pilots, preserving coherent demodulation. The cost is one quadrant subtraction, one lookup table mapping, and one complex multiplication.

[0205] As a fallback, if the quadrant differences of multiple pilots within a frame remain inconsistent after a majority vote, it indicates that the rotation phase experienced by each pilot is not the same, meaning the carrier loop is not truly locked to a stable phase. In this case, reverse rotation should not be performed; instead, it should be determined as a false lock and the system should revert to the reacquisition state to re-establish lock. As an alternative approach, ambiguity can also be determined directly from the frame header sequence without using pilots. The phase of the frame header symbol is also known a priori, and the difference between its decision quadrant and the local quadrant also provides the quadrant difference. This approach is usable in frame structures without pilots outside the frame header, at the cost of only being able to determine ambiguity once per frame header, and failing to follow up if a phase jump occurs within a block. The inherent fourfold phase ambiguity of carrier synchronization is thus directly determined and compensated for by the known quadrant relationship of the pilots, and demodulation always maintains a coherent form.

[0206] After the loop reaches steady state, it is necessary to distinguish between two different types of frequency offset changes. One type is slow drift caused by crystal oscillator temperature drift, Doppler shift, etc., whose rate of change is much lower than the loop bandwidth. The carrier loop can already track continuously, and if reacquisition is triggered due to this, it will break the established lock. The other type is frequency offset jump caused by RF front-end local oscillator switching, channel frequency hopping, or the reappearance of a signal interruption. Its amplitude may far exceed the loop's acquisition band, and the loop cannot catch up no matter how it tracks. In this case, the only option is to return to S2 for reacquisition. Distinguishing between the two requires a dynamic frequency offset observation, which does not need to be built separately, as it already exists in the loop.

[0207] In some embodiments, the rate of change of the frequency control word is used as the criterion for frequency offset jump, and parallel frame header detection and coarse frequency offset estimation are re-executed when the rate of change exceeds a preset threshold.

[0208] In practical implementation, as shown by the transfer function of the phase loop, the integral branch continuously accumulates the average carrier phase error. In steady state, the mean of the phase error tends to zero, and the output of the proportional branch also tends to zero. The accumulated value of the integral branch precisely compensates for the current carrier frequency offset; that is, the frequency control word in steady state is proportional to the current carrier frequency offset. The first-order difference of the frequency control word is taken. This yields the rate of change of frequency offset. This quantity is a state variable already calculated within the loop, requiring no additional detection hardware. To suppress false triggering caused by noise, a moving average can be applied to the first-order difference before comparing it with the threshold.

[0209] The tiered responses based on the criteria are as follows: If the first-order differential is below the preset threshold, it is judged as a slow drift, and no intervention is taken; the carrier loop continues tracking, and the lock is not interrupted. If the first-order differential is above the preset threshold, it is judged as a frequency offset jump, triggering the aforementioned reacquisition state. It returns to S2 to re-execute parallel frame header detection and coarse frequency offset estimation, and reuses the coarse frequency offset channel assisted by the frame header to push the frequency offset back into the acquisition band. The threshold is set according to the loop bandwidth: the value should be higher than the maximum frequency control word change rate that the loop can generate under normal tracking, and lower than the change rate corresponding to the jump. The difference between the two is usually more than an order of magnitude, and the selection of the threshold has a wide margin.

[0210] The same synchronization status flag can also be used for graded switching of loop parameters: in reacquisition and soft-start states, the coefficients of the timing loop, phase loop, and amplitude loop are all switched to a larger set, thus widening the loop bandwidth and quickly reducing frequency offset and timing error; after the tracking state stabilizes, the coefficients of the three loops are uniformly switched to a smaller set, narrowing the loop bandwidth, reducing the contribution of noise to the loop, and decreasing steady-state jitter. The bandwidth switching is driven by the same status flag, and the three loops switch synchronously to avoid mutual interference between loops under different bandwidths. If the transition detection is triggered multiple times consecutively and each reacquisition fails, the frame counter in the reacquisition state is used as a fallback, freezing the loop state and reporting a loss of lock. The slowly drifting frequency offset is thus handed over to the carrier loop for continuous tracking without interrupting the lock, and reacquisition is only triggered when a frequency offset transition occurs.

[0211] The aforementioned S1 to S3 arithmetic units are synchronized through register clocking, forming a fully pipelined architecture, thereby ensuring that the processing of a parallel block is completed within a single clock cycle.

[0212] The same or similar parts in the various embodiments of this application may be referred to each other; the technical features described in the various embodiments may be combined with each other to form new embodiments without conflict.

[0213] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A method for joint frame synchronization and carrier synchronization in a parallel wireless communication receiver, characterized in that, Includes the following steps: S1. Perform parallel timing synchronization on the parallel sampling points obtained by downconversion to obtain parallel symbols with symbol rate alignment; S2. Perform parallel frame header detection on the parallel symbols. The parallel frame header detection is achieved through differential conjugate correlation between the local frame header sequence and the parallel symbols. In response to the correlation value of the differential conjugate correlation satisfying the frame header determination condition, output the frame header locking flag and the intra-frame offset of the frame header within the parallel block. Perform coarse frequency offset estimation based on the correlation value to obtain the coarse frequency offset. Feed the coarse frequency offset back to the down-conversion numerically controlled oscillator for frequency offset compensation. S3. In response to the frame header lock flag being valid, a joint loop processing of carrier synchronization and automatic gain control is performed on the parallel symbols. The joint loop processing simultaneously performs carrier phase error detection and carrier amplitude error detection on the same parallel symbol to obtain carrier phase error and carrier amplitude error respectively. The carrier phase error is filtered by the carrier loop to obtain a frequency control word, and the frequency control word is fed back to the down-conversion digitally controlled oscillator. The carrier amplitude error is filtered by the carrier loop to obtain an amplitude control word, and the amplitude control word is fed back to the matched filter output.

2. The frame synchronization and carrier joint synchronization method for a parallel wireless communication receiver according to claim 1, characterized in that, The joint loop processing of S3 operates in four states driven by a frame header reference. The frame header reference is the local frame header sequence that has been located in the parallel frame header detection. The four states include soft-start state, tracking state, gap maintenance state, and recapture state. In the soft-start state, the frame header reference is used as the reference symbol for carrier phase error detection. In response to the mean value of the carrier phase error being lower than the convergence threshold for multiple consecutive clock cycles, the system enters the tracking state. In the tracking state, the hard decision result of the parallel symbol is used as the reference for the carrier phase error detection, and the carrier phase is periodically checked with the frame header reference. In response to the check deviation exceeding the false lock threshold or the frame header lock flag failing for multiple consecutive frames, the system enters the reacquisition state. In response to entering a known pilot gap, the system enters the gap maintenance state. In the gap-maintaining state, the missing pilot symbols are replaced with the frame header reference to maintain the update of the joint loop processing, and the tracking state is returned in response to leaving the pilot gap; In the re-acquisition state, the parallel frame header detection is re-executed and the coarse frequency offset is re-estimated. In response to successful re-acquisition, the system returns to the soft-start state.

3. The frame synchronization and carrier joint synchronization method for a parallel wireless communication receiver according to claim 1, characterized in that, S1 includes the following sub-steps: S11. Write the parallel sampling points into the parallel shift storage space; S12. Starting from the read start pointer, read the sampling points from the parallel shift storage space, divide them into multiple groups according to the step size of half a symbol period, and input them into the parallel Farrow filter bank at fractional intervals to obtain parallel interpolation results with alternating sign points and zero crossing points. The number of groups of the parallel interpolation results is twice the ratio of the number of parallel sampling points to the oversampling factor plus one. S13. Taking adjacent sign points, zero crossing points and sign points in the parallel interpolation results as a group, calculate the timing error through the parallel Gardner timing error detector; S14. The timing error is filtered by a timing loop filter and output to a timing numerically controlled oscillator.

4. The frame synchronization and carrier joint synchronization method for a parallel wireless communication receiver according to claim 3, characterized in that, The update amount of the fractional interval is the product of the timing control word output by the timing loop filter and the number of parallel paths corresponding to the parallel sampling point. The fractional interval is obtained by taking the modulo of a sampling interval by the sum of the previous fractional interval and the update amount.

5. The frame synchronization and carrier joint synchronization method for a parallel wireless communication receiver according to claim 4, characterized in that, In response to an overflow of the accumulated result of the fractional interval, the read start pointer is decremented by one; in response to an underflow of the accumulated result of the fractional interval, the read start pointer is incremented by one; the initial value of the read start pointer is the oversampling factor. After the frame header lock flag is valid, the read start pointer is continuously updated, and the intra-frame offset is synchronously corrected in the opposite direction as the read start pointer is adjusted.

6. The frame synchronization and carrier joint synchronization method for a parallel wireless communication receiver according to claim 1, characterized in that, In step S2, the differential conjugate correlation simultaneously calculates correlation values ​​for multiple candidate start positions of the local frame header sequence and the parallel symbols within one clock cycle. The number of candidate start positions is equal to the number of symbols in a parallel block. The intra-frame offset is determined by the candidate start positions whose correlation values ​​satisfy the frame header determination conditions.

7. The method for joint frame synchronization and carrier synchronization of a parallel wireless communication receiver according to claim 6, characterized in that, The frame header determination condition is that the modulus of the correlation value exceeds an adaptive threshold, and the adaptive threshold is the product of the cumulative average of the correlation value over multiple consecutive parallel blocks and a preset multiplier coefficient.

8. The frame synchronization and carrier joint synchronization method for a parallel wireless communication receiver according to claim 1, characterized in that, In S2, the coarse frequency offset is calculated from the phase angle of the correlation value of the differential conjugate correlation, and in the same locking process, the coarse frequency offset estimation is only performed once when the frame header locking flag is first effective.

9. The method for joint frame synchronization and carrier synchronization of a parallel wireless communication receiver according to claim 1, characterized in that, In step S3, the carrier phase error is obtained by cross product operation between the parallel symbols and the hard decision results of the parallel symbols. The cross product operation is implemented by taking the sign, multiplying and subtracting, and does not include division and inverse trigonometric function operations.

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