An insulated gate bipolar transistor device and a method of fabricating the same

Abstract

The application discloses an insulated gate bipolar transistor device and a preparation method thereof, and the method comprises the following steps: 1, depositing a mask on an intermediate substrate, etching to form a groove, and obtaining an etched intermediate substrate; 2, sequentially adopting a first cleaning process, a second cleaning process and a third cleaning process to clean the etched intermediate substrate; each cleaning process comprises a hydrofluoric acid sub-process; wherein the hydrofluoric acid sub-process is as follows: preparing a hydrofluoric acid solution according to a volume ratio of hydrofluoric acid to deionized water of 1:(50-200); placing the etched intermediate substrate in the hydrofluoric acid solution, and soaking at 20-30 DEG C for 180-600s; 3, using the cleaned intermediate substrate to prepare the insulated gate bipolar transistor device. The application prolongs the contact reaction time of the cleaning solution and the polymer by continuously soaking the groove with low-concentration HF for multiple times, and the etching rate of the field area oxide layer is extremely low under the low-concentration HF, so that the additional over-etching loss of the field oxide is greatly reduced.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device fabrication technology, specifically relating to an insulated gate bipolar transistor (IGBT) device and its fabrication method, applicable to the mass production of 600V~1700V Trench-FS type IGBT devices. Background Technology

[0002] Trench field-stop insulated gate bipolar transistors (FS-IGBTs) are core power switching devices for new energy vehicles, photovoltaic energy storage, industrial frequency conversion, and rail transportation. In mainstream mass production processes, PETEOS oxide thin film is used as the hard mask layer for dry etching of silicon trenches to ensure the accuracy of trench pattern morphology.

[0003] The existing standard wet processing flow after trench etching is as follows: Step 1: Cleaning with conventional diluted hydrofluoric acid (DHF) (short time) + high-temperature sulfuric acid-hydrogen peroxide mixture (SPM) + ammonia-hydrogen peroxide mixture (SC1) to remove large particles and loose contaminants from the wafer surface; Step 2: High-concentration buffered hydrofluoric acid (BOE) etching (short time) to quickly remove the entire PETEOS (Plasma-Enhanced Tetraethyl Orthosilicate, a silicon dioxide thin film prepared by plasma-enhanced chemical vapor deposition (PECVD)) hard mask; Step 3: Secondary conventional DHF (short time) + high-temperature SPM + SC1 cleaning to remove mask etching byproducts and residual impurities on the surface.

[0004] The existing technology has the following core defects: 1. Incomplete removal of trench polymers: During dry trench etching, dense fluorocarbon polymers are deposited on the sidewalls, corners, and deep bottoms of the trenches. Traditional processes using low-concentration HF have insufficient contact time with the etching byproduct polymers in the trench, resulting in inadequate removal capacity. High-concentration BOE etching, with its rapid reaction rate and extremely short trench wetting time, can only remove loose surface residues, leaving stubborn polymers deep within the trenches for a long time. These residual polymers isolate the silicon substrate from the subsequent high-temperature gate oxide growth interface, generating a large number of interface trap charges and interface states, severely damaging the gate oxide quality. 2. Severe over-etching of the field oxide layer: High-concentration BOE has a high corrosion rate for thermally grown field oxides. The combination of two cleaning processes plus a single strong etching process causes significant additional loss of field oxides over a large area.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] To address the aforementioned problems in the prior art, this invention provides an insulated-gate bipolar transistor device and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution: In a first aspect, the present invention provides a method for fabricating an insulated gate bipolar transistor device, comprising the following steps: S1. A mask is deposited on the intermediate substrate. After photolithography patterning, trenches are formed by fluorine-based plasma dry etching to obtain the etched intermediate substrate. S2. The etched intermediate substrate is cleaned sequentially using the first cleaning process, the second cleaning process and the third cleaning process to remove the residual fluorocarbon polymer in the mask and the trench. Each cleaning process includes a hydrofluoric acid sub-process, an SPM sub-process, and an SC1 sub-process; the hydrofluoric acid sub-process is as follows: a hydrofluoric acid solution is prepared according to a volume ratio of hydrofluoric acid to deionized water of 1:(50-200); the etched intermediate substrate is placed in the hydrofluoric acid solution and immersed at 20-30°C for 180-600 seconds; S3. An insulated gate bipolar transistor device is fabricated using the intermediate substrate cleaned in step S2.

[0007] Secondly, the present invention provides an insulated gate bipolar transistor device, which is obtained by the above-described preparation method.

[0008] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. This invention abandons the traditional high-concentration BOE etching system and adopts a three-stage low-concentration HF progressive etching and long-term immersion cleaning process. Through multiple continuous immersions of the trench with low-concentration HF, the contact reaction time between the cleaning process and the polymer on the trench sidewalls and bottom is significantly extended. This softens, peels off, and removes stubborn fluorocarbon polymers from the surface, middle, and deep layers, solving the problem of trench residue. At the same time, the low-concentration HF has an extremely low etching rate on the field oxide layer, significantly reducing the additional over-etching loss of field oxygen.

[0009] 2. The method provided by this invention, while completing the complete removal of the PETEOS hard mask, greatly improves the cleanliness of the trench and ensures the integrity of the field oxygen. It significantly reduces the overall drift and batch dispersion of the IGBT threshold voltage Vth from the source of the process, improves core electrical parameters such as gate leakage current, on-state voltage drop, and blocking withstand voltage, improves chip yield and long-term operational reliability, and the process is compatible with existing 8 / 12-inch IGBT mass production lines, which is conducive to large-scale mass production.

[0010] 3. This method employs low-concentration HF throughout the process, resulting in an extremely low etching rate for the thermally grown field oxide. Compared to the traditional high-concentration BOE process, the additional etching amount of field oxide is significantly reduced. Simultaneously, the clean, defect-free silicon / gate oxide interface and more uniform and complete field oxide structure after cleaning suppress overall Vth drift from the source, reducing batch dispersion.

[0011] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0012] Figure 1 This is a flowchart illustrating a method for fabricating an insulated gate bipolar transistor device according to an embodiment of the present invention; Figure 2 This is a schematic diagram of an intermediate substrate structure after trench etching, provided in an embodiment of the present invention. Detailed Implementation

[0013] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a detailed explanation of an insulated gate bipolar transistor device and its fabrication method based on the present invention.

[0014] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and concrete understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.

[0015] It should be noted that, in this document, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not explicitly listed.

[0016] Currently, after trench etching of IGBTs, a three-stage process is generally adopted, consisting of conventional cleaning with low-concentration HF, removal of the hard mask with high-concentration BOE, and secondary cleaning with low-concentration HF. High-concentration BOE has a fast etching rate, and in order to reduce the additional corrosion of field oxide, the immersion time of both low-concentration HF and BOE solutions in the trench is relatively short. However, the fluorocarbon polymer residue inside the high aspect ratio trench is serious. At the same time, due to the fast etching rate of high-concentration BOE solution, the over-etching of the field oxide layer is large, and the field oxide thickness is thinned. Incomplete removal of the polymer residue in the trench will lead to more interface defects in the subsequent gate oxide growth, large overall drift of the IGBT threshold voltage Vth, high batch dispersion, and low device yield and reliability.

[0017] To address the above problems, this invention provides an insulated-gate bipolar transistor (IGBT) device, which is fabricated using the following method, see below. Figure 1 Specifically, it includes the following steps: S1, such as Figure 2 As shown, a mask is deposited on the intermediate substrate, and trenches are formed by fluorine-based plasma dry etching to obtain the etched intermediate substrate.

[0018] For example, the mask deposition on the intermediate substrate is performed by using a plasma-enhanced tetraethyl orthosilicate (TIA) process to deposit a mask on the surface of the intermediate substrate to form a PETEOS hard mask.

[0019] S2. The etched intermediate substrate is cleaned sequentially using the first cleaning process, the second cleaning process, and the third cleaning process to remove residual fluorocarbon polymers in the mask and trenches. Each cleaning process includes a hydrofluoric acid sub-process, a SPM sub-process, and an SC1 sub-process; the hydrofluoric acid sub-process is as follows: a hydrofluoric acid solution is prepared according to a volume ratio of hydrofluoric acid to deionized water of 1:(50-200); the etched intermediate substrate is placed in the hydrofluoric acid solution and immersed at 20-30°C for 180-600 seconds.

[0020] In one embodiment of the present invention, the first cleaning process includes a first hydrofluoric acid sub-process, a first SPM sub-process, and a first SC1 sub-process. The first hydrofluoric acid sub-process includes: preparing a first hydrofluoric acid solution at a volume ratio of hydrofluoric acid to deionized water of 1:(100-200); immersing the etched intermediate substrate in the first hydrofluoric acid solution at 20-30°C for 180-240 seconds. In the first hydrofluoric acid sub-process, the surface structure of the PETEOS hard mask is slowly and uniformly etched in the first hydrofluoric acid solution, weakening the bonding force between the mask and the polymer; simultaneously, the low-concentration solution fully penetrates the deep holes of the trenches, wetting and softening the surface fluorocarbon polymer, and initially removing loose residues.

[0021] Preferably, the first hydrofluoric acid sub-process includes: preparing a first hydrofluoric acid solution with a volume ratio of hydrofluoric acid to deionized water of 1:100; placing the etched intermediate substrate in the first hydrofluoric acid solution and immersing it at 23°C for 120 seconds.

[0022] In some examples, the first SPM sub-process includes: preparing a first SPM cleaning solution at a sulfuric acid to hydrogen peroxide volume ratio of (5~10):1; placing the intermediate substrate after the first hydrofluoric acid sub-process in the first SPM cleaning solution and treating it at a temperature of 120~130°C for 300~600 s to remove residual carbon from the polymer. The first SC1 sub-process includes: preparing a first SC1 cleaning solution at a volume ratio of ammonium hydroxide, hydrogen peroxide, and deionized water of 1:(1~2):(10~50); placing the intermediate substrate after the first SPM sub-process in the first SC1 cleaning solution and treating it at a temperature of 35~75°C for 300~600 s to remove particles produced after the reaction of the first hydrofluoric acid and the first SPM cleaning solution.

[0023] In one embodiment of the present invention, the second cleaning process includes a second hydrofluoric acid sub-process, a second SPM sub-process, and a second SC1 sub-process. The second hydrofluoric acid sub-process includes: preparing a second hydrofluoric acid solution at a volume ratio of hydrofluoric acid to deionized water of 1:(50-100); immersing the intermediate substrate after the first cleaning process in the second hydrofluoric acid solution at 20-30°C for 300-600 seconds. In the second hydrofluoric acid sub-process, the main thickness of the PETEOS hard mask is continuously etched, further penetrating the depth of the trench, decomposing and peeling off the dense fluorocarbon polymer in the middle layer; through a second long-term immersion, local residual impurities on the trench sidewalls are eliminated, and the trench interface is simultaneously and evenly slightly trimmed to ensure a smooth interface.

[0024] Preferably, the second hydrofluoric acid sub-process includes: preparing a second hydrofluoric acid solution with a volume ratio of hydrofluoric acid to deionized water of 1:50; placing the intermediate substrate after the first cleaning process in the second hydrofluoric acid solution and immersing it at 23°C for 180 seconds.

[0025] In some examples, the second SPM sub-process includes: preparing a second SPM cleaning solution at a sulfuric acid to hydrogen peroxide volume ratio of (5~10):1; placing the intermediate substrate after the second hydrofluoric acid sub-process in the second SPM cleaning solution and treating it at a temperature of 120~130°C for 300~600 s to remove residual carbon from the polymer. The second SC1 sub-process includes: preparing a second SC1 cleaning solution at a volume ratio of ammonium hydroxide, hydrogen peroxide, and deionized water of 1:(1~2):(10~50); placing the intermediate substrate after the second SPM sub-process in the second SC1 cleaning solution and treating it at a temperature of 35~75°C for 300~600 s to remove particles produced after the reaction of the second hydrofluoric acid and the second SPM cleaning solution.

[0026] In one embodiment of the present invention, the third cleaning process includes a third hydrofluoric acid sub-process, a third SPM sub-process, and a third SC1 sub-process. The third hydrofluoric acid sub-process includes: preparing the third hydrofluoric acid according to a volume ratio of hydrofluoric acid to deionized water of 1:(100-200); placing the intermediate substrate after the second cleaning process in the third hydrofluoric acid and immersing it at 20-30°C for 180-360 seconds. In the third hydrofluoric acid sub-process, the remaining PETEOS hard mask is removed; stubborn dense fluorocarbon polymers at the corners and bottom of the trenches are removed, achieving thorough cleaning of the trenches; a trace amount of HF solution passivates interface defects on the silicon surface, and the low corrosion characteristics throughout the process provide good control over the additional etching of the field oxide layer, maximizing the preservation of the original thickness and uniformity of the field oxide.

[0027] Preferably, the third hydrofluoric acid sub-step includes: preparing the third hydrofluoric acid according to a volume ratio of hydrofluoric acid to deionized water of 1:100; placing the intermediate substrate after the second cleaning step in the third hydrofluoric acid and immersing it at 23°C for 180 seconds.

[0028] In some examples, the third SPM sub-process includes: preparing a third SPM cleaning solution at a sulfuric acid to hydrogen peroxide volume ratio of (5~10):1; placing the intermediate substrate after the third hydrofluoric acid sub-process in the third SPM cleaning solution and treating it at 120~130°C for 300~600s to remove residual carbon from the polymer. The third SC1 sub-process includes: preparing a third SC1 cleaning solution at a volume ratio of ammonium hydroxide, hydrogen peroxide, and deionized water of 1:(1~2):(10~50); placing the intermediate substrate after the third SPM sub-process in the third SC1 cleaning solution and treating it at 35~75°C for 300~600s to remove particles produced after the reaction of the third hydrofluoric acid and the third SPM cleaning solution.

[0029] For example, the sulfuric acid used above has a concentration of not less than 98 wt%, the hydrogen peroxide has a concentration of 28 wt% to 30 wt%, and the ammonium hydroxide has a concentration of 29 wt% to 30 wt%.

[0030] S3. An insulated gate bipolar transistor device is fabricated using the intermediate substrate cleaned in step S2.

[0031] The preparation method provided by the present invention will be further illustrated below with reference to specific embodiments.

[0032] Example 1 1. Substrate preparation: 8-inch N-type zone melting high-resistivity silicon was selected, a 2500Å PETEOS hard mask was deposited, and a silicon trench with a dry etching depth of 6μm was obtained to obtain the etched intermediate substrate.

[0033] 2. The intermediate substrate after etching is cleaned, including three cleaning processes, as follows.

[0034] First cleaning step: (1) Prepare a low-concentration first hydrofluoric acid system according to the volume ratio of HF (hydrofluoric acid):DIW (deionized water) = 1:100, soak at 23°C for 120s, and then soak in the polymer (polymer, for example, SiF) in the trench. x SiCl y The reaction was fully completed, and the 500 Å thick TEOS was removed.

[0035] (2) High temperature first SPM cleaning solution (H2SO4:H2O2 = 5:1 by volume, temperature 125℃, time 600s) to clean and remove residual carbon in polymer.

[0036] (3) High temperature first SC1 cleaning solution (NH4OH:H2O2:H2O (DIW) = 1:2:50 by volume, temperature 50℃, time 300s) to remove byproducts produced after the reaction of first hydrofluoric acid and first SPM cleaning solution.

[0037] Second cleaning process: (1) Prepare a low-concentration second hydrofluoric acid system according to the volume ratio HF:DIW=1:50, soak at 23°C for 180s, and mix with the polymer (SiF) in the trench. x SiCl y The reaction was fully completed, and the 1500 Å thick TEOS was removed.

[0038] (2) High temperature second SPM cleaning solution (H2SO4:H2O2=5:1, temperature 125℃, time 600s) to clean and remove residual carbon in polymer.

[0039] (3) High temperature second SC1 cleaning solution (NH4OH:H2O2:H2O (DIW) = 1:2:50, temperature 50℃, time 300s) to remove byproducts produced after the reaction of second hydrofluoric acid and second SPM cleaning solution.

[0040] Third cleaning process: (1) Prepare a low-concentration hydrofluoric acid system according to the volume ratio HF:DIW=1:100, soak at 23°C for 180s, and mix with the polymer (SiF) in the trench. x SiCl y The reaction was fully completed, and a 700 Å thick TEOS layer was removed.

[0041] (2) High temperature third SPM cleaning solution (H2SO4:H2O2=5:1, temperature 125℃, time 600s) to clean and remove residual carbon in polymer.

[0042] (3) High temperature third SC1 cleaning solution (NH4OH:H2O2:H2O(DIW)) = 1:2:50, temperature 50℃, time 300s) to remove the byproducts produced after the reaction of third hydrofluoric acid and third SPM cleaning solution.

[0043] 3. Subsequently, gate oxide, polysilicon, and ion implantation processes are routinely performed on the cleaned intermediate substrate to obtain an insulated gate bipolar transistor (IGBT) device.

[0044] The performance of the IGBT device prepared in Example 1 was tested, and the results are shown in Table 1.

[0045] Comparative Example 1 The difference between Comparative Example 1 and Example 1 lies in the cleaning process of the etched intermediate substrate in step 2. The cleaning process in Comparative Example 1 is as follows: First cleaning step: Use low-concentration hydrofluoric acid DHF (volume ratio HF:H2O=1:100), cleaning conditions: 60s at 23℃. SPM cleaning solution (volume ratio H2SO4:H2O2 = 5:1), cleaning conditions: treatment at 125℃ for 600s). SC1 cleaning solution (volume ratio of NH4OH:H2O2:H2O=1:2:50), cleaning conditions: treatment at 50℃ for 300s.

[0046] Second cleaning step: BOE cleaning solution (volume ratio HF:NH4F=1:7) is used, and the cleaning conditions are: treatment at 23℃ for 60s; SC1 cleaning solution (volume ratio of NH4OH:H2O2:H2O=1:2:50), cleaning conditions: treatment at 50℃ for 300s.

[0047] The third cleaning step: using low-concentration hydrofluoric acid DHF (volume ratio HF:H2O=1:1000), cleaning conditions: treatment at 23℃ for 60s). SPM cleaning solution (volume ratio H2SO4:H2O2 = 5:1), cleaning conditions: treatment at 125℃ for 600s). SC1 cleaning solution (volume ratio of NH4OH:H2O2:H2O=1:2:50), cleaning conditions: treatment at 50℃ for 300s.

[0048] The remaining steps are the same as in Example 1. The performance of the IGBT device prepared in Comparative Example 1 was tested, and the results are shown in Table 1.

[0049] Table 1. Performance test results of the IGBT devices prepared in Example 1 and Comparative Example 1

[0050] As shown in Table 1, Example 1 and Comparative Example 1 show significant differences in key performance parameters of IGBT devices, fully demonstrating the technical effects of the three-step cleaning process described in this invention in improving device consistency, reducing leakage current, and increasing yield.

[0051] Regarding threshold voltage (Vth) stability, the average Vth drift value of Example 1 was 0.056V, lower than that of Comparative Example 1 (0.064V). This result indicates that the multiple low-concentration HF+SPM+SC1 combined cleaning process used in Example 1 can more effectively remove polymer residues (such as SiF2) from the trench sidewalls and bottom. x , SiCl y This reduces interface state density fluctuations, thereby suppressing Vth drift and improving the reliability of the device during long-term operation. Furthermore, the batch 3σ dispersion of Vth in Example 1 is 0.010V, which is better than the 0.011V in Comparative Example 1, indicating that the cleaning process of this invention significantly enhances the consistency of device parameters, which is beneficial for yield control in large-scale production.

[0052] Regarding the additional etching thickness of the field oxygen, Example 1 achieved only 207 Å, significantly lower than the 513 Å of Comparative Example 1. This parameter reflects the degree of unintended damage to the field oxygen during the cleaning process. Example 1, through stepwise, low-concentration, targeted HF etching combined with high-temperature oxidation cleaning (SPM / SC1), achieved efficient removal of the polymer within the trenches while maximizing the protection of the field oxygen structure integrity. This avoided the risk of electric field distortion or breakdown due to over-etching, thereby improving the device's breakdown voltage performance and long-term reliability.

[0053] Regarding the average gate leakage current, Example 1 shows 48nA, which is more than 58% lower than the 115nA in Comparative Example 1. This significant optimization indicates that the cleaning process of the present invention effectively reduces the gate oxide layer defect density and interface states, reduces the gate leakage channel, and improves the switching efficiency and static power consumption control capability of the IGBT, which is particularly important for high-frequency and high-power applications.

[0054] Regarding the yield of finished chips, Example 1 achieved 96.4%, which is higher than the 95.2% of Comparative Example 1. This yield improvement is a comprehensive reflection of multi-dimensional performance optimization, including improved Vth consistency, reduced field oxygen damage, and reduced gate leakage current. These all help to reduce the number of defective products caused by parameter deviations or structural defects, thereby improving the overall manufacturing yield and reducing production costs.

[0055] Table 1 shows that the three-step cleaning process described in this invention, by controlling the HF concentration, cleaning sequence, and accompanying SPM / SC1 treatment, achieves systematic optimization of key performance parameters of IGBT devices, especially showing significant advantages in Vth stability, field oxygen protection, leakage current suppression, and yield improvement. These performance improvements are not due to a single factor, but rather the synergistic effect of the cleaning process on interface quality, material damage control, and process repeatability, meeting the requirements of precision manufacturing of semiconductor devices. The method provided by this invention has simple logical steps, requires no equipment modification, consumes low-concentration solutions, exhibits high batch process stability, reduces rework and defect losses, and is suitable for large-scale industrial application.

[0056] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0057] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A method for fabricating an insulated gate bipolar transistor device, characterized in that, Includes the following steps: S1. A mask is deposited on the intermediate substrate. After photolithography patterning, trenches are formed by fluorine-based plasma dry etching to obtain the etched intermediate substrate. S2. The etched intermediate substrate is cleaned sequentially using the first cleaning process, the second cleaning process and the third cleaning process to remove the residual fluorocarbon polymer in the mask and the trench. Each cleaning process includes a hydrofluoric acid sub-process, an SPM sub-process, and an SC1 sub-process; the hydrofluoric acid sub-process is as follows: a hydrofluoric acid solution is prepared according to a volume ratio of hydrofluoric acid to deionized water of 1:(50-200); the etched intermediate substrate is placed in the hydrofluoric acid solution and immersed at 20-30°C for 180-600 seconds; S3. An insulated gate bipolar transistor device is fabricated using the intermediate substrate cleaned in step S2.

2. The method for fabricating an insulated gate bipolar transistor device according to claim 1, characterized in that, The first cleaning process includes a first hydrofluoric acid sub-process, a first SPM sub-process, and a first SC1 sub-process; the first hydrofluoric acid sub-process includes: preparing a first hydrofluoric acid solution with a hydrofluoric acid to deionized water volume ratio of 1:(100-200); placing the etched intermediate substrate in the first hydrofluoric acid solution and immersing it at 20-30°C for 180-240 seconds; The second cleaning process includes a second hydrofluoric acid sub-process, a second SPM sub-process, and a second SC1 sub-process; the second hydrofluoric acid sub-process includes: preparing a second hydrofluoric acid solution with a volume ratio of hydrofluoric acid to deionized water of 1:(50-100); placing the intermediate substrate after the first cleaning process in the second hydrofluoric acid solution and immersing it at 20-30°C for 300-600 seconds; The third cleaning process includes a third hydrofluoric acid sub-process, a third SPM sub-process, and a third SC1 sub-process; the third hydrofluoric acid sub-process includes: preparing the third hydrofluoric acid according to a hydrofluoric acid to water volume ratio of 1:(100-200); placing the intermediate substrate after the second cleaning process in the third hydrofluoric acid and immersing it at 20-30°C for 180-360 seconds.

3. The method for fabricating an insulated gate bipolar transistor device according to claim 2, characterized in that, The first hydrofluoric acid sub-process includes: preparing a first hydrofluoric acid solution with a volume ratio of hydrofluoric acid to deionized water of 1:100; placing the etched intermediate substrate in the first hydrofluoric acid solution and immersing it at 23°C for 120 seconds; The second hydrofluoric acid sub-process includes: preparing a second hydrofluoric acid solution with a volume ratio of hydrofluoric acid to deionized water of 1:50; placing the intermediate substrate after the first cleaning process in the second hydrofluoric acid solution and immersing it at 23°C for 180 seconds; The third hydrofluoric acid sub-process includes: preparing the third hydrofluoric acid according to a volume ratio of hydrofluoric acid to deionized water of 1:100; placing the intermediate substrate after the second cleaning process in the third hydrofluoric acid and immersing it at 23°C for 180 seconds.

4. The method for fabricating an insulated gate bipolar transistor device according to claim 1, characterized in that, In step S1, the mask deposition on the intermediate substrate is performed by using a plasma-enhanced tetraethyl orthosilicate process to deposit a mask on the surface of the intermediate substrate.

5. The method for fabricating an insulated gate bipolar transistor device according to claim 2, characterized in that, The first SPM sub-process includes: preparing a first SPM cleaning solution according to a sulfuric acid to hydrogen peroxide volume ratio of (5~10):1; placing the intermediate substrate after the first hydrofluoric acid sub-process in the first SPM cleaning solution and treating it at a temperature of 120~130℃ for 300~600s; The first SC1 sub-process includes: preparing a first SC1 cleaning solution according to the volume ratio of ammonium hydroxide, hydrogen peroxide and deionized water of 1:(1~2):(10~50); placing the intermediate substrate after the first SPM sub-process in the first SC1 cleaning solution and treating it at a temperature of 35~75°C for 300~600s.

6. The method for fabricating an insulated gate bipolar transistor device according to claim 5, characterized in that, The second SPM sub-process includes: preparing a second SPM cleaning solution according to the volume ratio of sulfuric acid to hydrogen peroxide of (5~10):1; placing the intermediate substrate after the second hydrofluoric acid sub-process in the second SPM cleaning solution and treating it at a temperature of 120~130℃ for 300~600s; The second SC1 sub-process includes: preparing a second SC1 cleaning solution according to the volume ratio of ammonium hydroxide, hydrogen peroxide and deionized water of 1:(1~2):(10~50); placing the intermediate substrate after the second SPM sub-process in the second SC1 cleaning solution and treating it at a temperature of 35~75°C for 300~600s.

7. The method for fabricating an insulated gate bipolar transistor device according to claim 6, characterized in that, The third SPM sub-process includes: preparing a third SPM cleaning solution according to a sulfuric acid to hydrogen peroxide volume ratio of (5~10):1; placing the intermediate substrate after the third hydrofluoric acid sub-process in the third SPM cleaning solution and treating it at a temperature of 120~130℃ for 300~600s; The third SC1 sub-process includes: preparing a third SC1 cleaning solution according to the volume ratio of ammonium hydroxide, hydrogen peroxide and deionized water of 1:(1~2):(10~50); placing the intermediate substrate after the third SPM sub-process in the third SC1 cleaning solution and treating it at a temperature of 35~75°C for 300~600s.

8. The method for fabricating an insulated gate bipolar transistor device according to any one of claims 5-7, characterized in that, The concentration of the sulfuric acid is not less than 98 wt%, the concentration of the hydrogen peroxide is 28 wt% to 30 wt%, and the concentration of the ammonium hydroxide is 29 wt% to 30 wt%.

9. An insulated-gate bipolar transistor device, characterized in that, It is obtained by the preparation method described in any one of claims 1-8.

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