Semiconductor device and electric appliance

Abstract

The application provides a semiconductor device and an electrical equipment, and relates to the technical field of semiconductors. The semiconductor device comprises a substrate layer, a junction field effect layer, the junction field effect layer is arranged on one side of the substrate layer, the junction field effect layer is provided with a plurality of body sections and a plurality of target doped sections, the body sections are arranged at intervals along a first direction, the target doped sections are arranged at intervals along a second direction, the target doped sections are connected with the body sections, the body sections and the target doped sections have the same doping type, the first direction and the second direction are surface extension directions of the substrate layer, and the first direction and the second direction intersect. The target doped sections in the semiconductor device are equivalent to extensions of the body sections, the depletion zones between the body sections can be made to be closer to each other without increasing the area of a source region, the width of a conduction channel in the junction field effect layer is weakened, and the short-circuit resistance of the semiconductor device is ensured.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and electrical equipment. Background Technology

[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are power semiconductors widely used in various power devices and systems. Short-circuit withstand capability is a key focus for MOSFET performance optimization.

[0003] According to relevant technology centers, injecting different concentrations of the same type of impurity particles into the source region of a MOSFET can create a ballast resistor in the source region, thereby improving the short-circuit withstand capability of the MOSFET.

[0004] However, forming a ballast resistor with sufficient short-circuit withstand capability requires a source region of sufficient size, which increases the area of ​​the MOSFET and affects the fabrication efficiency of the MOSFET. Summary of the Invention

[0006] This application provides a semiconductor device and electrical equipment, which aims to improve the short-circuit withstand capability of the semiconductor device without increasing the source area.

[0007] In a first aspect, embodiments of this application provide a semiconductor device, comprising: basal layer; A junction field-effect layer; the junction field-effect layer is disposed on one side of the substrate layer; The junction field-effect layer is provided with multiple body portions and multiple target doped portions; the body portions are spaced apart along a first direction, and the target doped portions are spaced apart along a second direction; the target doped portions are connected to the body portions; The bulk portion and the target doped portion have the same doping type; the first direction and the second direction are the surface extension directions of the substrate layer, and the first direction and the second direction intersect.

[0008] Optionally, the semiconductor device further includes a source metal layer; the junction field-effect layer is further provided with multiple source portions and multiple body contact portions; At least a portion of the source portion is enclosed within the body portion; The body contact portions are spaced apart along the second direction, and at least a portion of the body contact portions are enclosed in the source portions; the body contact portions and the body portions have the same doping type; Along the thickness direction of the substrate layer, the source metal layer is disposed on the side of the source portion and the body contact portion facing away from the substrate layer; the source metal layer and the body contact portion form an ohmic contact.

[0009] Optionally, along the second direction, the target doped portion is aligned with the body contact portion, and / or, along the second direction, the target doped portion and the body contact portion are alternately spaced.

[0010] Optionally, the target doped portions located on opposite sides of the same body portion are offset along the second direction so that the body contact portion is aligned with the target doped portion located on one side of the body portion and alternately spaced with the target doped portion located on the other side of the body portion.

[0011] Optionally, along the second direction, the body contact portions of two adjacent body portions are aligned, or, along the second direction, the body contact portions of two adjacent body portions are staggered.

[0012] Optionally, in the target doped portions located on the same side of the body portion, at least two of the target doped portions are aligned with the same body contact portion.

[0013] Optionally, the target doping portion includes a first sub-portion and / or a second sub-portion; Along the first direction, the size of the first sub-part is larger than the size of the second sub-part; The first sub-part is connected to two adjacent body parts on both sides along the first direction; The second sub-part is connected to one of the body parts along one side of the first direction.

[0014] Optionally, for two adjacent body portions, along the second direction, the second sub-portion is spaced apart on the side of one body portion away from the other body portion; Alternatively, along the second direction, the first sub-parts are spaced apart on one side of one of the body parts that is away from the other body part; Alternatively, along the second direction, the first sub-part and the second sub-part are alternately spaced on one side of the body part away from the other body part.

[0015] Optionally, along the second direction, the second sub-sections are alternately spaced between two adjacent body sections.

[0016] Optionally, along the second direction, the first sub-parts are spaced apart between two adjacent body parts, and at least a portion of the first sub-parts are located within the interval between two adjacent second sub-parts.

[0017] Optionally, the upper limit of the doping concentration of the target doped portion is greater than the upper limit of the doping concentration of the bulk portion.

[0018] Optionally, the semiconductor device further includes a gate oxide layer and a polysilicon layer, wherein the gate oxide layer is disposed on the side of the junction field-effect layer opposite to the substrate layer; and the polysilicon layer is disposed on the side of the gate oxide layer opposite to the junction field-effect layer. Along the first direction, the gate oxide layer and the polysilicon layer begin and terminate at two adjacent bulk portions; Along the thickness direction of the substrate layer, the projection of the target doped portion lies within the gate oxide layer.

[0019] Optionally, the base layer includes: Substrate layer; A drift layer; along the thickness direction of the substrate layer, the drift layer is located between the substrate layer and the junction field-effect layer; The semiconductor device further includes: Drain metal layer; along the thickness direction of the substrate layer, the drain metal layer is disposed on the side of the substrate layer opposite to the drift layer; A source metal layer is disposed on the side of the polysilicon layer opposite to the junction field-effect layer along the thickness direction of the substrate layer; a source hole is formed adjacent to the polysilicon layer along the first direction, and the source metal layer also fills the source hole; Passivation layer; the passivation layer is disposed between the source metal layer and the polysilicon layer.

[0020] Optionally, the first direction is perpendicular to the second direction.

[0021] Secondly, embodiments of this application provide an electrical device including a semiconductor device as described in any of the first aspects.

[0022] Beneficial effects In this embodiment, by setting a target doped portion connected to the bulk portion within the junction field-effect layer (JFET), and having the same doping type as the bulk portion, the area of ​​the bulk portion is effectively increased while the area of ​​the JFET is reduced. A depletion region can be formed between the target doped portion and the JFET. Under short-circuit conditions, a high voltage exists between the source and drain, causing this depletion region to expand. Due to the reduced area of ​​the JFET, the depletion regions formed by adjacent bulk portions and the JFET are more likely to converge, potentially even clamping the JFET, thus limiting the path of short-circuit current, increasing the short-circuit withstand time of the semiconductor device, and improving its short-circuit withstand capability. The target doped portion is independent of the bulk portion and isolated from the source region formed within the bulk portion, without increasing the source region area. Therefore, it has minimal impact on the area of ​​the semiconductor device, ensuring efficient semiconductor device manufacturing. Attached Figure Description

[0023] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a top view schematic diagram of the first type of semiconductor device provided in the embodiments of this application; Figure 2 This is an embodiment of the present application. Figure 1 A schematic diagram of the cross-sectional structure of the provided semiconductor device along AA; Figure 3 This is an embodiment of the present application. Figure 1 A schematic diagram of the cross-sectional structure of the provided semiconductor device along BB; Figure 4 This is an embodiment of the present application. Figure 1 A schematic diagram of the cross-sectional structure of the provided semiconductor device along CC; Figure 5 This is an embodiment of the present application. Figure 1 A schematic diagram of the cross-sectional structure of the provided semiconductor device along DD; Figure 6 This is a schematic diagram of the electronic circuit path in the semiconductor device provided in the embodiments of this application; Figure 7 This is a second top view schematic diagram of the semiconductor device provided in the embodiments of this application; Figure 8 This is a third top view schematic diagram of the semiconductor device provided in the embodiments of this application; Figure 9 This is a fourth top view schematic diagram of the semiconductor device provided in the embodiments of this application; Figure 10 This is a fifth top view schematic diagram of the semiconductor device provided in the embodiments of this application; Figure 11 This is a sixth top view schematic diagram of the semiconductor device provided in the embodiments of this application; Figure 12 This is a seventh top view schematic diagram of the semiconductor device provided in the embodiments of this application; Figure 13 This is a top view schematic diagram of the eighth type of semiconductor device provided in the embodiments of this application; Figure 14 This is a top view schematic diagram of the ninth type of semiconductor device provided in the embodiments of this application; Figure 15 This is a top view schematic diagram of the tenth type of semiconductor device provided in the embodiments of this application.

[0024] Figure label: 1. Substrate layer; 2. Junction field-effect layer; 3. Polysilicon layer; 4. Source metal layer; 5. Source via; 6. Drain metal layer; 7. Passivation layer; 11. Substrate layer; 12. Drift layer; 21. Bulk portion; 22. Target doped portion; 23. Source portion; 24. Bulk contact portion; 221. First sub-portion; 222. Second sub-portion; X, first direction; Y, second direction; Z, thickness direction; W, carrier movement direction. Detailed Implementation

[0026] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0027] In the embodiments of this application, the terms "first", "second", "third", "fourth" are used to distinguish the same or similar items with essentially the same function and effect, only for the purpose of clearly describing the technical solution of the embodiments of this application, and should not be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated.

[0028] In the embodiments of this application, the terms "upper" and "lower" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0029] In the description of this specification, the terms "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0030] In the embodiments of this application, "multiple" means two or more, and "at least one" means one or more, unless otherwise explicitly specified.

[0031] The features such as "parallel," "perpendicular," and "identical" used in the embodiments of this application include features in the strict sense of "parallel," "perpendicular," and "identical," as well as cases where "approximately parallel," "approximately perpendicular," and "approximately identical" include certain tolerances. Taking into account the measurement and the tolerances associated with the measurement of a specific quantity (e.g., limitations of the measurement system), they represent the acceptable deviation range for a specific value as determined by a person skilled in the art. For example, "approximately" can mean within one or more standard deviations, or within 10% or 5% of the value.

[0032] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open and encompassing, that is, "including, but not limited to".

[0033] Silicon carbide-metal-oxide-semiconductor field-effect transistors (SiC MOSFETs) are power devices based on SiC semiconductor materials. Compared to traditional silicon-based MOSFETs, they offer advantages such as high temperature resistance (junction temperature up to 200-250℃), high voltage resistance (breakdown voltage up to several kilovolts), low conduction loss, and superior high-frequency switching characteristics (switching speed 2-5 times that of silicon devices). They are widely used in high-voltage, high-power applications such as new energy vehicles (e.g., vehicle inverters, DC-DC converters), photovoltaic inverters, energy storage systems, and industrial frequency converters. Short-circuit withstand capability is a key area of ​​interest for manufacturers in the optimized design of SiC MOSFETs.

[0034] In related technologies, preparing N- (lightly doped N-) within the N+ (heavily doped N-type) source region of a SiC MOSFET can form a ballast resistor. This enhances the depletion between the P-well and N- during short-circuit withstand, thereby increasing the short-circuit capability of the SiC MOSFET. However, forming a ballast resistor with sufficient short-circuit withstand capability requires a sufficiently large N-type doped region, which increases the area of ​​a single cell, thus affecting the fabrication efficiency of the SiC MOSFET.

[0035] Based on this, embodiments of this application provide a semiconductor device and an electrical appliance.

[0036] Firstly, in conjunction with reference Figure 1 , Figure 2 , Figure 3 , Figure 4 and Figure 5 , Figure 1 This is a top view schematic diagram of a semiconductor device provided in an embodiment of this application. Figure 2 , Figure 3 , Figure 4 and Figure 5 They are respectively Figure 1 The schematic diagram shows the interface structure of a semiconductor device along AA, BB, CC, and DD. An embodiment of this application provides a semiconductor device including: a substrate layer 1; a junction field-effect layer 2; the junction field-effect layer 2 is disposed on one side of the substrate layer 1; the junction field-effect layer 2 has multiple body portions 21 and multiple target doped portions 22; the body portions 21 are spaced apart along a first direction X, and the target doped portions 22 are spaced apart along a second direction Y; the target doped portions 22 are connected to the body portions 21; the body portions 21 and the target doped portions 22 have the same doping type; the first direction X and the second direction Y are the surface extension directions of the substrate layer 1, and the first direction X and the second direction Y intersect.

[0037] The semiconductor device provided in this application embodiment can be a vertically structured SiC MOSFET. This semiconductor device includes a substrate layer 1 and a junction field-effect layer 2 disposed on one side of the substrate layer 1. The substrate layer 1 can be formed using silicon carbide material, such as 4H-SiC material, to meet the requirements of the semiconductor device for withstand voltage, thermal conductivity, and high-temperature operational reliability. Along the thickness direction Z of the substrate layer 1, the junction field-effect layer 2 (JFET region) is disposed on one side of the upper surface of the substrate layer 1. The junction field-effect layer 2 can be an N-type doped region, and depending on the doping type, it can include phosphorus doping (P-doping), nitrogen doping (N-doping), etc. The junction field-effect layer 2 can be formed by epitaxial growth, or its local doping state can be adjusted by ion implantation on the basis of the epitaxial layer. Taking phosphorus doping as an example, its doping concentration range can be 1e11 cm⁻¹. -2 ~5e14 cm-2 The junction field-effect layer 2 is mainly used to form current channels between adjacent bulk portions 21 and participate in current transport in the source-drain direction when the semiconductor device is turned on.

[0038] In this embodiment, the junction field-effect layer 2 is provided with multiple body portions 21 and multiple target doped portions 22. The body portions 21 can be Pwell regions (also known as P-wells, P-body, or bulk regions), and the body portions 21 are spaced apart along a first direction X. Figure 1 As shown, the first direction X can be defined as the X direction in the figure. Multiple bulk portions 21 are arranged sequentially along the first direction X, with a junction field-effect layer 2 of a certain width maintained between adjacent bulk portions 21. Each bulk portion 21 can be in the form of a strip, band, or long island structure, and can extend along the second direction YY. The formation of the bulk portions 21 can include P-type ion implantation, including aluminum doping (AL-doping), boron doping (B-doping), gallium doping (Ga-doping), etc. Taking boron doping as an example, boron ion implantation is used to form a P-type doped region, and high-temperature annealing is performed after implantation to activate the implanted impurities. The doping concentration range can be: 1e12 cm -2 ~1e15 cm -2 The body portion 21, together with the subsequently formed source portion 23, gate oxide layer, and polysilicon layer 3, defines the channel region.

[0039] Multiple target doped portions 22 are disposed in the junction field-effect layer 2 and spaced apart along the second direction Y. For example Figure 1 As shown, the second direction Y can be defined as the Y direction in the figure, and the target doped portion 22 is arranged periodically or non-periodically along the second direction Y. The first direction X and the second direction Y are both surface extension directions of the substrate layer 1, and the first direction X and the second direction Y intersect. In some embodiments, the first direction X and the second direction Y can be perpendicular; in other embodiments, the first direction X and the second direction Y can also be arranged at a non-perpendicular angle, as long as both are located in the surface extension plane of the substrate layer 1 and can enable the bulk portion 21 and the target doped portion 22 to form an intersecting or staggered fit.

[0040] The target doped portion 22 is connected to the bulk portion 21, and the target doped portion 22 and the bulk portion 21 have the same doping type. In this embodiment, the bulk portion 21 is P-type doped, and the target doped portion 22 is also P-type doped. The target doped portion 22 can be formed by the same P-type ion implantation process as the bulk portion 21, or it can be formed after the bulk portion 21 is formed by additional photolithography mask and ion implantation steps. Taking boron doping as an example, the doping concentration range of the target doped portion 22 can be 1e12 cm⁻¹. -2 ~1e16 cm-2 The implantation depth of the target doped portion 22 can be the same as or less than the implantation depth of the body portion 21, so that the target doped portion 22 mainly acts on the current channel region near the surface of the junction field-effect layer 2. The planar shape of the target doped portion 22 can be rectangular, strip-shaped, block-shaped, island-shaped, or other shapes suitable for layout, and at least one end or side of it is connected to the body portion 21, so that the target doped portion 22 becomes a doped (P-type) conditioning structure that extends from the body portion 21 into the interior or side of the junction field-effect layer 2.

[0041] For example, in a specific structure of a semiconductor device provided in the application embodiment, multiple body portions 21 are spaced apart along a first direction X, and each body portion 21 extends along a second direction Y; multiple target doped portions 22 are disposed between adjacent body portions 21 or on the sides of body portions 21, and are arranged spaced apart along the second direction Y. Each target doped portion 22 can extend from the sidewall of the corresponding body portion 21 toward the adjacent body portion 21. The target doped portion 22 can be separated from the adjacent body portion 21, or it can be connected to two adjacent body portions 21, thereby forming doping adjustment structures with different intensities. Through this arrangement, the target doped portions 22 can form multiple discrete doping (P-type) adjustment structures in the junction field-effect layer 2.

[0042] During the operation of a semiconductor device, when in a normal conduction state, the junction field-effect layer 2 between adjacent body portions 21 can serve as part of a current path. Current flows from the source side through the channel region (formed in the body portion 21), the junction field-effect layer 2, and the drift region to the drain side (formed on the side of the substrate layer 1 facing away from the junction field-effect layer 2). When a short circuit occurs, the current increases rapidly in the channel-on state, forming a current concentration in a local low-resistivity region. Since this embodiment introduces a target doped portion 22 with the same type of doping as the body portion 21 into the junction field-effect layer 2, the target doped portion 22 can work with the body portion 21 to change the morphology of the local depletion region, restricting the current path in the junction field-effect layer 2. This makes it difficult for the short-circuit current to concentrate along a single low-resistivity path, thereby reducing the local current density and local temperature rise, and improving short-circuit withstand capability.

[0043] Specifically, since this embodiment introduces a target doped portion 22 with the same type of doping as the bulk portion 21 into the junction field-effect layer 2, and the target doped portion 22 is connected to the bulk portion 21, the target doped portion 22 can serve as a doping adjustment structure extending from the bulk portion 21 to the side of the junction field-effect layer 2. Taking the junction field-effect layer 2 as N-type doped and both the bulk portion 21 and the target doped portion 22 as P-type doped as an example, a PN junction structure can be formed between the target doped portion 22 and the surrounding N-type junction field-effect layer 2. When the semiconductor device is in an off-state, on-state, or short-circuit state, this PN junction structure will form a certain depletion region around the target doped portion 22. Since the target doped portion 22 is connected to the bulk portion 21, the depletion region formed around the target doped portion 22 can connect with or approach the depletion region around the bulk portion 21, thereby changing the effective conductivity width of the junction field-effect layer 2 region between adjacent bulk portions 21 and weakening the carrier throughput.

[0044] Furthermore, the target doped portions 22 are spaced apart along the second direction Y, so that the depletion regulation effect is not concentrated in a single local location, but forms multiple distributed regulation points along the second direction Y. Therefore, when the semiconductor device is normally turned on, the junction field-effect layer 2 can still retain the necessary conductive channels to ensure current transmission between the source and drain; however, under short-circuit conditions, due to the increase in current and the expansion of the depletion region, the locations in the junction field-effect layer 2 that would normally easily form current channels are restricted by the target doped portions 22 and the surrounding depletion region, causing the current channels to be narrowed or separated, thus making it difficult for the short-circuit current to concentrate and flow through a single local area.

[0045] Compared to methods that form ballast resistors by injecting different concentrations of the same type of impurity particles into the source region, this embodiment does not simply rely on increasing the source region size to generate sufficient depletion. Instead, it sets a target doped portion 22 in the junction field-effect layer 2, and achieves planar adjustment of the current channel through the connection relationship between the body portion 21 and the target doped portion 22 and their cross arrangement in the first direction X and the second direction Y. Therefore, this embodiment can improve the short-circuit withstand capability of the SiC MOSFET without significantly increasing the area of ​​the source region (source portion 23). The target doped portion 22 can be formed by local windowing of the layout and ion implantation, and its fabrication process is compatible with that of the body portion 21, which helps to reduce additional process complexity and maintain the repeatability of device cell arrangement and manufacturing efficiency.

[0046] Compared to the solution that relies solely on expanding the source portion 23 to form the ballast resistor, this technical solution achieves current regulation by introducing the target doped portion 22 into the junction field-effect layer 2. This can improve short-circuit withstand capability at a smaller area cost, while also taking into account device cell density and fabrication efficiency.

[0047] Furthermore, compared to traditional SiC MOSFETs, this embodiment adds a target doped portion 22 to the junction field-effect layer 2, effectively increasing the area of ​​the bulk distribution. When surge current flows into the semiconductor device, the larger area of ​​the P-type doped region can reduce the voltage drop across the PN junction of the SiC MOSFET, thereby weakening the thermal power of the surge current and reducing the risk of local heat accumulation. In some embodiments, the target doped portion 22 connects two adjacent bulk portions 21 (Pwells), making the bulk portions 21 between cells more tightly connected. When surge current flows in, charge carriers (electrons and holes) can be transferred through the target doped portion 22, reducing the risk of local cell failure due to heat generation caused by charge carrier accumulation.

[0048] In this embodiment, by setting a target doped portion connected to the bulk portion within the junction field-effect layer (JFET), and having the same doping type as the bulk portion, the area of ​​the bulk portion is effectively increased while the area of ​​the JFET is reduced. A depletion region can be formed between the target doped portion and the JFET. Under short-circuit conditions, a high voltage exists between the source and drain, causing this depletion region to expand. Due to the reduced area of ​​the JFET, the depletion regions formed by adjacent bulk portions and the JFET are more likely to converge, potentially even clamping the JFET, thus limiting the path of short-circuit current, increasing the short-circuit withstand time of the semiconductor device, and improving its short-circuit withstand capability. The target doped portion is independent of the bulk portion and isolated from the source region formed within the bulk portion, without increasing the source region area. Therefore, it has minimal impact on the area of ​​the semiconductor device, ensuring efficient semiconductor device manufacturing.

[0049] Optionally, the semiconductor device further includes a source metal layer 4; the junction field-effect layer 2 is also provided with a plurality of source portions 23 and a plurality of body contact portions 24; at least a portion of the source portions 23 is enclosed in the body portions 21; the body contact portions 24 are spaced apart along the second direction Y, and at least a portion of the body contact portions 24 is enclosed in the source portions 23; the body contact portions 24 and the body portions 21 have the same doping type; along the thickness direction Z of the substrate layer 1, the source metal layer 4 is disposed on the side of the source portions 23 and the body contact portions 24 facing away from the substrate layer 1; the source metal layer 4 and the body contact portions 24 form an ohmic contact.

[0050] In some embodiments, a plurality of source regions 23 and a plurality of body contact regions 24 are also formed in the junction field-effect layer 2. The source regions 23 can be N-type source regions, formed by N-type ion implantation, and are at least partially located inside the body regions 21 and close to the upper surface of the junction field-effect layer 2. Taking phosphorus doping as an example, the doping concentration range of the source regions 23 can be: 1e11 cm -2~5e15 cm -2 .

[0051] The body contact portion 24 can be a heavily p-type doped region, spaced along the second direction Y within the source portion 23, at least partially surrounded by the source portion 23, and simultaneously communicating downwards with the body portion 21. The body contact portion 24 can be formed by implanting a high dose of p-type doped ions to reduce the body contact resistance. Taking boron doping as an example, the doping concentration range of the body contact portion 24 can be 1e13 cm⁻¹. -2 ~1e16cm -2 The source metal layer 4 is disposed on the side of the source portion 23 and the body contact portion 24 facing away from the substrate layer 1. It can be nickel (Ni), titanium (Ti), aluminum (Al) or a composite metal layer thereof. The source metal layer 4 forms an ohmic contact with the body contact portion 24. The source metal layer 4 can also cover part of the source portion 23 at the same time, so that both the source portion 23 and the body contact portion 24 can be effectively led out by the source metal layer 4, thereby forming a stable source.

[0052] The target doped portion 22 is not directly connected to the body contact portion 24 and does not occupy the area of ​​the source portion 23. On the one hand, it can prevent the source portion 23 from being disconnected, thus not changing the flow path of electrons in the source portion 23 and preventing the original channel from being occupied by the target doped portion 22, which would affect the conduction performance of the device. On the other hand, it can increase the saturation current of the semiconductor device during forward conduction and reduce the on-resistance.

[0053] Through the source metal layer 4, multiple source portions 23, and multiple body contact portions 24, the semiconductor device provided in this embodiment of the application forms a more complete source and body contact structure on the basis of the adjustment function of the target doping portion 22. At least a portion of the source portion 23 is wrapped in the body portion 21, which is beneficial to maintaining the current transport path when the SiC MOSFET is normally turned on. The body contact portions 24 are arranged at intervals along the second direction Y, and at least a portion of them are wrapped in the source portions 23, which can make the body contact portions 24 form distributed contact points inside the source portions 23, thereby improving the potential fixation effect of the body portion 21.

[0054] Since the body contact portion 24 and the body portion 21 have the same doping type, the body contact portion 24 can form a continuous electrical connection path with the body portion 21. The source metal layer 4 is disposed along the thickness direction Z of the substrate layer 1 on the side of the source portion 23 and the body contact portion 24 facing away from the substrate layer 1, and forms an ohmic contact with the body contact portion 24, which is beneficial for stabilizing and clamping the potential of the body portion 21 to the source potential. Thus, under short-circuit conditions, the body portion 21, the body contact portion 24, the source portion 23, and the target doped portion 22 can form a synergistic constraint, making the current distribution inside the semiconductor device more stable, improving the short-circuit impact resistance and operational reliability.

[0055] Optionally, refer to Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 12 , Figure 13 , Figure 14 and Figure 15 ,in, Figure 6 This is a schematic diagram of the electronic circuit path in a semiconductor device provided in an embodiment of this application. Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 12 , Figure 13 , Figure 14 and Figure 15 The following are top view structural schematic diagrams of different types of semiconductor devices provided in the embodiments of this application; along the second direction Y, the target doped portion 22 is aligned with the body contact portion 24, and / or, along the second direction Y, the target doped portion 22 and the body contact portion 24 are alternately spaced.

[0056] like Figure 6 As shown, when the semiconductor device is forward-biased, electrons move along the carrier movement direction W, that is, electrons move from the source portion 23 to the junction field-effect layer 2. The movement channel includes... Figure 6 The area indicated by the dashed box corresponds to the body contact portion 24 and is the main formation area of ​​the conductive channel. When setting the target doped portion 22, maximizing its occupation of this area can enhance the sealing effect on the conductive channel and significantly improve the short-circuit withstand capability of the semiconductor device. However, this also increases the on-resistance. Therefore, in order to balance short-circuit withstand capability and on-resistance under normal conduction conditions, the target doped portion 22 is aligned with the body contact portion 24 along the second direction Y, and / or, the target doped portion 22 and the body contact portion 24 are alternately spaced along the second direction Y.

[0057] In some embodiments, the target doped portion 22 is aligned with the body contact portion 24 along the second direction Y; for example, a target doped portion 22 is provided on the outside of each body contact portion 24, such that the center line of the target doped portion 22 is aligned with the center line of the body contact portion 24 in the second direction Y, thereby so that the target doped portion 22 is concentrated on the junction field effect layer 2 region near the body contact portion 24.

[0058] In some embodiments, the target doped portion 22 and the body contact portion 24 are alternately spaced along the second direction Y. For example, a first position, a second position, a third position, a fourth position, a fifth position, and a sixth position are sequentially provided along the second direction Y, with the body contact portion 24 located at the first, third, and fifth positions, and the target doped portion 22 located at the second, fourth, and sixth positions, thereby placing the target doped portion 22 in the region between adjacent body contact portions 24.

[0059] In some embodiments, along the second direction Y, a portion of the target doped portion 22 is aligned with the body contact portion 24, while another portion of the target doped portion 22 is alternately spaced with the body contact portion 24. For example, for a target doped portion 22 connected to the same body portion 21, along the first direction X, one side of the target doped portion 22 is aligned with the body contact portion 24, while the other side of the target doped portion 22 is alternately spaced with the body contact portion 24.

[0060] In this embodiment, the target doped portion 22 and the body contact portion 24 can be aligned along the second direction Y. Since the body contact portion 24 can be used to lead out and fix the potential of the body portion 21 to the source metal layer 4, the vicinity of the body contact portion 24 is typically a location where the potential control effect of the body portion 21 is strong. When the target doped portion 22 and the body contact portion 24 are aligned, the potential fixing effect of the body contact portion 24 and the electric field modulation effect of the target doped portion 22 form a superimposed combination. Therefore, the junction field-effect layer 2 near the body contact portion 24 can obtain a stronger current confinement effect, which is beneficial for suppressing the current concentration from the local area during short circuits. It should be noted that when the target doped portion 22 and the body contact portion 24 are aligned, the dimension of the target doped portion 22 along the second direction Y is smaller than the dimension of the body contact portion 24 along the second direction Y.

[0061] Along the second direction Y, the target doped portion 22 can also be alternately spaced with the body contact portion 24. In this case, the target doped portion 22 can be arranged between adjacent body contact portions 24, avoiding the positions corresponding to the body contact portions 24. On the one hand, this minimizes the on-resistance under normal conduction conditions; on the other hand, under short-circuit conditions, the expanding depletion region can encroach on the positions corresponding to the body contact portions 24 along the second direction Y, thereby making the short-circuit current limiting effect along the second direction Y in the junction field-effect layer 2 more continuous. Thus, regardless of whether an aligned method or an alternating spacing method is used, the short-circuit withstand capability of the device can be improved by improving the current distribution in the junction field-effect layer 2.

[0062] Optionally, refer to Figure 14The target doped portions 22 located on opposite sides of the same body portion 21 are offset along the second direction Y so that the body contact portion 24 is aligned with the target doped portion 22 located on one side of the body portion 21 and is alternately spaced with the target doped portion 22 located on the other side of the body portion 21.

[0063] In some embodiments, target doped portions 22 are provided on both opposite sides of the same body portion 21. The target doped portions 22 located on one side of the body portion 21 are arranged sequentially in a first group of positions along the second direction Y, and the target doped portions 22 located on the other side of the body portion 21 are arranged sequentially in a second group of positions along the second direction Y. The first group of positions and the second group of positions are staggered. For example, the target doped portions 22 on the first side are aligned with the body contact portions 24 in the second direction Y, and the target doped portions 22 on the second side are located between two adjacent body contact portions 24. In this way, the body contact portions 24 are arranged correspondingly with one side of the target doped portions 22, while being arranged alternately with the other side of the target doped portions 22.

[0064] After offsetting the target doped portions 22 on both sides of the body portion 21, the body contact portion 24 is aligned with the target doped portion 22 located on one side of the body portion 21, while alternating with the target doped portion 22 located on the other side of the body portion 21. Thus, one side of the body portion 21 can achieve strong potential fixation and current limiting through alignment, while the other side can compensate for any misaligned positions of the body contact portion 24 through alternating spacing, improving the continuity of the short-circuit current limiting effect. The different distribution patterns on both sides make the electric field and current regulation on both sides of the same body portion 21 more balanced, helping to reduce the risk of unilateral current concentration and local thermal runaway under short-circuit conditions, and improving short-circuit withstand capability without significantly increasing the device area.

[0065] Optionally, refer to Figure 7 , Figure 8 , Figure 9 , Figure 14 , Figure 15 Along the second direction Y, the body contact portions 24 of two adjacent body portions 21 are aligned, or, referring to Figure 10 , Figure 11 , Figure 12 and Figure 13 Along the second direction Y, the body contact portions 24 of two adjacent body portions 21 are staggered.

[0066] In some embodiments, the body contact portions 24 in two adjacent body portions 21 are aligned along the second direction Y. Here, two adjacent body portions 21 can refer to two body portions 21 adjacent along the first direction X. For example, multiple body contact portions 24 are provided in each of two adjacent Pwells, and each body contact portion 24 has the same arrangement position in the second direction Y, thereby forming a regular matrix body contact structure. This method facilitates the formation of regular ohmic contact points between the source metal layer 4 and the body contact portions 24.

[0067] In other embodiments, the body contact portions 24 of two adjacent body portions 21 are staggered along the second direction Y. Here, two adjacent body portions 21 can refer to two body portions 21 adjacent along the first direction X. For example, the body contact portions 24 in one body portion 21 are located in a first group of positions in the second direction Y, and the body contact portions 24 in the other body portion 21 are located in a second group of positions, with the second group of positions situated between the first group of adjacent positions. This staggering method allows the body contact portions 24 to be distributed dispersed in the plane, reducing the concentration of multiple contact areas in the same lateral position. Both implementations can be selected according to the requirements of metal wiring and current balancing.

[0068] In this embodiment, the body contact portions 24 in two adjacent body portions 21 can be aligned along the second direction Y. When the body contact portions 24 in two adjacent body portions 21 are aligned, the body contact portions 24 in different body portions 21 can form a regular contact array, and the contact path between the source metal layer 4 and the body contact portions 24 is also more consistent. Since the potential fixed positions of each body portion 21 are basically corresponding, the potential response of adjacent cells in the on and short-circuit states is more consistent, which is beneficial to reducing the current unevenness caused by potential differences between adjacent body portions 21.

[0069] The body contact portions 24 in two adjacent body portions 21 can also be staggered along the second direction Y. When the body contact portions 24 are staggered, they form a dispersed distribution in the plane, which can prevent multiple body contact portions 24 from concentrating at the same position in the second direction Y, thereby making the coverage of the potential lead-out position of the body portion 21 more uniform. Thus, the alignment scheme is beneficial to improving contact consistency, and the staggered scheme is beneficial to improving the distribution uniformity of potential lead-out positions; both can be used in conjunction with the target doped portion 22 to make the current distribution in the junction field-effect layer 2 more balanced and improve the stability of the device under short-circuit impact.

[0070] Optionally, refer to Figure 9 In the target doped portion 22 located on the same side as the body portion 21, at least two target doped portions 22 are aligned with the same body contact portion 24.

[0071] In some embodiments, among a plurality of target doped portions 22 located on the same side of the body portion 21, at least two target doped portions 22 are aligned with the same body contact portion 24. For example, for a body contact portion 24, two target doped portions 22 are provided on the same side of the body contact portion 24 along the second direction Y, and both of them correspond to the body contact portion 24 in the second direction Y, that is, the projections of the two of them along the first direction X are both located within the body contact portion 24.

[0072] It is understandable that, among the target doped portions 22 located on the same side as the body portion 21, the number of target doped portions 22 aligned with the same body contact portion 24 can be three or even more. It should be noted that when at least two target doped portions 22 are aligned with the same body contact portion 24, the sum of the dimensions of these target doped portions 22 along the second direction Y is less than the dimension of the body contact portion 24 along the second direction Y.

[0073] This scheme can utilize a single contact portion 24 in conjunction with multiple target doping portions 22 to create a strong local doping (P-type) adjustment effect in the surrounding area.

[0074] In this embodiment, at least two target doped portions 22 located on the same side of the body portion 21 are aligned with the same body contact portion 24. This expands the range of the doping adjustment structure (target doped portions 22) near the body contact portion 24 without increasing the number of body contact portions 24, thereby improving layout utilization efficiency. Under short-circuit conditions, current tends to concentrate in low-resistance paths. The synergistic effect of multiple target doped portions 22 and the same body contact portion 24 can disperse and restrict the current path in this region, reducing local current density and heat concentration. Therefore, this embodiment can improve the short-circuit withstand capability of semiconductor devices while maintaining a relatively simple body contact structure.

[0075] Optionally, refer to Figure 1 , Figures 7-15 The target doped portion 22 includes a first sub-portion 221 and / or a second sub-portion 222; along the first direction X, the size of the first sub-portion 221 is larger than the size of the second sub-portion 222; at least a portion of the first sub-portion 221 is connected to two adjacent body portions 21 on both sides along the first direction X; the second sub-portion 222 is connected to a body portion 21 on one side along the first direction X.

[0076] In some embodiments, refer to Figure 7 , Figure 8 , Figure 9 and Figure 10The target doped portion 22 includes a first sub-portion 221. The first sub-portion 221 has a larger size along the first direction X. It is connected to two adjacent body portions 21 on both sides along the first direction X, so that the first sub-portion 221 spans the junction field effect layer 2 region between the adjacent body portions 21.

[0077] In other embodiments, reference is made to Figure 12 , Figure 13 , Figure 14 and Figure 15 The target doped portion 22 includes a second sub-portion 222, which has a smaller size along the first direction X. It is connected to a body portion 21 on only one side, and is spaced apart from the adjacent body portion 21 on the other side.

[0078] In yet other embodiments, reference is made to Figure 1 and Figure 11 The target doped portion 22 includes a first sub-portion 221 and a second sub-portion 222. The first sub-portion 221 is used to connect two adjacent body portions 21, and the second sub-portion 222 is used to be disposed in a local region on one side of the body portion 21. The first sub-portion 221 and the second sub-portion 222 can be formed by the same P-type ion implantation step, or they can be formed separately by different masks, so as to adjust their size, depth and doping concentration.

[0079] In this embodiment, the target doped portion 22 may include a first sub-portion 221. Since the first sub-portion 221 is connected to two adjacent body portions 21 on both sides along the first direction X, it forms a laterally connected doping adjustment structure between the two adjacent body portions 21. This structure enhances the depletion effect of the junction field-effect layer 2 region between adjacent body portions 21, making it less likely for short-circuit current to concentrate through the local region between the two body portions 21. The first sub-portion 221 connects the two adjacent body portions, making the body portions 21 between cells more tightly connected. When surge current is injected, charge carriers (electrons and holes) can be transferred through the target doped portion 22, reducing the risk of local cell failure due to heat generation caused by charge carrier aggregation.

[0080] The target doped portion 22 may also include a second sub-portion 222. Since the second sub-portion 222 is connected to a body portion 21 on one side along the first direction X, it is more suitable for local current limiting regulation of a single-sided region of the body portion 21, thereby improving the distribution of edge or local current channels.

[0081] Furthermore, the target doped portion 22 can also simultaneously include a first sub-portion 221 and a second sub-portion 222. In this case, the first sub-portion 221 undertakes the overall adjustment function between adjacent body portions 21, while the second sub-portion 222 undertakes the local compensation function, and the two complement each other in terms of their range of action and adjustment intensity. Thus, this scheme can flexibly configure the shape of the target doped portion 22 according to different cell positions, improving the device's current balancing capability and short-circuit withstand capability.

[0082] Optionally, refer to Figure 12 , Figure 13 , Figure 14 and Figure 15 For two adjacent body portions 21, along the second direction Y, a second sub-portion 222 is spaced apart on the side of one body portion 21 facing away from the other body portion 21; or, refer to Figure 7 , Figure 8 , Figure 9 , Figure 10 and Figure 11 Along the second direction Y, the first sub-parts 221 are spaced apart on one side of one body part 21 away from the other body part 21; or, refer to Figure 1 Along the second direction Y, the first sub-part 221 and the second sub-part 222 are alternately and spaced on one side of one body part 21 away from the other body part 21.

[0083] In some embodiments, for two adjacent body portions 21, along the second direction Y, a second sub-portion 222 is spaced apart on the side of one body portion 21 away from the other body portion 21. For example, the second sub-portion 222 is located in the outer edge region and is connected to one side of the corresponding body portion 21.

[0084] In other embodiments, along the second direction Y, a first sub-segment 221 is spaced apart on one side of one body segment 21 away from the other body segment 21, and the first sub-segment 221 may have a larger first direction X dimension for forming a wider doping (P-type) tuning structure on that side.

[0085] In some other embodiments, along the second direction Y, the first sub-section 221 and the second sub-section 222 are alternately spaced on the side of one body section 21 facing away from the other body section 21. For example, the first sub-section 221 is located in odd-numbered positions, and the second sub-section 222 is located in even-numbered positions. This alternation allows the first sub-section 221, which is wider along the first direction X, and the second sub-section 222, which is narrower along the first direction X, to complement each other, which is suitable for structures with uneven current distribution in the outer region or strong edge electric field.

[0086] In this embodiment, for two adjacent body portions 21, a second sub-portion 222 can be disposed at intervals along the second direction Y on the side of one body portion 21 away from the other body portion 21. Since the second sub-portion 222 is connected to the body portion 21 on only one side, it can serve as a local adjustment structure on the outside of the body portion 21 to segment and restrict the current path in the outer junction field-effect layer 2 region, thereby reducing current concentration in the outer region.

[0087] The first sub-section 221 can also be disposed at intervals along the second direction Y on one side of one body section 21 away from the other body section 21. Since the first sub-section 221 has a larger dimension along the first direction X, it can form a doped (P-type) conditioning structure with a larger coverage area on this side, thereby enhancing the overall electric field conditioning effect of the outer region.

[0088] The first sub-section 221 and the second sub-section 222 can also be alternately arranged along the second direction Y on the side of one body section 21 facing away from the other body section 21. In this case, the first sub-section 221 provides a wider range of adjustment, while the second sub-section 222 provides local compensation. The alternating arrangement of the two can create a strong and weak combined, continuously distributed current-limiting adjustment effect in the outer region along the second direction Y. Thus, different arrangement methods can be selected according to the electric field and current distribution requirements of the outer region, improving the short-circuit withstand capability of the board.

[0089] Optionally, refer to Figure 12 , Figure 13 , Figure 14 and Figure 15 Along the second direction Y, the second sub-section 222 is alternately arranged between two adjacent body sections 21.

[0090] In some embodiments, along the second direction Y, second sub-sections 222 are alternately spaced between two adjacent body sections 21. For example, two adjacent body sections 21 are respectively a first body section 21 and a second body section 21. A portion of the plurality of second sub-sections 222 are connected to the first body section 21, and another portion is connected to the second body section 21, and they are arranged alternately along the second direction Y. A certain interval can be maintained between the second sub-sections 222 connected to the first body section 21 and the second sub-sections 222 connected to the second body section 21 so that they do not overlap at the same position in the second direction Y. The second sub-sections 222 can adopt a strip-shaped, block-shaped, or island-shaped structure, and their size along the first direction X can be smaller than the spacing between adjacent body sections 21. During manufacturing, staggered P-type implantation windows can be opened between adjacent body sections 21 to form alternating second sub-sections 222 by ion implantation.

[0091] In this embodiment, the second sub-section 222 is alternately disposed between two adjacent body sections 21 along the second direction Y. Since the second sub-section 222 is connected to a body section 21 on one side along the first direction X, when multiple second sub-sections 222 are respectively connected to two adjacent body sections 21 and alternately arranged along the second direction Y, the doping (P-type) regulation structure between adjacent body sections 21 can present a left-right staggered distribution. This staggered distribution means that the current limiting regulation effect is not concentrated on one side of the same body section 21, but is alternately distributed between two adjacent body sections 21. Furthermore, the second sub-section 222 itself has a relatively flexible size, which can segment and constrain the local current channel without completely blocking the conductive path of the junction field-effect layer 2. Thus, when the semiconductor device is normally conducting, the junction field-effect layer 2 can still provide the necessary current channel; under short-circuit conditions, the alternately disposed second sub-sections 222, together with the expansion of the depletion region, can increase the dispersion of the current path, making it less likely for the current to flow continuously and concentratedly on one side. This alternating left-right local adjustment structure can improve the current balance between adjacent body sections 21, reduce the risk of local concentration, and thus enhance the short-circuit withstand capability of semiconductor devices.

[0092] Optionally, refer to Figure 1 and Figure 11 Along the second direction Y, the first sub-part 221 is spaced between two adjacent body parts 21, and at least part of the first sub-part 221 is located within the interval between two adjacent second sub-parts 222.

[0093] In some embodiments, along the second direction Y, a first sub-section 221 is spaced apart between two adjacent body sections 21, and a second sub-section 222 is also spaced between these two adjacent body sections 21. Multiple second sub-sections 222 can be connected to two adjacent body sections 21 respectively, forming an alternating arrangement along the second direction Y; at least a portion of the first sub-sections 221 are located within the interval between two adjacent second sub-sections 222. The first sub-sections 221 can connect to two adjacent body sections 21 on both sides along the first direction X, forming a bridging P-type adjustment region; the second sub-sections 222 can connect to one body section 21 on one side along the first direction X, forming a partial P-type adjustment region. For example, the second sub-section 222, first sub-section 221, second sub-section 222, and first sub-section 221 can be sequentially arranged along the second direction Y. The first sub-section 221 and the second sub-section 222 can have the same injection depth, or the first sub-section 221 can have a slightly deeper injection depth to enhance its flow-limiting effect.

[0094] In this embodiment, after the first sub-section 221 is disposed within the interval between two adjacent second sub-sections 222, the first sub-section 221 can supplement the doping (P-type) adjustment effect in the interval region. Furthermore, the first sub-section 221 is connected to two adjacent body sections 21 on both sides along the first direction X, thus it not only fills the adjustment gap between the second sub-sections 222, but also forms a lateral connection adjustment structure between adjacent body sections 21. Therefore, the first sub-section 221 provides overall connection and reinforcement adjustment, while the second sub-section 222 provides local compensation and dispersion adjustment; the two are spatially embedded and functionally complementary. This structure enables more continuous and sufficient current-limiting adjustment between adjacent body sections 21, thereby reducing the risk of current concentration in local areas under short-circuit conditions and improving device stability and short-circuit withstand capability.

[0095] Optionally, the upper limit of the doping concentration of the target doped portion 22 is greater than the upper limit of the doping concentration of the bulk portion 21.

[0096] In some embodiments, both the target doped portion 22 and the bulk portion 21 are p-type doped, and the upper limit of the doping concentration of the target doped portion 22 is greater than the upper limit of the doping concentration of the bulk portion 21. For example, the upper limit of the doping concentration of the bulk portion 21 is 1e15 cm⁻¹. -2 The doping concentration is less than the upper limit of 1e16 cm⁻¹ of the target doping portion 22. -2 It should be noted that this scheme does not limit the specific doping concentration relationship between the target doped portion 22 and the bulk distribution when fabricating semiconductor devices. For example, the doping concentration of the target doped portion 22 can be greater than the doping concentration of the bulk portion 21, or the doping concentration of the target doped portion 22 can be equal to the doping concentration of the bulk distribution, or the doping concentration of the target doped portion 22 can be less than the doping concentration of the bulk distribution.

[0097] The upper limit of the doping concentration of the target doped portion 22 is greater than the upper limit of the doping concentration of the bulk portion 21. For example, the bulk portion 21 uses a relatively low dose implantation upper limit to ensure channel formation, while the target doped portion 22 uses a relatively high dose implantation upper limit to enhance the current limiting effect.

[0098] In this technical solution, the upper limit of the doping concentration of the target doped portion 22 is greater than the upper limit of the doping concentration of the bulk portion 21. Since the target doped portion 22 and the bulk portion 21 have the same doping type, the target doped portion 22 does not change the basic conductivity type of the bulk portion 21, but forms a stronger local doping (P-type) modulation structure on the basis of the bulk portion 21. The target doped portion 22, with a higher upper limit of doping concentration in Pwell, can generate a more significant depletion and electric field modulation effect in the junction field-effect layer 2. Thus, under normal conduction conditions, the target doped portion 22 can exist as an additional modulation structure in the junction field-effect layer 2; under short-circuit conditions, when the current increases rapidly, the target doped portion 22 can more effectively limit the local current channel and suppress current concentration. Compared to simply increasing the length or area of ​​the source portion 23 to achieve ballast effect, this scheme improves short-circuit tolerance by enhancing the local adjustment capability of the target doped portion 22, which helps to reduce the dependence on the expansion of the source portion 23 area, thus balancing short-circuit reliability and device area utilization.

[0099] Optionally, refer to Figure 2 , Figure 3 , Figure 4 and Figure 5 The semiconductor device also includes a gate oxide layer (not shown in the figure) and a polysilicon layer 3. The gate oxide layer is disposed on the side of the junction field-effect layer 2 facing away from the substrate layer 1; the polysilicon layer 3 is disposed on the side of the gate oxide layer facing away from the junction field-effect layer 2; along the first direction X, the gate oxide layer and the polysilicon layer 3 start and end at two adjacent bulk portions 21; along the thickness direction Z of the substrate layer 1, the projection of the target doped portion 22 is located within the gate oxide layer.

[0100] The semiconductor device may further include a gate oxide layer and a polysilicon layer 3. The gate oxide layer is formed on the side of the junction field-effect layer 2 facing away from the substrate layer 1, and can be formed by thermal oxidation, silicon oxide deposition, or a combination of thermal oxidation and deposition. The polysilicon layer 3 is disposed on the side of the gate oxide layer facing away from the junction field-effect layer 2, and can be formed by chemical vapor deposition. Along the first direction X, the gate oxide layer and the polysilicon layer 3 begin and terminate at two adjacent bulk portions 21, that is, the gate oxide layer and the polysilicon layer 3 are located above the channel region between the two bulk portions 21. Viewed along the thickness direction Z of the substrate layer 1, the projection of the target doped portion 22 is located within the gate oxide layer, for example, the target doped portion 22 is disposed in the junction field-effect layer 2 below the coverage of the gate oxide layer. This embodiment allows the target doped portion 22 to be arranged corresponding to the gate region, facilitating the adjustment of the electric field distribution in the adjacent region of the channel.

[0101] In this embodiment, the gate oxide layer is disposed on the side of the junction field-effect layer 2 facing away from the substrate layer 1, and the polysilicon layer 3 is disposed on the side of the gate oxide layer facing away from the junction field-effect layer 2. Since the polysilicon layer 3 exerts a control effect on the area near the surface of the junction field-effect layer 2 through the gate oxide layer, the positions of the gate oxide layer and the polysilicon layer 3 directly affect the channel formation and conduction control.

[0102] Along the first direction X, the gate oxide layer and the polysilicon layer 3 begin and terminate at two adjacent bulk portions 21, so that the gate control structure corresponds to the channel region between the adjacent bulk portions 21, ensuring the normal control and conduction function of the semiconductor device. Further, along the thickness direction Z of the substrate layer 1, the projection of the target doped portion 22 lies within the gate oxide layer, indicating that the target doped portion 22 corresponds to the gate oxide layer coverage area on the plane. Thus, the target doped portion 22 can be arranged below or near the gate control region to modulate the electric field of the junction field-effect layer 2 region near the channel. Specifically, when the semiconductor device withstands voltage, the PN junction formed by the target doped portion 22 will shield part of the electric field emitted by the polysilicon layer 3, weakening the influence of the electric field on the gate oxide layer, thereby protecting the gate oxide layer.

[0103] Optionally, refer to Figure 2 , Figure 3 , Figure 4 and Figure 5 The substrate 1 includes: a substrate layer 11; a drift layer 12; the drift layer 12 is located between the substrate layer 11 and the junction field-effect layer 2 along the thickness direction Z of the substrate layer 1; the semiconductor device further includes: a drain metal layer 6; the drain metal layer 6 is disposed on the side of the substrate layer 11 away from the drift layer 12 along the thickness direction Z of the substrate layer 1; a source metal layer 4 is disposed on the side of the polysilicon layer 3 away from the junction field-effect layer 2 along the thickness direction Z of the substrate layer 1; a source hole 5 is formed between adjacent polysilicon layers 3 along the first direction X, and the source metal layer 4 is also filled in the source hole 5; and a passivation layer 7 is disposed between the source metal layer 4 and the polysilicon layer 3.

[0104] In some embodiments, the substrate 1 includes a substrate layer 11 and a drift layer 12. The substrate layer 11 is an N-type heavily doped silicon carbide substrate, and the drift layer 12 is an N-type lightly doped silicon carbide epitaxial layer. The drift layer 12 is located between the substrate layer 11 and the junction field-effect layer 2 along the thickness direction Z of the substrate layer 1. A drain metal layer 6 is disposed on the side of the substrate layer 11 facing away from the drift layer 12, and can be made of Ni-based or Ti-based metal and formed into an ohmic contact through annealing. A source metal layer 4 is disposed on the side of the polysilicon layer 3 facing away from the junction field-effect layer 2. A source hole 5 is formed between adjacent polysilicon layers 3, and the source metal layer 4 fills the source hole 5 and contacts the source portion 23 and the body contact portion 24 downwards. A passivation layer 7 is disposed between the source metal layer 4 and the polysilicon layer 3 to isolate the source metal layer 4 and the polysilicon layer 3. This embodiment forms a vertical conductive structure with the drain on the back side and the source on the front side.

[0105] In this embodiment, the substrate layer 1 includes a substrate layer 11 and a drift layer 12, with the drift layer 12 located between the substrate layer 11 and the junction field-effect layer 2. Since the substrate layer 11 supports the device and forms the drain-side connection base, and the drift layer 12 is used for longitudinal withstand voltage and current transport, this structure constitutes the main conductive path of the longitudinal SiC MOSFET. A drain metal layer 6 is disposed on the side of the substrate layer 11 facing away from the drift layer 12, allowing drain current to be drawn out from the back of the device. A source metal layer 4 is disposed on the side of the polysilicon layer 3 facing away from the junction field-effect layer 2 and fills the source via 5 formed by adjacent polysilicon layers 3, enabling the source metal layer 4 to contact the source portion 23 and the body contact portion 24 through the source via 5, thereby completing source-side current collection and potential fixation of the body portion 21. Furthermore, the passivation layer 7 is disposed between the source metal layer 4 and the polysilicon layer 3, which can isolate the source metal layer 4 and the gate, and prevent electrical connection between the source metal layer 4 and the polysilicon layer 3. Thus, the drain side, drift layer 12, junction field-effect layer 2, gate control structure, source side and target doping portion 22 form a complete synergy, enabling the semiconductor device to maintain vertical conduction capability.

[0106] Optionally, the first direction X is perpendicular to the second direction Y.

[0107] In some embodiments, the first direction X is perpendicular to the second direction Y. Specifically, a plurality of body portions 21 are spaced apart along the first direction X, and a plurality of target doped portions 22 are spaced apart along the second direction Y. The first direction X and the second direction Y are orthogonal, and the source portion 23, the body contact portion 24, and the target doped portions 22 can be designed for photolithography based on this orthogonal coordinate relationship. For example, the body portions 21 can be designed as strip-shaped Pwells extending along the second direction Y, and the plurality of body portions 21 are repeatedly arranged in the first direction X; the target doped portions 22 can be periodically distributed between adjacent or corresponding body portions 21 along the second direction Y. Since the first direction X is perpendicular to the second direction Y, the alignment, staggering, or alternating spacing relationship between the target doped portions 22 and the body contact portions 24 can be directly defined by the XY coordinates. This embodiment facilitates the formation of a regular cell array.

[0108] In this technical solution, the first direction X is perpendicular to the second direction Y. Since the body portion 21 is spaced apart along the first direction X, and the target doped portion 22 is spaced apart along the second direction Y, when the first direction X is perpendicular to the second direction Y, the body portion 21 and the target doped portion 22 can form a regular orthogonal pattern relationship within the surface of the substrate layer 1. This orthogonal relationship makes it easier to define the positional relationship of the body portion 21, the target doped portion 22, the source portion 23, and the body contact portion 24 using planar coordinates, and also facilitates the alignment, staggering, or alternating spacing of the target doped portion 22 and the body contact portion 24. Furthermore, the regular orthogonal arrangement helps improve cell repeatability, ensuring that the current channel length, potential fixation position, and target doped portion 22 adjustment position in different cells remain consistent. Therefore, during normal conduction, each cell can achieve a more balanced conduction state; under short-circuit conditions, the response of each cell to the short-circuit current is also more consistent, making it less likely that individual cells will prematurely bear excessive current and experience local failure. On the other hand, vertical arrangement also facilitates the design of photolithography and ion implantation windows, improves the position control accuracy and process consistency during the fabrication process, thereby enhancing the overall reliability of semiconductor devices.

[0109] Secondly, embodiments of this application provide an electrical device including a semiconductor device as described in any of the first aspects.

[0110] The electrical equipment can be a power electronic device used in fields such as artificial intelligence, high-performance computing, data centers, industrial transmission, electric vehicles, and smart grids, such as server power supplies, vehicle inverters, charging piles, and frequency converters.

[0111] This electrical device can achieve the same technical effect as the semiconductor device in the aforementioned embodiments, and will not be described again here to avoid repetition.

[0112] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: basal layer; A junction field-effect layer; the junction field-effect layer is disposed on one side of the substrate layer; The junction field-effect layer is provided with multiple body portions and multiple target doped portions; the body portions are spaced apart along a first direction, and the target doped portions are spaced apart along a second direction; the target doped portions are connected to the body portions; The bulk portion and the target doped portion have the same doping type; the first direction and the second direction are the surface extension directions of the substrate layer, and the first direction and the second direction intersect.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a source metal layer; the junction field-effect layer is further provided with multiple source portions and multiple body contact portions; At least a portion of the source portion is enclosed within the body portion; The body contact portions are spaced apart along the second direction, and at least a portion of the body contact portions are enclosed in the source portions; the body contact portions and the body portions have the same doping type; Along the thickness direction of the substrate layer, the source metal layer is disposed on the side of the source portion and the body contact portion facing away from the substrate layer; the source metal layer and the body contact portion form an ohmic contact.

3. The semiconductor device according to claim 2, characterized in that, Along the second direction, the target doped portion is aligned with the body contact portion, and / or, along the second direction, the target doped portion and the body contact portion are alternately spaced.

4. The semiconductor device according to claim 3, characterized in that, The target doped portions located on opposite sides of the same body portion are offset along the second direction so that the body contact portion is aligned with the target doped portion located on one side of the body portion and alternately spaced with the target doped portion located on the other side of the body portion.

5. The semiconductor device according to claim 3, characterized in that, Along the second direction, the body contact portions of two adjacent body portions are aligned, or along the second direction, the body contact portions of two adjacent body portions are staggered.

6. The semiconductor device according to claim 3, characterized in that, In the target doped portions located on the same side of the body portion, at least two of the target doped portions are aligned with the same body contact portion.

7. The semiconductor device according to claim 2, characterized in that, The target doped portion includes a first sub-portion and / or a second sub-portion; Along the first direction, the size of the first sub-part is larger than the size of the second sub-part; The first sub-part is connected to two adjacent body parts on both sides along the first direction; The second sub-part is connected to one of the body parts along one side of the first direction.

8. The semiconductor device according to claim 7, characterized in that, For two adjacent body portions, along the second direction, the second sub-parts are spaced apart on the side of one body portion that is away from the other body portion; Alternatively, along the second direction, the first sub-parts are spaced apart on one side of one of the body parts that is away from the other body part; Alternatively, along the second direction, the first sub-part and the second sub-part are alternately spaced on one side of the body part away from the other body part.

9. The semiconductor device according to claim 7, characterized in that, Along the second direction, the second sub-parts are alternately spaced between two adjacent body parts.

10. The semiconductor device according to claim 8, characterized in that, Along the second direction, the first sub-parts are spaced apart between two adjacent body parts, and at least a portion of the first sub-parts are located within the interval between two adjacent second sub-parts.

11. The semiconductor device according to claim 1, characterized in that, The upper limit of the doping concentration of the target doped portion is greater than the upper limit of the doping concentration of the bulk portion.

12. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a gate oxide layer and a polysilicon layer, wherein the gate oxide layer is disposed on the side of the junction field-effect layer opposite to the substrate layer; and the polysilicon layer is disposed on the side of the gate oxide layer opposite to the junction field-effect layer. Along the first direction, the gate oxide layer and the polysilicon layer begin and terminate at two adjacent bulk portions; Along the thickness direction of the substrate layer, the projection of the target doped portion lies within the gate oxide layer.

13. The semiconductor device according to claim 12, characterized in that, The base layer includes: Substrate layer; A drift layer; along the thickness direction of the substrate layer, the drift layer is located between the substrate layer and the junction field-effect layer; The semiconductor device further includes: Drain metal layer; along the thickness direction of the substrate layer, the drain metal layer is disposed on the side of the substrate layer opposite to the drift layer; A source metal layer is disposed on the side of the polysilicon layer opposite to the junction field-effect layer along the thickness direction of the substrate layer; a source hole is formed adjacent to the polysilicon layer along the first direction, and the source metal layer also fills the source hole; Passivation layer; the passivation layer is disposed between the source metal layer and the polysilicon layer.

14. The semiconductor device according to claim 1, characterized in that, The first direction is perpendicular to the second direction.

15. An electrical appliance, characterized in that, The electrical equipment includes a semiconductor device as described in any one of claims 1 to 14.

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