SiC mosfet device with esd protection and method of manufacturing the same

Abstract

The application relates to the technical field of semiconductor power devices, and provides a SiC MOSFET device with ESD protection and a preparation method thereof. The device is provided with a shared floating P well in an N-type epitaxial layer of an ESD functional area, two mutually separated N-type doped areas are formed in the device, two reverse series-connected PN junctions are formed by the two N-type doped areas and the shared floating P well, a back-to-back SiC Zener diode is formed, and the back-to-back SiC Zener diode is connected in parallel between a gate and a source, so that asymmetric bidirectional voltage clamping is realized, and the clamping voltage is lower than the FN tunneling starting voltage of a gate oxide layer; the ESD protection structure of the device is synchronously formed through the same process as the doped areas and the polysilicon layer of the MOSFET cell, no additional photoetching mask is needed, and no active area is occupied. The application can comprehensively protect the gate oxide layer under positive and negative ESD impacts, and meanwhile, the gate burnout resistance is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor power device technology, specifically to SiC MOSFET devices with ESD protection and their fabrication methods. Background Technology

[0002] Silicon carbide (SiC), as a third-generation wide-bandgap semiconductor material, possesses significant advantages such as high critical breakdown field strength, high thermal conductivity, and high electron saturation drift velocity. SiC MOSFETs have become core power switching devices in high-power applications such as electric drives for new energy vehicles, photovoltaic inverters, and rail transportation. In the pursuit of higher power density and higher switching frequencies, the thickness of the gate dielectric layer (GOX) of SiC MOSFETs has been continuously reduced with device structure optimization. Since SiC MOSFETs inevitably encounter electrostatic discharge (ESD) events during chip manufacturing, probe testing, device packaging, circuit board assembly, and even end-system maintenance, their GOX is highly susceptible to irreversible breakdown damage due to transient overvoltages, leading to threshold voltage drift, increased gate leakage current, or even complete failure. Therefore, providing SiC MOSFET GOX with sufficiently fast response, precise protection voltage windows, and minimal impact on normal switching characteristics is a key technology for improving the reliability and service life of SiC power devices.

[0003] To overcome this challenge, Chinese invention patent CN112951922B proposes an integrated ESD SiC power MOSFET device and its fabrication method. ESD discharge is achieved by integrating a PN junction diode in the epitaxial layer below the gate bonding region. This PN junction diode is formed by synchronous ion implantation with the body and source regions of the MOSFET cell, eliminating the need for additional photolithography masking steps and not occupying the active cell area. Furthermore, by setting a sharp corner morphology at the edge of the PN junction, the breakdown voltage of the diode can be adjusted. However, this solution has limitations: the integrated PN junction diode is only a unidirectional conducting structure, providing only forward ESD overvoltage protection to the gate; when the gate is subjected to reverse electrostatic discharge, the gate oxide layer still directly bears the overvoltage stress and cannot be effectively protected, still posing a risk of breakdown failure.

[0004] Chinese invention patent CN113299641B proposes a SiC MOS device that improves the backflush characteristics of ESD protection circuits. This is achieved by setting mutually spaced source P-type and drain P-type regions on the epitaxial layer and constructing two sets of nMOSFET structures to form an ESD protection circuit, thereby reducing the ESD trigger voltage, increasing the holding voltage, and suppressing the backflush effect. However, this solution mainly optimizes the overall ESD circuit characteristics of the device and does not address the specific protection design for the fact that the gate ESD tolerance of SiC MOSFETs is much lower than that of the source and drain. Furthermore, the structure requires independently dividing the device area and setting up multiple interconnect electrodes, which increases chip area overhead and process complexity to some extent, and fails to fully utilize the idle space around the gate pads to achieve zero-additional-cost ESD integration. Summary of the Invention

[0005] To help solve the above-mentioned technical problems, this application provides a SiC MOSFET device with ESD protection and a method for fabricating the same.

[0006] In a first aspect, this application provides a SiC MOSFET device with ESD protection, comprising: An N-type epitaxial layer, wherein an ESD functional area and a gate pad area are provided within the N-type epitaxial layer; The ESD region shares a floating P-well, which is a lightly P-type doped region located within the N-type epitaxial layer of the ESD functional region. The gate and source are both heavily N-type doped regions, located on the upper side of the shared floating P-well in the ESD region and separated from each other. The gate-side N-type doped region and the ESD region share a floating P-well to form a first PN junction, and the source-side N-type doped region and the ESD region share a floating P-well to form a second PN junction. The first PN junction and the second PN junction are connected in reverse series to form a back-to-back SiC Zener diode. One end of the back-to-back SiC Zener diode is electrically connected to the gate-side N-type doped region, and the other end is electrically connected to the source-side N-type doped region.

[0007] Also includes: A field oxide layer is located on the upper surface of the N-type epitaxial layer in the gate pad region; The gate pad polysilicon is located on the upper surface of the field oxide layer and has a multi-branch parallel wiring structure to disperse the current density and heat concentration under ESD impact. The gate pad region P-well is a lightly P-type doped region located within the N-type epitaxial layer of the gate pad region and directly below the polysilicon of the gate pad.

[0008] Also includes: An interlayer dielectric layer covers the N-type epitaxial layer, the field oxide layer, and the polysilicon gate pad. The gate metal and source metal are located above the interlayer dielectric layer; The gate metal is electrically connected to the gate-side N-type doped region through a first gate via and electrically connected to the gate pad polysilicon through a second gate via. Both the first gate via and the second gate via penetrate the interlayer dielectric layer. The source metal is electrically connected to the source-side N-type doped region through a first source via, and the first source via penetrates the interlayer dielectric layer.

[0009] The N-type epitaxial layer further includes a MOSFET cell active region, wherein the MOSFET cell active region comprises: The cell region P-type base region is a lightly P-type doped region located within the N-type epitaxial layer of the MOSFET cell active region; The contact region between the heavy N-type doped source region and the heavy P-type doped body region is located inside the upper side of the P-type base region of the cell region; A gate oxide layer is located on the upper surface of the N-type epitaxial layer in the active region of the MOSFET cell. The source region polysilicon is located on the upper surface of the gate oxide layer and is electrically connected to the gate pad polysilicon to transfer the ESD discharge effect of the gate pad region P well to the gate oxide layer through the polysilicon path, thereby protecting the gate oxide layer and the polysilicon and preventing the gate oxide layer from being subjected to ESD overcurrent impact. The source metal is also electrically connected to the contact region of the heavily N-type doped source region and the heavily P-type doped body through a second source via, the second source via penetrating the interlayer dielectric layer.

[0010] The back-to-back SiC Zener diodes are asymmetric bidirectional voltage clamping structures. The shared floating P-well in the ESD region is in an electrically floating state. The forward clamping voltage and reverse clamping voltage of the back-to-back SiC Zener diodes are not equal, which are used to match the different withstand voltage requirements of the gate forward bias and reverse bias, and both are lower than the FN tunneling initiation voltage of the gate oxide layer.

[0011] The gate pad region P-well, the ESD region shared floating P-well, and the cell region P-type base region are all lightly P-type doped regions formed by the same ion implantation process, and have the same doping concentration and junction depth; the gate-side heavily N-type doped region, the source-side heavily N-type doped region, and the heavily N-type doped source region are all heavily N-type doped regions formed by the same ion implantation process, and have the same doping concentration and junction depth.

[0012] The gate pad polysilicon has a parallel staggered strip structure or a multi-layered nested spiral structure. The parallel interlaced strip structure includes multiple parallel strip polysilicon branches, with the ends of each strip branch alternately connected to the opposite side borders of the gate pad area, forming multiple parallel current discharge paths. The multi-layered nested structure includes multiple loops of nested polysilicon branches from the inside out. Each loop-shaped branch is interconnected at its end, forming a multi-layered parallel spiral current discharge path.

[0013] Also includes: An N-type substrate is located below the N-type epitaxial layer; The drain electrode is located below the N-type substrate.

[0014] Secondly, this application provides a method for fabricating a SiC MOSFET device with ESD protection, used to fabricate a SiC MOSFET device as described in any one of the first aspects, wherein the method includes the following steps: An N-type substrate is provided, and an N-type epitaxial layer is formed on the front side of the N-type substrate; Independent gate pad regions P-wells and ESD regions share a floating P-well are formed within the N-type epitaxial layer, and a cell region P-type base region is formed within the N-type epitaxial layer of the MOSFET cell active region. The gate pad regions P-wells, the ESD regions share a floating P-well, and the cell region P-type base region are all lightly P-type doped regions. Within the shared floating P-well of the ESD region, a gate-side heavily N-type doped region and a source-side heavily N-type doped region are formed, which are separated from each other. At the same time, a heavily N-type doped source region is formed within the P-type base region of the cell region. The gate-side heavily N-type doped region, the source-side heavily N-type doped region, and the heavily N-type doped source region are all heavily N-type doped regions. A heavily P-type doped contact region is formed within the P-type base region of the cell region; A field oxide layer is formed in the gate pad region, a gate oxide layer is formed in the cell active region, a polysilicon layer is deposited and patterned, and gate pad polysilicon and source polysilicon located on the field oxide layer are simultaneously formed. The gate pad polysilicon and the source polysilicon are electrically connected, and the gate pad polysilicon is formed as a multi-branch parallel wiring structure. An interlayer dielectric layer and contact holes penetrating the interlayer dielectric layer are formed, and gate metal and source metal are formed. The gate metal is made ohmic contact with the heavily N-type doped region on the gate side and the polysilicon of the gate pad through a first gate via and a second gate via, respectively. The source metal is made ohmic contact with the heavily N-type doped region on the source side, the heavily N-type doped source region, and the heavily P-type doped body contact region through a first source via and a second source via, respectively. A drain electrode is formed on the back side of the N-type substrate.

[0015] The processes for forming the gate pad P-well, the shared floating P-well in the ESD region, the P-type base region in the cell region, the gate-side heavily N-type doped region, the source-side heavily N-type doped region, the heavily N-type doped source region, the gate oxide layer, and the polysilicon layer are performed synchronously with the corresponding process steps of a standard SiC MOSFET, without the need for additional photolithography masks. The formed shared floating P-well in the ESD region is electrically floating. The shared floating P-well in the ESD region, together with the gate-side heavily N-type doped region and the source-side N-type doped region, constitute a back-to-back SiC Zener diode, achieving asymmetric bidirectional voltage clamping between the gate and the source. The clamping voltage is lower than the FN tunneling initiation voltage of the gate oxide layer. Furthermore, when patterning the polysilicon layer, the gate pad polysilicon is formed into a parallel staggered strip structure or a multi-layer nested spiral structure.

[0016] In summary, compared with the prior art, this application has the following advantages: This application proposes an integrated back-to-back SiC Zener diode MOSFET, designed with an asymmetric bidirectional voltage clamping structure between the gate and source. This structure primarily protects the GOX of the SiC MOSFET from overvoltage stress, thereby improving the device's gate ESD capability. Simultaneously, this application proposes various gate routing methods above the gate pad to increase the polypath and improve the gate's current discharge capability under ESD high-voltage surges. The integrated back-to-back Zener diode consists of a floating p-type region and two independent n+ regions embedded between the gate and source. One n+ region is electrically connected to the gate, while the other n+ region is electrically connected to the source through a shared ohmic contact. Because this integrated Zener diode is located within the space between the gate and source pads, it requires virtually no additional area or photomask. Attached Figure Description

[0017] Figure 1 This is a schematic cross-sectional view of the SiC MOSFET device of this application; Figure 2 for Figure 1 The corresponding equivalent circuit schematic; Figure 3 A schematic diagram of the first design structure for a traditional gate pad polysilicon structure. Figure 4 A schematic diagram of a traditional gate pad polysilicon second design structure; Figure 5 This is a schematic diagram of the first design structure of the gate pad polysilicon in this application; Figure 6 This is a schematic diagram of the second polysilicon gate pad design structure of this application. Figure 7 This is a schematic cross-sectional view of the SiC MOSFET device corresponding to step 1 of the fabrication method of the SiC MOSFET device in this application. Figure 8 This is a schematic cross-sectional view of the SiC MOSFET device corresponding to step 2 of the fabrication method of the SiC MOSFET device in this application. Figure 9 This is a schematic cross-sectional view of the SiC MOSFET device corresponding to step 3 of the fabrication method of the SiC MOSFET device in this application. Figure 10 This is a schematic cross-sectional view of the SiC MOSFET device corresponding to step 4 of the fabrication method of the SiC MOSFET device in this application. Figure 11 This is a schematic cross-sectional view of the SiC MOSFET device corresponding to step 5 of the fabrication method of the SiC MOSFET device in this application. Figure 12 This is a schematic cross-sectional view of the SiC MOSFET device corresponding to step 6 of the fabrication method of the SiC MOSFET device in this application. Figure 13 This is a schematic cross-sectional view of the SiC MOSFET device corresponding to step 7 of the fabrication method of the SiC MOSFET device in this application. Figure 14 This is a schematic cross-sectional view of the SiC MOSFET device corresponding to step 8 of the fabrication method of the SiC MOSFET device in this application.

[0018] Figure reference numerals: 1-Drain electrode; 2-N-type substrate; 3-N-type epitaxial layer; 4-1-Gate pad region P-well; 4-2-ESD region shared floating P-well; 4-3-Cell region P-type base region; 5-1-Gate-side N-type doped region; 5-2-Source-side N-type doped region; 5-3-Heavy N-type doped source region; 6-Heavy P-type dopant contact region; 7-1-Gate pad polysilicon; 7-2-Source region polysilicon; 8-Gate oxide layer; 9-Interlayer dielectric layer; 10-Gate metal; 10-1-First gate via; 10-2-Second gate via; 11-Source metal; 11-1-First source via; 11-2-Second source via; 12-Field oxide layer. Detailed Implementation

[0019] The present application will be further described below with reference to the accompanying drawings. The structure and principle of the present application are very clear to those skilled in the art. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

[0020] Before describing the specific implementation methods, a unified explanation of all English abbreviations and terms used in this article is provided: SiC (Silicon Carbide) is silicon carbide; MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is a metal-oxide-semiconductor field-effect transistor. ESD (Electro-Static Discharge) is electrostatic discharge; GOX (Gate Oxide) is the gate oxide layer; FN (Fowler-Nordheim) refers to the Fowler-Nordheim tunneling effect; Poly (polycrystalline silicon) is a type of polycrystalline silicon. PW (P-Well) is a lightly p-type doped well; NPLUS (N+) is a heavily N-type doped region; PP (P+) is a heavily p-type doped region; FOX (Field Oxide) is the field oxide layer; AA (Active Area) is the active area; ILD (Inter-Layer Dielectric) is an interlayer dielectric layer; CT (Contact) refers to the contact hole; CT_G (Gate Contact) is the gate contact hole; CT_S (Source Contact) is the source contact hole; EPI (Epitaxy) is an extension; The spacer is for injecting into the sidewall (sidewall spacer layer).

[0021] To clearly describe the device structure, all spatial orientation terms in this application are defined with reference to the N-type epitaxial layer 3.

[0022] "Above", "above", "upper surface", and "top" all refer to the direction from the N-type epitaxial layer 3 away from the N-type substrate 2 or the surface in that direction; "Down", "below", "bottom", and "back side" all refer to the direction from the N-type epitaxial layer 3 to the N-type substrate 2 or the surface in that direction; "Inner upper side" refers to the area inside a functional layer or doped region, close to its upper surface; "Front side" refers to the side of the wafer where the main process is carried out, that is, the side where the upper surface of the N-type epitaxial layer 3 is located. "Back side" refers to the side of the wafer opposite to "front side" where the drain electrode is led out, i.e., the side where the lower surface of N-type substrate 2 is located.

[0023] The specific embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0024] Figure 1 This is a schematic cross-sectional view of the SiC MOSFET device of this application. (Combined with...) Figure 1 The SiC MOSFET device in this embodiment includes, from bottom to top, a drain electrode 1, an N-type substrate 2, and an N-type epitaxial layer 3. The upper surface of the N-type epitaxial layer 3 is divided into a gate pad region, an ESD functional region, and a MOSFET cell active region along the horizontal direction. The gate pad region is a non-active region, and the ESD functional region and the MOSFET cell active region together constitute the active region (AA).

[0025] The N-type epitaxial layer 3 contains three independent, electrically isolated lightly P-type doped regions, which are formed synchronously through the same PW ion implantation process. The three lightly P-type doped regions are: the gate pad region P-well 4-1 below the gate pad region, the ESD region shared floating P-well 4-2 below the ESD functional region, and the cell region P-type base region 4-3 below the MOSFET cell active region.

[0026] The ESD region shares a floating P-well 4-2 in an electrically floating state. Inside, on its upper side, are two independent, non-contact heavily N-type doped regions: a gate-side heavily N-type doped region 5-1 near the gate and a source-side heavily N-type doped region 5-2 near the source. The gate-side heavily N-type doped region 5-1 and the ESD region share the floating P-well 4-2 to form a first PN junction Zener diode, while the source-side heavily N-type doped region 5-2 and the ESD region share the same floating P-well 4-2 to form a second PN junction Zener diode. The two PN junctions are connected in reverse series, forming a back-to-back SiC Zener diode structure. They are connected in parallel between the gate and source of the device, forming an asymmetric bidirectional voltage clamping structure between the gate and source. This clamps the gate voltage below the FN tunneling initiation value, protecting the gate oxide layer 8 (GOX) from overvoltage stress.

[0027] Inside the upper part of the P-type base region 4-3 in the cell region, a heavily N-type doped source region 5-3 and a heavily P-type doped contact region 6 are formed. The heavily N-type doped source region 5-3 serves as the source doping region of the MOSFET, and the heavily P-type doped contact region 6 is used to achieve a low-resistance ohmic contact between the P-type base region and the source metal. The heavily N-type doped region 5-1 on the gate side, the heavily N-type doped region 5-2 on the source side, and the heavily N-type doped source region 5-3 in the active region of the MOSFET cell are formed synchronously through the same NPLUS ion implantation process. The heavily P-type doped contact region 6 is formed through a separate PP ion implantation process.

[0028] A field oxide layer 12 (FOX) is formed on the upper surface of the N-type epitaxial layer 3 in the gate pad region to achieve electrical isolation between the non-active region and the active region; a gate oxide layer 8 (GOX) is formed on the upper surface of the N-type epitaxial layer 3 in the ESD functional region and the active region of the MOSFET cell.

[0029] It should be noted that the field oxide layer 12 is formed on the upper surface of the N-type epitaxial layer 3 in the gate pad region. The lower boundary of the field oxide layer 12 is the upper surface of the N-type epitaxial layer 3 in the gate pad region, covering the N-type epitaxial layer 3 region above the P-well 4-1 in the gate pad region; the upper boundary of the field oxide layer 12 is in contact with the lower surface of the gate pad polysilicon 7-1; the left boundary of the field oxide layer 12 extends to the left edge of the gate pad region; the right boundary of the field oxide layer 12 is adjacent to the left edge of the gate oxide layer 8, and the adjacent position is the boundary between the gate pad region and the active region. The field oxide layer 12 is a continuous and complete dielectric layer. The second gate via 10-2 is located directly above the gate pad polysilicon 7-1, and the bottom of the second gate via 10-2 is exposed on the upper surface of the gate pad polysilicon 7-1, without penetrating the field oxide layer 12. The field oxide layer 12 and the gate oxide layer 8 are adjacent at the boundary between the gate pad region and the active region, and together they cover the entire upper surface of the N-type epitaxial layer 3.

[0030] Gate oxide layer 8 is formed on the upper surface of N-type epitaxial layer 3 within the active region, which includes the ESD functional region and the MOSFET cell active region. The lower boundary of gate oxide layer 8 is the upper surface of N-type epitaxial layer 3, covering the upper surfaces of the ESD region shared floating P-well 4-2, gate-side heavily N-type doped region 5-1, source-side heavily N-type doped region 5-2, cell region P-type base region 4-3, and heavily N-type doped source region 5-3. The left boundary of gate oxide layer 8 is adjacent to the right edge of field oxide layer 12, at the boundary between the gate pad region and the active region. The right boundary of gate oxide layer 8 extends to the right edge of the MOSFET cell active region. The upper boundary of gate oxide layer 8 contacts the lower surface of interlayer dielectric layer 9 in the ESD functional region and contacts the lower surface of source region polysilicon 7-2 in the MOSFET cell active region. The gate oxide layer 8 has openings directly below the first gate via 10-1, the first source via 11-1, and the second source via 11-2. The first gate via 10-1 passes through the opening to expose the upper surface of the heavily N-type doped region 5-1 on the gate side. The first source via 11-1 passes through the opening to expose the upper surface of the heavily N-type doped region 5-2 on the source side. The second source via 11-2 passes through the opening to expose the upper surfaces of both the heavily N-type doped source region 5-3 and the heavily P-type doped contact region 6.

[0031] A gate pad polysilicon 7-1 (poly at the gate pad) is formed on the upper surface of the field oxide layer 12, and an active region polysilicon 7-2 (poly at the source region) is formed on the upper surface of the gate oxide layer 8 of the MOSFET cell active region. The gate pad polysilicon 7-1 and the source region polysilicon 7-2 are formed simultaneously through the same polysilicon deposition and etching process, and are electrically connected. A gate pad region P-well 4-1 is disposed directly below the gate pad polysilicon 7-1. The gate pad region P-well 4-1 can protect the gate oxide layer 8 and the polysilicon, prevent the polysilicon from being subjected to ESD overcurrent impact, and improve the ESD discharge capability.

[0032] The entire upper surface of the polysilicon layer and the N-type epitaxial layer 3 is covered with an interlayer dielectric layer 9 (ILD) to achieve electrical insulation between the polysilicon layer and the upper metal electrode.

[0033] The interlayer dielectric layer 9 has a first gate via 10-1 (CT_G), a second gate via 10-2 (CT_G), a first source via 11-1 (CT_S), and a second source via 11-2 (CT_S), all of which penetrate the interlayer dielectric layer 9 vertically. The bottom of the first gate via 10-1 passes through the gate oxide layer 8 and exposes the upper surface of the gate-side N-type doped region 5-1. The bottom of the second gate via 10-2 exposes the upper surface of the gate pad polysilicon 7-1. The bottom of the first source via 11-1 passes through the gate oxide layer 8 and exposes the upper surface of the heavily N-type doped region 5-2 on the source side. The bottom of the second source via 11-2 passes through the gate oxide layer 8 and exposes the upper surface of the heavily N-type doped source region 5-3 and the heavily P-type doped contact region 6.

[0034] A gate metal 10 and a source metal 11 are formed on the upper surface of the interlayer dielectric layer 9. The gate metal 10 fills the interior of the first gate via 10-1 and the second gate via 10-2, and simultaneously forms ohmic contacts with the heavily N-type doped region 5-1 on the gate side and the polysilicon pad 7-1 on the gate side to achieve electrical connection; the source metal 11 fills the interior of the first source via 11-1 and the second source via 11-2, and simultaneously forms ohmic contacts with the heavily N-type doped region 5-2 on the source side, the heavily N-type doped source region 5-3, and the heavily P-type doped body contact region 6 to achieve electrical connection.

[0035] Drain electrode 1 is formed on the back side of N-type substrate 2 and serves as the drain lead of the device.

[0036] Figure 2 for Figure 1 The equivalent circuit diagram of the SiC MOSFET device with ESD protection is shown. The circuit mainly includes a main power MOSFET, a parasitic body diode, and a back-to-back SiC Zener diode connected in parallel between the gate and source. The main power MOSFET has a drain, a source, and a gate, corresponding to the MOSFET structure of the active region of the device cell; The parasitic body diode is connected in reverse parallel between the drain and the source, which is the inherent parasitic body diode of the SiC MOSFET; The back-to-back SiC Zener diode consists of two Zener diodes connected in reverse series and then connected in parallel between the gate and the source. This corresponds to two reverse PN junction structures within the device's ESD functional area, formed by the shared floating P-well 4-2 of the ESD region, the gate-side N-type doped region 5-1, and the source-side N-type doped region 5-2. These structures are used to achieve bidirectional voltage clamping between the gate and the source. Below the polysilicon pad 7-1, the polysilicon and gate oxide layer 8 are also protected by the gate pad P-well 4-1 to avoid ESD current surges and to assist in ESD current discharge.

[0037] The ESD protection working principle of this device is as follows: When the gate is subjected to a forward ESD overvoltage impact, the PN junction formed by the gate-side N-type doped region 5-1 and the ESD region sharing the floating P-well 4-2 is forward biased and conducts, while the PN junction formed by the source-side N-type doped region 5-2 and the ESD region sharing the floating P-well 4-2 is reverse biased and breaks down. The ESD current is discharged from the gate metal 10 through the gate-side N-type doped region 5-1, the ESD region sharing the floating P-well 4-2, and the source-side N-type doped region 5-2 to the source metal 11, clamping the gate-source voltage within a safe range.

[0038] When the gate is subjected to a reverse ESD overvoltage impact, the PN junction formed by the source-side N-type doped region 5-2 and the ESD region sharing a floating P-well 4-2 is forward biased and conducts, while the PN junction formed by the gate-side N-type doped region 5-1 and the ESD region sharing a floating P-well 4-2 is reverse biased and breaks down. The ESD current is discharged from the source metal 11 through the source-side N-type doped region 5-2, the ESD region sharing a floating P-well 4-2, and the gate-side N-type doped region 5-1 to the gate metal 10, thus achieving voltage clamping. Under both operating conditions, overvoltage breakdown of the gate oxide layer 8 can be avoided, achieving bidirectional ESD protection for the gate in both forward and reverse directions.

[0039] Figure 3 This is a schematic diagram of the first design structure of a traditional gate pad polysilicon. Figure 4 This is a schematic diagram of a traditional gate pad polysilicon second design structure, in which... Figure 3 The conventional polysilicon gate pad design shown employs a single-ring frame structure: polysilicon forms a closed ring frame only around the perimeter of the gate pad area, with no polysilicon covering the center area of ​​the pad. Gate signals and ESD currents are conducted only through narrow strips of polysilicon around the perimeter. This structure has a very limited conductive cross-sectional area, and under ESD impact, the current will be concentrated entirely on the ring frame, resulting in high local current density. This makes the polysilicon prone to melting and burning due to heat concentration.

[0040] Figure 4 The conventional gate pad polysilicon second design structure shown adopts a solid monolithic structure: the entire gate pad area is covered with polysilicon, forming a continuous and complete solid polysilicon layer. Although this structure has a large conductive area, the ESD current will be concentrated on the shortest DC path with the least resistance, and there is still a problem of excessively high local current density; at the same time, the monolithic polysilicon introduces a large parasitic capacitance, which negatively affects the switching speed of the device.

[0041] The principle behind the multi-branch parallel routing structure of the gate pad polysilicon 7-1 for ESD current dispersion and heat concentration suppression is as follows: Traditional solid or single-ring frame polysilicon structures, when subjected to ESD impact, tend to concentrate current along the single conductive path with the lowest resistance, resulting in extremely high local current density. The instantaneous Joule heating can cause a rapid increase in the local temperature of the polysilicon, exceeding its melting point and causing burn-out failure. This application, by graphically dividing the gate pad polysilicon 7-1 into a multi-branch parallel routing structure, distributes the ESD current to multiple parallel branches for simultaneous conduction. The current amplitude borne by a single branch is significantly reduced, effectively lowering the current density per unit area. Simultaneously, the multi-branch structure increases the total contact area between the polysilicon and the surrounding dielectric layer, facilitating the rapid dissipation of heat generated during the ESD pulse along the sidewalls of each branch to the surrounding dielectric, mitigating local heat concentration effects, and ultimately improving the gate structure's resistance to burn-out under ESD impact.

[0042] Regarding the unequal forward and reverse clamping voltages of back-to-back SiC Zener diodes, the design principle is as follows: In practical applications of SiC MOSFETs, the drive voltage applied to the gate during normal operation is typically a forward bias, while the gate oxide layer 8's tolerance under reverse bias is much lower than its tolerance under forward bias. If the clamping voltage of the ESD protection structure is symmetrically designed, i.e., the forward clamping voltage equals the reverse clamping voltage, the following contradictory situation may occur: If a higher clamping voltage is set according to the forward operating voltage requirement, the reverse clamping voltage will also be correspondingly higher. When subjected to a reverse ESD impact, the gate oxide layer 8 may have already undergone FN tunneling or even breakdown before reaching the reverse clamping voltage; if a lower clamping voltage is set according to the reverse tolerance, the forward clamping voltage may be lower than the gate drive voltage required for normal operation, causing the device to fail to turn on normally. This application employs an asymmetric bidirectional voltage clamping structure, with unequal values ​​for the forward and reverse clamping voltages. This allows for independent design to address the different withstand voltage requirements of forward and reverse gate bias, ensuring normal device operation while maximizing protection of the gate oxide layer 8 from overvoltage stress. Furthermore, both the forward and reverse clamping voltages are designed to be lower than the FN tunneling initiation voltage of the gate oxide layer 8, ensuring that under ESD impacts from any direction, the ESD protection structure breaks down and conducts before the gate oxide layer, clamping the gate voltage within a safe range.

[0043] Figure 5 This is a schematic diagram of the first design structure of the gate pad polysilicon in this application. Figure 6 This is a schematic diagram of the second design structure of the gate pad polysilicon of this application. The gate pad polysilicon 7-1 of this application adopts a distributed multi-path parallel wiring structure to replace the traditional solid whole-wafer or single-ring frame polysilicon structure, in order to disperse the current density and heat concentration under ESD impact.

[0044] Specifically, it includes the following two typical designs: The first design structure of the gate pad polysilicon in this application is: a parallel interlaced strip polysilicon structure (corresponding to...). Figure 5 The gate pad polysilicon 7-1 has a parallel staggered strip structure. Within the gate pad area, it contains multiple horizontally parallel strip polysilicon branches. The ends of each strip branch are alternately connected to the left and right side borders of the gate pad area, forming multiple parallel current discharge paths that are interconnected end to end. This structure can evenly distribute the large ESD current to multiple strip branches, avoiding excessive current density in a single path that could lead to local overheating and burnout. At the same time, the sidewall boundaries of the multiple branches significantly increase the heat dissipation area.

[0045] The second design structure of the gate pad polysilicon in this application is: a multi-layer nested polysilicon structure (corresponding to...). Figure 6 The gate pad polysilicon 7-1 features a multi-layered nested loop structure. Within the gate pad area, it contains multiple loop-shaped polysilicon branches nested sequentially from the inside out. These loop-shaped branches are interconnected at their ends, forming a multi-layered parallel spiral current discharge path. This structure allows the ESD current to diffuse layer by layer from the center outwards, resulting in a more uniform current distribution and a larger heat dissipation area. Simultaneously, the spiral path effectively increases the sheet resistance of the polysilicon, providing a certain degree of current limiting and further reducing local peak current.

[0046] The aforementioned ESD protection structure is located entirely within the terminal idle space between the gate pad and the source pad, requiring virtually no additional chip area. Furthermore, all doping, thin film, and patterning steps are completed synchronously with the standard SiC MOSFET process, eliminating the need for additional photomasks and thus not increasing chip manufacturing costs.

[0047] This application also provides a method for fabricating a SiC MOSFET device with ESD protection.

[0048] Combination Figures 7 to 14 This application provides a method for fabricating the above-mentioned device, the process flow of which includes the following steps: Step 1: Provide EPI wafers.

[0049] A silicon carbide epitaxial wafer consisting of an N-type substrate 2 and an N-type epitaxial layer 3 formed on the front side of the N-type substrate 2 is provided, and the wafer surface is subjected to standard cleaning treatment.

[0050] Step 2: PW photolithography, etching, and implantation to form the PW region.

[0051] By defining the implantation window through photolithography and etching, light-concentration P-type ion implantation and activation are performed, and three independent light P-type doped regions are simultaneously formed in the N-type epitaxial layer 3, namely the gate pad region P-well 4-1, the ESD region shared floating P-well 4-2, and the cell region P-type base region 4-3.

[0052] Step 3: Long spacer, NPLUS photolithography, etching, and implantation to form the NPLUS region.

[0053] First, implantation sidewalls (spacers) are grown on the wafer surface. Then, N-type heavily doped implantation windows are defined by photolithography and etching. High-concentration N-type ion implantation is performed and activated. Within the shared floating P-well 4-2 in the ESD region, mutually isolated gate-side heavily doped N-type regions 5-1 and source-side heavily doped N-type regions 5-2 are formed simultaneously. At the same time, heavily doped source regions 5-3 are formed simultaneously within the P-type base region 4-3 in the cell region.

[0054] Step 4: PP photolithography, etching, and implantation to form the PP region.

[0055] The P-type heavy doping implantation window is defined by photolithography and etching, and high-concentration P-type ion implantation and activation are performed to form a heavy P-type dopant contact region 6 in the P-type base region 4-3 of the cell region and on the side of the heavy N-type doped source region 5-3.

[0056] Step 5: Grow the field oxide layer FOX and define the active region AA.

[0057] A field oxide layer 12 is formed on the wafer surface by thermal oxidation or deposition. The field oxide layer of the active region is removed by photolithography and etching, while the field oxide layer 12 of the non-active regions such as the gate pad region is retained, thus defining the active region (AA) range.

[0058] Step 6: GOX gate oxide layer is grown, and polycrystalline silicon (poly) is prepared.

[0059] A gate oxide layer 8 is grown on the surface of the N-type epitaxial layer 3 in the active region using a thermal oxidation process. Subsequently, a polysilicon layer is deposited all over the front side of the wafer. After photolithography and etching patterning, gate pad polysilicon 7-1 is simultaneously formed on the surface of the field oxide layer 12 in the gate pad region, and source polysilicon 7-2 is simultaneously formed on the surface of the gate oxide layer 8 in the cell active region. The gate pad polysilicon 7-1 and the source polysilicon 7-2 are electrically connected. The gate pad polysilicon 7-1 is etched into a distributed multi-path parallel routing structure.

[0060] Step 7: Define contact holes CT_S and CT_G.

[0061] After depositing and planarizing the interlayer dielectric layer 9 (ILD) on the front side of the wafer, the first gate via 10-1, the second gate via 10-2, the first source via 11-1, and the second source via 11-2 are formed in the interlayer dielectric layer 9 through photolithography and etching processes: The bottom of the first gate via 10-1 passes through the gate oxide layer 8, exposing the surface of the gate-side N-type doped region 5-1, and the bottom of the second gate via 10-2 exposes the surface of the gate pad polysilicon 7-1. The bottom of the first source via 11-1 passes through the gate oxide layer 8, exposing the surface of the heavily N-type doped region 5-2 on the source side. The bottom of the second source via 11-2 passes through the gate oxide layer 8, simultaneously exposing the surfaces of the heavily N-type doped source region 5-3 and the heavily P-type doped contact region 6.

[0062] Step 8: Metal sputtering and back-end processes.

[0063] A metal layer is sputtered and patterned on the front side of the wafer to form gate metal 10 and source metal 11. Gate metal 10 fills the first gate via 10-1 and the second gate via 10-2, and simultaneously forms ohmic contacts with the heavily N-type doped region 5-1 on the gate side and the polysilicon pad 7-1 on the gate. Source metal 11 fills the first source via 11-1 and the second source via 11-2, and simultaneously forms ohmic contacts with the heavily N-type doped region 5-2 on the source side, the heavily N-type doped source region 5-3, and the heavily P-type doped body contact region 6. After thinning the back side of the N-type substrate 2, metal is deposited and annealed to form the drain electrode 1, completing the device fabrication.

[0064] In this fabrication method, all core process steps from step 2 to step 6, including PW implantation, NPLUS implantation, gate oxide layer 8 (GOX) growth, and polysilicon patterning, are performed synchronously with the standard SiC MOSFET fabrication process. No additional photolithography mask step is required, resulting in strong process compatibility and low manufacturing cost.

[0065] The technical scope of this application is not limited to the contents of the above specification. Those skilled in the art can make various modifications and variations to the above embodiments without departing from the technical concept of this application, and all such modifications and variations should fall within the scope of this application.

Claims

1. A SiC MOSFET device with ESD protection, characterized in that, include: The N-type epitaxial layer (3) has an ESD functional area and a gate pad area. The ESD region shares a floating P-well (4-2), which is a lightly P-type doped region located within the N-type epitaxial layer (3) of the ESD functional region; The gate-side N-type doped region (5-1) and the source-side N-type doped region (5-2) are both heavily N-type doped regions, located inside the upper side of the shared floating P-well (4-2) of the ESD region and separated from each other; The gate-side N-type doped region (5-1) and the ESD region share a floating P-well (4-2) to form a first PN junction. The source-side N-type doped region (5-2) and the ESD region share a floating P-well (4-2) to form a second PN junction. The first PN junction and the second PN junction are connected in reverse series to form a back-to-back SiC Zener diode. One end of the back-to-back SiC Zener diode is electrically connected to the gate-side N-type doped region (5-1), and the other end is electrically connected to the source-side N-type doped region (5-2).

2. The SiC MOSFET device according to claim 1, characterized in that, Also includes: A field oxide layer (12) is located on the upper surface of the N-type epitaxial layer (3) in the gate pad region; The gate pad polysilicon (7-1) is located on the upper surface of the field oxide layer (12) and has a multi-branch parallel wiring structure to disperse the current density and heat concentration under ESD impact; The gate pad region P-well (4-1) is a lightly P-type doped region located within the N-type epitaxial layer (3) of the gate pad region and directly below the gate pad polysilicon (7-1).

3. The SiC MOSFET device according to claim 2, characterized in that, Also includes: Interlayer dielectric layer (9) covers the N-type epitaxial layer (3), the field oxide layer (12) and the gate pad polysilicon (7-1). Gate metal (10) and source metal (11) are located above the interlayer dielectric layer (9); The gate metal (10) is electrically connected to the gate-side N-type doped region (5-1) through a first gate via (10-1) and to the gate pad polysilicon (7-1) through a second gate via (10-2). Both the first gate via (10-1) and the second gate via (10-2) penetrate the interlayer dielectric layer (9). The source metal (11) is electrically connected to the source-side N-type doped region (5-2) through a first source via (11-1), and the first source via (11-1) penetrates the interlayer dielectric layer (9).

4. The SiC MOSFET device according to claim 3, characterized in that, The N-type epitaxial layer (3) also includes a MOSFET cell active region, which comprises: The cell region P-type base region (4-3) is a lightly P-type doped region located within the N-type epitaxial layer (3) of the MOSFET cell active region; The heavy N-type doped source region (5-3) and the heavy P-type doped contact region (6) are located inside the upper side of the P-type base region (4-3) of the cell region; The gate oxide layer (8) is located on the upper surface of the N-type epitaxial layer (3) in the active region of the MOSFET cell; The source region polysilicon (7-2) is located on the upper surface of the gate oxide layer (8) and is electrically connected to the gate pad polysilicon (7-1) to transfer the ESD discharge effect of the gate pad region P-well (4-1) to the gate oxide layer (8) through the polysilicon path, thereby protecting the gate oxide layer (8) and the polysilicon and preventing the gate oxide layer (8) from being subjected to ESD overcurrent impact. The source metal (11) is also electrically connected to the heavy N-type doped source region (5-3) and the heavy P-type doped contact region (6) through a second source via (11-2), and the second source via (11-2) penetrates the interlayer dielectric layer (9).

5. The SiC MOSFET device according to claim 4, characterized in that, The back-to-back SiC Zener diodes are asymmetric bidirectional voltage clamping structures. The ESD region shares a floating P-well (4-2) which is electrically floating. The forward clamping voltage and reverse clamping voltage of the back-to-back SiC Zener diodes are not equal, which are used to match the different withstand voltage requirements of the gate forward bias and reverse bias respectively, and both are lower than the FN tunneling initiation voltage of the gate oxide layer (8).

6. The SiC MOSFET device according to claim 4, characterized in that, The gate pad region P-well (4-1), the ESD region shared floating P-well (4-2), and the cell region P-type base region (4-3) are lightly P-type doped regions formed by the same ion implantation process, and have the same doping concentration and junction depth; the gate-side heavily N-type doped region (5-1), the source-side heavily N-type doped region (5-2), and the heavily N-type doped source region (5-3) are heavily N-type doped regions formed by the same ion implantation process, and have the same doping concentration and junction depth.

7. The SiC MOSFET device according to claim 2, characterized in that, The gate pad polysilicon (7-1) has a parallel interlaced strip structure or a multi-layered nested spiral structure; The parallel interlaced strip structure includes multiple parallel strip polysilicon branches, with the ends of each strip branch alternately connected to the opposite side borders of the gate pad area, forming multiple parallel current discharge paths. The multi-layered nested structure includes multiple loops of nested polysilicon branches from the inside out. Each loop-shaped branch is interconnected at its end, forming a multi-layered parallel spiral current discharge path.

8. The SiC MOSFET device according to claim 1, characterized in that, Also includes: The N-type substrate (2) is located below the N-type epitaxial layer (3); The drain electrode (1) is located below the N-type substrate (2).

9. A method for fabricating a SiC MOSFET device with ESD protection, used to fabricate a SiC MOSFET device as described in any one of claims 1-8, characterized in that, The method includes the following steps: An N-type substrate (2) is provided, and an N-type epitaxial layer (3) is formed on the front side of the N-type substrate (2); An independent gate pad region P-well (4-1), a shared floating P-well (4-2) for the ESD region, and a cell region P-type base region (4-3) are formed in the N-type epitaxial layer (3) of the MOSFET cell active region. The gate pad region P-well (4-1), the shared floating P-well (4-2) for the ESD region, and the cell region P-type base region (4-3) are all lightly P-type doped regions. Within the shared floating P-well (4-2) in the ESD region, a gate-side heavily N-type doped region (5-1) and a source-side heavily N-type doped region (5-2) are formed, while a heavily N-type doped source region (5-3) is formed within the P-type base region (4-3) in the cell region. The gate-side heavily N-type doped region (5-1), the source-side heavily N-type doped region (5-2), and the heavily N-type doped source region (5-3) are all heavily N-type doped regions. A heavily P-type doped contact region (6) is formed within the P-type base region (4-3) of the cell region; A field oxide layer (12) is formed in the gate pad region, a gate oxide layer (8) is formed in the cell active region, a polysilicon layer is deposited and patterned, and a gate pad polysilicon (7-1) and a source polysilicon (7-2) located on the field oxide layer (12) and the gate oxide layer (8) are formed simultaneously. The gate pad polysilicon (7-1) and the source polysilicon (7-2) are electrically connected, and the gate pad polysilicon (7-1) is formed as a multi-branch parallel wiring structure. An interlayer dielectric layer (9) and a contact hole penetrating the interlayer dielectric layer (9) are formed, and a gate metal (10) and a source metal (11) are formed. The gate metal (10) makes ohmic contact with the gate-side N-type doped region (5-1) and the gate pad polysilicon (7-1) through the first gate via (10-1) and the second gate via (10-2), respectively. The source metal (11) makes ohmic contact with the source-side N-type doped region (5-2), the heavily N-type doped source region (5-3), and the heavily P-type doped body contact region (6) through the first source via (11-1) and the second source via (11-2), respectively. A drain electrode (1) is formed on the back side of the N-type substrate (2).

10. The preparation method according to claim 9, characterized in that, The process and standard SiC for forming the gate pad region P-well (4-1), the ESD region shared floating P-well (4-2), the cell region P-type base region (4-3), the gate-side heavily N-type doped region (5-1), the source-side heavily N-type doped region (5-2), the heavily N-type doped source region (5-3), the gate oxide layer (8), and the polysilicon layer. The corresponding process steps of the MOSFET are executed synchronously, and no additional photomask is required; the ESD region shared floating P-well (4-2) is in an electrically floating state, and the ESD region shared floating P-well (4-2), together with the gate-side N-type doped region (5-1) and the source-side N-type doped region (5-2), constitute a back-to-back SiC Zener diode, realizing asymmetric bidirectional voltage clamping between the gate and the source, and the clamping voltage is lower than the FN tunneling start voltage of the gate oxide layer (8); and when the polysilicon layer is patterned, the gate pad polysilicon (7-1) is formed into a parallel staggered strip structure or a multi-layer nested spiral structure.

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