Trench gate semiconductor device and method of manufacturing the same

Abstract

The application discloses a trench gate semiconductor device, and the trench gate longitudinally passes through a first well region of a second conductive type doping. A second well region of the second conductive type doping is formed in self-alignment with a bottom of a gate trench; a third doping region of a first conductive type doping longitudinally passes through the second well region. The second well region outside the third doping region completely covers a bottom corner of the gate trench, so as to reduce the electric field intensity at the bottom corner of the gate trench. When the device is turned on, a surface of the first well region covered by a side of a gate conductive material layer forms a first channel, and a surface of the second well region covered by the gate conductive material layer at the bottom of the gate trench forms a second channel; the third doping region and the second channel form an auxiliary turn-on path to reduce the on-resistance of the device. The application further discloses a manufacturing method of the trench gate semiconductor device. The application can reduce the on-resistance of the device while reducing the electric field intensity at the bottom corner of the trench gate by covering the bottom of the trench gate with the second well region.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a trench gate semiconductor device. This invention also relates to a method for manufacturing a trench gate semiconductor device. Background Technology

[0002] Trench SiC MOSFETs, also known as trench-gate SiC MOSFETs, often achieve this by implanting oxide at the bottom of the trench to protect the reliability of the gate oxide. However, this reduces the on-resistance of the device to some extent, affecting its performance. This will be further explained below: like Figure 1 The diagram shown is a schematic of the structure of an existing trench gate semiconductor device; taking an N-type MOSFET as an example, an existing trench gate semiconductor device includes: N-type doped semiconductor epitaxial layer 101.

[0003] A first well region 102 with P-type doping is formed in the surface region of the semiconductor epitaxial layer 101, and a trench gate passes longitudinally through the first well region 102.

[0004] The semiconductor epitaxial layer 101 at the bottom of the first well region 102 forms a drift region 101a.

[0005] An N-type heavily doped source region 103, aligned with the side of the trench gate, is formed in the surface region of the first well region 102.

[0006] The trench gate includes a gate oxide layer 104 formed on the inner surface of the gate trench and a polysilicon gate 105 filled in the gate trench.

[0007] A second well region 106 with P-type doping is formed at the bottom of the gate trench through self-alignment.

[0008] The second well region 106 completely covers the bottom corner of the gate trench to reduce the electric field strength at the bottom corner of the gate trench.

[0009] At the bottom of the drift region 101a, an N-type heavily doped drain region 107 is also formed.

[0010] A p-type heavily doped body lead-out region 108 is also formed in the surface region of the first well region 102, and there is a gap between the body lead-out region 108 and the trench gate. The body lead-out region 108 is used to lead out the first well region 102.

[0011] Both the body lead-out region 108 and the source region 103 are connected to the source electrode, which is composed of the front metal layer 111, through a contact hole 110 at the top that passes through the interlayer membrane 109. Figure 1 Only the front metal layer 111 corresponding to the source electrode is shown in the image.

[0012] The polysilicon gate 105 is connected to the gate formed by the front metal layer 111 through the corresponding contact hole 110 at the top. The gate is in Figure 1 The corresponding cross-section is not shown.

[0013] Depend on Figure 1 As shown, after the second well region 106 is formed, when the device is turned on, Figure 1 The electron conduction path indicated by the middle arrow only passes through the region shown by the dashed coil 112 and cannot pass through the bottom region of the trench gate. Therefore, the electron conduction path is narrowed, which increases the on-resistance of the device. Thus, the introduction of the second well region 106 increases the on-resistance of the device. Summary of the Invention

[0014] The technical problem to be solved by the present invention is to provide a trench gate semiconductor device that can reduce the electric field strength at the bottom corner of the trench gate and reduce the on-resistance of the device by covering the bottom of the trench gate with a doped region of the opposite doping type to the drift region. To this end, the present invention also provides a method for manufacturing the trench gate semiconductor device.

[0015] To solve the above-mentioned technical problems, the trench gate semiconductor device provided by the present invention includes: Semiconductor epitaxial layer doped with the first conductivity type.

[0016] A first well region doped with a second conductivity type is formed in the surface region of the semiconductor epitaxial layer, and a trench gate extends longitudinally through the first well region.

[0017] The semiconductor epitaxial layer at the bottom of the first well region forms a drift region.

[0018] A first conductivity type heavily doped source region is formed in the surface region of the first well region, which is aligned with the side of the trench gate.

[0019] The trench gate includes a gate dielectric layer formed on the inner surface of the gate trench and a gate conductive material layer filled in the gate trench.

[0020] A second well region with a second conductivity type doped is formed at the bottom of the gate trench in a self-aligned manner; a third doped region with a first conductivity type doped is formed in the second well region and extends longitudinally from the bottom surface of the gate trench into the drift region at the bottom of the second well region.

[0021] The second well region outside the third doped region completely covers the bottom corner of the gate trench to reduce the electric field strength at the bottom corner of the gate trench.

[0022] When the device is turned on, a first channel is formed on the surface of the first well region covered by the side of the gate conductive material layer, and a second channel is formed on the surface of the second well region covered by the gate conductive material layer at the bottom of the gate trench; the third doped region and the second channel form an auxiliary conduction path to reduce the on-resistance of the device.

[0023] A further improvement is that the center position of the third doped region is aligned with the center position of the gate trench along the width direction of the gate trench.

[0024] The sidewalls of the third doped region are defined by self-aligned sacrificial inner sidewalls formed on the sidewalls of the gate trench, which are removed before the gate dielectric layer is formed.

[0025] A further improvement is that the trench gate semiconductor device is a MOSFET.

[0026] A heavily doped drain region of the first conductivity type is also formed at the bottom of the drift region.

[0027] A further improvement is that a heavily doped body lead-out region of a second conductivity type is also formed in the surface region of the first well region, and there is a gap between the body lead-out region and the trench gate.

[0028] Both the body lead-out region and the source region are connected to the source electrode, which is composed of a front metal layer, through a contact hole at the top.

[0029] The gate conductive material layer is connected to the gate, which is composed of the front metal layer, through the corresponding contact hole at the top.

[0030] A further improvement is that the material of the semiconductor epitaxial layer includes Si or SiC.

[0031] A further improvement is that the material of the gate dielectric layer includes a silicon oxide layer.

[0032] The material of the gate conductive material layer includes polycrystalline silicon.

[0033] A further improvement is that the injection concentration in the second well region is 1E18 cm⁻¹. -2 ~1E19cm -2 The implantation concentration of the third doped region is 1E18cm⁻¹. -2 ~1E19cm -2 .

[0034] A further improvement is that the trench gate semiconductor device is an N-type device, with the first conductivity type being N-type and the second conductivity type being P-type; or, the trench gate semiconductor device is a P-type device, with the first conductivity type being P-type and the second conductivity type being N-type.

[0035] To solve the above-mentioned technical problems, the manufacturing method of the trench gate semiconductor device provided by the present invention includes the following steps: A semiconductor epitaxial layer doped with a first conductivity type is provided, and a first well region doped with a second conductivity type is formed in a surface region of the semiconductor epitaxial layer, and a source region heavily doped with the first conductivity type is formed in a selected region of the surface region of the first well region.

[0036] A gate trench formation region is defined and the semiconductor epitaxial layer is etched to form a gate trench. The gate trench passes through the source region and the first well region at the bottom of the source region. The semiconductor epitaxial layer at the bottom of the first well region forms a drift region.

[0037] A second well region is formed by self-aligning ion implantation of a second conductivity type at the bottom of the gate trench.

[0038] A sacrificial inner wall is formed by self-alignment on the side of the gate trench.

[0039] Ion implantation of the first conductivity type is performed to form a third doped region through the second well region at the bottom of the gate trench. The bottom surface of the third doped region enters the drift region. The side of the third doped region is defined by the self-alignment of the sacrificial inner sidewalls on both sides of the gate trench. The second well region outside the third doped region completely covers the bottom corner of the gate trench to reduce the electric field strength at the bottom corner of the gate trench.

[0040] Removing the sacrificial inner wall and forming a trench gate in the gate trench includes: forming a gate dielectric layer on the inner surface of the gate trench and filling the gate trench with a gate conductive material layer; when the device is turned on, a first channel is formed on the surface of the first well region covered by the side of the gate conductive material layer, and a second channel is formed on the surface of the second well region covered by the gate conductive material layer at the bottom of the gate trench; the third doped region and the second channel form an auxiliary conduction path to reduce the on-resistance of the device.

[0041] A further improvement is that the trench gate semiconductor device is a MOSFET.

[0042] A heavily doped drain region of the first conductivity type is also formed at the bottom of the drift region.

[0043] A further improvement is that, after forming the first well region, it also includes: A heavily doped body lead-out region of the second conductivity type is formed in the surface region of the first well region, and there is a gap between the body lead-out region and the trench gate.

[0044] After forming the trench grid, it also includes: An interlayer film is formed, a contact hole is formed through the interlayer film, a front metal layer is formed, and the front metal layer is patterned to form the source and gate; the body lead-out region and the source region are both connected to the source through the corresponding contact hole at the top; the gate conductive material layer is connected to the gate through the corresponding contact hole at the top.

[0045] A further improvement is that the material of the semiconductor epitaxial layer includes Si or SiC.

[0046] A further improvement is that the material of the gate dielectric layer includes a silicon oxide layer.

[0047] The material of the gate conductive material layer includes polycrystalline silicon.

[0048] A further improvement is that the injection concentration in the second well region is 1E18 cm⁻¹. -2 ~1E19cm -2 The implantation concentration of the third doped region is 1E18cm⁻¹. -2 ~1E19cm -2 .

[0049] A further improvement is that, before defining the formation region of the gate trench, a hard mask layer is formed; Then, before etching the semiconductor epitaxial layer, the hard mask layer is etched first.

[0050] The hard mask layer is removed after the trench gate is formed.

[0051] A further improvement is that the trench gate semiconductor device is an N-type device, with the first conductivity type being N-type and the second conductivity type being P-type; or, the trench gate semiconductor device is a P-type device, with the first conductivity type being P-type and the second conductivity type being N-type.

[0052] This invention, based on the use of a second well region with a doping type opposite to that of the drift region covering the bottom region of the gate trench, adds a third doped region extending from the bottom surface of the gate trench through the second well region. The doping type of the third doped region is the same as that of the drift region, i.e., both are doped with the first conductivity type. In this way, the channel formed by the third doped region and the gate conductive material layer covering the surface of the second well region, i.e., the second channel, can form an auxiliary conduction path, thereby making the conduction path of the drift region into the first channel more dispersed, thus reducing the on-resistance of the device. At the same time, in this invention, the second well region still maintains complete coverage of the bottom corner of the gate trench, thus reducing the electric field intensity at the bottom corner of the trench, achieving protection of the gate dielectric layer at the bottom corner of the gate trench, thereby improving the reliability of the device. Therefore, this invention can reduce the electric field intensity at the bottom corner of the trench gate and reduce the on-resistance of the device by covering the bottom of the trench gate with a doped region with a doping type opposite to that of the drift region, i.e., the second well region. Attached Figure Description

[0053] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments: Figure 1 This is a schematic diagram of the structure of an existing trench gate semiconductor device; Figure 2 This is a schematic diagram of the structure of a trench gate semiconductor device according to an embodiment of the present invention; Figures 3-7 This is a schematic diagram of the device structure in each step of the manufacturing method of the trench gate semiconductor device according to an embodiment of the present invention. Detailed Implementation

[0054] like Figure 2 The diagram shown is a structural schematic of a trench gate semiconductor device according to an embodiment of the present invention; the trench gate semiconductor device according to an embodiment of the present invention includes: Semiconductor epitaxial layer 201 doped with the first conductivity type.

[0055] A first well region 202 with a second conductivity type doped is formed in the surface region of the semiconductor epitaxial layer 201, and a trench gate extends longitudinally through the first well region 202.

[0056] The semiconductor epitaxial layer 201 at the bottom of the first well region 202 forms a drift region 201a.

[0057] A first conductivity type heavily doped source region 203 is formed in the surface region of the first well region 202, which is aligned with the side of the trench gate.

[0058] The trench gate includes a gate dielectric layer 204 formed on the inner surface of the gate trench 302 and a gate conductive material layer 205 filled in the gate trench 302. Please refer to [reference needed] for the gate trench 302. Figure 4 As shown.

[0059] In this embodiment of the invention, the gate dielectric layer 204 is made of silicon oxide. In other embodiments, the gate dielectric layer 204 may also be made of other dielectric materials such as LK material, as needed.

[0060] In this embodiment of the invention, the gate conductive material layer 205 is made of polysilicon. In other embodiments, the gate conductive material layer 205 may also be made of metal.

[0061] A second well region 206 with a second conductivity type doped is formed at the bottom of the gate trench 302 in a self-aligned manner; a third doped region 212 with a first conductivity type doped is formed in the second well region 206 and extends longitudinally from the bottom surface of the gate trench 302 into the drift region 201a at the bottom of the second well region 206.

[0062] In some embodiments, the injection concentration of the second well region 206 is 1E18cm⁻¹. -2 ~1E19cm -2 The implantation concentration of the third doped region 212 is 1E18cm⁻¹. -2 ~1E19cm -2 .

[0063] The second well region 206 outside the third doped region 212 completely covers the bottom corner of the gate trench 302 to reduce the electric field strength at the bottom corner of the gate trench 302.

[0064] When the device is turned on, a first channel is formed on the surface of the first well region 202 covered by the side of the gate conductive material layer 205, and a second channel is formed on the surface of the second well region 206 covered by the gate conductive material layer 205 at the bottom of the gate trench 302; the third doped region 212 and the second channel form an auxiliary conduction path to reduce the on-resistance of the device. Figure 2 In the diagram, the current conduction path is represented by an arrow. It can be seen that the conduction path passing through the region shown by the dashed coil 213a is the dominant conduction path. Figure 1 The conduction path of the region shown by the dashed coil 112 in the existing structure is the same; Figure 2 In the diagram, the conduction path in the region shown by the dashed coil 213b is the auxiliary conduction path passing through the third doped region 212 and the second channel. This auxiliary conduction path is... Figure 1 The added conduction path is based on the existing structure shown, therefore Figure 2 There are more corresponding conduction paths, thus reducing the on-resistance of the device.

[0065] In this embodiment of the invention, the center position of the third doped region 212 is aligned with the center position of the gate trench 302 along the width direction of the gate trench 302.

[0066] The sidewalls of the third doped region 212 are defined by self-alignment of sacrificial inner sidewalls 303 formed on the sidewalls of the gate trench 302, which are removed before the gate dielectric layer 204 is formed. Please refer to [reference needed for details on sacrificial inner sidewalls 303]. Figure 6 As shown.

[0067] In this embodiment of the invention, the trench gate semiconductor device is a MOSFET. A heavily doped drain region 207 of a first conductivity type is also formed at the bottom of the drift region 201a. In other embodiments, the trench gate semiconductor device can also be an IGBT, in which case the drain region 207 on the back side needs to be replaced with a collector region doped with a second conductivity type.

[0068] A second conductivity type heavily doped body lead-out region 208 is also formed in the surface region of the first well region 202, and there is a gap between the body lead-out region 208 and the trench gate.

[0069] Both the body lead-out region 208 and the source region 203 are connected to the source electrode, which is composed of the front metal layer 211, through a contact hole 210 at the top that passes through the interlayer membrane 209. Figure 2 Only the front metal layer 211 corresponding to the source electrode is shown in the image.

[0070] The gate conductive material layer 205 is connected to the gate composed of the front metal layer 211 through the corresponding contact hole 210 at the top. The gate is in Figure 2 The corresponding cross-section is not shown.

[0071] In this embodiment of the invention, the semiconductor epitaxial layer 201 is made of SiC, and the trench gate semiconductor device is a SiC device. In other embodiments, the semiconductor epitaxial layer 201 may also be made of Si or other semiconductor materials.

[0072] In this embodiment of the invention, the trench gate semiconductor device is an N-type device, with the first conductivity type being N-type and the second conductivity type being P-type. In other embodiments, the trench gate semiconductor device may also be a P-type device, with the first conductivity type being P-type and the second conductivity type being N-type.

[0073] In this embodiment of the invention, based on the use of a second well region 206 with a doping type opposite to that of the drift region 201a to cover the bottom region of the gate trench 302, a third doped region 212 is added, extending from the bottom surface of the gate trench 302 through the second well region 206. The doping type of the third doped region 212 is the same as that of the drift region 201a, i.e., both are doped with the first conductivity type. In this way, the channel formed by the third doped region 212 and the gate conductive material layer 205 covering the surface of the second well region 206, i.e., the second channel, can form an auxiliary conduction path, thereby enabling the drift region 201a to... The conduction paths into the first channel are more dispersed, thus reducing the on-resistance of the device. Simultaneously, in this embodiment, the second well region 206 still completely covers the bottom corner of the gate trench 302, thereby reducing the electric field strength at the bottom corner and protecting the gate dielectric layer 204 at the bottom corner of the gate trench 302, thus improving the device's reliability. Therefore, this embodiment can reduce the electric field strength at the bottom corner of the trench gate and simultaneously reduce the on-resistance of the device by covering the bottom of the trench gate with a doped region (the second well region 206) with a doping type opposite to that of the drift region 201a.

[0074] like Figures 3 to 7The diagram shown is a schematic representation of the device structure in each step of the manufacturing method of the trench gate semiconductor device according to an embodiment of the present invention. The manufacturing method of the trench gate semiconductor device according to an embodiment of the present invention includes the following steps: Step S101, as follows Figure 3 As shown, a semiconductor epitaxial layer 201 doped with a first conductivity type is provided, and a first well region 202 doped with a second conductivity type is formed in a surface region of the semiconductor epitaxial layer 201, and a source region 203 heavily doped with the first conductivity type is formed in a selected region of the surface region of the first well region 202.

[0075] In the method of this embodiment of the invention, the trench gate semiconductor device is a MOSFET.

[0076] A heavily doped drain region 207 of a first conductivity type is also formed at the bottom of the provided semiconductor epitaxial layer 201.

[0077] The method in this embodiment of the invention, after forming the first well region 202, further includes: A heavily doped body lead-out region 208 of the second conductivity type is formed in the surface region of the first well region 202, and there is a gap between the body lead-out region 208 and the trench gate.

[0078] In the method of this embodiment, the material of the semiconductor epitaxial layer 201 is SiC. In other embodiments, the material of the semiconductor epitaxial layer 201 may also be other semiconductor materials such as Si.

[0079] Step S102, as follows Figure 4 As shown, the formation region of the gate trench 302 is defined and the semiconductor epitaxial layer 201 is etched to form the gate trench 302. The gate trench 302 passes through the source region 203 and the first well region 202 at the bottom of the source region 203. The semiconductor epitaxial layer 201 at the bottom of the first well region 202 forms a drift region 201a.

[0080] In the method of this embodiment of the invention, before defining the formation region of the gate trench 302, the method further includes: forming a hard mask layer 301.

[0081] Subsequently, before etching the semiconductor epitaxial layer 201, the hard mask layer 301 is etched first.

[0082] The hard mask layer 301 is subsequently... Figure 7 The corresponding trench gate is removed after the step of forming the trench gate.

[0083] Step S103, as follows Figure 5 As shown, a second conductivity type ion implantation is performed to form a second well region 206 at the bottom of the gate trench 302 through self-alignment.

[0084] In the method of this embodiment of the invention, the injection concentration of the second well region 206 is 1E18cm⁻¹. -2 ~1E19cm -2 .

[0085] Step S104, as follows Figure 6 As shown, a sacrificial inner wall 303 is formed by self-alignment on the side of the gate trench 302.

[0086] Step S105, as follows Figure 6 As shown, ion implantation of the first conductivity type is performed to form a third doped region 212 at the bottom of the gate trench 302, which extends through the second well region 206. The bottom surface of the third doped region 212 enters the drift region 201a. The side of the third doped region 212 is defined by the self-alignment of the sacrificial inner sidewalls 303 on both sides of the gate trench 302. The second well region 206 outside the third doped region 212 completely covers the bottom corner of the gate trench 302 to reduce the electric field strength at the bottom corner of the gate trench 302.

[0087] In the method of this embodiment of the invention, the implantation concentration of the third doped region 212 is 1E18cm⁻¹. -2 ~1E19cm -2 .

[0088] Step S106, as follows Figure 7 As shown, removing the sacrificial inner wall 303 and forming a trench gate in the gate trench 302 includes: forming a gate dielectric layer 204 on the inner surface of the gate trench 302 and filling the gate trench 302 with a gate conductive material layer 205; when the device is turned on, a first channel is formed on the surface of the first well region 202 covered by the side of the gate conductive material layer 205, and a second channel is formed on the surface of the second well region 206 covered by the gate conductive material layer 205 at the bottom of the gate trench 302; the third doped region 212 and the second channel form an auxiliary conduction path to reduce the on-resistance of the device.

[0089] In the method of this embodiment of the invention, the material of the gate dielectric layer 204 includes a silicon oxide layer, such as formed by a thermal oxidation process.

[0090] The material of the gate conductive material layer 205 includes polycrystalline silicon.

[0091] After forming the trench grid, it also includes: Back Figure 2As shown, an interlayer film 209 is formed, a contact hole 210 is formed through the interlayer film 209, a front metal layer 211 is formed, and the front metal layer 211 is patterned to form the source and gate; the body lead-out region 208 and the source region 203 are both connected to the source through the corresponding contact hole 210 at the top; the gate conductive material layer 205 is connected to the gate through the corresponding contact hole 210 at the top.

[0092] In the method of this embodiment, the trench gate semiconductor device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, the trench gate semiconductor device can also be a P-type device, with the first conductivity type being P-type and the second conductivity type being N-type.

[0093] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A trench gate semiconductor device, characterized in that, include: Semiconductor epitaxial layer doped with the first conductivity type; A first well region doped with a second conductivity type is formed in the surface region of the semiconductor epitaxial layer, and a trench gate longitudinally passes through the first well region; The semiconductor epitaxial layer at the bottom of the first well region forms a drift region; A first conductivity type heavily doped source region is formed in the surface region of the first well region, which is aligned with the side of the trench gate; The trench gate includes a gate dielectric layer formed on the inner surface of the gate trench and a gate conductive material layer filled in the gate trench. A second well region with a second conductivity type doped is formed at the bottom of the gate trench in a self-aligned manner; a third doped region with a first conductivity type doped is formed in the second well region and extends longitudinally from the bottom surface of the gate trench into the drift region at the bottom of the second well region; The second well region outside the third doped region completely covers the bottom corner of the gate trench to reduce the electric field strength at the bottom corner of the gate trench. When the device is turned on, a first channel is formed on the surface of the first well region covered by the side of the gate conductive material layer, and a second channel is formed on the surface of the second well region covered by the gate conductive material layer at the bottom of the gate trench. The third doped region and the second channel form an auxiliary conduction path to reduce the on-resistance of the device.

2. The trench gate semiconductor device as described in claim 1, characterized in that: Along the width direction of the gate trench, the center position of the third doped region is aligned with the center position of the gate trench; The sidewalls of the third doped region are defined by self-aligned sacrificial inner sidewalls formed on the sidewalls of the gate trench, which are removed before the gate dielectric layer is formed.

3. The trench gate semiconductor device as described in claim 1, characterized in that: The trench gate semiconductor device is a MOSFET; A heavily doped drain region of the first conductivity type is also formed at the bottom of the drift region.

4. The trench gate semiconductor device as described in claim 1, characterized in that: A heavily doped body lead-out region of a second conductivity type is also formed in the surface region of the first well region, and there is a gap between the body lead-out region and the trench gate; Both the body lead-out region and the source region are connected to the source electrode, which is composed of a front metal layer, through a contact hole at the top. The gate conductive material layer is connected to the gate, which is composed of the front metal layer, through the corresponding contact hole at the top.

5. The trench gate semiconductor device as described in claim 1, characterized in that: The material of the semiconductor epitaxial layer includes Si or SiC.

6. The trench gate semiconductor device as claimed in claim 1, characterized in that: The material of the gate dielectric layer includes a silicon oxide layer; The material of the gate conductive material layer includes polycrystalline silicon.

7. The trench gate semiconductor device as claimed in claim 1, characterized in that: The injection concentration in the second well region is 1E18cm. -2 ~1E19cm -2 The implantation concentration of the third doped region is 1E18cm⁻¹. -2 ~1E19cm -2 .

8. The trench gate semiconductor device according to any one of claims 1 to 7, characterized in that: The trench gate semiconductor device is an N-type device with an N-type first conductivity type and a P-type second conductivity type; or, the trench gate semiconductor device is a P-type device with a P-type first conductivity type and an N-type second conductivity type.

9. A method for manufacturing a trench gate semiconductor device, characterized in that, Includes the following steps: A semiconductor epitaxial layer doped with a first conductivity type is provided, and a first well region doped with a second conductivity type is formed in a surface region of the semiconductor epitaxial layer, and a source region heavily doped with the first conductivity type is formed in a selected region of the surface region of the first well region; The formation region of the gate trench is defined and the semiconductor epitaxial layer is etched to form the gate trench, which passes through the source region and the first well region at the bottom of the source region; The semiconductor epitaxial layer at the bottom of the first well region forms a drift region; A second well region is formed by self-aligning ion implantation of a second conductivity type at the bottom of the gate trench. A sacrificial inner wall is formed by self-alignment on the side of the gate trench; Ion implantation of the first conductivity type is performed to form a third doped region through the second well region at the bottom of the gate trench. The bottom surface of the third doped region enters the drift region. The side of the third doped region is defined by the self-alignment of the sacrificial inner sidewalls on both sides of the gate trench. The second well region outside the third doped region completely covers the bottom corner of the gate trench to reduce the electric field strength at the bottom corner of the gate trench. Removing the sacrificial inner wall and forming a trench gate in the gate trench includes: forming a gate dielectric layer on the inner surface of the gate trench and filling the gate trench with a gate conductive material layer; when the device is turned on, a first channel is formed on the surface of the first well region covered by the side of the gate conductive material layer, and a second channel is formed on the surface of the second well region covered by the gate conductive material layer at the bottom of the gate trench; the third doped region and the second channel form an auxiliary conduction path to reduce the on-resistance of the device.

10. The method for manufacturing a trench gate semiconductor device as described in claim 9, characterized in that: The trench gate semiconductor device is a MOSFET; A heavily doped drain region of the first conductivity type is also formed at the bottom of the drift region.

11. The method for manufacturing a trench gate semiconductor device as described in claim 9, characterized in that: After the first well region is formed, the method further includes: A heavily doped body lead-out region of a second conductivity type is formed in the surface region of the first well region, and there is a gap between the body lead-out region and the trench gate; After forming the trench grid, it also includes: An interlayer film is formed, a contact hole is formed through the interlayer film, a front metal layer is formed, and the front metal layer is patterned to form the source and gate; the body lead-out region and the source region are both connected to the source through the corresponding contact hole at the top; the gate conductive material layer is connected to the gate through the corresponding contact hole at the top.

12. The method for manufacturing a trench gate semiconductor device as described in claim 9, characterized in that: The material of the semiconductor epitaxial layer includes Si or SiC.

13. The method for manufacturing a trench gate semiconductor device as described in claim 9, characterized in that: The material of the gate dielectric layer includes a silicon oxide layer; The material of the gate conductive material layer includes polycrystalline silicon.

14. The method for manufacturing a trench gate semiconductor device as described in claim 9, characterized in that: The injection concentration in the second well region is 1E18cm. -2 ~1E19cm -2 The implantation concentration of the third doped region is 1E18cm⁻¹. -2 ~1E19cm -2 .

15. The method for manufacturing a trench gate semiconductor device as described in claim 9, characterized in that: Before defining the formation region of the gate trench, the method further includes: forming a hard mask layer; Then, before etching the semiconductor epitaxial layer, the hard mask layer is etched first; The hard mask layer is removed after the trench gate is formed.

16. The method for manufacturing a trench gate semiconductor device according to any one of claims 9 to 15, characterized in that: The trench gate semiconductor device is an N-type device with an N-type first conductivity type and a P-type second conductivity type; or, the trench gate semiconductor device is a P-type device with a P-type first conductivity type and an N-type second conductivity type.

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