Power unit, power device and high voltage integrated circuit

Abstract

The application provides a power unit, a power device and a high-voltage integrated circuit, wherein the power unit comprises: a semiconductor substrate of a second conductive type; an epitaxial layer of the second conductive type; a first well region of a first conductive type, a second well region of the first conductive type and a first doped region of the first conductive type, the first well region and the second well region are arranged at intervals, and the first doped region is located in the epitaxial layer between the first well region and the second well region; an isolation medium layer is located on the epitaxial layer, the first well region and the second well region, and a first opening and a second opening are arranged at intervals on the isolation medium layer; a source region of the first conductive type is in contact with the first well region through the first opening; a drain region of the first conductive type is in contact with the second well region through the second opening; and a gate lead-out region is projected between the source region and the drain region and covers at least part of the first well region. The application can obtain a power unit with high current capacity and high voltage resistance.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a power unit, power device, and high-voltage integrated circuit. Background Technology

[0002] High Voltage Integrated Circuit (HVIC) is a technology that integrates high-voltage power devices and low-voltage control circuits. HVIC bootstrap and startup modules typically use Junction Gate Field-Effect Transistors (JFETs). In the bootstrap module, when the bootstrap JFET is forward-biased, the power supply charges the bootstrap capacitor through the JFET. Furthermore, during reverse blocking, the bootstrap capacitor receives switching point changes, and current flows from the drain to the source, raising its potential and creating reverse bias with the gate, automatically pinching off the current and constructing a depletion region to withstand the voltage. In the startup module, the high-voltage power supply supplies power to the startup module through the JFET, automatically pinching off after reaching a certain voltage. Both applications require the JFET device to possess both high current capability and high voltage withstand capability. Summary of the Invention

[0003] The purpose of this invention is to provide a power unit, a power device, and a high-voltage integrated circuit, so that the power unit has high current capability and high voltage withstand capability.

[0004] To achieve the above and other related objectives, the present invention provides a power unit comprising:

[0005] Semiconductor substrate of the second conductivity type;

[0006] An epitaxial layer of the second conductivity type is located on the semiconductor substrate;

[0007] A first well region of a first conductivity type, a second well region of a first conductivity type, and a first doped region of a first conductivity type, wherein the first well region and the second well region extend from the surface of the epitaxial layer into the epitaxial layer, the first well region and the second well region are spaced apart, and the first doped region is located in the epitaxial layer between the first well region and the second well region.

[0008] An isolation dielectric layer is located on the epitaxial layer, the first well region, and the second well region; the isolation dielectric layer is provided with a first opening and a second opening at intervals.

[0009] The source region of the first conductivity type contacts the first well region through the first opening of the isolation dielectric layer;

[0010] The drain region of the first conductivity type contacts the second well region through the second opening of the isolation dielectric layer;

[0011] A gate lead-out region, the projection of which is located between the source region and the drain region, the projection of which at least partially covers the first well region.

[0012] Optionally, in the power unit, the depth of the first doped region in the epitaxial layer is less than the depth of the first well region and the second well region in the epitaxial layer.

[0013] Optionally, in the power unit, the first doped region extends from the first surface of the epitaxial layer into the epitaxial layer; the isolation dielectric layer is located on the epitaxial layer, the first well region, the first doped region, and the second well region, and the first surface of the epitaxial layer is the surface of the epitaxial layer away from the semiconductor substrate.

[0014] Optionally, in the power unit, the first doped region is located in the epitaxial layer, and there is a first distance between the first doped region and the first surface of the epitaxial layer, wherein the first surface of the epitaxial layer is the surface of the epitaxial layer away from the semiconductor substrate.

[0015] Optionally, in the power unit, the projection of the gate lead-out region also covers at least a portion of the first doped region.

[0016] Optionally, in the power unit, the projection of the gate lead-out region covers a portion of the first well region, the first doped region, and a portion of the second well region.

[0017] Optionally, in the power unit, the width of the second well region is greater than the width of the first well region.

[0018] Optionally, in the power unit, the power unit further includes a field plate located on an isolation dielectric layer on the second well region and between the gate lead-out region and the drain region.

[0019] Optionally, in the power unit, the field plate is a single-layer field plate or a multi-layer field plate.

[0020] Optionally, in the power unit, the single-layer field plate includes multiple concentric circle structures with different radii, and the concentric circle structures with different radii are connected together.

[0021] Optionally, in the power unit, the single-layer field plate comprises a single helical structure.

[0022] Optionally, in the power unit, the multilayer field plates include multiple concentric circle structures, with a portion of two adjacent field plates staggered and another portion of two adjacent field plates overlapping.

[0023] Optionally, in the power unit, each of the field plates includes one of a polycrystalline silicon resistive field plate, a polycrystalline silicon floating field plate, or a metal field plate.

[0024] Optionally, the power unit further includes a first buried layer of a second conductivity type, located at the junction of the second well region and the epitaxial layer.

[0025] Optionally, the power unit further includes a buffer doped layer of a second conductivity type, which is disposed around the first buried layer.

[0026] Optionally, in the power unit, the power unit further includes: a second doped region of a second conductivity type, which is located on the lower surface of the first doped region and connected to the first well region and the second well region.

[0027] Optionally, in the power unit, the doping concentration of the second doped region is greater than the doping concentration of the epitaxial layer.

[0028] Optionally, in the power unit, the second doped region and the first doped region are fabricated using the same photomask.

[0029] Optionally, in the power unit, there is one first doped region and one second doped region, with the second doped region located on the lower surface of the first doped region.

[0030] Optionally, in the power unit, there are multiple first doped regions and multiple second doped regions, and the first doped regions and the second doped regions are stacked alternately.

[0031] Optionally, in the power unit, the number of the first doped region and the number of the second doped region are equal, or the number of the first doped region is one more than the number of the second doped region.

[0032] Optionally, in the power unit, the source region is located on the first well region; the drain region is located on the second well region; and the gate lead-out region is located on the isolation dielectric layer between the source region and the drain region.

[0033] Optionally, in the power unit, the power unit further includes a first metal layer, a second metal layer, and a third metal layer, wherein the source region is shorted out through the first metal layer as the source, the drain region is shorted out through the second metal layer as the drain, and the gate lead-out region is shorted out through the third metal layer as the gate.

[0034] Optionally, in the power unit, the power unit further includes a body region of a second conductivity type and a fourth metal layer. The isolation dielectric layer is also provided with a third opening. The body region contacts the epitaxial layer through the third opening of the isolation dielectric layer. The body region is short-circuited out through the fourth metal layer as the body electrode.

[0035] Optionally, in the power unit, the isolation dielectric layer has a beak-shaped form at the first opening, the second opening, and the third opening.

[0036] Optionally, in the power unit, the thickness of the isolation dielectric layer below the gate lead-out region is equal to the thickness of the isolation dielectric layer outside the gate lead-out region.

[0037] Optionally, in the power unit, the thickness of the isolation dielectric layer below the gate lead-out region is less than the thickness of the isolation dielectric layer outside the gate lead-out region, and a step is formed on the isolation dielectric layer below the gate lead-out region.

[0038] Optionally, in the power unit, the power unit further includes: a second buried layer of a second conductivity type, which is located at the junction of the bottom of the second well region near the first doped region and the epitaxial layer.

[0039] Optionally, in the power unit, the bottom morphology of the second well region near the first doped region may be flat or uneven.

[0040] Optionally, in the power unit, an intermittent implantation method is used to make the bottom morphology of the second well region near the first doped region uneven.

[0041] Optionally, in the power unit, if the first conductivity type is P-type, then the second conductivity type is N-type; or, if the first conductivity type is N-type, then the second conductivity type is P-type.

[0042] To achieve the above and other related objectives, the present invention also provides a power device comprising one or more power units as described above.

[0043] To achieve the above and other related objectives, the present invention also provides a high-voltage integrated circuit, including one or more power units as described above.

[0044] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0045] This invention connects the first well region and the second well region through a first doped region. When the power cell is turned on, the current path is the first metal layer, source region, first well region, first doped region, second well region, drain region, and second metal layer. Therefore, this invention optimizes the conduction current path of the power cell. Compared with the traditional JFET cell, this invention has a lower on-resistance, i.e., a higher current capability.

[0046] Furthermore, the current path of the present invention is close to the surface of the epitaxial layer, and the invention optimizes the conduction current path of the power cell. Compared with the traditional JFET cell, the present invention has a lower on-resistance, that is, a higher current capability.

[0047] Secondly, when the power cell is blocked, the gate lead-out region of the present invention can deplete the first doped region connecting the first well region and the second well region, thereby pinching off the conductive channel of the first doped region and disconnecting the current path; when the power cell is turned on, it can accumulate the carriers in the first well region, the first doped region connecting the first well region and the second well region, and the second well region, increasing the carrier concentration in the current path and further reducing the on-resistance of the power cell.

[0048] Furthermore, the first buried layer and cache doped layer below the drain of the present invention can improve the longitudinal breakdown of the device and enhance the breakdown voltage capability of the device; and the field plate of the power unit can play an auxiliary depletion role for the second well region, reduce the surface electric field of the device, effectively increase the effective doping concentration of the second well region, and maintain a sufficiently high breakdown voltage capability; and the second buried layer of the power unit can assist the depletion of the second well region when the power unit is turned off, thereby improving the breakdown voltage capability of the device.

[0049] In addition, the second well region of the present invention has an uneven morphology at the bottom near the first doped region, which can reduce the surface electric field of the power unit, effectively increase the effective doping concentration of the second well region, and maintain sufficient high voltage withstand capability.

[0050] Furthermore, the present invention provides a second doped region on the lower surface of the first doped region, which can deplete the first doped region connecting the first well region and the second well region when the device is turned off, effectively pinching off the conductive path of the device and reducing the reverse leakage current of the device; and the number of the first doped regions of the power unit can be multiple, each of which can connect the first well region and the second well region, providing an additional conductive path when the device is turned on and reducing the on-resistance of the device. Attached Figure Description

[0051] Figure 1 This is a schematic diagram of the structure and conduction current path of a traditional JFET cell;

[0052] Figure 2a This is a schematic diagram of the power unit structure according to Embodiment 1 of the present invention;

[0053] Figure 2b This is a schematic diagram of the conduction current path of the power unit in Embodiment 1 of the present invention;

[0054] Figure 3 This is a comparison diagram of the current capability of the power unit of Embodiment 1 of the present invention and a conventional JFET unit;

[0055] Figure 4 This is a schematic diagram of the power unit structure according to Embodiment 2 of the present invention;

[0056] Figure 5 This is a schematic diagram of the power unit structure according to Embodiment 3 of the present invention;

[0057] Figure 6 This is a schematic diagram of the power unit structure of Embodiment 4 of the present invention;

[0058] Figure 7 This is a schematic diagram of the power unit structure of Embodiment 5 of the present invention;

[0059] Figure 8 This is a schematic diagram of the power unit structure of Embodiment Six of the present invention;

[0060] Figure 9 This is a schematic diagram of the power unit structure of Embodiment 7 of the present invention;

[0061] Figure 10 This is a schematic diagram of the power unit structure of Embodiment 8 of the present invention;

[0062] Figure 11 This is a schematic diagram of the power unit structure of Embodiment 9 of the present invention. Detailed Implementation

[0063] Figure 1The structure of a conventional JFET cell is shown, which may include a semiconductor substrate 01 of the second conductivity type, an epitaxial layer 015, a doped buried layer 02 of the second conductivity type, a well region 03 of the first conductivity type, a doped region 04 of the second conductivity type, a fourth metal layer 011, a body region 05 of the second conductivity type, a first metal layer 012, a source region 06 of the first conductivity type, a second metal layer 014, a drain region 08 of the first conductivity type, an isolation dielectric layer 09, a third metal layer 013, and a gate lead-out region 07 of the second conductivity type. The well region 03 is located in the epitaxial layer 015; the doped buried layer 02 is located at the junction of the well region 03 and the epitaxial layer 015; the doped region 04 is located in the first well region 03; the body region 05 is located on the epitaxial layer 015, and the fourth metal layer 011 is shorted to the body region 05; the source region 06 is located on the well region 03, and the first metal layer 012 is shorted to the source region 06; the drain region 08 is located on the well region 03, and the second metal layer 014 is shorted to the drain region 08; the gate lead-out region 07 is located on the doped region 04, and the third metal layer 013 is shorted to the gate lead-out region 07; the isolation dielectric layer 09 is located on the epitaxial layer 015, the well region 03, and the doped region 04, and is used to separate the body region 05, the source region 06, the gate lead-out region 07, and the drain region 08.

[0064] Due to the obstruction of the doped region 04 below the gate lead-out region 07 in the traditional JFET cell, the current path can only bypass the bottom of the well region 03, resulting in a longer current path and higher on-resistance.

[0065] The power unit proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0066] Example 1:

[0067] Figure 2a This invention illustrates a power unit that may specifically include:

[0068] Semiconductor substrate 1 of the second conductivity type;

[0069] An epitaxial layer 21 of the second conductivity type is located on the semiconductor substrate 1;

[0070] A first well region 3 of a first conductivity type, a second well region 4 of a first conductivity type, and a first doped region 5 of a first conductivity type, wherein the first well region 3 and the second well region 4 extend from the surface of the epitaxial layer 21 into the epitaxial layer 21, the first well region 3 and the second well region 4 are spaced apart, and the first doped region 5 is located in the epitaxial layer 21 between the first well region 3 and the second well region 4.

[0071] An isolation dielectric layer 9 is located on the epitaxial layer 21, the first well region 3 and the second well region 4, and the isolation dielectric layer 9 is provided with a first opening and a second opening at intervals.

[0072] The source region 7 of the first conductivity type contacts the first well region 3 through the first opening of the isolation dielectric layer 9;

[0073] The drain region 8 of the first conductivity type contacts the second well region 4 through the second opening of the isolation dielectric layer 9;

[0074] A gate lead-out region 10, the projection of which is located between the source region 7 and the drain region 8, and the projection of which at least partially covers the first well region 3.

[0075] In this embodiment, the first conductivity type is preferably opposite to the second conductivity type. Specifically, if the first conductivity type is P-type, then the second conductivity type is N-type, or if the first conductivity type is N-type, then the second conductivity type is P-type. For example, when the first conductivity type is N-type and the second conductivity type is P-type, the power unit may include: a P-type semiconductor substrate, a P-type epitaxial layer, an N-type first well region, an N-type second well region, an N-type doped region, an N-type source region, an N-type drain region, an isolation dielectric layer, and a gate lead-out region.

[0076] The semiconductor substrate 1 in this embodiment can be a conventional substrate for a JFET cell or device, for example, the semiconductor substrate 1 of the second conductivity type can be a silicon substrate. The semiconductor substrate 1 is lightly doped, and the doping concentration can be referenced to that of the semiconductor substrate of a conventional JFET cell or device.

[0077] The epitaxial layer 21 can be a conventional epitaxial layer of a traditional JFET cell or device. The epitaxial layer 21 is lightly doped, and the doping concentration can be referenced to that of the epitaxial layer of a traditional JFET cell or device. The formation process of the epitaxial layer 21 is preferably a chemical deposition process, but is not limited thereto.

[0078] The doping concentration of the first well region 3 can be referenced to the doping concentration of the first well region in a conventional JFET cell or device. In this embodiment, the doping concentration of the second well region 4 is preferably the same as the doping concentration of the first well region 3. The width of the second well region 4 is preferably greater than the width of the first well region 3 to improve breakdown voltage. The doping concentration of the first doped region 5 is preferably greater than the doping concentration of the first well region 3; furthermore, the doping concentration of the first doped region 5 is preferably 10 times the doping concentration of the first well region 3. 2 ~10 3 In this embodiment, the first doped region 5 is heavily doped, which can reduce resistance. The first well region 3, the second well region 4, and the first doped region 5 in this embodiment can be formed using an ion implantation process.

[0079] The first doped region 5 extends from the first surface of the epitaxial layer 21 into the epitaxial layer 21, or the first doped region 5 is located within the epitaxial layer 21. A first distance exists between the first doped region 5 and the first surface of the epitaxial layer 21, and this first distance is greater than 0. The first surface of the epitaxial layer 21 is the surface of the epitaxial layer 21 furthest from the semiconductor substrate 1. When the first doped region 5 can extend from the first surface of the epitaxial layer 21 into the epitaxial layer 21, the isolation dielectric layer 9 is located on the epitaxial layer 21, the first well region 3, the first doped region 5, and the second well region 4. When the first doped region 5 is located within the epitaxial layer 21, the isolation dielectric layer 9 is located on the epitaxial layer 21, the first well region 3, and the second well region 4.

[0080] In this embodiment, there is one first doped region 5. The depth of the first doped region 5 in the epitaxial layer 21 is preferably less than the depth of the first well region 3 and the second well region 4 in the epitaxial layer 21, to facilitate depletion.

[0081] In this embodiment, the power unit connects the first well region 3 and the second well region 4 through the first doped region 5, and the entire structure (first doped region 5, first well region 3, and second well region 4) serves as the well region of the power unit. Therefore, when the power unit is turned on, the current path is: first metal layer 12, source region 7, first well region 3, first doped region 5, second well region 4, drain region 8, and second metal layer 14. The current path is close to the surface of the epitaxial layer (see reference). Figure 2b Compared to traditional JFET cells (i.e., traditional power cells), this invention has lower on-resistance, meaning it has higher current capability. (See also...) Figure 3 In this embodiment, the bottom morphology of the second well region 4 near the first doped region 5 is flat.

[0082] In this embodiment, the power unit further includes a body region 6 of a second conductivity type, the body region 6 being located on an epitaxial layer 21 of the second conductivity type, and the isolation dielectric layer 9 separating the body region 6, the source region 7, and the drain region 8. In this embodiment, a third opening is further provided on the isolation dielectric layer 9. The power unit may include a fourth metal layer 11, a body region 6, a first metal layer 12, a source region 7, a second metal layer 14, a drain region 8, a gate lead-out region 10, and a third metal layer 13. The body region 6 contacts the epitaxial layer 21 through the third opening of the isolation dielectric layer 9, and the body region 6 is shorted out through the fourth metal layer 11 as the body electrode. The source region 7 is located on the first well region 3, and the source region 7 is shorted out through the first metal layer 12 as the source electrode. The drain region 8 is located on the second well region 4, and the drain region 8 is shorted out through the second metal layer 14 as the drain electrode. The gate lead-out region 10 is located on the isolation dielectric layer 9 between the source region 7 and the drain region 8, and the gate lead-out region 10 is shorted out through the third metal layer 13 as the gate electrode. The position of the gate lead-out region 10 includes the following scenarios: First, the projection of the gate lead-out region 10 covers a portion of the first well region 3; Second, the projection of the gate lead-out region 10 covers a portion of the first well region 3 and at least a portion of the first doped region 5, i.e., the projection of the gate lead-out region 10 covers a portion of the first well region 3 and also covers a portion or all of the first doped region 5; Third, the projection of the gate lead-out region 10 covers a portion of the first well region 3 and also covers the first doped region 5 and a portion of the second well region 4. In this embodiment, the gate lead-out region 10 acts as a pinch-off, and the more it covers, the better the effect. That is, the effect is better when the projection of the gate lead-out region 10 covers a portion of the first well region, the first doped region 5, and a portion of the second well region 4.

[0083] In this embodiment, the gate can be connected to a positive potential, a negative potential, or ground, or shorted to the source, or controlled by a driving circuit alone. The gate lead-out region 10 in this embodiment can accumulate carriers in the first well region 3, the first doped region 5 connecting the first well region 3 and the second well region 4, and the second well region 4, further reducing the on-resistance of the power unit.

[0084] In this embodiment, the body region 6, source region 7, and drain region 8 are all heavily doped, specifically referring to the doping concentrations of the body, source, and drain regions in a traditional JFET cell or device. The materials of the fourth metal layer 11, the first metal layer 12, the second metal layer 14, and the third metal layer 13 may include metals or alloys. The material of the gate lead-out region 10 may be polysilicon.

[0085] In this embodiment, the material of the isolation dielectric layer 9 can be the same as that of the insulating dielectric layer of a conventional JFET cell or device, such as silicon oxide. The thickness of the isolation dielectric layer 9 can be the same as that of the insulating dielectric layer of a conventional JFET cell or device. The isolation dielectric layer 9 mainly serves an isolation function, separating the body region 6, the source region 7, and the drain region 8, that is, separating the body electrode, the source electrode, and the drain electrode. The shape of the isolation dielectric layer 9 at the first opening, the second opening, and the third opening is preferably bird beak shaped. In this embodiment, the thickness of the isolation dielectric layer 9 below the gate lead-out region 10 is equal to the thickness of the isolation dielectric layer 9 outside the gate lead-out region 10.

[0086] Continue reading Figure 2a The power unit may further include: a first buried layer 2 of a second conductivity type, located at the junction of the second well region 4 and the epitaxial layer 21. The first buried layer 2 is located below the drain electrode. The ion doping concentration of the first buried layer 2 is preferably greater than the doping concentration of the second well region 4, and can be specifically set according to process requirements. In this embodiment, the method for forming the first buried layer 2 may include:

[0087] An oxide layer and an epitaxial layer 21 are sequentially formed on the semiconductor substrate 1 using a deposition process;

[0088] A first well region 3, a second well region 4, and a first doped region 5 are formed in the epitaxial layer 21 using an ion implantation process;

[0089] An annealing process is performed, and the oxide layer diffuses outwards to form the first buried layer 2.

[0090] In this embodiment, the first buried layer 2 formed by the above method is distributed in the second well region 4, the epitaxial layer 21, and the semiconductor substrate 1.

[0091] When the first metal layer 12 is positively charged, the first doped region 5 connecting the first well region 3 and the second well region 4 will deplete each other with the semiconductor substrate 1. At the same time, the gate lead-out region 10 will also deplete the first doped region 5, eventually pinching off the first doped region 5, breaking the current path, and the power unit will bear the breakdown voltage through the depletion region of the second well region 4. Meanwhile, the first buried layer 2 on the lower surface of the second well region 4 below the drain can improve the longitudinal breakdown of the device.

[0092] Example 2:

[0093] This embodiment illustrates a second type of power unit. Please refer to... Figure 4Specifically, the power unit in this embodiment may include: a semiconductor substrate 1 of a second conductivity type, an epitaxial layer 21 of a second conductivity type, a first well region 3 of a first conductivity type, a second well region 4 of a first conductivity type, a first doped region 5 of a first conductivity type, a body region 6, a fourth metal layer 11, a source region 7, a first metal layer 12, a drain region 8, a second metal layer 14, an isolation dielectric layer 9, a gate lead-out region 10, a third metal layer 13, a first buried layer 2 of a second conductivity type, and a single-layer field plate 15. The power unit in this embodiment is provided with a single-layer field plate 15. When the power unit is reverse-biased, the single-layer field plate 15 can assist in the depletion of the second well region 4, reduce the surface electric field of the power unit, effectively increase the effective doping concentration of the second well region 4, and maintain sufficient high breakdown voltage capability.

[0094] The configuration of the semiconductor substrate 1, epitaxial layer 21, first well region 3, second well region 4, first doped region 5, body region 6, fourth metal layer 11, source region 7, first metal layer 12, drain region 8, second metal layer 14, isolation dielectric layer 9, gate lead-out region 10, third metal layer 13, and first buried layer 2 in this embodiment can be referred to in Embodiment 1, and will not be repeated here.

[0095] In this embodiment, the single-layer field plate 15 is located on the isolation dielectric layer 9 on the second well region 4, and between the gate lead-out region 10 and the drain region 8. The single-layer field plate 15 can be a polysilicon resistive field plate, a polysilicon floating field plate, or a metal field plate, but is not limited thereto. Further, the single-layer field plate 15 is preferably a polysilicon resistive field plate. The single-layer field plate 15 can be a plurality of concentric circle structures with different radii, and the concentric circle structures with different radii are connected together, or it can be a single spiral structure. For example, when the single-layer field plate 15 is a polysilicon resistive field plate, the single-layer field plate 15 is a single spiral structure.

[0096] Example 3:

[0097] This embodiment illustrates a third type of power unit. Please refer to... Figure 5Specifically, the power unit of this embodiment may include: a semiconductor substrate 1 of a second conductivity type, an epitaxial layer 21 of a second conductivity type, a first well region 3 of a first conductivity type, a second well region 4 of a first conductivity type, a first doped region 5 of a first conductivity type, a body region 6, a fourth metal layer 11, a source region 7, a first metal layer 12, a drain region 8, a second metal layer 14, an isolation dielectric layer 9, a gate lead-out region 10, a third metal layer 13, a first buried layer 2 of a second conductivity type, and a multilayer field plate 20. The power unit of this embodiment is provided with a multilayer field plate 20. When the power unit is reverse blocked, the multilayer field plate 20 can better assist in the depletion of the second well region 4, reduce the surface electric field of the device, effectively increase the effective doping concentration of the second well region 4, and maintain sufficient high breakdown voltage capability.

[0098] The configuration of the semiconductor substrate 1, epitaxial layer 21, first well region 3, second well region 4, first doped region 5, body region 6, fourth metal layer 11, source region 7, first metal layer 12, drain region 8, second metal layer 14, isolation dielectric layer 9, gate lead-out region 10, third metal layer 13, and first buried layer 2 in this embodiment can be referred to in Embodiment 1, and will not be repeated here.

[0099] The power unit in this embodiment employs a multi-layer field plate 20, for example... Figure 5 The double-layer field plate 20 is located on the isolation dielectric layer 9 on the second well region 4, and between the gate lead-out region 10 and the drain region 8. Each field plate can be a polysilicon resistive field plate, a polysilicon floating field plate, or a metal field plate, but is not limited to these. The multilayer field plate 20 includes multiple concentric circle structures, with a portion of adjacent field plates staggered and another portion of adjacent field plates overlapping, for example... Figure 5 The upper and middle layers of the field plates overlap and stagger with the lower layers on both sides below them to form parasitic capacitances. The radii of the multiple concentric circles in each layer of the multi-layered field plates 20 can be different.

[0100] Example 4:

[0101] This embodiment illustrates a fourth type of power unit, which can be combined with Figure 6Specifically, the power unit of this embodiment may include: a semiconductor substrate 1 of a second conductivity type, an epitaxial layer 21 of a second conductivity type, a first well region 3 of a first conductivity type, a second well region 4 of a first conductivity type, a first doped region 5 of a first conductivity type, a body region 6, a fourth metal layer 11, a source region 7, a first metal layer 12, a drain region 8, a second metal layer 14, an isolation dielectric layer 9, a gate lead-out region 10, a third metal layer 13, a first buried layer 2 of a second conductivity type, and a buffer doped layer 16 of a second conductivity type. The power unit of this embodiment is provided with a buffer doped layer 16 of a second conductivity type. When the power unit is reverse blocked, the first buried layer 2 with the buffer doped layer 16 can improve the longitudinal breakdown of the device and increase the breakdown voltage of the device. When the power unit includes a field plate, the field plate can play an auxiliary depletion role for the second well region 4, reduce the surface electric field of the device, effectively increase the effective doping concentration of the second well region 4, and maintain a sufficiently high breakdown voltage.

[0102] The arrangement of the semiconductor substrate 1, epitaxial layer 21, first well region 3, second well region 4, first doped region 5, body region 6, fourth metal layer 11, source region 7, first metal layer 12, drain region 8, second metal layer 14, isolation dielectric layer 9, gate lead-out region 10, third metal layer 13, and first buried layer 2 in this embodiment can refer to Embodiment 1, and will not be repeated here. The power unit in this embodiment may or may not have a field plate. If a single-layer field plate is used, the single-layer field plate arrangement in Embodiment 2 can be referred to; if multiple field plates are used, the multi-layer field plate arrangement in Embodiment 3 can be referred to. For example, Figure 6 The power unit includes a semiconductor substrate 1, an epitaxial layer 21, a first well region 3, a second well region 4, a first doped region 5, a body region 6, a fourth metal layer 11, a source region 7, a first metal layer 12, a drain region 8, a second metal layer 14, an isolation dielectric layer 9, a gate lead-out region 10, a third metal layer 13, a single-layer field plate 15, a first buried layer 2, and a buffer doped layer 16.

[0103] In this embodiment, the buffer doped layer 16 is disposed around the first buried layer 2, that is, the buffer doped layer 16 is disposed around the first buried layer 2. The doping concentration of the buffer doped layer 16 is preferably lower than that of the first buried layer 2 and higher than that of the second well region 4, that is, the doping concentration of the second well region 4, the buffer doped layer 16, and the first buried layer 2 has a gradual trend, so that the electric field is more uniform.

[0104] Example 5:

[0105] This embodiment illustrates a fifth type of power unit, which can be combined with Figure 7Specifically, the power unit of this embodiment may include: a semiconductor substrate 1 of a second conductivity type, an epitaxial layer 21 of a second conductivity type, a first well region 3 of a first conductivity type, a second well region 4 of a first conductivity type, a first doped region 5 of a first conductivity type, a body region 6, a fourth metal layer 11, a source region 7, a first metal layer 12, a drain region 8, a second metal layer 14, an isolation dielectric layer 9, a gate lead-out region 10, a third metal layer 13, a first buried layer 2 of a second conductivity type, and a second doped region 17 of a second conductivity type. The power unit of this embodiment is provided with a second doped region 17. When the power unit is reverse blocked, the second doped region 17 and the first doped region 5 can deplete each other, which can enhance the pinch-off effect on the first doped region 5, reduce the pinch-off voltage of the power unit, and reduce the reverse leakage current of the device.

[0106] The configuration of the semiconductor substrate 1, epitaxial layer 21, first well region 3, second well region 4, first doped region 5, body region 6, fourth metal layer 11, source region 7, first metal layer 12, drain region 8, second metal layer 14, isolation dielectric layer 9, gate lead-out region 10, third metal layer 13, and first buried layer 2 in this embodiment can refer to Embodiment 1, and will not be repeated here. The power unit in this embodiment may or may not have a field plate. If a single-layer field plate is used, the configuration of the single-layer field plate in Embodiment 2 can be referred to; if multiple field plates are used, the configuration of the multi-layer field plate in Embodiment 3 can be referred to. This embodiment may or may not have a buffer doped layer 16 of the second conductivity type. If a buffer doped layer 16 is used, the configuration of the buffer doped layer 16 in Embodiment 4 can be referred to. For example, Figure 7 The power unit includes a semiconductor substrate 1, an epitaxial layer 21, a first well region 3, a second well region 4, a first doped region 5, a body region 6, a fourth metal layer 11, a source region 7, a first metal layer 12, a drain region 8, a second metal layer 14, an isolation dielectric layer 9, a gate lead-out region 10, a third metal layer 13, a single-layer field plate 15, a first buried layer 2, a buffer doped layer 16, and a second doped region 17.

[0107] In this embodiment, the second doped region 17 is located on the lower surface of the first doped region 5 and is connected to the first well region 3 and the second well region 4. There is one second doped region 17 in this embodiment. The second doped region 17 and the first doped region 5 can be fabricated using the same photomask. The doping concentration of the second doped region 17 is greater than the doping concentration of the epitaxial layer 21. Because the doping concentration of the epitaxial layer 21 is relatively low, the first doped region 5 cannot be completely depleted by it. Increasing the doping concentration of the second doped region 17 allows for greater depletion of the first doped region 5, enhancing the pinch-off effect on the first doped region 5.

[0108] Example 6:

[0109] This embodiment illustrates a sixth type of power unit, which can be combined with Figure 8 Specifically, the power unit of this embodiment may include: a semiconductor substrate 1 of a second conductivity type, an epitaxial layer 21 of a second conductivity type, a first well region 3 of a first conductivity type, a second well region 4 of a first conductivity type, a first doped region 5 of a first conductivity type, a body region 6, a fourth metal layer 11, a source region 7, a first metal layer 12, a drain region 8, a second metal layer 14, an isolation dielectric layer 9, a gate lead-out region 10, a third metal layer 13, a first buried layer 2 of a second conductivity type, and a second buried layer 18 of a second conductivity type. The power unit of this embodiment is provided with a second buried layer 18. When the power unit is reverse-biased, the introduced second buried layer 18 can assist in the depletion of the second well region 4, increasing the device's breakdown voltage capability.

[0110] The configuration of the semiconductor substrate 1, epitaxial layer 21, first well region 3, second well region 4, first doped region 5, body region 6, fourth metal layer 11, source region 7, first metal layer 12, drain region 8, second metal layer 14, isolation dielectric layer 9, gate lead-out region 10, third metal layer 13, and first buried layer 2 in this embodiment can refer to Embodiment 1, and will not be repeated here. The power unit in this embodiment may or may not have a field plate. If a single-layer field plate is used, the configuration of the single-layer field plate in Embodiment 2 can be referred to; if multiple field plates are used, the configuration of the multi-layer field plate in Embodiment 3 can be referred to. This embodiment may or may not have a buffer doped layer 16. If a buffer doped layer 16 is used, the configuration of the buffer doped layer 16 in Embodiment 4 can be referred to. This embodiment may or may not have a second doped region 17 of a second conductivity type. If a second doped region 17 is used, the configuration of the second doped region 17 in Embodiment 5 can be referred to. For example... Figure 8 The power unit includes: a semiconductor substrate 1, an epitaxial layer 21, a first well region 3, a second well region 4, a first doped region 5, a body region 6, a fourth metal layer 11, a source region 7, a first metal layer 12, a drain region 8, a second metal layer 14, an isolation dielectric layer 9, a gate lead-out region 10, a third metal layer 13, a first buried layer 2, a single-layer field plate 15, a buffer doped layer 16, a second doped region 17, and a second buried layer 18.

[0111] In this embodiment, the second buried layer 18 of the power unit is located at the junction of the bottom of the second well region 4 near the first doped region 5 and the epitaxial layer 21. The doping concentration of the second buried layer 18 is preferably the same as the doping concentration of the buffer doped layer 16.

[0112] Example 7:

[0113] This embodiment illustrates a seventh power unit, which can be combined with Figure 9Specifically, the power unit of this embodiment may include: a semiconductor substrate 1 of a second conductivity type, an epitaxial layer 21 of a second conductivity type, a first well region 3 of a first conductivity type, a second well region 4 of a first conductivity type, a first doped region 5 of a first conductivity type, a body region 6, a fourth metal layer 11, a source region 7, a first metal layer 12, a drain region 8, a second metal layer 14, an isolation dielectric layer 9, a gate lead-out region 10, a third metal layer 13, a first buried layer 2 of a second conductivity type, and a second doped region 17 of a second conductivity type. The power unit of this embodiment has multiple first doped regions 5, the number of first doped regions 5 and second doped regions 17 are equal, or the number of first doped regions 5 is one more than the number of second doped regions 17, and the first doped regions 5 and second doped regions 17 are stacked alternately. During reverse blocking, the second doped region 17 and the upper first doped region 5 can mutually deplete each other, enhancing the pinch-off effect on the upper first doped region 5, reducing the pinch-off voltage of the device, and reducing reverse leakage current. The second doped region 17 will also mutually deplete with the lower first doped region 5, pinching off the lower first doped region 5. Meanwhile, when the power unit is turned on, the first doped region 5 below will form an additional channel, reducing the on-resistance of the power unit.

[0114] The configuration of the semiconductor substrate 1, epitaxial layer 21, first well region 3, second well region 4, body region 6, fourth metal layer 11, source region 7, first metal layer 12, drain region 8, second metal layer 14, isolation dielectric layer 9, gate lead-out region 10, third metal layer 13, and first buried layer 2 in this embodiment can be referred to in Embodiment 1, and will not be repeated here. The power unit in this embodiment may or may not have a field plate. If a single-layer field plate is used, the configuration of the single-layer field plate in Embodiment 2 can be referred to; if multiple field plates are used, the configuration of the multi-layer field plate in Embodiment 3 can be referred to. This embodiment may or may not have a buffer doped layer 16 of the second conductivity type. If a buffer doped layer 16 is used, the configuration of the buffer doped layer 16 in Embodiment 4 can be referred to. This embodiment may or may not have a second buried layer 18 of the second conductivity type. If a second buried layer 18 is used, the configuration of the second buried layer 18 in Embodiment 6 can be referred to.

[0115] In this embodiment, the number of first doped regions 5 is multiple, and the number of second doped regions 17 is one or more. The number of first doped regions 5 and second doped regions 17 is equal, or the number of first doped regions 5 is one more than the number of second doped regions 17. The first doped regions 5 and second doped regions 17 are stacked alternately. For example... Figure 8The power unit includes: a semiconductor substrate 1, an epitaxial layer 21, a first well region 3, a second well region 4, a first doped region 5, a body region 6, a fourth metal layer 11, a source region 7, a first metal layer 12, a drain region 8, a second metal layer 14, an isolation dielectric layer 9, a gate lead-out region 10, a third metal layer 13, a first buried layer 2, a single-layer field plate 15, a buffer doped layer 16, and a second doped region 17. There are two first doped regions 5, which are disposed on the upper and lower sides of the second doped region 17.

[0116] In this embodiment, the first doped region 5 of each layer can be the same or different, but is more preferably the same, and the first doped region 5 of each layer connects the first well region 3 and the second well region 4. The first doped region 5 of each layer can refer to the configuration of the first doped layer 5 in Embodiment 1. The depth of the first doped region 5 in the epitaxial layer 21 is preferably less than the depth of the first well region 3 and the second well region 4 in the epitaxial layer 21, so as to facilitate depletion.

[0117] The second doped region 17 in each layer can be the same or different, but is more preferably the same. The second doped region 17 in each layer can refer to the configuration of the second doped region 17 in Embodiment 5. The second doped region 17 and the first doped region 5 can be fabricated using the same photomask. The doping concentration of the second doped region 17 is greater than the doping concentration of the epitaxial layer 21.

[0118] Example 8:

[0119] This embodiment illustrates an eighth power unit, which can be combined with Figure 10 Specifically, the power unit of this embodiment may include: a semiconductor substrate 1 of a second conductivity type, an epitaxial layer 21 of a second conductivity type, a first well region 3 of a first conductivity type, a second well region 4 of a first conductivity type, a first doped region 5 of a first conductivity type, a body region 6, a fourth metal layer 11, a source region 7, a first metal layer 12, a drain region 8, a second metal layer 14, an isolation dielectric layer 9, a gate lead-out region 10, a third metal layer 13, and a first buried layer 2 of a second conductivity type. The bottom morphology of the second well region 4 near the first doped region 5 is uneven. The uneven bottom morphology of the second well region 4 near the first doped region 5 in the power unit of this embodiment can reduce the surface electric field of the power unit and increase the breakdown voltage of the power unit, which is equivalent to increasing the effective doping concentration of the second well region 4 while maintaining a sufficiently high breakdown voltage.

[0120] The configuration of the semiconductor substrate 1, epitaxial layer 21, first well region 3, second well region 4, first doped region 5, body region 6, fourth metal layer 11, source region 7, first metal layer 12, drain region 8, second metal layer 14, isolation dielectric layer 9, gate lead-out region 10, third metal layer 13, and first buried layer 2 in this embodiment can refer to Embodiment 1, and will not be repeated here. The power unit in this embodiment may or may not have a field plate. If a single-layer field plate is used, the configuration of the single-layer field plate in Embodiment 2 can be referred to; if a multi-layer field plate is used, the configuration of the multi-layer field plate in Embodiment 3 can be referred to. This embodiment may or may not have a buffer doped layer 16 of the second conductivity type. If a buffer doped layer 16 is used, the configuration of the buffer doped layer 16 in Embodiment 4 can be referred to. This embodiment may or may not have a second doped region 17 of the second conductivity type. If a second doped region 17 is used, the configuration of the second doped region 17 in Embodiment 5 can be referred to. For example... Figure 10 The power unit includes: a semiconductor substrate 1, an epitaxial layer 21, a first well region 3, a second well region 4, a first doped region 5, a body region 6, a fourth metal layer 11, a source region 7, a first metal layer 12, a drain region 8, a second metal layer 14, an isolation dielectric layer 9, a gate lead-out region 10, a third metal layer 13, a first buried layer 2, a single-layer field plate 15, a buffer doped layer 16, and a second doped region 17. The bottom of the second well region 4, which is close to the first doped region 5, has an uneven topography.

[0121] In this embodiment, the second well region 4, which has an uneven bottom morphology near the first doped region 5, can be formed by methods such as intermittent implantation.

[0122] Example 9:

[0123] This embodiment illustrates a ninth power unit, which can be combined with Figure 11 Specifically, the power unit of this embodiment may include: a semiconductor substrate 1 of a second conductivity type, an epitaxial layer 21 of a second conductivity type, a first well region 3 of a first conductivity type, a second well region 4 of a first conductivity type, a first doped region 5 of a first conductivity type, a body region 6, a fourth metal layer 11, a source region 7, a first metal layer 12, a drain region 8, a second metal layer 14, an isolation dielectric layer 9, a gate lead-out region 10, a third metal layer 13, and a first buried layer 2 of a second conductivity type. A step is formed on the isolation dielectric layer 9 below the gate lead-out region 10, meaning the thickness of the isolation dielectric layer 9 below the gate lead-out region 10 is less than the thickness of the isolation dielectric layers 9 outside the gate lead-out region 10. The thinner isolation dielectric layer 9 below the gate lead-out region 10 enhances the control effect of the gate lead-out region 10 on the first doped region 5 when the power unit is reverse-biased.

[0124] The configuration of the semiconductor substrate 1, epitaxial layer 21, first well region 3, first doped region 5, body region 6, fourth metal layer 11, source region 7, first metal layer 12, drain region 8, second metal layer 14, isolation dielectric layer 9, gate lead-out region 10, third metal layer 13, and first buried layer 2 in this embodiment can refer to Embodiment 1, and will not be repeated here. The power unit in this embodiment may or may not have a field plate. If a single-layer field plate is used, the configuration of the single-layer field plate in Embodiment 2 can be referred to; if multiple field plates are used, the configuration of the multi-layer field plate in Embodiment 3 can be referred to. This embodiment may or may not have a buffer doped layer 16 of the second conductivity type. If a buffer doped layer 16 is used, the configuration of the buffer doped layer 16 in Embodiment 4 can be referred to. This embodiment may or may not have a second doped region 17 of the second conductivity type. If a second doped region 17 is used, the configuration of the second doped region 17 in Embodiment 5 or 7 can be referred to. This embodiment can set the bottom morphology of the second well region 4 near the first doped region 5 to be flat or uneven. If it is set to be uneven, the configuration of the second well region 4 in Embodiment 8 can be referred to; if it is set to be flat, the configuration of the second well region 4 in Embodiment 1 can be referred to. This embodiment can provide a second buried layer 18 of a second conductivity type, or it can not provide a second buried layer 18 of a second conductivity type. If a second buried layer 18 is provided, the configuration of the second buried layer 18 in Embodiment 6 can be referred to. For example Figure 11 The power unit includes: a semiconductor substrate 1, an epitaxial layer 21, a first well region 3, a second well region 4, a first doped region 5, a body region 6, a fourth metal layer 11, a source region 7, a first metal layer 12, a drain region 8, a second metal layer 14, an isolation dielectric layer 9, a gate lead-out region 10, a third metal layer 13, a first buried layer 2, and a single-layer field plate 15. A step is formed on the isolation dielectric layer 9 below the gate lead-out region 10.

[0125] In this embodiment, the thickness of the isolation dielectric layer 9 on the lower surface of the gate lead-out region 10 is preferably less than 2 / 3 of the thickness of the isolation dielectric layer 9 at other locations (outside the gate lead-out region 10), and the thinner the better, as long as the isolation dielectric layer 9 is not broken down when a voltage is applied. Specifically, it can be set according to the voltage of the source and the gate.

[0126] In summary, the power unit provided by this invention connects the first well region and the second well region through the first doped region. When the power unit is turned on, the current path is the first metal layer, source region, first well region, first doped region, second well region, drain region, and second metal layer. The current path is close to the surface of the epitaxial layer. Therefore, this invention optimizes the conduction current path of the power unit and has a lower on-resistance.

[0127] This invention also provides a power device comprising one or more power units as described above (i.e., the power units in Embodiments 1 to 9). The power device is preferably a JFET device, but is not limited thereto. When the power device is turned on, the current path is: first metal layer, source region, first well region, first doped region, second well region, drain region, and second metal layer. The current path is close to the surface of the epitaxial layer. Therefore, this invention optimizes the on-current path of the power device, and compared to a traditional JFET device, the power device of this invention has a lower on-resistance.

[0128] Furthermore, the present invention also provides a high-voltage integrated circuit, which includes one or more power units as described above (i.e., the power units in Embodiments 1 to 9). When the integrated circuit is turned on, the current path is a first metal layer, a source region, a first well region, a first doped region, a second well region, a drain region, and a second metal layer. The current path is close to the surface of the epitaxial layer. Therefore, the high-voltage integrated circuit of the present invention has a lower on-resistance, which enables the high-voltage integrated circuit to have high current capability and high voltage withstand capability.

[0129] Furthermore, it is understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the scope of protection of the present invention.

[0130] Furthermore, it should be understood that the invention is not limited to the specific methods, compounds, materials, manufacturing techniques, uses, and applications described herein, which can vary. It should also be understood that the terminology described herein is used only to describe particular embodiments and not to limit the scope of the invention. It must be noted that the singular forms “a,” “an,” and “the” used herein and in the appended claims include plural bases unless the context clearly indicates otherwise. Thus, for example, a reference to “a step” means a reference to one or more steps, and may include secondary steps. All conjunctions used should be understood in the broadest sense. Therefore, the word “or” should be understood to have the definition of logical “or” rather than logical “exclusive”, unless the context clearly indicates otherwise. Structures described herein will be understood to also refer to functional equivalents of that structure. Language that can be interpreted as approximate should be understood in that way unless the context clearly indicates otherwise.

Claims

1. A power unit, characterized in that, include: Semiconductor substrate of the second conductivity type; An epitaxial layer of the second conductivity type is located on the semiconductor substrate; A first well region of a first conductivity type, a second well region of a first conductivity type, and a first doped region of a first conductivity type, wherein the first well region and the second well region extend from the surface of the epitaxial layer into the epitaxial layer, the first well region and the second well region are spaced apart, and the first doped region is located in the epitaxial layer between the first well region and the second well region. An isolation dielectric layer is located on the epitaxial layer, the first well region, and the second well region; the isolation dielectric layer is provided with a first opening and a second opening at intervals. The source region of the first conductivity type contacts the first well region through the first opening of the isolation dielectric layer; The drain region of the first conductivity type contacts the second well region through the second opening of the isolation dielectric layer; A gate lead-out region, the projection of which is located between the source region and the drain region, the projection of which at least partially covers the first well region.

2. The power unit as described in claim 1, characterized in that, The depth of the first doped region in the epitaxial layer is less than the depth of the first well region and the second well region in the epitaxial layer.

3. The power unit as described in claim 1, characterized in that, The first doped region extends from the first surface of the epitaxial layer into the epitaxial layer; the isolation dielectric layer is located on the epitaxial layer, the first well region, the first doped region, and the second well region, and the first surface of the epitaxial layer is the surface of the epitaxial layer away from the semiconductor substrate.

4. The power unit as described in claim 1, characterized in that, The first doped region is located in the epitaxial layer, and there is a first distance between the first doped region and the first surface of the epitaxial layer. The first surface of the epitaxial layer is the surface of the epitaxial layer that is away from the semiconductor substrate.

5. The power unit as described in claim 1, characterized in that, The projection of the gate lead-out region also covers at least a portion of the first doped region.

6. The power unit as described in claim 1, characterized in that, The projection of the gate lead-out region covers a portion of the first well region, the first doped region, and a portion of the second well region.

7. The power unit as claimed in claim 1, characterized in that, The width of the second well region is greater than the width of the first well region.

8. The power unit as claimed in claim 1, characterized in that, The power unit further includes a field plate located on an isolation dielectric layer on the second well region and between the gate lead-out region and the drain region.

9. The power unit as described in claim 8, characterized in that, The field plate can be a single-layer field plate or a multi-layer field plate.

10. The power unit as claimed in claim 9, characterized in that, The single-layer field plate includes multiple concentric circular structures with different radii, and the concentric circular structures with different radii are connected together.

11. The power unit as claimed in claim 9, characterized in that, The single-layer field plate comprises a single spiral structure.

12. The power unit as claimed in claim 9, characterized in that, The multi-layered field plate includes multiple concentric circular structures, with a portion of two adjacent field plates staggered and another portion of two adjacent field plates overlapping.

13. The power unit as claimed in claim 9, characterized in that, Each of the field plates comprises one of a polycrystalline silicon resistive field plate, a polycrystalline silicon floating field plate, or a metal field plate.

14. The power unit as claimed in claim 1, characterized in that, The power unit further includes a first buried layer of a second conductivity type, located at the junction of the second well region and the epitaxial layer.

15. The power unit as claimed in claim 14, characterized in that, The power unit further includes a buffer doped layer of a second conductivity type, which is disposed around the first buried layer.

16. The power unit as claimed in claim 1, characterized in that, The power unit further includes a second doped region of a second conductivity type, which is located on the lower surface of the first doped region and connected to the first well region and the second well region.

17. The power unit as claimed in claim 16, characterized in that, The doping concentration of the second doped region is greater than the doping concentration of the epitaxial layer.

18. The power unit as claimed in claim 16, characterized in that, The second doped region and the first doped region are fabricated using the same photomask.

19. The power unit as claimed in claim 16, characterized in that, There is one first doped region and one second doped region, with the second doped region located on the lower surface of the first doped region.

20. The power unit as claimed in claim 16, characterized in that, There are multiple first doped regions and multiple second doped regions, and the first doped regions and the second doped regions are stacked alternately on top of each other.

21. The power unit as claimed in claim 16, characterized in that, The number of the first doped region and the number of the second doped region are equal, or the number of the first doped region is one more than the number of the second doped region.

22. The power unit as claimed in claim 1, characterized in that, The source region is located on the first well region; the drain region is located on the second well region; and the gate lead-out region is located on the isolation dielectric layer between the source region and the drain region.

23. The power unit as claimed in claim 1, characterized in that, The power unit further includes a first metal layer, a second metal layer, and a third metal layer. The source region is shorted out through the first metal layer to serve as the source, the drain region is shorted out through the second metal layer to serve as the drain, and the gate lead-out region is shorted out through the third metal layer to serve as the gate.

24. The power unit as claimed in claim 1, characterized in that, The power unit further includes a body region of a second conductivity type and a fourth metal layer. A third opening is provided on the isolation dielectric layer. The body region contacts the epitaxial layer through the third opening of the isolation dielectric layer. The body region is shorted out through the fourth metal layer as the body electrode.

25. The power unit as claimed in claim 24, characterized in that, The isolation medium layer has a beak-shaped form at the first, second, and third openings.

26. The power unit as claimed in claim 1, characterized in that, The thickness of the isolation dielectric layer below the gate lead-out region is equal to the thickness of the isolation dielectric layer outside the gate lead-out region.

27. The power unit as claimed in claim 1, characterized in that, The thickness of the isolation dielectric layer below the gate lead-out region is less than the thickness of the isolation dielectric layer outside the gate lead-out region, and a step is formed on the isolation dielectric layer below the gate lead-out region.

28. The power unit as claimed in claim 1, characterized in that, The power unit further includes a second buried layer of a second conductivity type, located at the junction of the bottom of the second well region near the first doped region and the epitaxial layer.

29. The power unit as claimed in claim 1, characterized in that, The bottom morphology of the second well region near the first doped region is either flat or uneven.

30. The power unit as claimed in claim 29, characterized in that, The use of intermittent implantation results in an uneven bottom morphology of the second well region near the first doped region.

31. The power unit as claimed in claim 1, characterized in that, If the first conductivity type is P-type, then the second conductivity type is N-type; or, if the first conductivity type is N-type, then the second conductivity type is P-type.

32. A power device, characterized in that, It includes one or more power units as described in any one of claims 1 to 31.

33. A high-voltage integrated circuit, characterized in that, It includes one or more power units as described in any one of claims 1 to 31.

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