Method of fabricating an anti-latching semiconductor structure and semiconductor structure

Abstract

The application provides a preparation method of an anti-latch-up semiconductor structure and the semiconductor structure. The preparation method of the anti-latch-up semiconductor structure comprises the following steps: providing a semiconductor substrate, the semiconductor substrate has opposite first and second surfaces, and the first surface is used for preparing a semiconductor element; the semiconductor substrate is thinned as a whole from the second surface side to a first preset thickness, so as to remove a deep semiconductor substrate area which can generate charge diffusion and trigger a latch-up effect under the action of a single particle incidence; partial etching is performed on the thinned second surface, so as to form a groove structure; the groove top of the groove structure is located on the second surface; the distance between the groove bottom of the groove structure and the first surface is a second preset thickness; and the groove structure is filled with a low-stress material. The semiconductor structure provided by the application significantly reduces the triggering probability of the latch-up effect, while the mechanical integrity and subsequent process compatibility of the wafer are maintained.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing technology, and in particular to a method for preparing an anti-latch-up semiconductor structure and the semiconductor structure thereof. Background Technology

[0002] In standard CMOS processes, the N-well, P-type semiconductor substrate, and active region naturally form a pair of parasitic BJTs (one PNP and one NPN), connected end-to-end to form a PNPN structure similar to a silicon controlled rectifier (SCR). When subjected to external disturbances such as ESD or voltage overshoot, one BJT may be accidentally turned on, and its current becomes the base current of the other BJT, creating positive feedback. Once triggered, even if the disturbance disappears, both BJTs will remain on, forming a low-impedance short circuit between VDD and GND, triggering a large current. This is the latch-up effect, which can lead to chip malfunction or even burnout.

[0003] In existing technologies, the Czochralski (CZ) method is the mainstream process, offering low cost and the ability to produce large-size wafers. However, it contains many impurities (such as oxygen atoms), resulting in numerous defects within the wafer. To eliminate defects near the surface, a "denuded zone" is formed on the wafer surface. However, this layer is typically less than 50 μm thick, and the area beneath it is entirely defect-prone. When a single particle is incident, the resulting electron-hole pairs can reach depths exceeding 50 μm, penetrating deep into the defect region. Furthermore, the long lifetime and long diffusion of minority carriers make them prone to reaching the device region and causing latch-up.

[0004] Among existing technologies, the FZ method (floating zone melting) offers high purity, few defects, and inherently good latch-up resistance. However, it has extremely low yield and high price. 12-inch large-size wafers are more brittle and fragile, making it unaffordable for general consumer products. It is only used in special applications such as aerospace and nuclear physics. Summary of the Invention

[0005] This invention provides a method for fabricating an anti-latch-up semiconductor structure and a semiconductor structure. By removing deep defect regions and combining a low-stress material filling and support process, the charge collection volume and diffusion path generated by single-particle incident on the substrate are effectively reduced, significantly reducing the triggering probability of latch-up effect, while maintaining the mechanical integrity of the wafer and compatibility with subsequent processes.

[0006] In a first aspect, embodiments of the present invention provide a method for fabricating an anti-latch-up semiconductor structure, comprising: A semiconductor substrate is provided, the semiconductor substrate having opposing first and second surfaces, the first surface being used for fabricating semiconductor devices; The semiconductor substrate is thinned as a whole from the second surface side to the first preset thickness to remove the deep semiconductor substrate region that can generate charge diffusion and trigger latch-up effect under single-particle incident action. Partial etching is performed on the thinned second surface to form a groove structure; the top of the groove structure is located on the second surface; the distance between the bottom of the groove structure and the first surface is the second preset thickness; Low-stress material is filled into the groove structure.

[0007] Optionally, after filling the groove structure with a low-stress material, the following steps are also included: The filled second surface is then planarized.

[0008] Optionally, the first preset thickness is 100μm to 200μm.

[0009] Optionally, the second preset thickness is 40 μm to 60 μm.

[0010] Optionally, the area of ​​the groove structure accounts for 20% to 95% of the total area of ​​the second surface.

[0011] Optionally, partial etching is performed on the thinned second surface to form a groove structure with a second preset thickness, specifically including: Photoresist is coated onto the thinned second surface, and after exposure and development, a photoresist mask with a preset etching pattern is formed. Using a photoresist mask as an etching barrier layer, deep reactive ion etching is performed on the second surface to a depth corresponding to the second preset thickness, forming a groove structure.

[0012] Optionally, before performing overall thinning of the semiconductor substrate from the second surface side, the method further includes: The support carrier is bonded to the first surface side using a temporary bonding process. After the groove structure is filled with a low-stress material, the following is also included: Debond the support carrier from the semiconductor substrate and remove the support carrier.

[0013] In a second aspect, embodiments of the present invention also provide a semiconductor structure, prepared based on the preparation method of any of the latch-up-resistant semiconductor structures in the first aspect, wherein the semiconductor structure comprises: A semiconductor substrate has a first surface and a second surface disposed opposite to each other, the distance between the second surface and the first surface being a first preset thickness; the semiconductor substrate includes a groove structure; the top of the groove structure is located on the second surface; the distance between the bottom of the groove structure and the first surface is a second preset thickness; the groove structure is filled with a low-stress material; A semiconductor element located on the first surface of a semiconductor substrate.

[0014] Optionally, the first preset thickness is 100μm to 200μm.

[0015] Optionally, the second preset thickness is 40 μm to 60 μm.

[0016] This invention provides a method for fabricating an anti-latch-up semiconductor structure and a semiconductor mechanism. By thinning the semiconductor substrate to a first predetermined thickness, the deep semiconductor substrate region below the surface clean layer is removed, effectively reducing the charge collection volume and diffusion path generated by single-particle incident on the semiconductor substrate, and significantly reducing the probability of latch-up triggering. Furthermore, by etching and filling with a low-stress material, warping or fragmentation of the thinned wafer is prevented in subsequent processes, and its insulating properties further block the path of charge from the back side of the semiconductor substrate into the device region. The technical method and corresponding semiconductor structure of this invention significantly reduce the probability of latch-up triggering while maintaining the mechanical integrity of the wafer and compatibility with subsequent processes. Attached Figure Description

[0017] Figure 1 This is a schematic flowchart illustrating a method for fabricating an anti-latch-up semiconductor structure according to an embodiment of the present invention. Figure 2 and Figure 3 for Figure 1 A schematic diagram of the fabrication method of the latch-up-resistant semiconductor structure shown; Figure 4 and Figure 5 These are schematic diagrams of a groove structure provided in an embodiment of the present invention; Figure 6 A schematic flowchart illustrating another method for fabricating an anti-latch-up semiconductor structure provided in an embodiment of the present invention; Figure 7 This is a schematic flowchart illustrating another method for fabricating an anti-latch-up semiconductor structure provided in an embodiment of the present invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be fully described below with reference to the accompanying drawings in the embodiments of this invention, through specific implementation methods. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort fall within the protection scope of this invention.

[0019] Figure 1 This is a schematic flowchart illustrating a method for fabricating an anti-latch-up semiconductor structure according to an embodiment of the present invention. Figure 2 and Figure 3 for Figure 1The diagram illustrates the fabrication method of the anti-latch-up semiconductor structure. The anti-latch-up semiconductor structure fabrication method provided in this embodiment addresses the risk of single-event latch-up caused by deep defect regions in CZ-process silicon wafers. (Reference) Figure 1 The present invention provides a method for fabricating an anti-latch-up semiconductor structure, comprising: S110. A semiconductor substrate is provided, the semiconductor substrate having opposing first and second surfaces, the first surface being used to fabricate semiconductor elements.

[0020] The semiconductor substrate 100 can be understood as a base material used to prepare semiconductor devices, and it has a first surface 101 (device preparation surface) and a second surface 102 (back side) with opposite sides; the first surface 101 can be understood as the front side of the semiconductor substrate 100; the second surface 102 can be understood as the back side of the semiconductor substrate 100.

[0021] For details, please refer to Figure 2 A P-type single-crystal silicon wafer grown by the CZ method is provided as a semiconductor substrate, the semiconductor substrate having a first surface (front side) and a second surface (back side) opposite to each other, wherein the first surface has been completed or is to be used for the fabrication of semiconductor devices.

[0022] S120. The semiconductor substrate is thinned as a whole from the second surface side to a first preset thickness to remove the deep semiconductor substrate region that can generate charge diffusion and trigger latch-up effect under the action of single particle incident.

[0023] The first preset thickness h1 can be understood as the final total thickness of the semiconductor substrate 100 after overall thinning; the deep substrate region can be understood as the bulk defect region located below the surface clean layer in the CZ-grown silicon wafer. This region contains a large number of defects such as oxygen precipitates and dislocations. Electron-hole pairs generated by single-particle incident have a long minority carrier lifetime and a large diffusion length in this region, and are easy to enter the device region to trigger latch-up effect.

[0024] For details, please refer to Figure 3 Figure a) shows that the substrate is thinned from the second surface 102 side of the semiconductor substrate 100 by means of grinding or other methods, reducing the total thickness of the substrate from the initial thickness to a first preset thickness h1. In this process, the deep defect region located below the surface clean zone (approximately 50 μm) in the substrate is completely removed, reducing the risk of long-distance diffusion of charge in the defect region after single-particle incident.

[0025] S130. Partial etching is performed on the thinned second surface to form a groove structure; the top of the groove structure is located on the second surface; the distance between the bottom of the groove structure and the first surface is the second preset thickness.

[0026] The groove structure 110 can be understood as a recessed area formed by etching on the side of the second surface 102, with the top of the groove located on the second surface 102 and the distance between the bottom of the groove and the first surface 101 being the second preset thickness h2; the second preset thickness h2 can be understood as the remaining substrate thickness between the bottom of the groove structure 110 and the first surface 101.

[0027] For details, please refer to Figure 3 As shown in Figure b), a groove pattern is defined on the thinned second surface 102 using photolithography, and partial etching is performed to form a groove structure 110. The top of the groove structure 110 is flush with the thinned back surface, and the distance between the bottom of the groove and the first surface 101 is a second preset thickness h2, meaning that only one ultrathin silicon layer is retained directly below the device area. The unetched area retains the first preset thickness h1, providing mechanical support for the wafer.

[0028] S140. Fill the groove structure with low-stress material.

[0029] The low-stress material can be understood as an insulating or semi-insulating material filled in the groove structure 110, such as polyimide, benzocyclobutene BCB, spin-coated glass SOG, or low-stress silicon dioxide.

[0030] For details, please refer to Figure 3 As shown in Figure c), the groove structure 110 is filled with a low-stress material. Liquid polymer is coated onto the second surface 102 using a spin-coating process and then inserted into the groove structure 110, followed by thermosetting; alternatively, low-stress silicon oxide is filled using chemical vapor deposition. The filled low-stress material provides mechanical support, preventing warping or fragmentation of the thinned wafer in subsequent processes. Simultaneously, its insulating properties further block the path of charge from the back of the substrate into the device region.

[0031] This invention provides a method for fabricating an anti-latch-up semiconductor structure. By thinning the semiconductor substrate to a first predetermined thickness, the deep semiconductor substrate region below the surface clean layer is removed, effectively reducing the charge collection volume and diffusion path generated by single-particle incident charges in the semiconductor substrate, significantly lowering the probability of latch-up triggering. Furthermore, etching and filling with a low-stress material prevents warping or fragmentation of the thinned wafer in subsequent processes, while its insulating properties further block the path of charge from the back side of the semiconductor substrate into the device region. This invention significantly reduces the probability of latch-up triggering while maintaining the mechanical integrity of the wafer and compatibility with subsequent processes.

[0032] In a specific embodiment, referring to 2, the first surface 101101 of the semiconductor substrate 100100 also has the following structure: STI shallow trench isolation 1 (silicon dioxide insulating dielectric trench) for achieving electrical isolation between devices and preventing leakage or latch-up effects from propagating between adjacent transistors; N-well 2 and P-well 3, doped silicon regions formed by ion implantation process, for fabricating N-type MOSFETs and P-type MOSFETs, respectively; N+ heavily doped active region 4, as the source or drain region of the transistor, for providing a low-resistance ohmic contact interface, thereby fabricating lead-out metal electrodes to achieve electrical connection with external circuits.

[0033] In an optional embodiment, after filling the groove structure with a low-stress material, the method further includes planarizing the filled second surface.

[0034] Specifically, after the low-stress material filling is completed, the filling material usually overflows the groove structure 110 and covers the entire second surface 102, resulting in an uneven surface. At this point, the filled second surface 102 is planarized by using a polishing slurry and polishing pad to remove the excess filling material from the second surface 102 until the second surface 102 of the semiconductor substrate 100 is exposed. This ensures that the filling material in the groove is flush with the second surface 102 of the substrate, restoring the overall flatness of the wafer back side. After planarization, the second surface 102 obtains a flat surface morphology, providing good interface conditions for subsequent back-side metallization, annealing, bonding, or packaging processes. It also ensures the high consistency of the filling material within the groove, avoiding subsequent process problems caused by protrusions or depressions in the filling material.

[0035] In an optional embodiment, the first preset thickness h1 is 100 μm to 200 μm.

[0036] In an optional embodiment, the second preset thickness h2 is 40 μm to 60 μm.

[0037] Figure 4 and Figure 5 These are schematic diagrams of a groove structure provided in an embodiment of the present invention. In an optional embodiment, the area of ​​the groove structure 110 accounts for 20% to 95% of the total area of ​​the second surface 102.

[0038] Specifically, Figure 4 and Figure 5 Two optional groove structures 110 are shown. Figure 3The grooves are arranged in a grid array. The green areas in the figure are grooves filled with low-stress material after etching. The overall structure is a grid-like structure with horizontal and vertical crisscrosses, forming a periodic grid distribution on the back of the wafer. The light gray squares are the unetched and retained semiconductor substrate areas. The advantage of this pattern is that the stress distribution of the entire wafer is uniform and the support consistency of the substrate retention area is good. Figure 4 The grooves are concentric rings, with the green area being annular grooves filled with low-stress material. They are distributed in multiple concentric rings from the center of the wafer outwards. The light gray area between the rings is the preserved semiconductor substrate area. This pattern has a radially symmetrical structure, and the stress transitions evenly along the wafer radius, resulting in better control of wafer warpage.

[0039] Figure 6 This is a schematic flowchart illustrating another method for fabricating an anti-latch-up semiconductor structure provided in an embodiment of the present invention.

[0040] Regarding the above embodiment, "S130, partially etching is performed on the thinned second surface to form a groove structure; the top of the groove structure is located on the second surface; the distance between the bottom of the groove structure and the first surface is a second preset thickness" can be further refined as follows: Photoresist is coated onto the thinned second surface, and after exposure and development, a photoresist mask with a preset etching pattern is formed. Using a photoresist mask as an etching barrier layer, deep reactive ion etching is performed on the second surface to a depth corresponding to the second preset thickness, forming a groove structure.

[0041] like Figure 6 As shown, the refinement process includes the following steps: S210. A semiconductor substrate is provided, the semiconductor substrate having opposing first and second surfaces, the first surface being used to fabricate semiconductor elements.

[0042] S220. The semiconductor substrate is thinned as a whole from the second surface side to a first preset thickness to remove the deep substrate region in the semiconductor substrate that can generate charge diffusion and trigger latch-up effect under the action of single particle incident.

[0043] S231. Photoresist is coated on the thinned second surface, and after exposure and development, a photoresist mask with a preset etching pattern is formed.

[0044] The preset etching pattern can be understood as a mask pattern corresponding to the position and shape of the groove structure 110; the photoresist mask can be understood as the photoresist pattern area retained on the second surface 102 after exposure and development.

[0045] Specifically, after the overall thinning to the first preset thickness h1 is completed, a layer of photoresist is coated on the second surface 102 using a spin-coating process. The substrate coated with photoresist is placed in an exposure device, and ultraviolet exposure (or electron beam direct writing) is performed using a mask with a preset groove pattern. The diffraction or dissolution characteristics of the exposed area change. Subsequently, a development process is performed to remove the photoresist from the exposed area (positive photoresist) or the unexposed area (negative photoresist), forming a photoresist mask with a preset etching pattern on the second surface 102. This mask has windows at the locations where grooves are to be formed, exposing the substrate surface, while other areas remain covered and protected by photoresist.

[0046] S232. Using a photoresist mask as an etching barrier layer, perform deep reactive ion etching on the second surface to a depth corresponding to the second preset thickness to form a groove structure.

[0047] Deep reactive ion etching can be understood as a dry etching process with high anisotropy.

[0048] Specifically, using a photoresist mask as an etching barrier layer, the substrate is placed in a deep reactive ion etching (DRIE) apparatus to perform highly anisotropic etching on the silicon region exposed on the second surface 102. A Bosch process (alternating introduction of SF6 etching gas and C4F8 passivation gas) is employed to etch the silicon material downwards within the windowed area of ​​the photoresist mask. The etching depth is precisely controlled by online endpoint detection (such as optical emission spectroscopy monitoring or etching time control). Etching stops when the distance between the bottom of the trench and the first surface 101 reaches a second preset thickness h2, forming a trench structure 110 with vertical sidewalls.

[0049] S240, Fill the groove structure with low-stress material.

[0050] In an optional embodiment, a hard mask layer is deposited on the thinned second surface, the hard mask layer being a silicon oxide layer, a silicon nitride layer, or a stacked structure of silicon oxide and silicon nitride; Photoresist is coated on the surface of the hard mask layer, and after exposure and development, a photoresist mask with a preset etching pattern is formed. Using the photoresist mask as a cover, the hard mask layer is etched to transfer the preset etching pattern to the hard mask layer; Using the patterned hard mask layer as an etching barrier layer, deep reactive ion etching is performed on the second surface to etch to a depth corresponding to the second preset thickness, forming the groove structure.

[0051] The hard mask layer can be understood as an inorganic thin film formed on the second surface through chemical vapor deposition or thermal oxidation processes, such as silicon oxide (SiO2) or silicon nitride (SiN). x Or its stacked layers.

[0052] Specifically, after the overall thinning to the first preset thickness h1, a hard mask layer is first deposited on the second surface using plasma-enhanced chemical vapor deposition or thermal oxidation. Then, photoresist is coated onto the surface of the hard mask layer, and after exposure and development, a photoresist mask with a preset etching pattern is formed. Using the photoresist mask as a shield, reactive ion etching or wet etching is used to etch the hard mask layer, transferring the preset etching pattern to the hard mask layer, forming a patterned hard mask layer. Next, residual photoresist is removed by oxygen plasma ashing or a stripper. Finally, using the patterned hard mask layer as an etching barrier layer, deep reactive ion etching is performed on the second surface to a depth corresponding to the second preset thickness h2, forming a groove structure. Compared to photoresist masks, hard mask layers have a higher etching selectivity and can maintain pattern integrity during long-term, high-power etching processes, making them particularly suitable for fabricating groove structures requiring large etching depths and high pattern precision. Meanwhile, stacked hard masks can further reduce stress accumulation during the etching process, preventing mask cracking or peeling.

[0053] Figure 7 This is a schematic flowchart illustrating another method for fabricating an anti-latch-up semiconductor structure provided in an embodiment of the present invention.

[0054] Regarding the above embodiment, after "S110, providing a semiconductor substrate, the semiconductor substrate having opposing first and second surfaces, the first surface being used to fabricate a semiconductor element," the method further includes: The support carrier is bonded to the first surface side using a temporary bonding process. Furthermore, following "S140, filling the groove structure with low-stress material", it also includes: Debond the support carrier from the semiconductor substrate and remove the support carrier.

[0055] like Figure 7 As shown, the process includes the following steps: S310. A semiconductor substrate is provided, the semiconductor substrate having opposing first and second surfaces, the first surface being used to fabricate semiconductor elements.

[0056] S311, The support carrier is bonded to the first surface side by a temporary bonding process.

[0057] The supporting carrier can be understood as a rigid substrate.

[0058] Specifically, after providing the semiconductor substrate 100, a temporary bonding adhesive (such as photosensitive adhesive or thermoplastic adhesive) is first applied to its first surface 101 (the surface on which the semiconductor element has been fabricated or is to be fabricated). Then, a support carrier (such as a glass wafer or silicon wafer) is attached to the first surface 101. The bonding adhesive is cured by heating or ultraviolet curing, thus achieving bonding between the semiconductor substrate 100 and the support carrier. The support carrier is used to provide mechanical support for the semiconductor substrate in subsequent thinning, etching, and dielectric backfilling processes, compensating for insufficient structural strength of the thinned substrate and suppressing wafer warpage and breakage. S320. The semiconductor substrate is thinned as a whole from the second surface side to a first preset thickness to remove the deep substrate region in the semiconductor substrate that can generate charge diffusion and trigger latch-up effect under the action of single particle incident.

[0059] S330. Partial etching is performed on the thinned second surface to form a groove structure; the top of the groove structure is located on the second surface; the distance between the bottom of the groove structure and the first surface is a second preset thickness.

[0060] S340, Fill the groove structure with low-stress material.

[0061] S341. Debond the support carrier from the semiconductor substrate and remove the support carrier.

[0062] Specifically, after completing the low-stress material filling and subsequent planarization, the bonding adhesive is ablated by an appropriate debonding method, such as heating, ultraviolet light irradiation or laser scanning, to release the bond between the support carrier and the semiconductor substrate 100, and then the support carrier is removed.

[0063] refer to Figure 3 Figure c) shows that this embodiment of the invention also provides a semiconductor structure, prepared based on the method for preparing the anti-latch-up semiconductor structure of the above embodiments. The semiconductor structure includes: Semiconductor substrate 100 has a first surface 101 and a second surface 102 disposed opposite to each other, the distance between the second surface 102 and the first surface 101 being a first preset thickness h1; semiconductor substrate 100 includes a groove structure 110; the top of the groove structure 110 is located on the second surface 102; the distance between the bottom of the groove structure 110 and the first surface 101 is a second preset thickness h2; the groove structure 110 is filled with a low-stress material; a semiconductor element is located on the first surface 101 of semiconductor substrate 100.

[0064] Specifically, the semiconductor structure provided in this embodiment of the invention includes a semiconductor substrate 100 and a semiconductor element 200 located on its first surface 101. The semiconductor substrate 100 has a first surface 101 and a second surface 102 opposite to each other, and the distance between the second surface 102 and the first surface 101 is a first preset thickness h1 (e.g., 100 μm-200 μm). The semiconductor substrate 100 includes a groove structure 103, the top of which is located on the second surface 102, and the distance between the bottom of which is located on the first surface 101 is a second preset thickness h2 (e.g., 40 μm-60 μm). The groove structure 103 is filled with a low-stress material.

[0065] In one specific embodiment, a semiconductor element 200 is also formed on the first surface 101 of the semiconductor substrate 100. The semiconductor element 200 includes the following structures: a shallow trench isolation 1 (silicon dioxide insulating dielectric trench) for electrical isolation between devices to prevent leakage or latch-up propagation between adjacent transistors; an N-well 2 and a P-well 3, doped silicon regions formed by ion implantation, for fabricating N-type MOSFETs and P-type MOSFETs, respectively; and an N+ heavily doped active region 4, serving as the source or drain region of the transistor, for providing a low-resistance ohmic contact interface, thereby fabricating lead-out metal electrodes to achieve electrical connection with external circuits. When high-energy particles (such as protons and heavy ions) are incident on the semiconductor substrate 100, a large number of electron-hole pairs are generated in the substrate. Because the trench structure 103 thins the substrate directly below the device region to a second preset thickness h2 (40μm-60μm), and the trench is filled with an insulating low-stress material, the collection volume and diffusion path of charge in the substrate are significantly limited. Meanwhile, the STI shallow trench isolation 1 and the well structure (N-well 2, P-well 3) further restrict the lateral diffusion of charge carriers, making it difficult for the charge generated by single-particle incident to reach the active region of the device (N+ heavily doped active region 4) to trigger the latch-up effect, thereby effectively improving the latch-up resistance of integrated circuits in the radiation environment.

[0066] Optionally, the first preset thickness h1 is 100μm to 200μm. This thickness range ensures that the substrate has sufficient mechanical strength to support the semiconductor device 200 and subsequent process operations, while being significantly thinner than the original CZ silicon wafer (approximately 700μm-800μm), removing most of the deep defect areas.

[0067] Optionally, the second preset thickness h2 is 40 μm to 60 μm (e.g., 50 μm). This thickness range retains a sufficient silicon layer directly below the device region to maintain device performance, while allowing the charge generated by a single particle to recombine or be collected before reaching the device region, significantly weakening the latch-up triggering condition.

[0068] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A method for fabricating an anti-latch-up semiconductor structure, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate having opposing first and second surfaces, the first surface being used for fabricating semiconductor elements; The semiconductor substrate is thinned as a whole from the second surface side to a first preset thickness to remove the deep semiconductor substrate region that can generate charge diffusion and trigger latch-up effect under single-particle incident action. Partial etching is performed on the thinned second surface to form a groove structure; The top of the groove structure is located on the second surface; the distance between the bottom of the groove structure and the first surface is a second preset thickness; The groove structure is filled with a low-stress material.

2. The method for preparing the anti-latch-up semiconductor structure according to claim 1, characterized in that, After filling the groove structure with a low-stress material, the method further includes: The second surface after filling is planarized.

3. The method according to claim 1, characterized in that, The first preset thickness is 100μm to 200μm.

4. The method according to claim 1, characterized in that, The second preset thickness is 40μm to 60μm.

5. The method for preparing the anti-latch-up semiconductor structure according to claim 1, characterized in that, The area of ​​the groove structure accounts for 20% to 95% of the total area of ​​the second surface.

6. The method for fabricating the anti-latch-up semiconductor structure according to claim 1, characterized in that, Partial etching is performed on the thinned second surface to form a groove structure of a second predetermined thickness, specifically including: Photoresist is coated onto the thinned second surface, and after exposure and development, a photoresist mask with a preset etching pattern is formed. Using the photoresist mask as an etching barrier layer, deep reactive ion etching is performed on the second surface to a depth corresponding to the second preset thickness, forming the groove structure.

7. The method for preparing the anti-latch-up semiconductor structure according to claim 1, characterized in that, Before the overall thinning of the semiconductor substrate from the second surface side, the method further includes: A support carrier is bonded to the first surface side using a temporary bonding process; After the groove structure is filled with a low-stress material, the following is also included: The bond between the support carrier and the semiconductor substrate is released, and the support carrier is removed.

8. A semiconductor structure, characterized in that, The semiconductor structure is prepared according to the method for preparing the anti-latch-up semiconductor structure according to any one of claims 1-7, wherein the semiconductor structure comprises: A semiconductor substrate having a first surface and a second surface disposed opposite to each other, the distance between the second surface and the first surface being a first preset thickness; the semiconductor substrate includes a groove structure; the top of the groove structure is located on the second surface; the distance between the bottom of the groove structure and the first surface is a second preset thickness; the groove structure is filled with a low-stress material; A semiconductor element is located on the first surface of the semiconductor substrate.

9. The semiconductor structure according to claim 8, characterized in that, The first preset thickness is 100μm to 200μm.

10. The semiconductor structure according to claim 8, characterized in that, The second preset thickness is 40μm to 60μm.

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