A back contact solar cell and a method of manufacturing the same

Abstract

The present application relates to a kind of back contact solar cell and its preparation method.Therein back contact solar cell includes: silicon substrate, the back light surface of silicon substrate includes first area, second area and interval area;First doped layer is arranged in first area;Second doped layer, including set in the middle part of second area and set in the end of interval area, the end of second doped layer includes first part close to its middle part and second part away from its middle part;Second doped layer includes intrinsic hydrogenated amorphous silicon layer and second doped silicon layer, which are sequentially stacked from the back light surface of silicon substrate outward;Conductive layer, set to the side of first doped layer and second doped layer away from silicon substrate, and the first part of the end of second doped layer is not covered by conductive layer;The doping concentration of active doping atoms of the first part of the end of second doped silicon layer is higher than the doping concentration of active doping atoms of its middle part.The solar cell can keep stable performance during long-term use.

Description

Technical Field

[0001] This application relates to the field of solar cell technology, and in particular to a back-contact solar cell and its fabrication method. Background Technology

[0002] With the global energy structure shifting towards clean energy, crystalline silicon solar cells, as the core component of the photovoltaic industry, have always had their conversion efficiency and stability as the core directions of technological research and development. Among them, back-contact (BC) solar cells, by placing both positive and negative electrodes on the back side of the cell, completely eliminate the obstruction of incident light by the front grid lines, significantly improving photon utilization. Hybrid back-contact cells, on the other hand, refer to cells fabricated by applying different types of passivation contact technologies to the back side of the back-contact cell through hybrid design, overcoming the performance limitations of single passivation or contact structures, thereby improving photoelectric conversion efficiency. The back side of this type of cell typically has alternating regions of different polarities, and these different polarity regions employ differentiated layer structures.

[0003] The core design principle of current mainstream hybrid back-contact battery structures is to achieve efficient carrier extraction through partitioned passivation contacts. Taking an n-type silicon substrate as an example, the back side of the silicon substrate includes alternating n-type and p-type conductive regions, as well as a spacer region between the n-type and p-type conductive regions. In the n-type conductive region, a stacked structure of silicon oxide and phosphorus-doped polycrystalline silicon layers is used, utilizing the tunneling effect and passivation contacts to reduce carrier recombination. In the p-type conductive region, an intrinsic hydrogenated amorphous silicon layer and a boron-doped silicon layer are used to construct selective carrier channels. Carrier collection is then achieved through a conductive layer (e.g., a transparent conductive oxide (TCO) layer) and a metal electrode, achieving a breakthrough in efficiency. The spacer region further includes a first sub-spacer region near the n-type conductive region and a second sub-spacer region near the p-type conductive region. The silicon oxide and phosphorus-doped polycrystalline silicon layers extend to the first sub-spacer region, while the intrinsic hydrogenated amorphous silicon and boron-doped silicon layers extend to the second sub-spacer region and the first sub-spacer region. In the first sub-spacer region, the silicon oxide layer, the phosphorus-doped polycrystalline silicon layer, the intrinsic hydrogenated amorphous silicon layer, and the boron-doped silicon layer are stacked sequentially from the inside to the outside, and the conductive layer is disconnected at least in the first sub-spacer region.

[0004] The aforementioned back-contact solar cells will experience power degradation after prolonged use. Summary of the Invention

[0005] To solve the above-mentioned technical problems, this application provides a back-contact solar cell and a method for its fabrication, specifically including the following technical solutions.

[0006] On one hand, this application provides a back-contact solar cell, comprising: A silicon substrate includes a light-receiving surface and a back-lighting surface disposed opposite to each other. The back-lighting surface includes an alternately distributed first region and a second region, and a gap region located between adjacent first and second regions. The first doped layer includes a middle portion disposed in the first region and an end portion disposed in the spacer region. The first doped layer includes a silicon oxide layer and a first doped silicon layer sequentially stacked from the backlight surface of the silicon substrate outward. The second doped layer includes a middle portion disposed in the second region and an end portion disposed in the spacer region. The end portion of the second doped layer includes a first portion close to the middle portion and a second portion away from the middle portion. The second doped layer includes an intrinsic hydrogenated amorphous silicon layer and a second doped silicon layer sequentially stacked from the backlight surface of the silicon substrate outward. A conductive layer is disposed on the side of the first doped layer and the second doped layer away from the silicon substrate, and a first portion of the end of the second doped layer is not covered by the conductive layer. The electrode is located on the side of the conductive layer away from the silicon substrate; The doping concentration of active doped atoms in the first part of the end of the second doped silicon layer is higher than that in the middle part.

[0007] In one embodiment, the microstructure of the first portion at the end of the second doped silicon layer is amorphous or partially crystalline, and the microstructure of the middle portion of the second doped silicon layer is amorphous.

[0008] In one embodiment, the crystallization rate of the partially crystallized state is 5-68%.

[0009] In one embodiment, the crystallization rate of the partially crystallized state is 10-50%.

[0010] In one embodiment, the crystallization rate of the partially crystallized state is 20-40%.

[0011] In one embodiment, when the microstructure of the first portion at the end of the second doped silicon layer is amorphous, the microstructure is between 476 and 484 cm⁻¹. -1 The wavenumber positions show characteristic Raman peaks, and when the microstructure at the end of the second doped silicon layer is in a partially crystalline state, these peaks are observed at 476–484 cm⁻¹. -1 and 506~523cm -1 Wavenumber positions show characteristic Raman peaks; the middle part of the second doped silicon layer is at 476~484 cm⁻¹. -1 Wavenumber position reveals characteristic Raman peaks.

[0012] In one embodiment, the first doped silicon layer has the same conductivity type as the silicon substrate, and the second doped silicon layer has the opposite conductivity type to the silicon substrate.

[0013] In one embodiment, the silicon substrate is an n-type silicon substrate.

[0014] In one embodiment, the first doped silicon layer is a phosphorus-doped silicon layer.

[0015] In one embodiment, the second doped silicon layer is a boron-doped silicon layer.

[0016] In one embodiment, the active boron content of the first portion at the end of the second doped silicon layer is 8 × 10⁻⁶. 18 ~1×10 21 atoms / cm 3 The active boron content in the middle of the second doped silicon layer is 1×10⁻⁶. 17 ~7×10 18 atoms / cm 3 .

[0017] In one embodiment, a first portion of the end of the second doped layer is disposed directly on the silicon substrate, and at least a portion of the second portion of the end of the second doped layer covers the end of the first doped layer.

[0018] In one embodiment, the second portion at the end of the second doped silicon layer has the same microstructure as the middle portion of the second doped silicon layer.

[0019] In one embodiment, a second portion of the end of the second doped silicon layer also has a region not covered by the conductive layer.

[0020] In one embodiment, the concentration of active doped atoms in the region of the first portion of the middle part of the second doped silicon layer near its end is higher than the concentration in other regions of the middle part.

[0021] In one embodiment, the doping concentration of active doped atoms in the region of the first portion near the end of the middle portion of the second doped silicon layer is the same as the doping concentration of active doped atoms in the first portion at the end of the second doped silicon layer.

[0022] On the other hand, this application provides a method for fabricating a back-contact solar cell, comprising the following steps: Step 1: Provide a silicon substrate, the silicon substrate including a light-receiving surface and a back-lighting surface disposed opposite to each other, the back-lighting surface including an alternately distributed first region and a second region, and a gap region located between adjacent first regions and second regions; Step 2: Forming a first doped layer in the first region, including the following steps: A silicon oxide layer and a first doped silicon layer are sequentially formed on a first region of the back surface of a silicon substrate; The backlight surface of the silicon substrate is removed from the first doped silicon layer and silicon oxide layer located in the second region; Step 3: Forming a second doped layer in the second region, including the following steps: An intrinsic hydrogenated amorphous silicon layer and a second doped silicon layer are sequentially formed on the back side of a silicon substrate; Increase the doping concentration of active doped atoms in at least a portion of the second doped silicon layer corresponding to the spacer region; Remove the second doped silicon layer and the intrinsic hydrogenated amorphous silicon layer located in the first region of the backlight surface of the silicon substrate; Step 4: Prepare a conductive layer on the back surface of the silicon substrate, and remove at least the portion of the conductive layer corresponding to the second doped silicon layer with a high concentration of active doped atoms. Step 5: Fabricate an electrode on the side of the conductive layer that is away from the silicon substrate.

[0023] In one embodiment, increasing the doping concentration of active doped atoms in at least a portion of the second doped silicon layer corresponding to the spacer region includes: Annealing is performed by scanning at least a portion of the second doped silicon layer corresponding to the spacer region using a first laser. The first laser has a wavelength of 530~535nm, a power of 7.5~8.0W, a scanning speed of 35~45m / s, a spot diameter of 140~160μm, and a penetration depth of 1~5μm.

[0024] In one embodiment, increasing the doping concentration of active doped atoms in at least a portion of the second doped silicon layer corresponding to the spacer region includes: A doped atomic film is formed on the second doped silicon layer. A second laser is used to scan at least a portion of the second doped silicon layer corresponding to the portion of the spacer region corresponding to the doped atomic film, and then the doped atomic film is removed. The wavelength of the second laser is 530~535nm, the power is 30~35W, the scanning speed is 35~45m / s, the spot diameter is 140~160μm, and the penetration depth is 1~5μm.

[0025] In one embodiment, the second doped silicon layer is a boron-doped silicon layer, and the film layer containing doped atoms is a boron-containing film layer; In one embodiment, the thickness of the boron-containing film is 30~200 nm; In one embodiment, the mass percentage of boron in the boron-containing film is 2-15%; In one embodiment, the method for preparing the boron-containing film includes: deposition using a mixture of silane, diborane, and oxygen as reactants, at a deposition temperature of 160-230°C, for a deposition time of 500-600 s.

[0026] The present invention has at least one of the following beneficial effects: In the back-contact solar cell provided in this embodiment of the invention, the doping concentration of active doped atoms in the first part of the end of the second doped silicon layer not covered by the conductive layer is higher than that in the middle part of the second doped silicon layer. This reduces the defect density in the first part of the end of the second doped silicon layer, improves the acid and alkali resistance of the surface of the first part of the end of the second doped silicon layer, and keeps the performance of the solar cell stable during long-term use. Attached Figure Description

[0027] Figure 1 This is a flowchart of a back-contact solar cell fabrication method in one embodiment; Figure 2 This is a schematic diagram of the battery structure during the fabrication process of a back-contact solar cell in one embodiment; Figure 3 This is a schematic diagram of the battery structure during the fabrication process of a back-contact solar cell in one embodiment; Figure 4 This is a schematic diagram of the battery structure during the fabrication process of a back-contact solar cell in one embodiment; Figure 5 This is a schematic diagram of the battery structure during the fabrication process of a back-contact solar cell in one embodiment; Figure 6 This is a schematic diagram of the battery structure during the fabrication process of a back-contact solar cell in one embodiment; Figure 7 This is a schematic diagram of the battery structure during the fabrication process of a back-contact solar cell in one embodiment; Figure 8 This is a schematic diagram of the battery structure during the fabrication process of a back-contact solar cell in one embodiment; Figure 9 This is a schematic diagram of the battery structure during the fabrication process of a back-contact solar cell in one embodiment; Figure 10 This is a schematic diagram of the battery structure during the fabrication process of a back-contact solar cell in one embodiment; Figure 11 This is a schematic diagram of the battery structure during the fabrication process of a back-contact solar cell in one embodiment; Figure 12 This is a schematic diagram of the battery structure during the fabrication process of a back-contact solar cell in one embodiment; Figure 13 This is a schematic diagram of the battery structure during the fabrication process of a back-contact solar cell in one embodiment; Figure 14 This is a schematic diagram of the structure of a back-contact solar cell in one embodiment.

[0028] Reference numerals: 1. Silicon substrate; 2. Silicon oxide layer; 3. Polycrystalline silicon film; 4. First doped silicon layer; 5. Protective layer; 6. Electrode; 7. First region; 8. Second region; 9. Passivation layer; 10. Antireflection layer; 11. Intrinsic hydrogenated amorphous silicon layer; 12. Second doped silicon layer; 13. Conductive layer; 14. Doped atomic film layer. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description, in conjunction with the accompanying drawings and embodiments, is provided. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0030] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0031] The structures, proportions, sizes, etc., shown in the accompanying drawings of this specification are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size, without affecting the effects and objectives that the present invention can produce, should still fall within the scope of the technical content disclosed in the present invention.

[0032] The orientations or positional relationships indicated by terms such as "middle," "inner," and "outer" in this specification are based on the orientations or positional relationships shown in the accompanying drawings and are only for the purpose of simplifying the description. They are not intended to indicate or imply that the structure referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as limiting the present invention.

[0033] As described in the background section, the electric field strength at the boundary between the n-type and p-type conductive regions of traditional hybrid back-contact batteries is relatively weak, limiting their ability to capture and transport minority carriers (holes) generated in the n-type region. Especially during lateral carrier transport, insufficient concentration gradients easily lead to recombination losses, directly causing a decrease in the battery's fill factor (FF) and short-circuit current (Jsc), making it difficult to fully utilize the efficiency advantages of the back-contact structure, resulting in insufficient carrier extraction efficiency at the boundary between the n-type and p-type conductive regions.

[0034] Furthermore, in the intercalation region, some boron-doped silicon layers lack a conductive layer. This area is exposed to the external environment for extended periods, resulting in a high defect state density and poor acid and alkali resistance. During long-term use of the solar cell, this region is prone to interface degradation, leading to long-term power decay.

[0035] To address the above problems, this invention provides a back-contact solar cell and its fabrication method.

[0036] The active dopant atoms described in this application refer to dopant atoms that participate in the semiconductor's conductivity process by being incorporated into silicon. These active dopant atoms exist in a substitutional configuration (occupying lattice sites of silicon atoms) and can generate charge carriers. For example, p-type dopant atoms such as boron, aluminum, gallium, and indium can generate holes after being incorporated into silicon; n-type dopant atoms such as phosphorus, arsenic, antimony, and bismuth can generate electrons after being incorporated into silicon.

[0037] The following detailed description, in conjunction with the accompanying drawings, illustrates a back-contact solar cell and its fabrication method provided by the present invention.

[0038] This application provides a back-contact solar cell, comprising: The silicon substrate 1 includes a light-receiving surface and a back-lighting surface disposed opposite to each other. The back-lighting surface includes an alternately distributed first region 7 and a second region 8, and a spacer region located between adjacent first regions 7 and second regions 8. The first doped layer includes a middle portion disposed in the first region 7 and an end portion disposed in the spacer region; the first doped layer includes a silicon oxide layer 2 and a first doped silicon layer 4 sequentially stacked from the backlight surface of the silicon substrate 1 outward. The second doped layer includes a middle portion disposed in the second region 8 and an end portion disposed in the spacer region. The end portion of the second doped layer includes a first portion close to the middle portion and a second portion away from the middle portion. The second doped layer includes an intrinsic hydrogenated amorphous silicon layer 11 and a second doped silicon layer 12 sequentially stacked from the backlight surface of the silicon substrate 1 outward. The conductive layer 13 is disposed on the side of the first doped layer and the second doped layer away from the silicon substrate 1, and the first portion of the end of the second doped layer does not cover the conductive layer 13. Electrode 6 is disposed on the side of conductive layer 13 away from silicon substrate 1; The doping concentration of active doped atoms in the first part of the end of the second doped silicon layer 12 is higher than that of active doped atoms in the middle part.

[0039] Specifically, the silicon substrate 1 can be an electron-type (n-type) silicon substrate, such as a silicon substrate doped with elements such as phosphorus, arsenic, antimony, or bismuth. It can also be a hole-type (p-type) silicon substrate, such as a silicon substrate doped with elements such as boron, aluminum, gallium, or indium. In other embodiments, the silicon substrate 1 can be a monocrystalline silicon substrate or a polycrystalline silicon substrate. The silicon substrate 1 can be in the form of a sheet, and its light-receiving surface and backlighting surface can be square or rectangular.

[0040] The conductivity type of the first region 7 can be the same as that of the silicon substrate 1. Correspondingly, the conductivity type of the first doped silicon layer 4 disposed on the first region 7 is the same as that of the silicon substrate 1. The conductivity type of the second region 8 is opposite to that of the silicon substrate 1. Correspondingly, the conductivity type of the second doped silicon layer 12 disposed on the second region 8 is opposite to that of the silicon substrate 1. When the silicon substrate 1 is an n-type silicon substrate, the first doped silicon layer 4 is an n-type doped silicon layer, specifically a phosphorus-doped polycrystalline silicon layer; the second doped silicon layer 12 is a p-type doped silicon layer, specifically a boron-doped amorphous silicon layer. In the conventional preparation process of boron-doped silicon layers, not all the doped boron atoms can participate in the semiconductor's conductivity process: some boron atoms exist in a substitutional configuration (occupying lattice sites of silicon atoms). These are active boron atoms, capable of accepting electrons and generating holes, which are the core of achieving p-type conductivity.

[0041] Another portion of boron atoms exist interstitially (filling the gaps in the silicon lattice) or form boron clusters or compounds (such as B-Si and BO bonds). These are inactive boron atoms and cannot participate in electrical processes. In other words, after deposition, the total boron content of the boron-doped silicon layer is fixed, but the content of active boron atoms is much lower than the total boron content, resulting in a large amount of inactive boron.

[0042] The conductive layer 13 can be a transparent conductive oxide layer (TCO), which can be at least one of indium tin oxide, fluorine-doped tin oxide, aluminum-doped zinc oxide, gallium-doped zinc oxide, or indium zinc oxide. The electrode 6 can be a silver paste electrode.

[0043] The silicon oxide layer 2 serves to passivate the silicon substrate 1, and it also allows charge carriers to tunnel through the silicon oxide layer 2 to reach the first doped silicon layer 4. The intrinsic hydrogenated amorphous silicon layer 11 also serves to passivate the silicon substrate 1, and it also allows charge carriers to tunnel through the silicon oxide layer 2 to reach the second doped silicon layer 12.

[0044] In this embodiment, the first region 7, the second region 8, and the spacer region can all be elongated strips, and their length directions can be aligned in the same direction. Multiple first regions 7 and multiple second regions 8 can be arranged alternately along a direction perpendicular to their length direction. For example, the length directions of the first region 7, the second region 8, and the spacer region can be parallel to a set of opposite edges of the backlight surface of the silicon substrate 1, and multiple first regions 7 and multiple second regions 8 can be arranged alternately along a direction parallel to another set of opposite edges of the backlight surface of the silicon substrate 1.

[0045] It is understandable that for the entire back-contact solar cell, the second region 8 located in the middle area has a spacer region and a first region 7 on both sides. However, when the second region 8 is located at the edge of the solar cell, only the side closest to the middle area of ​​the solar cell has a spacer region and a first region 7. That is, the second doped silicon layer 12 located in the middle area of ​​the solar cell has two ends; while the second doped silicon layer 12 located at the edge of the solar cell has only one end.

[0046] In this embodiment, the doping concentration of active doped atoms in the first portion of the end of the second doped silicon layer 12 not covered by the conductive layer 13 is set to be higher than that in the middle portion of the second doped silicon layer 12. This reduces the defect density in the first portion of the end of the second doped silicon layer, improves the acid and alkali resistance of the surface of the first portion of the end of the second doped silicon layer, and enhances the stability of the first portion of the end of the second doped silicon layer when facing acidic environments such as water-dissolving CO2, thereby enhancing the stability of the battery. This ensures that the performance of the solar cell remains stable during long-term use.

[0047] Furthermore, taking the boron-doped second doped silicon layer 12 as an example, since active boron atoms, as acceptor impurities in the p-type conductive region, are the core source of photogenerated holes, the concentration of active boron atoms directly determines the hole concentration in the p-type conductive region. The higher the concentration of active boron atoms, the higher the concentration of holes that can participate in conduction in the p-type conductive region. A built-in electric field is formed between the n-type silicon substrate 1 and the p-type conductive region. The strength of this built-in electric field mainly depends on the product of the hole concentration and the electron concentration. Under the premise that the electron concentration of the n-type silicon substrate remains unchanged, increasing the concentration of active boron atoms at both ends of the p-type conductive region (i.e., at the interface with the n-type conductive region) can significantly increase the hole concentration in the p-type conductive region, thereby increasing the strength of the built-in electric field. The enhanced electric field strength can generate a stronger "extraction force," accelerating the migration speed of photogenerated holes from the pn junction depletion region to the interior of the p-type conductive region, reducing the residence time of photogenerated holes at the interface, thereby reducing carrier recombination losses and significantly improving the extraction and collection capability of the p-type conductive region for photogenerated holes. Meanwhile, the middle part of the p-type conductive region maintains a low concentration of active boron atoms, which can work with the first doped silicon layer 4 and silicon oxide layer 2 to achieve excellent interface passivation effect, reduce carrier recombination in the middle region, and ultimately achieve synergistic optimization of strong extraction at both ends and strong passivation in the middle, effectively improving the fill factor and photoelectric conversion efficiency of the full back contact solar cell.

[0048] In some embodiments, the microstructure of the first portion at the end of the second doped silicon layer 12 is amorphous or partially crystalline, and the microstructure of the middle portion of the second doped silicon layer 12 is amorphous.

[0049] The amorphous structure in the middle of the second doped silicon layer 12 allows for full utilization of its excellent passivation properties. The first portion at the ends of the second doped silicon layer 12, employing an amorphous or partially crystalline structure, can accommodate its higher concentration of active boron atoms, improving hole transport and extraction efficiency. When the ends are partially crystalline, the presence of the crystalline phase reduces the resistivity of the second doped silicon layer 12, decreasing resistance loss during hole transport. Simultaneously, the synergistic effect of partial crystalline structure and higher active boron atom concentration further optimizes the electrical characteristics of the interface between the p-type and n-type conductive regions. Combined with an enhanced built-in electric field, this accelerates hole extraction and collection, preventing recombination caused by hole accumulation at the interface. The second doped silicon layer 12, by setting a differentiated structure in which the ends are in an amorphous or partially crystalline state and the middle part is in a pure amorphous state, can be adapted to the higher concentration of active boron atoms at the ends of the layer than in the middle, and synergistically achieve strong passivation in the middle and strong transmission at both ends, effectively improving the fill factor, open circuit voltage and short circuit current of the battery.

[0050] In some implementations, the crystallization rate of the partially crystallized state is 5-68%.

[0051] For example, the crystallization rate of this partial crystallization state is 5%, 10%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 68%, or a range selected from any two of these.

[0052] By controlling the partial crystallization state of the first portion at the end of the second doped silicon layer 12 within the crystallinity range of 5-68%, a reasonable ratio match can be formed between the amorphous substrate and the crystalline phase, achieving a synergistic balance between passivation performance and conductivity transport performance. When the crystallinity is within this range, the film layer as a whole is still mainly composed of an amorphous structure, which can maintain a good interface passivation effect, reduce the interface state density, reduce carrier recombination, and help improve the open-circuit voltage of the battery. At the same time, the introduction of an appropriate amount of crystalline phase into the film layer can form a fast carrier transport channel, reduce the film resistivity, improve hole migration and collection efficiency, and help improve the short-circuit current of the battery.

[0053] In some implementations, the crystallization rate of the partially crystallized state is 10-50%.

[0054] For example, the crystallization rate of this partial crystallization state is 10%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, or a range selected from any two of these.

[0055] Further, the crystallization rate is preferably 10-50%, which can achieve a better match between passivation and transport. The crystallization ratio is moderate, so that the conductivity is not insufficient due to the crystallization rate, nor is the passivation characteristics of the amorphous substrate destroyed due to the crystallization rate. This allows the film layer to have both high passivation quality and good conductivity, further improving the fill factor of the battery.

[0056] In some implementations, the crystallization rate of the partially crystallized state is 20-40%.

[0057] For example, the crystallization rate of this partial crystallization state is 20%, 25%, 30%, 35%, 40%, or a range selected from any two of these.

[0058] When the crystallization rate is preferably set to 20-40%, the best synergistic effect of strong passivation in the middle and strong transmission at the ends can be achieved. The middle part maintains a pure amorphous structure, providing excellent interface passivation. The ends form moderate crystallization within this crystallization rate range, significantly improving conductivity without sacrificing passivation. This simultaneously improves the open-circuit voltage, short-circuit current and fill factor of the battery, ultimately improving the photoelectric conversion efficiency.

[0059] In some embodiments, when the microstructure of the first portion at the end of the second doped silicon layer 12 is amorphous, the microstructure is between 476 and 484 cm⁻¹. -1The wavenumber positions show characteristic Raman peaks. When the microstructure of the first part at the end of the second doped silicon layer 12 is in a crystalline state, the peaks are located at 476~484 cm⁻¹. -1 and 506~523cm -1 The wavenumber position shows characteristic Raman peaks; the middle part of the second doped silicon layer 12 is at 476~484 cm⁻¹. -1 Wavenumber position reveals characteristic Raman peaks.

[0060] The differences in film structure characterized by the Raman peaks described above result in excellent interface passivation in the middle part of the second doped silicon layer 12, effectively reducing carrier recombination and improving the open-circuit voltage of the battery. The first part at the end has better carrier transport capability, enhancing hole extraction and collection efficiency and improving the short-circuit current of the battery. Ultimately, the synergistic optimization of strong passivation in the middle part and strong transport at the end is achieved, effectively improving the fill factor, open-circuit voltage and short-circuit current of the battery, and improving the overall photoelectric conversion efficiency of the battery.

[0061] For example, when the microstructure of the first portion at the end of the second doped silicon layer 12 is amorphous, the wavenumber position of the characteristic Raman peak can be 476 cm⁻¹. -1 478cm -1 480cm -1 482cm -1 484cm -1 Or selected from any range of both. When the microstructure of the first portion at the end of the second doped silicon layer 12 is in a crystalline state, the wavenumber position of the characteristic Raman peak can be 476 cm⁻¹. -1 478cm -1 480cm -1 482cm -1 484cm -1 Or selected from any two of these ranges; and 506cm -1 510cm -1 515cm -1 520cm -1 523cm -1 Or selected from any range of two of them. The wavenumber position of the characteristic Raman peak in the middle of the second doped silicon layer 12 can be 476 cm⁻¹. -1 478cm -1 480cm -1 482cm -1 484cm -1 Or selected from any two of them.

[0062] In some embodiments, the active boron content of the first portion at the end of the second doped silicon layer 12 is 8 × 10⁻⁶. 18 ~1×1021 atoms / cm 3 The active boron content in the middle part of the second doped silicon layer 12 is 1×10⁻⁶. 17 ~7×10 18 atoms / cm 3 .

[0063] For example, the active boron content in the first portion at the end of the second doped silicon layer 12 can be 8 × 10⁻⁶. 18 atoms / cm 3 9×10 18 atoms / cm 3 10×10 18 atoms / cm 3 1×10 19 atoms / cm 3 5×10 19 atoms / cm 3 10×10 19 atoms / cm 3 1×10 20 atoms / cm 3 5×10 20 atoms / cm 3 1×10 21 atoms / cm 3 Or selected from any range of two of them. The active boron content in the middle of the second doped silicon layer 12 can be 1×10⁻⁶. 17 atoms / cm 3 5×10 17 atoms / cm 3 1×10 18 atoms / cm 3 5×10 18 atoms / cm 3 6×10 18 atoms / cm 3 7×10 18 atoms / cm 3 Or selected from any two of them.

[0064] The gradient design of the above-mentioned active boron concentration solves the technical problem of balancing passivation effect and carrier transport efficiency in traditional uniform doping processes. It achieves synergistic optimization of strong extraction at both ends and strong passivation in the middle, ultimately taking into account the open-circuit voltage, short-circuit current and fill factor of the cell, and effectively improving the overall photoelectric conversion efficiency and working stability of back contact solar cells.

[0065] This application intermittently sets the conductive layer 13 to cut off the conductive path between the first region 7 and the second region 8, preventing electrons from flowing directly from the first region 7 to the second region 8 through the conductive layer 13, thus avoiding internal short circuits in the solar cell and ensuring the open-circuit voltage. At the same time, the physical isolation formed at the discontinuity reduces the disordered recombination of charge carriers at the interface, lowers the series resistance, stabilizes the fill factor, and ensures the effective conversion between open-circuit voltage and short-circuit current.

[0066] In some implementations, such as Figure 14 As shown, the first portion of the end of the second doped layer is directly disposed on the silicon substrate 1, and at least a portion of the second portion of the end of the second doped layer covers the end of the first doped layer. Alternatively, the spacer region can be understood as being divided into two parts: a first sub-spacer region near the first region 7 and a second sub-spacer region near the second region 8. The first portion of the end of the second doped layer is located in the second sub-spacer region. The end of the first doped layer is located in the first sub-spacer region, and the second portion of the end of the second doped layer is located in the first sub-spacer region and covers the end of the first doped layer.

[0067] In some embodiments, the second portion at the end of the second doped silicon layer 12 has the same microstructure as the middle portion of the second doped silicon layer 12. For example, the second portion at the end of the second doped silicon layer 12 is also amorphous silicon.

[0068] In some embodiments, the second portion of the end of the second doped silicon layer 12 also has a region not covered by the conductive layer 13. That is, as... Figure 14 As shown, there is a certain distance between the edge of the conductive layer 13 on the second portion of the end of the second doped silicon layer 12 toward the middle portion of the second doped silicon layer 12 and the edge of the first portion of the end of the second doped silicon layer 12 toward the second portion of the end of the second doped silicon layer 12.

[0069] In some embodiments, the concentration of active doped atoms in the region of the first portion near its ends in the middle of the second doped silicon layer 12 is higher than the concentration in other regions of the middle portion. That is, as... Figure 14 As shown, the left and right edges of the middle of the second doped silicon layer 12 have a high doping concentration. Specifically, the doping concentration of active doped atoms in the first portion of the middle part of the second doped silicon layer 12 near its end is the same as the doping concentration of active doped atoms in the first portion of the end of the second doped silicon layer 12.

[0070] In some implementations, such as Figure 1 As shown, this application also provides a method for fabricating a back-contact solar cell, comprising the following steps: Step 1: Provide a silicon substrate 1. The silicon substrate 1 includes a light-receiving surface and a backlight surface disposed opposite to each other. The backlight surface includes a first region 7 and a second region 8 that are isolated from each other and alternately distributed, as well as a gap region located between adjacent first regions 7 and second regions 8. Step 2, forming a first doped layer in the first region 7, includes the following steps: A silicon oxide layer 2 and a first doped silicon layer 4 are sequentially formed on the first region 7 of the backlight surface of the silicon substrate 1; Remove the first doped silicon layer 4 and silicon oxide layer 2 located in the second region 8 on the backlight side of the silicon substrate 1; Step 3: Forming a second doped layer in the second region 8, including the following steps: An intrinsic hydrogenated amorphous silicon layer 11 and a second doped silicon layer 12 are sequentially formed on the back side of the silicon substrate 1. Increase the doping concentration of active doped atoms in at least a portion of the second doped silicon layer 12 corresponding to the spacer region; Remove the second doped silicon layer 12 and the intrinsic hydrogenated amorphous silicon layer 11 located in the first region 8 on the backlight side of the silicon substrate 1; Step 4: Prepare a conductive layer 13 on the back surface of the silicon substrate 1, and remove at least the portion of the conductive layer 13 corresponding to the portion of the second doped silicon layer 1 with a high concentration of active doped atoms. Step 5: Prepare electrode 6 on the side of conductive layer 13 that is away from silicon substrate 1.

[0071] Specifically, the silicon substrate 1 in step 1 is a single-crystal electronically type (n-type) silicon wafer with a resistivity of 4.0~4.5 Ω·cm. For example, the resistivity can be 4.0 Ω·cm, 4.2 Ω·cm, 4.3 Ω·cm, 4.4 Ω·cm, 4.5 Ω·cm, or a range selected from any two of these. The silicon substrate 1 is a square with a side length of 182 mm. In other embodiments, the silicon substrate 1 can also be a rectangle or a square with other side lengths. The first region 7 is an n-type conductive region, and the corresponding second region 8 is a p-type conductive region.

[0072] In step 2, a silicon oxide layer 2 can be prepared using a furnace tube oxidation method. The oxygen source is oxygen, the oxidation temperature is 550~600℃, and the oxidation time is 15~25min. The thickness of the prepared silicon oxide layer 2 is 1~2nm. For example, the oxidation temperature can be 550℃, 560℃, 570℃, 580℃, 590℃, 600℃, or any combination thereof; the oxidation time can be 15min, 18min, 20min, 22min, 23min, 24min, 25min, or any combination thereof; and the thickness of the silicon oxide layer 2 can be 1.0nm, 1.2nm, 1.4nm, 1.6nm, 1.8nm, 2.0nm, or any combination thereof.

[0073] A polycrystalline silicon film 3 is deposited on the surface of the silicon oxide layer 2. Phosphorus diffusion is performed on the polycrystalline silicon film 3, and an oxygen source is introduced during the phosphorus diffusion process to obtain the first doped silicon layer 4. The deposition temperature of the polycrystalline silicon film 3 when depositing on the surface of the silicon oxide layer 2 is 600~620℃ and the deposition time is 30~40min. The diffusion temperature of the polycrystalline silicon film 3 when performing phosphorus diffusion is 850~900℃ and the diffusion time is 40~50min.

[0074] Then, a polycrystalline silicon film 3 is deposited on the entire surface of the silicon oxide layer 2 by low-pressure chemical vapor deposition (LPCVD), using silane as the reaction precursor. The deposition temperature can be 600℃, 605℃, 610℃, 615℃, 620℃ or any combination thereof; the deposition time can be 30min, 32min, 33min, 35min, 36min, 37min, 38min, 39min, 40min or any combination thereof; the thickness of the polycrystalline silicon film 3 is 120~140nm, for example, the thickness can be 120nm, 125nm, 130nm, 133nm, 138nm, 140nm or any combination thereof. Phosphorus diffusion is performed on the polycrystalline silicon film 3 using a furnace tube diffusion method. An oxygen source (oxygen) is introduced during the diffusion process to complete the phosphorus-oxygen co-doping of the polycrystalline silicon film 3, resulting in a first doped silicon layer 4. The diffusion temperature can be 850℃, 860℃, 870℃, 885℃, 890℃, 900℃, or any combination thereof. The diffusion time can be 40 min, 41 min, 42 min, 44 min, 48 min, 50 min, or any combination thereof. The first doped silicon layer 4 is a doped polycrystalline silicon layer. Excellent interface passivation is achieved using the silicon oxide layer 2, which, together with the first doped silicon layer 4, forms a good field-effect passivation and carrier transport channel, effectively reducing carrier recombination and improving the open-circuit voltage and fill factor of the battery.

[0075] Meanwhile, in the aforementioned step of obtaining the first doped silicon layer 4 by phosphorus diffusion of the polycrystalline silicon film 3 using the furnace tube diffusion method, the phosphorus source used for doping reacts with oxygen at high temperature to generate P2O5. P2O5 further combines with SiO2 on the surface of the first doped silicon layer 4 to form a phosphorus-containing silicon dioxide layer, namely a phosphosilicate glass layer (PSG). PSG is highly hygroscopic, and if it remains, it will introduce impurity ions, affecting the subsequent deposition quality and battery performance. Furthermore, the phosphosilicate glass layer is easily corroded by hydrofluoric acid solution. Therefore, hydrofluoric acid solution is used to quickly remove it to avoid interfering with subsequent processes. The mass fraction of the hydrofluoric acid solution used to clean the first doped silicon layer 4 is 3% to 8%, and its mass fraction can be 3%, 4%, 5%, 6%, 8%, or any range selected from any two of these.

[0076] Furthermore, while removing the first doped silicon layer 4 and silicon oxide layer 2 on the back surface of the silicon substrate 1 located in the second region 8, a portion of the thickness of the silicon substrate 1 corresponding to the second region 8 can be further removed to form an opening region on the second region 8. The purpose is to remove the film layer interference in the first region 7, avoid ineffective recombination of charge carriers and expose the intrinsic surface of the silicon substrate 1, and ensure the subsequent tight film formation and efficient passivation of the second region 8, thereby achieving physical pre-isolation between the first region 7 and the second region 8.

[0077] Next, in step 3, an intrinsic hydrogenated amorphous silicon layer 11 is deposited on the back side of the silicon substrate 1 using plasma-enhanced chemical vapor deposition (PECVD). The reaction gases are silane and hydrogen, and the deposition temperature is 180–220°C, for example, this temperature can be 180°C, 190°C, 200°C, 200°C, 220°C, or a range selected from any two of these. The thickness of the intrinsic hydrogenated amorphous silicon layer 11 is 5–10 nm, for example, this thickness can be 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, or a range selected from any two of these.

[0078] Then, a second doped silicon layer 12 is deposited on the intrinsic hydrogenated amorphous silicon layer 11 using plasma-enhanced chemical vapor deposition (PECVD). Taking a boron-doped second doped silicon layer 12 as an example, the reactant gases are silane, diborane, and hydrogen, and the deposition temperature is 180–220°C, for example, this temperature can be 180°C, 190°C, 200°C, 200°C, 220°C, or a range selected from any two of these. The thickness of the second doped silicon layer 12 is 15–25 nm, for example, this thickness can be 15 nm, 18 nm, 20 nm, 22 nm, 24 nm, 25 nm, or a range selected from any two of these.

[0079] The intrinsic hydrogenated amorphous silicon layer 11 can perform high-quality chemical passivation and field-effect passivation on the surface of the silicon substrate 1, significantly reducing the surface state density and carrier recombination rate, and improving the open-circuit voltage of the battery. A second doped silicon layer 12 is disposed on top of it, which can protect the passivation layer from damage by subsequent processes, and on the other hand, it can provide a high concentration of holes as a p-type conductive layer, enhance the built-in electric field strength between it and the silicon substrate 1, and improve the hole extraction and collection capabilities.

[0080] By increasing the content of active boron atoms at the end of the second doped silicon layer 12, the content of active boron atoms at the end of the second doped silicon layer 12 is higher than that in the middle part, thereby enhancing the built-in electric field strength at the end of the second doped silicon layer 12, accelerating the extraction and collection speed of photogenerated holes, reducing carrier recombination, and improving the fill factor and conversion efficiency of the battery.

[0081] Further, in step 4, a conductive layer 13 can be deposited by magnetron sputtering (PVD). The conductive layer 13 can be a transparent conductive oxide (TCO) layer. The thickness of the conductive layer 13 is 75~85nm, for example, its thickness can be 75nm, 76nm, 78nm, 79nm, 80nm, 82nm, 85nm or a range selected from any two of these.

[0082] Further, in step 5, conductive silver paste is printed on the conductive layer 13 of the first region 7 and the second region 8 respectively. After drying to solidify the conductive silver paste, a back contact battery is obtained. The drying temperature is 100~150℃, for example, the drying temperature can be 100℃, 110℃, 120℃, 130℃, 150℃ or any combination thereof, and the drying time is 30~60min, for example, the drying time can be 30min, 35min, 40min, 45min, 50min, 55min, 60min or any combination thereof.

[0083] In some embodiments, taking boron atoms as an example, the doping concentration of active dopant atoms in at least a portion of the second doped silicon layer 1 corresponding to the spacer region can be increased in the following two ways. It is understood here that the region where the doping concentration of active dopant atoms is increased in this step is the first portion of the end of the final back-contact solar cell.

[0084] First implementation method: Annealing is performed by scanning at least a portion of the second doped silicon layer 12 corresponding to the spacer region (i.e., the aforementioned preset high doping concentration region) using a first laser. The wavelength of the first laser is 530~535nm, the power is 7.5~8.0W, the scanning speed is 35~45m / s, the spot diameter is 140~160μm, and the penetration depth is 1~5μm.

[0085] After the high-energy photons of the first laser are absorbed by the second doped silicon layer 12, localized high temperatures are generated that only affect the surface of the second doped silicon layer 12. This causes a brief thermal vibration and lattice relaxation in the silicon lattice. Boron atoms that were originally in the interstitial spaces gain enough energy to break through the lattice barrier, occupy lattice vacancies in silicon, and transform into substitutional active boron atoms, directly increasing the effective active boron concentration in the laser-irradiated area. The first laser has a short penetration depth, and the laser energy only acts on the two ends of the surface of the boron-doped silicon layer. The underlying intrinsic hydrogenated amorphous silicon layer 11, silicon substrate 1, silicon oxide layer 2, and other stacked structures are not damaged by the thermal effect of the first laser, and the underlying passivation stack is not damaged.

[0086] The second implementation method: A boron-containing film layer 14 (i.e., a doped atomic film layer) is formed on the second doped silicon layer 12. The boron-containing film layer 14 is covered by a second laser. At least a portion of the second doped silicon layer 12 corresponding to the spacer region (i.e., the aforementioned preset high doping concentration region) is scanned by the boron-containing film layer. The boron-containing film layer is then removed. The wavelength of the second laser is 530~535nm, the power is 30~35W, the scanning speed is 35~45m / s, the spot diameter is 140~160μm, and the penetration depth is 1~5μm.

[0087] The boron-containing film layer 14 is irradiated by the second laser, and the second laser is absorbed by the boron-containing film layer 14. The second laser scans the boron-containing film layer 14, and the boron in the boron-containing film layer 14 in the precisely scanned area propels the second doped silicon layer 12, resulting in a higher concentration of active boron atoms at the ends of the second doped silicon layer 12 than at the middle part of the second doped silicon layer 12.

[0088] In some embodiments, the boron-containing film layer 14 may be a borosilicate glass layer (BSG), the thickness of the boron-containing film layer 14 is 30~200nm, and the mass percentage of boron in the boron-containing film layer 14 is 2~15%.

[0089] The borosilicate glass layer has a high and stable boron content. The thickness of the boron-containing film can be 30 nm, 50 nm, 80 nm, 100 nm, 130 nm, 150 nm, 180 nm, 200 nm, or any combination thereof. The mass percentage of boron in the boron-containing film can be 2%, 5%, 8%, 10%, 12%, 13%, 15%, or any combination thereof. By controlling the thickness of the boron-containing film and the mass percentage of boron within the above ranges, a stable and appropriate supply of boron source can be provided for the subsequent second laser.

[0090] In some embodiments, the method for preparing the boron-containing film includes: deposition using a mixture of silane, diborane, and oxygen as reactants, wherein the deposition temperature is 160-230°C and the deposition time is 500-600 s.

[0091] Specifically, a boron-containing film layer 14 is deposited on the surface of the second doped silicon layer 12 using atmospheric pressure chemical vapor deposition (APCVD) without damaging the underlying intrinsic hydrogenated amorphous silicon layer 11, silicon oxide layer 2 of the silicon substrate 1, and other stacked structures. A mixture of silane, diborane, and oxygen is used as the gas source, and the deposition temperature is 160~230℃, for example, the deposition temperature can be 160℃, 170℃, 180℃, 190℃, 200℃, 210℃, 230℃, or a range selected from any two of these. The borosilicate glass layer is then removed by cleaning with a hydrofluoric acid solution, the mass fraction of which is 1~5%, for example, the mass fraction of which is 1%, 2%, 3%, 4%, 5%, or a range selected from any two of these.

[0092] Furthermore, after forming the second doped layer in the second region 8, step 3 also includes the following steps: Remove the intrinsic hydrogenated amorphous silicon layer 11 and the second doped silicon layer 12 located on the surface of the first region 7.

[0093] A laser with a wavelength of 532 nm can be used to etch the second doped silicon layer 12 on the surface of the first region 7 to remove all or part of the thickness of the second doped silicon layer 12; then an alkaline solution is used to clean the intrinsic hydrogen-containing amorphous silicon layer 11 and the remaining second doped silicon layer 12 from the laser etching.

[0094] In step S4, the conductive layer 13 corresponding to the portion of the second doped silicon layer with a high concentration of active doped atoms can be etched using a laser. The laser wavelength is 300-400 nm, such as 300 nm, 330 nm, 350 nm, 380 nm, 400 nm, or a range selected from any two of these. By intermittently setting the conductive layer 13, the conductive path between the first region 7 and the second region 8 is cut off, preventing short circuits inside the solar cell. Simultaneously, it reduces disordered recombination of charge carriers at the interface, lowering the series resistance.

[0095] In some embodiments, in step 3, the first doped silicon layer 4 and silicon oxide layer 2 on the backlight side of the silicon substrate 1 located in the second region 8 are removed, and an opening region is formed in the second region 8, including: A protective layer 5 is deposited on the surface of the first doped silicon layer 4 on the back side of the silicon substrate 1, and then cleaned with hydrofluoric acid solution after deposition. The protective layer 5 on the surface of the first doped silicon layer 4 located in the second region 8 is removed by etching; Remove the first doped silicon layer 4 and silicon oxide layer 2 located in the second region 8 to form an opening region in the second region 8; The silicon substrate 1 in the opening region is texturized and cleaned, while the protective layer 5 on the surface of the first doped silicon layer 4 in the first region 7 is removed.

[0096] Specifically, the protective layer 5 can be a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, or a nitrogen-containing polycrystalline silicon layer. For example, a silicon nitride layer can be deposited as the protective layer 5 using PECVD. The reaction gas source is silane and ammonia, the pressure is 133 Pa, the power is 3000 W, and the deposition temperature is 430~480℃, which can be 430℃, 440℃, 450℃, 460℃, 470℃, 480℃, or any combination thereof. The thickness of the protective layer 5 is 80~100 nm, which can be 80 nm, 85 nm, 90 nm, 100 nm, or any combination thereof.

[0097] The protective layer 5 on the surface of the first doped silicon layer 4 in the second region 8 is removed by laser etching, simultaneously generating an oxygen-containing silicon film. The oxygen-containing silicon film generated in the laser-etched region is then removed using hydrofluoric acid, with a mass fraction of 3-8%, for example, 3%, 4%, 5%, 6%, 7%, 8%, or any combination thereof. It should be noted that the oxygen-containing silicon film generated during laser etching is typically thin, thus the protective layer on the surface of the first region 7 can be retained during hydrofluoric acid cleaning. Next, the first doped silicon layer 4 located in the region other than the second region 8 is removed using an alkaline solution, which can be potassium hydroxide, sodium hydroxide, or a mixture of any two thereof, with a mass fraction of 20-30%, for example, 20%, 22%, 25%, 26%, 28%, 30%, or any combination thereof. Then, the silicon oxide layer 2 located in the region other than the second region 8 is removed using hydrofluoric acid, with a mass fraction of 3-8%, for example, 3%, 4%, 5%, 6%, 7%, 8%, or any combination thereof.

[0098] Then, a portion of the silicon substrate 1 corresponding to the second region 8 is removed by an alkaline solution containing texturing additives, forming an opening region on the second region 8, and simultaneously forming a textured surface on the surface of the opening region.

[0099] The alkaline solution containing texturing additives can be a mixture of 1.5% KOH solution and 8% isopropanol. The texturing temperature is 70-90℃, for example, 70℃, 72℃, 75℃, 78℃, 80℃, or any combination thereof. The texturing time is 30-40 min, for example, 30 min, 32 min, 33 min, 35 min, 36 min, 37 min, 38 min, 39 min, 40 min, or any combination thereof. After texturing, the reflectivity is no greater than 12.5%. Then, hydrofluoric acid solution is used for cleaning to remove residual texturing solution, obtaining a clean and highly reactive bare silicon surface, providing a good interface foundation for subsequent deposition, and simultaneously removing the protective layer 5 on the surface of the first doped silicon layer 4 on the first region 7. The mass fraction of the hydrofluoric acid solution is 3%-8%, for example, 3%, 4%, 5%, 6%, 8%, or any combination thereof.

[0100] In some embodiments, after texturing and cleaning, a passivation layer 9 and an antireflection layer 10 are sequentially deposited on the light-receiving surface of the silicon substrate 1.

[0101] The passivation layer 9 can be one or a combination of an aluminum oxide passivation layer, an amorphous silicon passivation layer, or a silicon oxide passivation layer. The thickness of the passivation layer 9 is 3-5 nm, for example, it can be 3 nm, 4 nm, 5 nm, or a range selected from any two of them. The antireflection layer 10 can be one or a combination of a silicon nitride, aluminum oxide, or silicon oxide layer. The thickness of the antireflection layer 10 is 70-80 nm, for example, it can be 70 nm, 72 nm, 75 nm, 76 nm, 78 nm, 80 nm, etc.

[0102] In some embodiments, before the first doped layer is formed in the first region 7 in step 2, the silicon substrate 1 is further pretreated, which includes etching the silicon substrate 1 with an alkaline solution to remove the surface damage layer of the silicon substrate 1.

[0103] After removing the surface damage layer of silicon substrate 1, the weight reduction of silicon substrate 1 is greater than 1.2g. For example, the weight reduction of silicon substrate 1 can be 1.3g, 1.4g, 1.5g, or a range selected from any two of these, which can completely remove the cutting damage layer of silicon substrate 1.

[0104] Specifically, the alkaline solution is a potassium hydroxide solution, a sodium hydroxide solution, or a mixture thereof. The alkaline solution has a mass fraction of 20-30%, such as 20%, 23%, 28%, 30%, or a range selected from any two of these.

[0105] Example A method for fabricating a back-contact solar cell includes the following steps: Step 1: Provide a silicon substrate 1. The silicon substrate 1 includes a light-receiving surface and a backlight surface disposed opposite to each other. The backlight surface includes an alternately distributed first region 7 and a second region 8, and a gap region located between adjacent first regions 7 and second regions 8.

[0106] Specifically, silicon substrate 1 is a single-crystal electronically type (n-type) silicon substrate with a resistivity of 4.2 Ω·cm and a square shape with a side length of 182 mm. The silicon substrate 1 is isotropically etched using a 25% sodium hydroxide alkaline solution to remove the damaged layer on its surface. After removing the damaged layer, the weight of silicon substrate 1 is reduced by 1.5 g. The first region 7 is an n-type conductive region, and the second region 8 is a p-type conductive region.

[0107] Step 2, forming a first doped layer in the first region 7, includes the following steps: Step 2.1: Sequentially form a silicon oxide layer 2 and a first doped silicon layer 4 on the back surface of the silicon substrate 1.

[0108] Specifically, such as Figure 2 As shown, a silicon oxide layer 2 was formed on the surface of the silicon substrate 1 using a furnace tube oxidation method. The oxygen source for the furnace tube oxidation method was oxygen, the oxidation temperature was 590℃, and the oxidation time was 20 min, resulting in a silicon oxide layer 2 with a thickness of 1.4 nm. Next, a polycrystalline silicon film 3 was deposited on the entire surface of the silicon oxide layer 2 using low-pressure chemical vapor deposition (LPCVD). Silane was used as the reaction precursor, the deposition temperature was 610℃, and the deposition time was 36 min, resulting in a polycrystalline silicon film 3 with a thickness of 130 nm.

[0109] like Figure 3 As shown, phosphorus diffusion was performed on the polycrystalline silicon film 3 using the furnace tube diffusion method. An oxygen source was introduced during the diffusion process. The oxygen source was oxygen. The diffusion temperature was 880℃ and the diffusion time was 45min. This completed the phosphorus-oxygen co-doping of the polycrystalline silicon film 3, resulting in a first doped silicon layer 4 with a thickness of 160nm.

[0110] Step 2.2: Remove the first doped silicon layer 4 and silicon oxide layer 2 on the backlight side of the silicon substrate 1 located in the second region 8 to form an opening region in the second region 8; Specifically, such as Figure 4 As shown, firstly, a protective layer 5 is deposited on the surface of the first doped silicon layer 4 on the back side of the silicon substrate 1 using the PECVD method. The protective layer 5 is a silicon nitride layer. The reaction gas source is silane and ammonia. The deposition temperature is 450℃. The thickness of the protective layer 5 is 100nm. After deposition, it is cleaned with a 5% hydrofluoric acid solution.

[0111] like Figure 5As shown, the protective layer 5 on the surface of the first doped silicon layer 4 in the second region 8 is etched using a laser with a wavelength of 532nm. During the laser etching, an oxygen-containing silicon film is generated. The generated oxygen-containing silicon film is removed using hydrofluoric acid with a mass fraction of 5%.

[0112] like Figure 6 As shown, specifically, the first doped silicon layer 4, which is disposed in the second region 8, is removed with 25% potassium hydroxide by mass, and the silicon oxide layer 2, which is disposed in the second region 8, is removed with 5% hydrofluoric acid by mass, thereby forming an opening region on the second region 8.

[0113] Step 3: Forming a second doped layer in the second region 8, including the following steps: Step 3.1: Texturing and cleaning the silicon substrate 1 in the opening area, while removing the protective layer 5 on the surface of the first doped silicon layer 4 in the first region 7.

[0114] like Figure 7 As shown, specifically, the exposed portion of the silicon substrate 1 is texturized using a texturing solution, which is a mixture of 5% KOH solution and 5% isopropanol. The texturing temperature is 80°C, and the texturing time is 35 minutes. After texturing, its reflectivity is no greater than 12.5%. Then, a 5% hydrofluoric acid solution is used for cleaning to remove residual texturing solution, resulting in a clean and highly reactive bare silicon surface. At the same time, the protective layer 5 on the surface of the first doped silicon layer 4 on the first region 7 is removed.

[0115] Step 3.2: Sequentially deposit a passivation layer 9 and an antireflection layer 10 on the light-receiving surface of the silicon substrate 1.

[0116] like Figure 8 As shown, in the ALD system, a 4 nm thick passivation layer 9 is deposited on the light-receiving surface of the silicon substrate 1. The passivation layer 9 is specifically an aluminum oxide layer. Then, a 75 nm thick antireflection layer 10 is deposited on the surface of the passivation layer 9. The antireflection layer 10 is specifically a silicon nitride layer.

[0117] Step 3.3: An intrinsic hydrogenated amorphous silicon layer 11 and a second doped silicon layer 12 are sequentially formed on the backlight surface of the silicon substrate 1. The second doped silicon layer 12 is a boron doped silicon layer.

[0118] Specifically, such as Figure 9 As shown, an intrinsic hydrogenated amorphous silicon layer 11 and a second doped silicon layer 12 are sequentially formed on the back surface of a silicon substrate 1 using a vapor deposition process. The intrinsic hydrogenated amorphous silicon layer 11 has a thickness of 8 nm and is used to achieve efficient passivation of the silicon substrate 1, reduce the interface state density, and reduce carrier recombination. The second doped silicon layer 12 is a 20 nm thick boron-doped microcrystalline silicon layer that constructs a p-type conductive channel to achieve efficient hole collection and transport.

[0119] Step 3.4: Increase the active boron content in the first part of the pre-set second doped silicon layer 12 end.

[0120] Specifically, such as Figure 10 As shown, APCVD was used with a mixture of silane, diborane, and oxygen as reactants to deposit a 60 nm thick doped atomic film 14 on the surface of the second doped silicon layer 12. The doped atomic film 14 was a boron-containing film, deposited at a temperature of 230 °C for 550 s. The boron-containing film was a borosilicate glass (BSG) layer. Then, a laser was used to scan the boron-containing film corresponding to the first portion at the predetermined end of the second doped silicon layer 12. The laser wavelength was 532 nm, the power was 30.2 W, the scanning speed was 40 m / s, the spot diameter was 150 μm, and the penetration depth was 3 μm. This precisely pushed the boron from the boron-containing film into the second doped silicon layer 12, increasing the active boron content in the first portion at the predetermined end of the second doped silicon layer 12 to form a heavily doped region. The active boron content in the heavily doped region was 1 × 10⁻⁶. 21 atoms / cm 3 The active boron content in other regions of the second doped silicon layer 12 is 7 × 10⁻⁶. 18 atoms / cm 3 .

[0121] Step 3.5: Remove the intrinsic hydrogenated amorphous silicon layer 11 and the second doped silicon layer 12 from the surface of the first region 7.

[0122] like Figure 11 As shown, the deposited doped atomic film layer 14 is removed by cleaning with a 3% HF solution. Then, the intrinsic hydrogenated amorphous silicon layer 11 and the second doped silicon layer 12 in the first region 7 are successively etched away by a laser with a wavelength of 532 nm. Finally, the surface of the etched area is cleaned with a 5% hydrofluoric acid solution.

[0123] Step 4: A conductive layer 13 is deposited on the side of the first doped layer and the second doped layer that is away from the silicon substrate 1.

[0124] like Figure 12 As shown, specifically, a conductive layer 13 is deposited by magnetron sputtering (PVD). The conductive layer 13 is an indium tin oxide film with a thickness of 80 nm.

[0125] like Figure 13 As shown, the conductive layer 13 corresponding to the first portion and part of the second portion of the end of the second doped silicon layer 12 is then etched with a 325nm wavelength laser, so that the conductive layer 13 is discontinuously disposed.

[0126] Step 5: Prepare electrode 6 on the side of conductive layer 13 that is away from silicon substrate 1.

[0127] like Figure 14As shown, specifically, conductive silver paste is printed on the side of the conductive layer 13 in the first region 7 and the second region 8 facing away from the silicon substrate 1 to form electrodes 6, which are then dried at 120°C for 40 minutes to obtain a back-contact solar cell. The conductive layer 13 in the first region 7 is spaced apart from the heavily doped region end of the second region 8 near the first region 7 by a distance a, where a is greater than 0. The conductive layer 13 in the second region 8 overlaps with the heavily doped region of the second region 8 near the first region 7 by an overlap length b, where b is greater than 0. This avoids the heavily doped region directly contacting the first region 7 simultaneously, preventing the formation of parasitic pn junctions or shunt paths that could lead to holes being incorrectly directed to the first region 7 and electrons leaking into the second region 8, resulting in severe carrier recombination and efficiency loss.

[0128] Comparative Example 1 Based on the embodiment, the difference from the embodiment is that: after step 3.3, in which an intrinsic hydrogenated amorphous silicon layer 11 and a second doped silicon layer 12 are sequentially formed on the backlight surface of the silicon substrate 1, step 3.5, in which the intrinsic hydrogenated amorphous silicon layer 11 and the second doped silicon layer 12 on the surface of the first region 7, are directly performed, and step 3.4, in which the active boron content at both ends of the second doped silicon layer 12 is not performed. All other steps are the same as in the embodiment.

[0129] Performance testing The performance of the back-contact solar cells prepared in the above embodiments and comparative examples was tested, and the results are shown in Table 1 below: Table 1. Test results of back-contact solar cells prepared in the examples and comparative examples. The difference between Comparative Example 1 and the Example is that the concentration of active boron atoms in the second doped silicon layer 12 of Comparative Example 1 is uniformly distributed throughout the entire film. As shown in Table 1, the Example enhances the built-in electric field strength between the end of the second region 8 (p-type conductive region) and the silicon substrate 1 by increasing the concentration of active boron atoms at both ends of the second doped silicon layer 12, thereby improving the hole extraction and collection capabilities. As a result, compared with Comparative Example 1, Example 1 shows improvements in short-circuit current, open-circuit voltage, and fill factor, and also improves photoelectric conversion efficiency.

[0130] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments have been described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0131] The embodiments described above are merely examples of several implementations of this application, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A back-contact solar cell, characterized in that, include: A silicon substrate (1) includes a light-receiving surface and a back-lighting surface disposed opposite to each other. The back-lighting surface includes an alternately distributed first region (7) and a second region (8), and a spacer region located between adjacent first regions (7) and second regions (8). The first doped layer includes a middle portion disposed in the first region (7) and an end portion disposed in the interval region. The first doped layer includes a silicon oxide layer (2) and a first doped silicon layer (4) sequentially stacked from the backlight surface of the silicon substrate (1) outward. The second doped layer includes a middle portion disposed in the second region (8) and an end portion disposed in the interval region. The end portion of the second doped layer includes a first portion close to the middle portion and a second portion away from the middle portion. The second doped layer includes an intrinsic hydrogenated amorphous silicon layer (11) and a second doped silicon layer (12) sequentially stacked from the backlight surface of the silicon substrate (1) outward. A conductive layer (13) is disposed on the side of the first doped layer and the second doped layer away from the silicon substrate (1), and a first portion of the end of the second doped layer does not cover the conductive layer (13). An electrode (6) is disposed on the side of the conductive layer (13) opposite to the silicon substrate (1); The doping concentration of active doped atoms in the first part of the end of the second doped silicon layer (12) is higher than that of active doped atoms in the middle part.

2. The back-contact solar cell as described in claim 1, characterized in that, The first part of the end of the second doped silicon layer (12) has an amorphous or partially crystalline structure, and the middle part of the second doped silicon layer (12) has an amorphous structure.

3. The back-contact solar cell as described in claim 2, characterized in that, The crystallization rate of the partially crystallized state is 5-68%; Preferably, the crystallization rate of the partially crystallized state is 10-50%; Preferably, the crystallization rate of the partially crystallized state is 20-40%.

4. The back-contact solar cell as described in claim 2, characterized in that, When the microstructure of the first portion at the end of the second doped silicon layer (12) is amorphous, at 476~484 cm⁻¹ -1 The wavenumber position shows characteristic Raman peaks. When the microstructure at the end of the second doped silicon layer (12) is in a partially crystalline state, the peaks are located at 476~484 cm⁻¹. -1 and 506~523cm -1 The wavenumber position shows characteristic Raman peaks; the middle part of the second doped silicon layer (12) is at 476~484 cm⁻¹. -1 Wavenumber position reveals characteristic Raman peaks.

5. The back-contact solar cell as described in claim 1, characterized in that, The first doped silicon layer (4) has the same conductivity type as the silicon substrate (1), and the second doped silicon layer (12) has the opposite conductivity type to the silicon substrate (1). Preferably, the silicon substrate (1) is an n-type silicon substrate; Preferably, the first doped silicon layer (4) is a phosphorus-doped silicon layer; Preferably, the second doped silicon layer (12) is a boron doped silicon layer; Preferably, the active boron content of the first portion at the end of the second doped silicon layer (12) is 8 × 10⁻⁶. 18 ~1×10 21 atoms / cm 3 The active boron content in the middle part of the second doped silicon layer (12) is 1×10 17 ~7×10 18 atoms / cm 3 .

6. The back-contact solar cell as described in claim 1, characterized in that, The first portion of the end of the second doped layer is directly disposed on the silicon substrate (1), and at least a portion of the second portion of the end of the second doped layer covers the end of the first doped layer; Preferably, the second portion of the end of the second doped silicon layer (12) has the same structure as the middle portion of the second doped silicon layer (12).

7. The back-contact solar cell according to claim 1, characterized in that, The second portion of the end of the second doped silicon layer (12) also has an area not covered by the conductive layer (13); Preferably, the concentration of active doped atoms in the region of the first part near the end of the middle portion of the second doped silicon layer (12) is higher than the concentration in other regions of the middle portion; Preferably, the doping concentration of active doped atoms in the region of the first part near the end of the middle portion of the second doped silicon layer (12) is the same as the doping concentration of active doped atoms in the first part at the end of the second doped silicon layer (12).

8. A method for fabricating a back-contact solar cell, characterized in that, Includes the following steps: Step 1: Provide a silicon substrate (1), the silicon substrate (1) includes a light-receiving surface and a back-lighting surface disposed opposite to each other, the back-lighting surface includes an alternately distributed first region (7) and a second region (8), and a gap region located between adjacent first region (7) and second region (8); Step 2, forming a first doped layer in the first region (7), includes the following steps: A silicon oxide layer (2) and a first doped silicon layer (4) are sequentially formed on the back surface of the silicon substrate (1). Remove the first doped silicon layer (4) and the silicon oxide layer (2) located in the second region (8) of the backlight surface of the silicon substrate (1). Step 3: Forming a second doped layer in the second region (8), including the following steps: An intrinsic hydrogenated amorphous silicon layer (11) and a second doped silicon layer (12) are sequentially formed on the back side of the silicon substrate (1). Increase the doping concentration of active doped atoms in at least a portion of the second doped silicon layer (12) corresponding to the portion of the spacer region; Remove the second doped silicon layer (12) and the intrinsic hydrogenated amorphous silicon layer (11) located in the first region (7) of the backlight surface of the silicon substrate (1). Step 4: Prepare a conductive layer (13) on the back surface of the silicon substrate (1), and remove at least the portion of the conductive layer (13) corresponding to the portion of the second doped silicon layer (12) with a high concentration of active doped atoms. Step 5: Prepare an electrode (6) on the side of the conductive layer (13) opposite to the silicon substrate (1).

9. The method for preparing a back-contact solar cell as described in claim 8, characterized in that, Increasing the doping concentration of active doped atoms in at least a portion of the second doped silicon layer (12) corresponding to the spacer region includes: Annealing is performed by scanning at least a portion of the second doped silicon layer (12) corresponding to the spacer region using a first laser, wherein the wavelength of the first laser is 530~535nm, the power is 7.5~8.0W, the scanning speed is 35~45m / s, the spot diameter is 140~160μm, and the penetration depth is 1~5μm.

10. The method for preparing a back-contact solar cell as described in claim 8, characterized in that, Increasing the doping concentration of active doped atoms in at least a portion of the second doped silicon layer (12) corresponding to the spacer region includes: A doped atomic film layer (14) is formed on the second doped silicon layer (12). The doped atomic film layer (14) corresponding to at least a portion of the second doped silicon layer (12) in the spacer region is scanned using a second laser, and then the doped atomic film layer (14) is removed. The wavelength of the second laser is 530~535nm, the power is 30~35W, the scanning speed is 35~45m / s, the spot diameter is 140~160μm, and the penetration depth is 1~5μm. Preferably, the second doped silicon layer (12) is a boron-doped silicon layer, and the doped atom-containing film layer (14) is a boron-containing film layer; Preferably, the thickness of the boron-containing film layer is 30~200 nm; Preferably, the mass percentage of boron in the boron-containing film layer is 2-15%; Preferably, the method for preparing the boron-containing film includes: deposition using a mixed gas of silane, diborane and oxygen as reactants, wherein the deposition temperature is 160~230℃ and the deposition time is 500~600s.

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