Method for manufacturing a solar cell

Abstract

The present disclosure relates to the technical field of solar cells, and discloses a preparation method of a solar cell. The preparation method of the solar cell comprises: forming a first doped semiconductor layer on a light-receiving surface of a base layer, and forming a second doped semiconductor layer on a back surface of the base layer; at least one of the first doped semiconductor layer and the second doped semiconductor layer comprises contact regions and non-contact regions arranged alternately, the surface of the contact region is relatively protruding from the surface of the non-contact region, the doping concentration of the contact region is greater than the doping concentration of the non-contact region; or forming the first doped semiconductor layer and the second doped semiconductor layer arranged alternately on the back surface of the base layer; the first doped semiconductor layer and the second doped semiconductor layer are configured as the contact regions; forming a first electrode and a second electrode. The present disclosure realizes regional differentiation processing, reduces the contact resistance, and improves the open-circuit voltage and short-circuit current of the cell.

Description

Technical Field

[0001] This disclosure relates to the field of solar cell technology, and more specifically, to a method for preparing a solar cell. Background Technology

[0002] In the manufacturing process of crystalline silicon solar cells, a uniform doped layer is typically formed across the entire surface of the silicon wafer to construct a PN junction, which is the core structure for achieving photoelectric conversion. For example, boron doping is performed on the surface of an N-type silicon wafer to form a PN junction. + Layer, or phosphorus doping to form N on the surface of a P-type silicon wafer. + However, this traditional uniform doping structure has inherent technical contradictions. On the one hand, the contact region requires a high doping concentration to ensure good ohmic contact and reduce contact resistance; on the other hand, the non-contact region requires a low doping concentration to suppress the "dead layer" effect, reduce Auger recombination and surface recombination of photogenerated carriers. Moreover, compared with the heavily doped contact region, the lightly doped non-contact region can reduce parasitic absorption of short-wavelength light, thereby improving the open-circuit voltage and short-circuit current of the battery. Since uniform doping cannot simultaneously meet the differentiated needs of these two regions, it severely limits the further improvement of the battery's photoelectric conversion efficiency. To overcome the above bottlenecks, selective emitter technology has been developed, which involves selectively patterning the doped regions on the battery surface to achieve heavy doping of the contact region and light doping of the non-contact region.

[0003] Currently, selective emitter technology includes secondary diffusion and doping paste printing. Secondary diffusion involves a first light doping diffusion to form a shallow junction, followed by a second heavy doping diffusion in the contact area. This process is cumbersome, involving multiple high-temperature doping preparations, limiting production capacity, incurring high thermal costs, and potentially damaging the silicon wafer. Doping paste printing involves screen printing a paste containing the dopant source to directly form heavy doping in the contact area. While this method simplifies some aspects of the process, it places extremely stringent requirements on the doping paste formulation, printing precision, and subsequent sintering process control. It is prone to problems such as uneven doping, increased PN junction leakage, or contamination of the cell surface, making it difficult to control product yield. Summary of the Invention

[0004] This disclosure provides a method for fabricating a solar cell to solve the problem that it is impossible to simultaneously reduce contact resistance and improve photoelectric conversion efficiency in the contact and non-contact areas.

[0005] In a first aspect, this disclosure provides a method for fabricating a solar cell, comprising: providing a substrate layer, the substrate layer including a light-receiving surface and a back-lighting surface disposed opposite to each other; forming a first doped semiconductor layer on the light-receiving surface of the substrate layer and forming a second doped semiconductor layer on the back-lighting surface of the substrate layer, the second doped semiconductor layer having a doping type opposite to that of the first doped semiconductor layer; at least one of the first doped semiconductor layer and the second doped semiconductor layer including alternately arranged contact regions and non-contact regions, the surface of the contact region being relatively convex to the surface of the non-contact region, the doping concentration of the contact region being greater than the doping concentration of the non-contact region, and an electrode structure being adapted to be disposed on the contact region; or, forming an alternately arranged first doped semiconductor layer and second doped semiconductor layer on the back-lighting surface of the substrate layer, the first doped semiconductor layer having a doping type opposite to that of the second doped semiconductor layer; the first doped semiconductor layer and the second doped semiconductor layer being configured as contact regions, and non-contact regions being formed between adjacent contact regions, the surface of the contact region being relatively convex to the surface of the non-contact region, the doping concentration of the contact region being greater than the doping concentration of the non-contact region; forming a first electrode and a second electrode, the first electrode being adapted to be connected to the first doped semiconductor layer, and the second electrode being adapted to be connected to the second doped semiconductor layer.

[0006] Beneficial effects: This disclosure utilizes photomasking technology to simultaneously achieve regional differentiation processing after the photopatterning masking step. It is divided into heavy doping treatment of the contact area and light doping or even no doping treatment of the non-contact area. The heavily doped contact area forms a good ohmic contact with the electrode structure, reducing the contact resistance. The lightly doped or even no-doped non-contact area can reduce parasitic absorption of short-wavelength light, thereby improving the open-circuit voltage and short-circuit current of the battery.

[0007] In some optional embodiments, forming the contact region and the non-contact region in the first doped semiconductor layer and / or the second doped semiconductor layer includes: forming an initial first semiconductor layer and / or an initial second semiconductor layer; doping the initial first semiconductor layer and the initial second semiconductor layer to obtain the initial first doped semiconductor layer and / or the initial second doped semiconductor layer; forming an initial shielding layer over the entire surface of the initial first doped semiconductor layer and / or the initial second doped semiconductor layer; patterning the initial shielding layer to form a shielding layer in a predetermined contact region in the initial first doped semiconductor layer and / or the initial second doped semiconductor layer, the shielding layer exposing a predetermined non-contact region; removing at least a portion of the thickness of the initial first doped semiconductor layer and / or the initial second doped semiconductor layer from the predetermined non-contact region to form the non-contact region and a contact region located between adjacent non-contact regions; and removing the shielding layer.

[0008] Beneficial effects: The contact area obtained by the above patterning process has highly doped elements, while the non-contact area has low-doped or even undoped elements. The highly doped contact area and the lightly doped or even undoped non-contact area form a high-performance selective emitter structure, which effectively reduces surface recombination and contact resistance, and improves the open-circuit voltage and fill factor of the battery.

[0009] In some alternative embodiments, the masking layer is configured as an inorganic masking layer or an organic masking layer, wherein the inorganic masking layer includes at least one of silicon nitride, silicon oxide, and aluminum oxide, and the organic masking layer includes at least one of photosensitive adhesive, wax, photosensitive polyimide, and etch-resistant paste.

[0010] Beneficial effects: This disclosure uses an inorganic or organic shielding layer as the shielding layer to achieve patterned processing of the shielding layer, reduce the difficulty of the process, and provide a good preparation environment for preparing lightly doped or even undoped non-contact regions while protecting the contact area.

[0011] In some alternative embodiments, a wet etching process is used to remove at least a portion of the thickness of the initial first doped semiconductor layer and / or the initial second doped semiconductor layer in the preset non-contact region, wherein the wet etching process uses an acidic solution.

[0012] Beneficial effects: This disclosure uses a wet etching process to remove at least a portion of the thickness of the initial first doped semiconductor layer and / or the initial second doped semiconductor layer in the preset non-contact area. It has good etching accuracy, and wet etching has no negative effect on the substrate layer, which can better protect the performance of the substrate layer, simplify the process, and reduce the process cost.

[0013] In some alternative implementations, the shielding layer is removed using organic solvents or plasma.

[0014] Beneficial effects: The present invention can effectively remove the shielding layer by means of organic solvent or plasma removal. The advantage of organic solvent removal is that it does not cause physical and chemical damage to the substrate layer, has a lower process difficulty, and is simple to operate. Compared with organic solvent removal, plasma removal has the advantage of leaving no residual liquid, which can better protect the morphology and structure of the film layer below the shielding layer.

[0015] In some optional embodiments, when a first doped semiconductor layer is formed on the light-receiving surface of the substrate and a second doped semiconductor layer is formed on the back-light-receiving surface of the substrate, forming the first doped semiconductor layer includes: forming an initial first semiconductor layer; performing a first surface treatment on one side surface of the initial first semiconductor layer to form a first textured structure on the surface of the initial first semiconductor layer; performing a doping treatment on the initial first semiconductor layer after the first surface treatment to form a first doped semiconductor layer; the first doped semiconductor layer is adapted to form the contact region and the non-contact region.

[0016] Beneficial effects: The method disclosed herein, which forms a first textured structure on the light-receiving surface of the substrate layer through a first surface treatment, greatly improves the light-trapping ability of the battery, thereby enhancing light absorption and the overall photoelectric conversion efficiency of the battery.

[0017] In some optional embodiments, after the second doped semiconductor layer is formed on the back surface of the substrate layer and before the first electrode and the second electrode are formed, the method further includes: performing a second surface treatment on the first doped semiconductor layer to form a second textured structure on the first textured structure, wherein the first textured structure and the second textured structure constitute a composite textured structure.

[0018] Beneficial effects: The addition of a second surface treatment in this disclosure can optimize the morphology of the damaged first textured surface structure, forming a composite textured surface structure and reducing reflectivity. On the other hand, the alkaline solution of the second surface treatment neutralizes the acidic solution remaining on the shielding layer, providing a good foundation for the subsequent deposition of the first passivation antireflection layer.

[0019] In some optional embodiments, the reflectivity of the first velvet structure ranges from 10% to 15%, and the reflectivity of the composite velvet structure ranges from 8% to 12%.

[0020] Beneficial effects: The present invention sets the reflectivity of the composite textured surface structure to be lower than that of the first textured surface structure, thereby reducing the reflection of incident light and improving the light trapping ability of the battery.

[0021] In some alternative embodiments, after obtaining the initial first doped semiconductor layer and / or the initial second doped semiconductor layer, and before forming an initial shielding layer over the entire surface of the initial first doped semiconductor layer and / or the initial second doped semiconductor layer, the method further includes: forming a first protective layer on the surface of the initial first doped semiconductor layer, and / or forming a second protective layer on the surface of the initial second doped semiconductor layer.

[0022] Beneficial effects: This disclosure protects the initial first doped semiconductor with a first protective layer and the initial second doped semiconductor layer with a second protective layer, thereby improving the coating effect of the initial shielding layer.

[0023] In some alternative implementations, the doping concentration of the non-contact region is greater than or equal to the doping concentration of the substrate layer.

[0024] Beneficial effects: If only a portion of the initial first doped semiconductor layer and / or the initial second doped semiconductor layer in the preset non-contact area is removed, the non-contact area still retains a portion of the initial first doped semiconductor layer and / or the initial second doped semiconductor layer. In this case, the doping concentration of the non-contact area is greater than the doping concentration of the substrate layer. If the entire thickness of the initial first doped semiconductor layer and / or the initial second doped semiconductor layer in the preset non-contact area is removed, thereby exposing the substrate layer, that is, the doping concentration of the non-contact area is equal to the doping concentration of the substrate layer. This disclosure achieves light doping or no doping treatment of the non-contact area through the above two different removal thicknesses, reducing parasitic absorption of short-wavelength light, thereby improving the open-circuit voltage and short-circuit current of the battery. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the specific embodiments of this disclosure or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0026] Figure 1 This diagram illustrates the structure after the formation of the first doped semiconductor layer in an embodiment of the present disclosure. Figure 2 This diagram illustrates the structure after an initial shielding layer is formed on the first doped semiconductor layer in an embodiment of this disclosure. Figure 3 This illustration shows a schematic diagram of the structure of the initial occlusion layer after graphical processing in an embodiment of this disclosure; Figure 4 This diagram illustrates the structure after removing a portion of the thickness from the first doped semiconductor layer in an embodiment of this disclosure. Figure 5 A schematic diagram of the structure after removing the shielding layer is shown in an embodiment of this disclosure; Figure 6 This diagram shows a structural schematic of the solar cell after fabrication in an embodiment of this disclosure. Figure 7 This diagram illustrates the structure after contact and non-contact regions are formed on the first and second doped semiconductor layers in an embodiment of this disclosure. Figure 8 A schematic diagram of the structure after removing the entire thickness of the first doped semiconductor layer is shown in an embodiment of this disclosure.

[0027] Explanation of reference numerals in the attached figures: 1. Substrate layer; 10. N-type silicon wafer; 2. First doped semiconductor layer; 20. P-type doped semiconductor layer; 3. Second doped semiconductor layer; 31. Tunneling oxide layer; 32. N-type doped semiconductor layer; 4. First passivation and antireflection layer; 5. Second passivation and antireflection layer; 6. First electrode; 7. Second electrode; a. Contact area; b. Non-contact area; A. Initial occlusion layer; B. Occlusion layer. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0029] like Figures 1 to 6 As shown, this disclosure provides a method for fabricating a solar cell, which can be used to fabricate back contact cells (BC cells), heterojunction cells (HJT cells), or tunnel oxide passivated contact cells (TOPCon cells). The method for fabricating this solar cell includes the following steps: S100 provides a substrate layer 1, which includes a light-receiving surface and a backlight surface disposed opposite to each other.

[0030] The substrate 1 can be an N-type silicon wafer 10, with the light-receiving surface being the light-receiving surface of the N-type silicon wafer 10 and the back-lighting surface being the back-lighting surface of the N-type silicon wafer 10.

[0031] S200, forming a first doped semiconductor layer 2 and a second doped semiconductor layer 3, wherein the doping type of the second doped semiconductor layer 3 is opposite to that of the first doped semiconductor layer 2.

[0032] One of the first doped semiconductor layer 2 and the second doped semiconductor layer 3 is configured as a P-type doped semiconductor layer 20, and the other is configured as an N-type doped semiconductor layer 32. The P-type doped semiconductor layer 20 is obtained by boron doping, and the N-type doped semiconductor layer 32 is obtained by phosphorus doping. This disclosure uses the example of the first doped semiconductor layer 2 being configured as a P-type doped semiconductor layer 20 and the second doped semiconductor layer 3 being configured as an N-type doped semiconductor layer 32 for illustration.

[0033] Forming a contact region a and a non-contact region b in the first doped semiconductor layer 2 and / or the second doped semiconductor layer 3 specifically includes the following steps: S211, forming an initial first semiconductor layer and / or an initial second semiconductor layer.

[0034] S212, the initial first semiconductor layer and the initial second semiconductor layer are doped to obtain the initial first doped semiconductor layer 2 and / or the initial second doped semiconductor layer 3.

[0035] S213, an initial shielding layer A is formed over the entire surface of the initial first doped semiconductor layer 2 and / or the initial second doped semiconductor layer 3.

[0036] S214, the initial shielding layer A is patterned to form a shielding layer B in a preset contact area a in the initial first doped semiconductor layer 2 and / or the initial second doped semiconductor layer 3, with the shielding layer B relatively exposed in a preset non-contact area b.

[0037] S215, remove at least a portion of the thickness of the initial first doped semiconductor layer 2 and / or the initial second doped semiconductor layer 3 in the preset non-contact region b to form the non-contact region b and the contact region a located between adjacent non-contact regions b.

[0038] For example, a wet etching process is used to remove at least a portion of the initial first doped semiconductor layer 2 and / or the initial second doped semiconductor layer 3 in a predetermined non-contact region b. The wet etching process uses an acidic solution. After removing at least a portion of the initial first doped semiconductor layer 2 and / or the initial second doped semiconductor layer 3 in the predetermined non-contact region b, not only is the thickness of the initial first doped semiconductor layer 2 and / or the initial second doped semiconductor layer 3 reduced, but the doping concentration in this region is also reduced, thereby forming a lightly doped or even undoped non-contact region b. This disclosure uses a wet etching process to remove at least a portion of the initial first doped semiconductor layer 2 and / or the initial second doped semiconductor layer 3 in the predetermined non-contact region b, which has good etching accuracy. Furthermore, wet etching has no negative effect on the substrate layer 1, effectively protecting the performance of the substrate layer 1, simplifying the process, and reducing process costs.

[0039] S216, Remove occlusion layer B.

[0040] For example, the shielding layer B can be removed using organic solvents or plasma. Both organic solvents and plasma removal methods can effectively remove the shielding layer B. The advantage of organic solvent removal is that it does not cause physical or chemical damage to the substrate layer 1, has lower process difficulty, and is simpler to operate. Compared with organic solvent removal, plasma removal has the advantage of leaving no residual liquid, which can better protect the film morphology and structure beneath the shielding layer B.

[0041] The shielding layer B is configured as an inorganic shielding layer or an organic shielding layer. The inorganic shielding layer includes at least one of silicon nitride, silicon oxide, and aluminum oxide, while the organic shielding layer includes at least one of photosensitive adhesive, wax spray, photosensitive polyimide, and anti-etching paste. This disclosure uses an inorganic or organic shielding layer as the shielding layer B to achieve patterning processing of the shielding layer B, reducing process difficulty and providing a favorable preparation environment for the lightly doped or even undoped non-contact region b while protecting the contact area a. Taking photosensitive adhesive as an example, photosensitive adhesive has high patterning precision, strong acid corrosion resistance, and a simple patterning process, thorough adhesive removal without residue, compatibility with mass production lines of related technologies, and low cost, which contributes to the industrialization of batteries.

[0042] In some embodiments, after obtaining the initial first doped semiconductor layer 2 and / or the initial second doped semiconductor layer 3, and before forming the initial shielding layer A over the entire surface of the initial first doped semiconductor layer 2 and / or the initial second doped semiconductor layer 3, the method further includes: A first protective layer is formed on the surface of the initial first doped semiconductor layer 2, and / or a second protective layer is formed on the surface of the initial second doped semiconductor layer 3. In this disclosure, the first protective layer can be configured as a borosilicate glass layer, and the second protective layer as a phosphosilicate glass layer. For example, the boron-doped first doped semiconductor layer 2 is subjected to high-temperature oxidation in an oxygen-containing atmosphere to advance the boron atom junction depth and simultaneously form a borosilicate glass layer on the surface. The formation of the phosphosilicate glass layer is similar and will not be described in detail here. Therefore, this disclosure protects the initial first doped semiconductor layer 2 with a first protective layer and the initial second doped semiconductor layer 3 with a second protective layer, thereby improving the coating effect of the initial shielding layer A.

[0043] Specifically, the initial first doped semiconductor layer 2 and / or the initial second doped semiconductor layer 3 are subjected to high-temperature oxidation treatment to form a first protective layer and / or a second protective layer. This disclosure improves the doping effect by advancing the junction depth of the doped elements through high-temperature oxidation treatment.

[0044] S300, a first passivation anti-reflection layer 4 and a second passivation anti-reflection layer 5 are formed. The first passivation anti-reflection layer 4 is formed on the side surface of the first doped semiconductor layer 2 that is opposite to the substrate layer 1, and the second passivation anti-reflection layer 5 is formed on the side surface of the second doped semiconductor layer 3 that is opposite to the substrate layer 1.

[0045] Before depositing the first passivation antireflection layer 4 and the second passivation antireflection layer 5, the N-type silicon wafer 10 is thoroughly cleaned using the RCA standard to remove organic contaminants and metal ions. Then, the first passivation antireflection layer 4 and the second passivation antireflection layer 5 are deposited using atomic layer deposition (ALD) and plasma-enhanced chemical vapor deposition (PECVD) processes. For example, the first passivation antireflection layer 4 includes a first alumina layer and a first silicon nitride layer, and the second passivation antireflection layer 5 includes a second alumina layer and a second silicon nitride layer. The first alumina layer and the second alumina layer are deposited using atomic layer deposition, and the first silicon nitride layer and the second silicon nitride layer are deposited using plasma-enhanced chemical vapor deposition.

[0046] S400, forming a first electrode 6 and a second electrode 7, the first electrode 6 being adapted to be connected to the first doped semiconductor layer 2, and the second electrode 7 being adapted to be connected to the second doped semiconductor layer 3.

[0047] It is worth noting that, in order to optimize the surface condition and ensure the ohmic contact performance between the first electrode 6 and the first doped semiconductor layer 2, and between the second electrode 7 and the second doped semiconductor layer 3, the first protective layer and the second protective layer need to be removed. The timing and method of removal will be explained in detail later.

[0048] The first electrode 6 and the second electrode 7 form an electrode structure. Specifically, through a screen printing sintering process or with the aid of a laser grooving process, the first electrode 6 passes through the first passivation antireflection layer 4 and is connected to the first doped semiconductor layer 2, and the second electrode 7 passes through the second passivation antireflection layer 5 and is connected to the second doped semiconductor layer 3.

[0049] In the battery prepared by the above steps, the doping concentration of the non-contact region b is greater than or equal to the doping concentration of the substrate layer 1. For example... Figure 5 and Figure 7 As shown, if only a portion of the initial first doped semiconductor layer 2 and / or the initial second doped semiconductor layer 3 of a predetermined thickness is removed from the non-contact region b, then the non-contact region b will still retain a portion of the initial first doped semiconductor layer 2 and / or the initial second doped semiconductor layer 3. In this case, the doping concentration of the non-contact region b is greater than the doping concentration of the substrate layer 1; as shown... Figure 7 and Figure 8 As shown, the entire thickness of the initial first doped semiconductor layer 2 and / or the initial second doped semiconductor layer 3 of the preset non-contact region b is removed, thereby exposing the substrate layer 1. That is, the doping concentration of the non-contact region b is equal to the doping concentration of the substrate layer 1.

[0050] In summary, this disclosure utilizes photomasking technology to simultaneously achieve regional differentiation processing after the photopatterning masking step. This involves heavily doping the contact region a and lightly doping or even undoped the non-contact region b. The heavily doped contact region a forms a good ohmic contact with the electrode structure, reducing contact resistance. The lightly doped or even undoped non-contact region b reduces parasitic absorption of short-wavelength light, thereby improving the battery's open-circuit voltage and short-circuit current. Furthermore, through the differentiation of doping concentration between the contact region a and the non-contact region b, the electrode structure connects to the heavily doped contact region a, while the lightly doped or even undoped non-contact regions b located on either side of the contact region a act as insulation, effectively reducing PN junction leakage.

[0051] In some optional embodiments, when the solar cell is a back-contact cell, in the fabrication method of the back-contact cell, a first doped semiconductor layer and a second doped semiconductor layer are alternately formed on the back surface of the substrate. The first doped semiconductor layer and the second doped semiconductor layer are configured as contact regions, and non-contact regions are formed between adjacent contact regions. The surface of the contact region protrudes relatively from the surface of the non-contact region, and the doping concentration of the contact region is greater than that of the non-contact region. For example, the substrate location where the first doped semiconductor layer is located is designated as a P-type region, the substrate location where the second doped semiconductor layer is located is designated as an N-type region, and the substrate location where the non-contact region is located is designated as an isolation region.

[0052] Back-contact batteries can be tunnel oxide passivated back-contact batteries (TBC batteries), heterojunction back-contact batteries (HBC batteries), hybrid passivated back-contact batteries (HTBC batteries), etc. Taking a tunnel oxide passivated back-contact battery as an example, a first doped semiconductor layer and a second doped semiconductor layer are alternately formed on the back surface of an N-type silicon wafer. The first doped semiconductor layer is configured as a combination of a first tunnel oxide layer and a P-type doped semiconductor layer, and the second doped semiconductor layer is configured as a combination of a second tunnel oxide layer and an N-type doped semiconductor layer. A contact area and a non-contact area are formed in the first and second doped semiconductor layers. Specifically, the following steps are included: forming an initial first tunnel oxide layer and an initial first amorphous silicon semiconductor layer on the back surface of the N-type silicon wafer. The initial first tunnel oxide layer and the initial amorphous silicon semiconductor layer constitute the initial first semiconductor layer. The bulk layer is boron-doped to obtain a P-type doped semiconductor layer. An initial masking layer is formed on the entire surface of the P-type doped semiconductor layer. The initial masking layer is patterned to form a masking layer in the P-type region. Then, the P-type doped semiconductor layer in the N-type region and the isolation region is removed. The initial second tunneling oxide layer and the initial second amorphous silicon semiconductor layer are deposited. The initial second tunneling oxide layer and the initial second amorphous silicon semiconductor layer constitute the initial second semiconductor layer. The initial second semiconductor layer is phosphorus-doped to obtain an N-type doped semiconductor layer. An initial masking layer is formed on the entire surface of the N-type doped semiconductor layer. The initial masking layer is patterned to form a masking layer in the N-type region. Then, the N-type doped semiconductor layer in the P-type region and the isolation region is removed. When removing the N-type doped semiconductor layer in the P-type region and the isolation region, the borosilicate glass layer on the P-type region is also removed. Finally, the phosphosilicate glass layer is removed using a chain-type phosphosilicate glass removal device.

[0053] In some alternative embodiments, when the solar cell is a heterojunction cell, the fabrication method of the heterojunction cell firstly forms a first doped semiconductor layer on the light-receiving surface of the substrate, and then forms a second doped semiconductor layer on the backlight surface of the substrate. The formation of the contact area and the non-contact area can be carried out using the following three processes: the first process is to form the contact area and the non-contact area on the first doped semiconductor layer; the second process is to form the contact area and the non-contact area on the second doped semiconductor layer; and the third process is to form the contact area and the non-contact area on both the first doped semiconductor layer and the second doped semiconductor layer.

[0054] In some alternative embodiments, when the solar cell described above is a tunneling oxide passivated contact cell, such as Figures 1 to 6As shown, in the method for preparing the tunneling oxide passivated contact cell, a first doped semiconductor layer 2 is first formed on the light-receiving surface of the substrate layer 1, and then a second doped semiconductor layer 3 is formed on the backlight surface of the substrate layer 1. At least one of the first doped semiconductor layer 2 and the second doped semiconductor layer 3 includes alternately arranged contact regions a and non-contact regions b. The surface of the contact region a protrudes relatively from the surface of the non-contact region b, and the doping concentration of the contact region a is greater than the doping concentration of the non-contact region b.

[0055] Specifically, a first doped semiconductor layer 2 is formed on the light-receiving surface of the N-type silicon wafer 10, and the first doped semiconductor layer 2 is configured as a P-type doped semiconductor layer 20. A second doped semiconductor layer 3 is formed on the back-lighting surface of the N-type silicon wafer 10, and the second doped semiconductor layer 3 is configured as a combined film layer of a tunneling oxide layer 31 and an N-type doped semiconductor layer 32. Based on this, the following description uses the formation of a contact region a and a non-contact region b in the first doped semiconductor layer 2 as an example, specifically including the following steps: like Figure 1 As shown, an initial first semiconductor layer is formed on the light-receiving surface of the N-type silicon wafer 10, and then the initial first semiconductor layer is subjected to boron doping treatment to obtain a P-type doped semiconductor layer 20. like Figure 2 As shown, an initial shielding layer A is formed over the entire surface of the P-type doped semiconductor layer 20; like Figure 3 As shown, the initial shielding layer A is patterned to form the shielding layer B in the preset contact area a in the P-type doped semiconductor layer 20. like Figure 4 As shown, at least a portion of the thickness of the P-type doped semiconductor layer 20 in the preset non-contact region b is removed; like Figure 5 As shown, remove the occlusion layer B.

[0056] It is understandable that after removing the shielding layer B, the process also includes polishing the N-type silicon wafer 10 to remove the borosilicate glass layer remaining in the contact area a; and removing the phosphosilicate glass layer using a chain-type phosphosilicate glass layer removal device before depositing the second passivation antireflection layer 5.

[0057] The contact region a obtained by the above patterning process has highly doped elements, while the non-contact region b has low-doped or even undoped elements. The highly doped contact region a and the lightly doped or even undoped non-contact region b form a high-performance selective emitter structure, which effectively reduces surface recombination and contact resistance, and improves the open-circuit voltage and fill factor of the battery.

[0058] In some other embodiments, such as Figure 7As shown, similarly, contact region a and non-contact region b can be formed in the second doped semiconductor layer 3. This preparation step is similar to the preparation step of forming contact region a and non-contact region b in the first doped semiconductor layer 2, and will not be repeated here.

[0059] like Figure 1 As shown, when a first doped semiconductor layer 2 is formed on the light-receiving surface of the substrate 1 and a second doped semiconductor layer 3 is formed on the backlight-receiving surface of the substrate 1, the formation of the first doped semiconductor layer 2 includes the following steps: forming an initial first semiconductor layer; performing a first surface treatment on one side surface of the initial first semiconductor layer to form a first textured structure on the surface of the initial first semiconductor layer; performing a doping treatment on the initial first semiconductor layer after the first surface treatment to form the first doped semiconductor layer 2; the first doped semiconductor layer 2 is adapted to form a contact region a and a non-contact region b. This method of forming a first textured structure on the light-receiving surface of the substrate 1 through a first surface treatment significantly improves the light-trapping ability of the battery, thereby enhancing light absorption and the overall photoelectric conversion efficiency of the battery.

[0060] like Figure 1 , Figure 4 and Figure 6 As shown, after the second doped semiconductor layer 3 is formed on the back surface of the substrate layer 1, and before the first electrode 6 and the second electrode 7 are formed, the method further includes: performing a second surface treatment on the first doped semiconductor layer 2 to form a second textured structure on the first textured structure, wherein the first textured structure and the second textured structure constitute a composite textured structure.

[0061] Specifically, both the second and first surface treatments can be performed using alkaline solutions. After the first surface treatment, this disclosure uses an acidic liquid to etch a portion of the initial first doped semiconductor layer 2 and / or the initial second doped semiconductor layer 3 in the pre-defined non-contact area b. Therefore, the first textured structure on the non-contact area b is corroded by the acidic solution, resulting in morphological damage. Although the contact area a is protected by the shielding layer B and will not be corroded, the acidic solution may still remain on the shielding layer B. This disclosure adds a second surface treatment, which on the one hand can optimize the morphology of the damaged first textured structure and form a composite textured structure, thereby reducing reflectivity. On the other hand, the alkaline solution of the second surface treatment neutralizes the acidic solution remaining on the shielding layer B, providing a good foundation for the subsequent deposition of the first passivation antireflection layer 4.

[0062] For example, the reflectivity of the first textured surface structure ranges from 10% to 15%, such as 10%, 13%, 15%, etc., while the reflectivity of the composite textured surface structure ranges from 8% to 12%, such as 8%, 10%, 12%, etc. This disclosure sets the reflectivity of the composite textured surface structure to be lower than that of the first textured surface structure, thereby reducing the reflection of incident light and improving the light-trapping capability of the battery.

[0063] The following description uses the specific fabrication process of a tunnel oxide passivated contact battery as an example.

[0064] Example 1 like Figure 5 As shown, in Example 1, the non-contact region b of the battery is lightly doped, and the solar cell fabrication method includes the following steps: like Figure 1 As shown, the light-receiving surface of the N-type silicon wafer 10 is first treated with an alkaline solution to form a first textured surface structure, and the reflectivity of the first textured surface structure is in the range of 10% to 15%.

[0065] An N-type silicon wafer 10 is placed in a tube diffusion furnace for boron doping. The doping temperature range is 900~1000℃ and the doping time is 30~90 min, resulting in a P-type doped semiconductor layer 20 with a sheet resistance range of 60~100 Ω / sq.

[0066] High-temperature oxidation is performed in an oxygen-containing atmosphere, with a process temperature range of 950~1050 ℃ and an oxidation time of 20~60 min, so that the boron atom junction depth reaches 0.3~1.0 μm, and a borosilicate glass layer is formed on the surface of the P-type doped semiconductor layer 20.

[0067] like Figure 2 and Figure 3 As shown, positive photosensitive adhesive is coated on the front side of the light-receiving surface, and then patterned by photomask. Only the positive photosensitive adhesive is retained as a mask in the preset contact area a, with a line width of 30~60 μm, while the positive photosensitive adhesive in the preset non-contact area b is removed.

[0068] like Figure 4 As shown, an acidic solution is used to remove at least a portion of the thickness of the borosilicate glass layer and the P-type doped semiconductor layer 20 in the preset non-contact region b, thereby reducing the doping concentration of the non-contact region b to a light doping concentration. The sheet resistance of the non-contact region b is in the range of 120~200 Ω / sq. Under the protection of the positive photosensitive adhesive, the borosilicate glass layer and the P-type doped semiconductor layer 20 of the contact region a are retained. Compared with the sheet resistance of the contact region a, the sheet resistance of the non-contact region b is larger and the conductivity is weaker. The acidic solution can be a hydrofluoric acid solution with a volume fraction of 5%~10% and an etching time of 20~50 s.

[0069] like Figure 5 As shown, residual photosensitive adhesive is removed using organic solvents or plasma, followed by surface polishing to remove the damaged layer. The polishing thickness is 0.1~0.5 μm, optimizing the surface condition.

[0070] like Figure 6 As shown, a tunneling oxide layer 31 and an intrinsic amorphous silicon layer are sequentially prepared on the back surface of an N-type silicon wafer 10. The thickness of the tunneling oxide layer 31 is 1.2~2.0 nm, and the thickness of the intrinsic amorphous silicon layer is 80~200 nm. The intrinsic amorphous silicon layer is subjected to phosphorus doping and crystallization by a high-temperature annealing process. The annealing temperature range is 800~900 ℃, and the annealing time is 10~60 min, resulting in an N-type doped semiconductor layer 32 and a phosphorus silicon glass layer. The sheet resistance of the N-type doped semiconductor layer 32 is 30~80 Ω / sq.

[0071] The phosphorus silicate glass layer on the back surface is removed using an acidic solution, which can be a hydrofluoric acid solution with a volume fraction of 5% to 10% and an etching time of 30 to 90 seconds, followed by surface cleaning.

[0072] An alkaline solution is used to perform a second surface treatment on the light-receiving surface of the N-type silicon wafer 10 to form a second textured surface structure. The second textured surface structure and the first textured surface structure constitute a composite textured surface structure, which optimizes the surface morphology and enhances light absorption. The reflectivity of the composite textured surface structure ranges from 8% to 12%.

[0073] The N-type silicon wafer 10 was thoroughly cleaned using the RCA standard, with a cleaning temperature of 70~85 ℃ and a cleaning time of 5~15 min.

[0074] A first alumina layer is deposited on the light-receiving surface of an N-type silicon wafer 10 using atomic layer deposition (ALD), and a second alumina layer is deposited on the back-light-receiving surface of the N-type silicon wafer 10. A first silicon nitride layer is deposited on the light-receiving surface of the N-type silicon wafer 10 using plasma-enhanced chemical vapor deposition (PECVD), and a second silicon nitride layer is deposited on the back-light-receiving surface of the N-type silicon wafer 10. The thicknesses of the first and second alumina layers range from 2 to 5 nm, the thicknesses of the first and second silicon nitride layers range from 70 to 90 nm, and the refractive indices range from 1.9 to 2.1. The first alumina layer and the first silicon nitride layer constitute a first passivation antireflection layer 4, and the second alumina layer and the second silicon nitride layer constitute a second passivation antireflection layer 5.

[0075] Silver paste is printed on the light-receiving surface and the backlight surface respectively. After sintering, a first electrode 6 and a second electrode 7 are formed. The first electrode 6 passes through the first passivation antireflection layer 4 and is connected to the contact area a. The second electrode 7 passes through the second passivation antireflection layer 5 and is connected to the N-type doped semiconductor layer 32. The peak sintering temperature range is 730~840 ℃ and the sintering time is 1~5s.

[0076] Example 2 like Figure 8 As shown, in Example 2, the non-contact region b is undoped. The difference between this solar cell fabrication method and that of Example 1 lies in the fact that, when using an acidic solution to remove at least a portion of the thickness of the borosilicate glass layer and the P-type doped semiconductor layer 20 in the predetermined non-contact region b, the volume fraction of the hydrofluoric acid solution is 5%~15%, and the etching time is 50~120s. Therefore, the thickness removed from the non-contact region b in Example 2 is greater than that removed from the non-contact region b in Example 1, and the N-type silicon wafer 10 is exposed in the non-contact region b in Example 2.

[0077] Comparative Example The fabrication process parameters of the comparative battery are the same as those of the battery in Example 1. The difference is that the non-contact region b is normally doped, that is, the borosilicate glass layer and the P-type doped semiconductor layer 20 of the preset thickness are not removed from the non-contact region b.

[0078] Based on this, the electrical performance of the batteries from Example 1, Example 2, and the comparative example was tested, and the data are shown in the table below:

[0079] As shown in the table above, the batteries of Example 1 and Example 2 outperform the comparative example in all current performance parameters, including photoelectric conversion efficiency (Eta), open-circuit voltage (Uoc), short-circuit current (Isc), fill factor (FF), and parallel resistance (Rsh). Furthermore, the series resistance (R) of the batteries of Example 1 and Example 2 is significantly lower. S The values ​​are all smaller than those of the comparative example, meaning that the design of reducing the doping concentration in the non-contact region b of both Example 1 and Example 2 cells can effectively improve the cell efficiency of solar cells.

[0080] Although embodiments of the present disclosure have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present disclosure, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A method for preparing a solar cell, characterized in that, include: A substrate layer is provided, the substrate layer comprising a light-receiving surface and a backlight surface disposed opposite to each other; A first doped semiconductor layer is formed on the light-receiving surface of the substrate, and a second doped semiconductor layer is formed on the back-light-receiving surface of the substrate. The doping type of the second doped semiconductor layer is opposite to that of the first doped semiconductor layer. At least one of the first and second doped semiconductor layers includes alternating contact regions and non-contact regions. The surface of the contact region protrudes relative to the surface of the non-contact region. The doping concentration of the contact region is greater than that of the non-contact region. An electrode structure is suitable for being disposed on the contact region. Alternatively, an alternating first and second doped semiconductor layers are formed on the back-light-receiving surface of the substrate. The doping type of the first and second doped semiconductor layers is opposite to that of the second doped semiconductor layer. The first and second doped semiconductor layers are configured as contact regions, and non-contact regions are formed between adjacent contact regions. The surface of the contact region protrudes relative to the surface of the non-contact region. The doping concentration of the contact region is greater than that of the non-contact region. A first electrode and a second electrode are formed, wherein the first electrode is adapted to be connected to the first doped semiconductor layer, and the second electrode is adapted to be connected to the second doped semiconductor layer.

2. The method for preparing a solar cell according to claim 1, characterized in that, Forming the contact region and the non-contact region in the first doped semiconductor layer and / or the second doped semiconductor layer includes: Forming an initial first semiconductor layer and / or an initial second semiconductor layer; The initial first semiconductor layer and the initial second semiconductor layer are doped to obtain an initial first doped semiconductor layer and / or an initial second doped semiconductor layer; An initial shielding layer is formed over the entire surface of the initial first doped semiconductor layer and / or the initial second doped semiconductor layer; The initial shielding layer is patterned to form a shielding layer in a preset contact area in the initial first doped semiconductor layer and / or the initial second doped semiconductor layer, wherein the shielding layer is relatively exposed in a preset non-contact area. At least a portion of the thickness of the initial first doped semiconductor layer and / or the initial second doped semiconductor layer in the preset non-contact area is removed to form the non-contact area and the contact area located between adjacent non-contact areas; Remove the masking layer.

3. The method for preparing a solar cell according to claim 2, characterized in that, The shielding layer is configured as an inorganic shielding layer or an organic shielding layer. The inorganic shielding layer includes at least one of silicon nitride, silicon oxide, and aluminum oxide. The organic shielding layer includes at least one of photosensitive adhesive, spray wax, photosensitive polyimide, and anti-etching paste.

4. The method for preparing a solar cell according to claim 2, characterized in that, The initial first doped semiconductor layer and / or the initial second doped semiconductor layer, with at least a portion of their thickness, in the preset non-contact area are removed using a wet etching process employing an acidic solution.

5. The method for preparing a solar cell according to claim 2, characterized in that, The shielding layer is removed using organic solvents or plasma.

6. The method for preparing a solar cell according to claim 1 or 2, characterized in that, When a first doped semiconductor layer is formed on the light-receiving surface of the substrate layer, and a second doped semiconductor layer is formed on the back-light-receiving surface of the substrate layer, forming the first doped semiconductor layer includes: Forming the initial first semiconductor layer; A first surface treatment is performed on one side surface of the initial first semiconductor layer to form a first textured structure on the surface of the initial first semiconductor layer; The initial first semiconductor layer after the first surface treatment is doped to form a first doped semiconductor layer; the first doped semiconductor layer is adapted to form the contact region and the non-contact region.

7. The method for preparing a solar cell according to claim 6, characterized in that, After forming the second doped semiconductor layer on the back surface of the substrate, and before forming the first electrode and the second electrode, the method further includes: The first doped semiconductor layer is subjected to a second surface treatment to form a second textured structure on the first textured structure, and the first textured structure and the second textured structure constitute a composite textured structure.

8. The method for preparing a solar cell according to claim 7, characterized in that, The reflectivity of the first velvet structure ranges from 10% to 15%, and the reflectivity of the composite velvet structure ranges from 8% to 12%.

9. The method for preparing a solar cell according to claim 2, characterized in that, After obtaining the initial first doped semiconductor layer and / or the initial second doped semiconductor layer, and before forming an initial shielding layer over the entire surface of the initial first doped semiconductor layer and / or the initial second doped semiconductor layer, the method further includes: A first protective layer is formed on the surface of the initial first doped semiconductor layer, and / or a second protective layer is formed on the surface of the initial second doped semiconductor layer.

10. The method for preparing a solar cell according to any one of claims 1 to 5, characterized in that, The doping concentration of the non-contact region is greater than or equal to the doping concentration of the substrate layer.

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