Wafer positioning method

Abstract

The application discloses a wafer positioning method, which comprises the following steps: acquiring position information of a pin trace left on a bearing film when a pin lifts up a chip, the pin trace having a preset position corresponding relationship with the chip; selecting position information of one pin trace as a reference point; according to a theoretical size of the chip, performing at least one step movement along each row arrangement direction of the chip array with the reference point as a starting point; determining an actual physical interval of the chip array according to a moving distance; taking the reference point as an origin, determining actual coordinate positions of each chip in the chip array according to the actual physical interval, and performing a suction operation of the chip according to the actual coordinate positions. The method helps to eliminate the dependence on a physical cutting path, so that accurate positioning and normal operation can be realized even in the case of missing, blurred or unrecognizable cutting path.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a method for positioning a wafer. Background Technology

[0002] In semiconductor wafer dicing and picking processes, multiple chips are arranged on a wafer, with dicing tracks between adjacent chips. Existing picking machines rely on visual positioning logic to identify the physical dicing tracks on the wafer surface when performing chip picking operations. Specifically, in areas with chips, positioning is based on the chip's location; in areas without chips, positioning is based on the dicing tracks. By identifying features such as the extension direction and spacing of the dicing tracks, the precise coordinates of each chip are determined, thereby guiding the nozzle to move sequentially and pick up the chips.

[0003] However, this positioning method, which relies heavily on a single physical marker, has inherent technical flaws. With the development of semiconductor manufacturing processes, non-blade-cut products (such as those using laser stealth cutting) are becoming increasingly common. These products do not leave obvious cutting marks on the wafer surface after cutting and separation, and may not even have visually identifiable cutting patterns. When such materials enter the picking machine, the vision system cannot capture the cutting pattern image, making positioning impossible via either the chip area or the cutting pattern. This triggers a positioning failure alarm, causing the entire picking operation to be interrupted and the equipment to malfunction. Furthermore, even for traditionally blade-cut products, the cutting pattern may become blurred or difficult to reliably identify due to process fluctuations, surface contamination, or film coverage, similarly leading to positioning failures. Summary of the Invention

[0004] One of the objectives of this invention is to provide a wafer positioning method to solve the technical problem in the prior art where the picking machine relies on the dicing track as a positioning reference, resulting in the inability to achieve accurate positioning and normal picking operation when the dicing track is missing or cannot be identified.

[0005] To achieve one of the aforementioned objectives, this invention provides a wafer positioning method, wherein the wafer is arranged with a chip array comprising multiple chips. The method comprises: acquiring position information of ejector pin marks left on a carrier film when ejector pins lift the chips, wherein the ejector pin marks have a preset positional correspondence with the chips; selecting the position information of one ejector pin mark as a reference point, and, based on the theoretical dimensions of the chips, performing at least one step movement along each arrangement direction of the chip array, starting from the reference point, and determining the actual physical spacing of the chip array based on the movement distance; using the reference point as the origin, determining the actual coordinate positions of each chip in the chip array based on the actual physical spacing, and performing chip picking operations according to the actual coordinate positions.

[0006] In an exemplary embodiment, obtaining the location information of the pin mark left on the carrier film when the pin lifts the chip includes: obtaining a detection image of the carrier film; determining a region whose difference satisfies a first preset condition as a candidate pin mark region based on the difference between the pixel value in the detection image and the pixel value in the background region; and determining the location information of the pin mark based on the candidate pin mark region when the geometric features of the candidate pin mark region satisfy a second preset condition.

[0007] In an exemplary embodiment, determining the region whose difference satisfies a first preset condition as a candidate pin mark region based on the difference between the pixel value in the detected image and the pixel value in the background region includes: taking the region composed of pixels in the detected image whose grayscale value is lower than a preset grayscale threshold as the candidate pin mark region.

[0008] In an exemplary embodiment, when the geometric features of the candidate pin mark region satisfy a second preset condition, determining the position information of the pin mark based on the candidate pin mark region includes: obtaining the coordinate information of at least three points on the edge contour of the candidate pin mark region; determining whether the contour of the candidate pin mark region is circular based on the coordinate information of the at least three points; if so, determining the position information of the pin mark based on the geometric center position of the candidate pin mark region.

[0009] In an exemplary embodiment, there are multiple ejector pins. The step of obtaining the position information of the ejector pin marks left on the carrier film when the ejector pins lift the chip includes: obtaining the position information of multiple ejector pin marks left on the carrier film when multiple ejector pins lift the same chip at the same time; determining the geometric center position of the multiple ejector pin marks based on the position information of the multiple ejector pin marks, and using the geometric center position as the ejector pin mark position information corresponding to the chip.

[0010] In one exemplary embodiment, the reference point is selected as the pin mark corresponding to the chip located in the central region of the chip array.

[0011] In an exemplary embodiment, the step of performing at least one step movement along each arrangement direction of the chip array and determining the actual physical spacing of the chip array based on the movement distance includes: performing at least one step movement along each arrangement direction of the chip array, and obtaining position information of the pin marks at the location after each step movement in each arrangement direction; and determining the actual physical spacing of the chip array based on the distance between the reference point and the pin marks obtained after the movement.

[0012] In an exemplary embodiment, the step of performing at least one step movement along each arrangement direction of the chip array and obtaining the position information of the pin marks at the current position after each step movement includes: performing M step movements and N step movements along the first direction and the second direction of the chip array, respectively, and obtaining the position information of the pin marks at the current position after each step movement; wherein M and N are both positive integers greater than or equal to 1; the step of determining the actual physical spacing of the chip array based on the distance between the reference point and the pin marks obtained after the movement includes: determining the distance between the reference point and the pin marks obtained after the movement. The first total distance between the ejector pin marks after the Mth step movement in the first direction and the second total distance between the reference point and the ejector pin marks after the Nth step movement in the second direction, wherein the first direction is the lateral arrangement direction of the chip array, the second direction is the longitudinal arrangement direction of the chip array, and the first direction and the second direction are perpendicular to each other; the corresponding actual physical spacing in the first direction and the actual physical spacing in the second direction are determined according to the ratio of the first total distance to the number of step movements M and the ratio of the second total distance to the number of step movements N.

[0013] In an exemplary embodiment, before performing M and N step movements along the first and second directions of the chip array, respectively, the method further includes: obtaining the theoretical dimensions of the chip, the theoretical dimensions including the theoretical lateral dimensions and the theoretical longitudinal dimensions of the chip; determining the theoretical step size for a single step in the first direction based on the theoretical lateral dimensions; determining the theoretical step size for a single step in the second direction based on the theoretical longitudinal dimensions; the step of performing M and N step movements along the first and second directions of the chip array, respectively, includes: performing M step movements in the first direction according to the theoretical step size in the first direction, and performing N step movements in the second direction according to the theoretical step size in the second direction.

[0014] In an exemplary embodiment, determining the actual coordinate position of each chip in the chip array based on the reference point as the origin and the actual physical spacing includes: generating a virtual grid distribution corresponding to the chip array with the reference point as the origin and the actual physical spacing in the first direction and the actual physical spacing in the second direction as the horizontal and vertical unit steps, respectively; and determining the actual coordinate position of each chip in the chip array based on the virtual grid distribution.

[0015] Compared with the prior art, the embodiments of the present invention have at least one of the following beneficial effects:

[0016] This invention employs a wafer positioning method that utilizes the ejector pin marks left on the carrier film when a chip is lifted by ejector pins as positioning markers. Based on the fixed correspondence between these markers and the chips, the ejector pin marks replace the physical dicing lines relied upon in traditional methods as the positioning reference, eliminating the dependence of the positioning process on the existence or identifiability of the dicing lines. Furthermore, by performing at least one step movement starting from the reference point and measuring the movement distance, the true physical spacing of the chip array in its current state is actively calibrated and obtained. This ensures that the obtained actual physical spacing accurately reflects the actual spatial relationship between the chips on the wafer, ultimately generating a virtual grid distribution. This is a positioning coordinate system with both a true origin and a true scale, enabling the nozzle to perform precise step movement and pick-up operations according to coordinates that match the actual chip arrangement without relying on physical dicing lines. This method helps eliminate dependence on physical dicing lines, enabling accurate positioning and normal operation even when dicing lines are missing, blurred, or unidentifiable. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a wafer structure with a chip array arranged in one embodiment of the present invention.

[0018] Figure 2 This is a schematic diagram of the structure of single and multiple ejector pins producing ejector pin marks in one embodiment of the present invention.

[0019] Figure 3 This is a schematic diagram of the steps of a wafer positioning method according to an embodiment of the present invention.

[0020] Figure 4 This is a schematic diagram of a structure in which stepping movement is performed based on a reference point in the first and second directions according to an embodiment of the present invention.

[0021] Figure 5 This is a schematic diagram of step S2 in one embodiment of the present invention.

[0022] Figure 6 This is a schematic diagram of the virtual grid distribution structure in one embodiment of the present invention. Detailed Implementation

[0023] The present invention will now be described in detail with reference to the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, methodological, or functional modifications made by those skilled in the art based on these embodiments are included within the scope of protection of the present invention.

[0024] It should be noted that the term "comprising" or any other variation thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0025] One embodiment of the present invention provides a wafer positioning method. This method is applicable to wafer picking machines in semiconductor testing processes. Figure 1 As shown, a chip array is arranged on a wafer, and the chip array contains multiple chips. The chips are arranged regularly on the wafer, and dicing lines are usually provided between adjacent chips. However, in non-diced products, dicing lines may be missing or unidentifiable. The method of the present invention does not rely on dicing lines for positioning, but uses the set of ejector pin marks generated during the chip ejection process as a positioning reference.

[0026] After semiconductor wafers are diced, the chips remain attached to a carrier film. This carrier film, also known as a dicing film or UV (Ultraviolet Curing Film), is an adhesive thin film. One side is adhered to the bottom of the chip, and the other side is fixed to the wafer frame. It is used to hold the chips in their original positions after dicing, preventing them from scattering. The carrier film is transparent or semi-transparent and has the physical property of being puncturable or dentable.

[0027] During the picking process, when a chip needs to be picked up, the ejector pin moves upward from below the carrier film. The tip of the ejector pin contacts the lower surface of the carrier film and lifts the chip from below, causing a partial detachment of the chip from the carrier film, making it easier for the nozzle to pick it up from above. During this lifting process, the tip of the ejector pin leaves a tiny indentation on the surface of the carrier film; this indentation is called the ejector pin mark (corresponding to...). Figure 1 Point B in the diagram). Because the ejector pin rises from directly below the chip, there is a fixed geometric correspondence between the position of the ejector pin mark and the position of the chip.

[0028] Specifically, when a single ejector pin is used, the center of the pin mark coincides with the center of the chip. When multiple ejector pins (e.g., four pins arranged in a square) simultaneously lift the same chip, the geometric centers of the multiple pin marks coincide with the chip center. In an alternative approach, the ejector pin's mounting position can also have a known fixed offset relative to the chip center. In this case, there is also a known fixed offset relationship between the pin mark and the chip center. As long as this offset is known and constant, the pin mark position can be converted to the chip center position through coordinate transformation, such as... Figure 2 As shown.

[0029] like Figure 3 As shown, one embodiment of the present invention provides a wafer positioning method, specifically including the following steps: Step S1: Obtain the position information of the ejector pin marks left on the carrier film when the ejector pin lifts the chip. The ejector pin marks and the chip have a preset positional correspondence.

[0030] Step S2: Select the position information of one of the pin marks as the reference point. Based on the theoretical size of the chip, take the reference point as the starting point and move at least once along each arrangement direction of the chip array. Determine the actual physical spacing of the chip array based on the moving distance.

[0031] Step S3: Using the reference point as the origin, determine the actual coordinate position of each chip in the chip array according to the actual physical spacing, and perform chip picking operation according to the actual coordinate position.

[0032] Thus, by utilizing the ejector pin marks left on the carrier film during chip lifting as positioning markers, and based on the inherent and fixed correspondence between these markers and the chips, the ejector pin marks replace the physical dicing lines relied upon in traditional solutions as the positioning reference. This effectively avoids the positioning process's dependence on the existence or identifiability of dicing lines. Furthermore, using the selected ejector pin mark location as a reference point, by performing at least one step movement and measuring the movement distance, the true physical spacing of the chip array in its current state is calibrated and obtained. This helps overcome the inconsistency between theoretical dimensions and actual arrangement caused by process deviations, carrier film stretching, and other factors, ensuring that the obtained actual physical spacing truly reflects the actual spatial relationship between chips on the current wafer.

[0033] Simultaneously, by using the reference point as the origin and the actual physical distance as the unit step size, the coordinate position of the chips in the chip array in actual space can be determined. Since this coordinate position is calculated based on real physical measurements, it perfectly matches the actual spatial arrangement of the chips on the carrier film. The nozzle moves and picks up chips according to this actual coordinate position, ensuring precise positioning and normal operation even if the cutting path is missing, blurred, or unidentifiable. Furthermore, this method requires no additional hardware, utilizes the inherent pin marks in the existing process flow as a positioning resource, exhibits good compatibility with existing picking machines, and has low implementation costs.

[0034] In this embodiment, different materials and models of carrier films have varying abilities to retain pin marks. To ensure the reliability of the method described in this invention during actual operation, the positioning and pick-up operations need to be completed within the effective retention time of the pin marks. For example, D-185 or D-485 type UV films, after placement time verification, show that pin marks will not disappear within a 48-hour effective retention time, while the retention time of D-147 type UV film has been verified to be 24 hours. That is, the wafer two-point positioning and pick-up operations are completed within 24 hours from the formation of the pin marks. For novel carrier films that have not been used before, pin marks can be pre-formed on the carrier film to be imported, and detection images of the carrier film can be acquired at preset time intervals. The effective retention time of the pin marks on the carrier film can be determined by the identifiable state of the pin marks in the detection images, thereby setting corresponding control time limits during formal operation to ensure that the operation is completed within the effective period of the pin marks.

[0035] Furthermore, the clarity of the pin marks varies depending on the chip size and the material of the carrier film. For carrier films that are harder or less prone to indentation, the quality of the marks can be improved by adjusting the tip radius of the pin, while keeping the lifting pressure constant. According to the pressure formula P=F / S, with a fixed pin lifting pressure F, the smaller the contact area S, the greater the pressure P, and the greater the local pressure exerted by the pin tip on the carrier film, thus making it easier to form clear and identifiable marks.

[0036] To address this, one specific embodiment provides various pins with different tip radii, such as R=0.1mm, R=0.06mm, R=0.05mm, R=0.035mm, and R=0.025mm. When the carrier film has high hardness or the marks are not obvious, pins with smaller tip radii (e.g., R=0.035mm or R=0.025mm) can be selected to reduce the contact area and increase the pressure, thereby forming sufficiently clear pin marks on the carrier film that can be stably identified by the vision system. When the carrier film has low hardness and is prone to leaving marks, or when the chip is thin and has weak pressure resistance, pins with larger tip radii (e.g., R=0.1mm) can be selected to increase the contact area and reduce the pressure, avoiding excessive damage to the carrier film or hidden damage to the chip due to excessive pressure.

[0037] Meanwhile, the lifting height of the ejector pin can be adaptively set according to the chip size and the material of the carrier film. For example, for larger chips or thicker carrier films, the lifting height can be appropriately increased to ensure sufficient separation between the chip and the carrier film. For smaller chips or thinner carrier films, the lifting height can be appropriately decreased. Through the above ejector pin selection and parameter settings, the chip safety and carrier film protection can be balanced while ensuring that ejector pin marks are identifiable, based on the actual chip size and carrier film material of the product.

[0038] In this embodiment, the location information of the pin marks can be obtained through a visual recognition system. The visual recognition system includes an image acquisition device mounted above the picking machine, such as a CCD (Charge Coupled Device) camera or a CMOS (Complementary Metal-Oxide Semiconductor) camera. This image acquisition device can capture inspection images of the carrier film, which include images of the pin marks on the carrier film.

[0039] Specifically, the image acquisition device captures a detection image of the carrier membrane at a predetermined position (e.g., directly above it). The detection image consists of multiple pixels, each with a corresponding pixel value. In the detection image of the carrier membrane, the pin marks differ in pixel value from the background area of ​​the carrier membrane itself. Pin marks are localized deformation areas caused by pressure applied to the carrier membrane by the pin tip. These areas appear as darker spots in the image, with pixel values ​​(e.g., grayscale values) lower than the surrounding unpressed background area of ​​the carrier membrane. Based on this physical phenomenon, pin marks can be identified by analyzing each pixel in the detection image.

[0040] In one embodiment, a detection image of the carrier film is acquired; each pixel in the detection image is traversed, and the pixel value of each pixel is compared with the pixel value of the background area. The region formed by pixels whose pixel values ​​differ from the pixel values ​​of the background area and meet a first preset condition is determined as a candidate pin mark region. Here, the candidate pin mark region refers to a potential image region that may belong to pin marks, marked from the detection image of the carrier film during image processing through preliminary screening (e.g., grayscale thresholding), but has not yet been precisely confirmed. It may contain real pin marks, or it may contain false marks such as dust and scratches.

[0041] Furthermore, the first preset condition refers to a pre-defined judgment rule used to distinguish whether a certain pixel may belong to the pin mark area. In one specific embodiment, the first preset condition can be a grayscale value lower than a preset grayscale threshold (e.g., 60); in another specific embodiment, the first preset condition can also be the value of a certain color component in the color image lower than a preset component threshold. The specific content of the first preset condition can be preset according to the material and color of the carrier film and the imaging characteristics of the image acquisition device, etc., and is used to quickly mark the areas in the detected image that have pixel value differences from the background area.

[0042] Because the surface of the carrier film may contain dust particles, bubbles, scratches, or other stains, these interfering substances may also appear as dark areas with pixel differences from the background area in the detection image. Therefore, the candidate pin mark area may contain some false marks. In order to identify the real pin marks from the candidate pin mark area and eliminate false marks, one embodiment analyzes the geometric features of the candidate pin mark area. The pin tip is processed into a hemispherical or arc shape, and the indentation formed on the carrier film when it contacts the carrier film has an approximately circular geometric contour. This pin mark is different from the geometric features of dust particles, scratches, and other interfering substances.

[0043] Based on this physical characteristic, in one embodiment, regions whose geometric features meet a second preset condition within the candidate ejector pin mark region are used to determine the location information of the ejector pin mark. The second preset condition here is a judgment rule used to determine whether the geometry of a candidate ejector pin mark region conforms to the inherent geometric features of the ejector pin mark. Its specific content can be preset according to the tip shape and size of the ejector pin, and is used to filter out regions from the candidate region whose geometric features match those of the ejector pin mark.

[0044] Thus, through the aforementioned two-stage screening architecture—first, preliminary screening based on pixel value differences to obtain candidate regions, and then precise screening based on geometric features to determine the true pin marks from the candidate regions—it can effectively eliminate interference from various false marks while ensuring processing speed, providing pin mark recognition accuracy and robustness. Specifically, the first preset condition achieves coarse screening with low computational load and fast processing speed, quickly narrowing the search range from the entire image to a few candidate regions; the second preset condition achieves fine screening with higher accuracy. The combination of both achieves the recognition effect of "accelerated coarse screening and accurate fine screening."

[0045] In one specific embodiment of the first preset condition, a grayscale threshold is used as the criterion for determining pixel differences. Specifically, after acquiring the detection image of the carrier film, the detection image is converted into a grayscale image, or a grayscale detection image is directly obtained by capturing it with a grayscale camera. Each pixel in the grayscale image has a grayscale value. The pin mark is a local deformation area caused by the pressure applied by the pin tip to the carrier film. This area appears as a darker spot on the carrier film and as a dark area with a lower grayscale value in the grayscale image; the background area of ​​the carrier film is not affected by the pin pressure and appears as a bright area with a higher grayscale value in the grayscale image.

[0046] Therefore, there is a significant difference in grayscale values ​​between the pin mark area and the background area of ​​the carrier film; the grayscale value of the pin mark area is lower than that of the background area. Based on this, pixels with grayscale values ​​lower than a preset grayscale threshold are identified as pin marks, while pixels with grayscale values ​​equal to or higher than the preset grayscale threshold are identified as belonging to the carrier film background area. The connected regions formed by all pixels with grayscale values ​​lower than the preset grayscale threshold are extracted as candidate pin mark areas. The specific value of the preset grayscale threshold can be preset according to the material and color of the carrier film.

[0047] Specifically, in practical applications, for UV films (such as D-185 or D-485 types), the grayscale value distribution of the background area ranges from 80 to 120, while the grayscale value distribution of the pin mark area ranges from 20 to 50. Therefore, the preset grayscale threshold is set to 60 to effectively distinguish between the two. Thus, preliminary screening of candidate areas using grayscale threshold segmentation has the advantages of low computational cost, fast processing speed, and simple implementation.

[0048] In one specific embodiment of the second preset condition, the outline shape of the candidate pin mark region is circular as the criterion for determining the true pin mark. Specifically, the edge outline of the candidate pin mark region is obtained and the coordinate information of at least three points is sampled from the edge outline; based on the coordinate information of the at least three points, it is determined whether the outline of the candidate pin mark region is circular; if so, the position information of the pin mark is determined based on the geometric center position of the candidate pin mark region.

[0049] In this embodiment, the edge contour can be implemented using an edge detection algorithm. To further improve the accuracy of the determination, more points (e.g., five, six, or more points) can be used on the edge contour for fitting and determination. Furthermore, the determination method for a circular contour is as follows: Substitute the coordinates of at least three sampled points into the circular equation (Xa)² + (Yb)² = r², where (a, b) represents the center coordinates and r represents the radius, and solve for whether there exists a set of (a, b, r) such that all sampled points satisfy this equation. If such a set of parameters exists, it indicates that the contour of the candidate region conforms to the circular feature, and the candidate region is determined to be a true pin mark; if such a set of parameters does not exist, it indicates that the contour of the candidate region does not conform to the circular feature, and the position information of the mark is determined based on the geometric center position of the candidate pin mark region.

[0050] After obtaining the position information of the ejector pin marks, select the position information of one of the ejector pin marks from multiple ejector pin marks as the reference point (corresponding to...). Figure 4 Point A in the diagram is used to establish a coordinate reference for the positioning process. Since the position of the ejector pin mark corresponds to the center of the chip in a predetermined manner, this reference point also serves as a reference point for the center position of a specific chip in the chip array. Using this reference point as the origin, the actual physical distances obtained through subsequent stepping and distance measurements can then form meaningful scale information within this coordinate system.

[0051] In one embodiment, the reference point is selected as the pin mark corresponding to the chip located in the central region of the chip array. The specific range of the central region can be determined according to the size of the chip array. In a specific embodiment, the central region refers to a preset range including the geometric center of the chip array. For a chip array with an odd number of rows and columns, the central region can be selected as the pin mark corresponding to the most central chip, such as... Figure 4 As shown; for a chip array with an even number of rows and columns, the central region can be selected as the pin mark corresponding to any one of the four chips located near the geometric center. In another specific embodiment, the central region can also be defined as the pin mark corresponding to any one of the chips within a circular area with a preset length as the radius and the wafer's geometric center as the center.

[0052] After determining the reference point, it is necessary to further determine the actual physical spacing of the chip array. For example... Figure 5 As shown, in one embodiment, step S2, which involves making at least one step movement along each arrangement direction of the chip array and determining the actual physical spacing of the chip array based on the movement distance, specifically includes the following steps.

[0053] Step S21: Perform at least one step movement along each arrangement direction of the chip array, and obtain the position information of the pin mark at the current position after each step movement in each arrangement direction.

[0054] Step S22: Determine the actual physical spacing of the chip array based on the distance between the reference point and the pin marks obtained after the movement.

[0055] In this embodiment, the actual physical spacing refers to the real physical distance between the centers of two adjacent chips on the current carrier film. This distance reflects the actual arrangement scale of the chips on the carrier film and may deviate from the theoretical size of the chips. Stepping movement refers to the action of the picker's nozzle or carrier platform moving from its current position to the next target position according to a preset direction and step size, driven by a drive mechanism (such as a linear motor or servo motor).

[0056] Before performing a stepping movement, it is necessary to determine the direction of movement and the distance to move each time. In one specific embodiment, the initial direction and theoretical step size of the stepping movement are determined by obtaining the theoretical dimensions of the chip. The theoretical dimensions of the chip refer to the standard length and width of the chip under ideal conditions, as marked on the chip design drawings; that is, the expected horizontal and vertical theoretical dimensions of the chip during design and manufacturing. These parameters are entered into the control system by the operator according to the product specifications, or they can be automatically entered by scanning the wafer label, or read directly from the wafer map file. The first direction (corresponding to) is determined based on the horizontal theoretical dimensions. Figure 4 or Figure 6 The theoretical step size for a single step in the horizontal (X) direction is determined based on the theoretical vertical dimension, and the second direction (corresponding to) is determined accordingly. Figure 4 or Figure 6 The theoretical step length of a single step along the longitudinal direction (Y) in the figure.

[0057] For example, if the theoretical dimensions of a certain chip model are 10 mm horizontally and 8 mm vertically, then when stepping horizontally, the theoretical step size for a single movement is 10 mm, and when stepping vertically, the theoretical step size for a single movement is 8 mm.

[0058] After completing a single step movement, the device can again obtain the position information of the ejector pin trace at the new location through a vision recognition system. This means that before the movement, the device has already obtained the precise coordinates of the ejector pin trace at the reference point through vision recognition; after the movement, the device again obtains the precise coordinates of the ejector pin trace at the new location through vision recognition. Then, based on the position information of the reference point and the position information of the ejector pin trace obtained after the movement, the actual coordinate difference between the two is calculated. Since the coordinates of the reference point and the coordinates of the trace after the movement are both located in the same coordinate system, the coordinate difference between the two is the actual distance traveled by the device during the actual step movement. In the case of only one movement, this actual distance traveled is the actual physical distance between two adjacent chips.

[0059] Since the chips are arranged in a two-dimensional array on the wafer, with both horizontal and vertical arrangement directions, in order to fully calibrate the actual arrangement scale of the chip array on the two-dimensional plane, it is necessary to obtain the actual physical spacing along both the horizontal and vertical directions.

[0060] In one specific embodiment, the first direction is the horizontal arrangement direction of the chip array, and the second direction is the vertical arrangement direction of the chip array, with the first and second directions perpendicular to each other. During the movement, multiple step movements are performed along the first and second directions respectively, with M steps in the first direction and N steps in the second direction, where M and N are both positive integers greater than or equal to 1. After all step movements are completed, the first total distance in the first direction between the reference point and the pin mark after the Mth step movement along the first direction, and the second total distance in the second direction between the reference point and the pin mark after the Nth step movement along the second direction are determined. The first total distance is the cumulative actual width of M chips arranged along the first direction, and the second total distance is the cumulative actual width of N chips arranged along the second direction. Continuing to refer to... Figure 4 As shown.

[0061] Then, the actual physical distance in the first direction is determined based on the ratio of the first total distance to the number of steps M; the actual physical distance in the second direction is determined based on the ratio of the second total distance to the number of steps N. By using multi-step movement and taking the average value to determine the actual physical distance, random errors that may exist in single-step measurement can be effectively eliminated.

[0062] After obtaining the actual physical spacing in the first and second directions, in one embodiment, a virtual mesh distribution corresponding to the chip array is generated using a reference point as the origin, the actual physical spacing in the first direction as the horizontal unit step, and the actual physical spacing in the second direction as the vertical unit step. The virtual mesh distribution is a virtual coordinate grid covering the entire wafer, constructed through coordinate calculations. Essentially, it is a positioning coordinate system with a real origin and real scale, replacing the positional reference function of physical cut lines in traditional positioning.

[0063] In the virtual mesh distribution, each mesh node corresponds to a chip in the chip array. The lateral distance between adjacent mesh nodes is equal to the actual physical spacing in the first direction, and the longitudinal distance between adjacent mesh nodes is equal to the actual physical spacing in the second direction. Based on this virtual mesh distribution, the actual coordinate positions of each chip in the chip array can be determined. After the actual coordinate positions of each chip are determined, the midpoint between two adjacent chips is the position of the virtual cut track, such as... Figure 6 As shown.

[0064] As mentioned earlier, in the single-pin embodiment, the center of the pin mark coincides with the chip center, and the chip center position can be obtained by identifying a single mark left by the pin. However, in practical applications, some chips are thin or brittle. If a single pin is used to apply concentrated force to the chip center during the lifting process, the chip may crack or break due to excessive local stress.

[0065] To address this issue, multiple ejector pins can be used to simultaneously lift the same chip. Multiple ejector pins apply lifting force at multiple contact points on the chip's bottom, distributing the force originally concentrated at a single point to multiple locations. This results in a more even distribution of force on the chip's bottom, effectively reducing localized stress in the chip's central area and lowering the risk of breakage for thin or brittle chips during the lifting process.

[0066] When multiple ejector pins simultaneously lift the same chip, they leave multiple pin marks on the carrier film. Each mark only reflects the contact point between the ejector pin and the carrier film, not the overall center of the chip. Therefore, it is necessary to determine the chip's center position based on the position information of the multiple pin marks. In one embodiment, the position information of the multiple pin marks left on the carrier film when multiple ejector pins simultaneously lift the same chip is obtained. Based on this position information, the geometric center position of the multiple pin marks is determined, and this geometric center position is used as the pin mark position information corresponding to the chip.

[0067] In this embodiment, the calculation of the geometric center depends on the arrangement of the multiple ejector pins. For example, when four ejector pins are used and arranged in a square on the bottom of the chip, the four pins leave four pin marks on the carrier film. After obtaining the position information of each of the four marks, the geometric center of the square formed by the four marks is calculated, and this geometric center is the center position of the chip. Specifically, the coordinates of the centers of the four pin marks are averaged to obtain the coordinates of the geometric center. Since the square arrangement has perfect symmetry in both the horizontal and vertical directions, the resultant force center of the four contact points is located at the geometric center of the chip; therefore, this geometric center position is the center position of the chip.

[0068] In summary, this invention provides a wafer positioning method. This method does not rely on physical dicing lines as a positioning reference. Instead, it utilizes the pin marks left on the carrier film when a chip is lifted by a pin as positioning markers. These marks have a fixed positional correspondence with the chip. Based on this, using the position of one of the pin marks as a reference point, the actual chip array is moved along each arrangement direction of the chip array, and the moving distance is measured. The actual physical spacing of the chip array in each direction is calibrated and obtained, thereby eliminating the deviation between theoretical dimensions and actual arrangement. Then, using the reference point as the origin and the actual physical spacing as the unit of measurement, the actual coordinate position of each chip in the chip array is determined. The picker nozzle performs chip picking according to these actual coordinate positions. This method helps eliminate dependence on physical dicing lines, enabling the picking machine to achieve accurate positioning and normal operation even when dicing lines are missing or unclear.

[0069] It should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This way of describing the specification is only for clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

[0070] The detailed descriptions listed above are merely specific descriptions of feasible embodiments of the present invention, and are not intended to limit the scope of protection of the present invention. All equivalent embodiments or modifications made without departing from the spirit of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for positioning a wafer, wherein a chip array comprising multiple chips is arranged on the wafer, characterized in that, The method includes: The position information of the ejector pin marks left on the carrier film when the ejector pin lifts the chip is obtained, and the ejector pin marks have a preset positional correspondence with the chip; Select the position information of one of the pin marks as a reference point. Based on the theoretical size of the chip, take the reference point as the starting point and move at least once along each arrangement direction of the chip array. Determine the actual physical spacing of the chip array based on the moving distance. Using the reference point as the origin, the actual coordinate position of each chip in the chip array is determined according to the actual physical distance, and the chip picking operation is performed according to the actual coordinate position.

2. The wafer positioning method according to claim 1, characterized in that, The acquisition of the location information of the pin marks left on the carrier film when the pin lifts the chip includes: Acquire a detection image of the carrier film; Based on the difference between the pixel values ​​in the detected image and the pixel values ​​in the background region, the region where the difference meets the first preset condition is determined as the candidate pin mark region; When the geometric features of the candidate pin mark region meet the second preset condition, the position information of the pin mark is determined based on the candidate pin mark region.

3. The wafer positioning method according to claim 2, characterized in that, The step of determining the region whose difference satisfies a first preset condition as a candidate pin mark region based on the difference between the pixel value in the detected image and the pixel value in the background region includes: The region formed by pixels in the detected image whose grayscale value is lower than a preset grayscale threshold is taken as the candidate pin mark region.

4. The wafer positioning method according to claim 2, characterized in that, When the geometric features of the candidate pin mark region meet the second preset condition, determining the position information of the pin mark based on the candidate pin mark region includes: Obtain the coordinate information of at least three points on the edge contour of the candidate pin mark region; Based on the coordinate information of the at least three points, determine whether the outline of the candidate pin mark region is circular; If so, the position information of the ejector pin mark is determined based on the geometric center position of the candidate ejector pin mark region.

5. The wafer positioning method according to claim 1, characterized in that, The ejector pins are multiple, and the acquisition of the position information of the ejector pin marks left on the carrier film when the ejector pins lift the chip includes: Obtain the position information of multiple pin marks left on the carrier film when multiple pins simultaneously push up the same chip; Based on the position information of the multiple ejector pin marks, the geometric center position of the multiple ejector pin marks is determined, and the geometric center position is used as the ejector pin mark position information corresponding to the chip.

6. The wafer positioning method according to claim 1, characterized in that, The reference point is selected as the pin mark corresponding to the chip located in the central region of the chip array.

7. The wafer positioning method according to claim 1, characterized in that, The step of moving at least once along each arrangement direction of the chip array, and determining the actual physical spacing of the chip array based on the moving distance, includes: Perform at least one step movement along each arrangement direction of the chip array, and obtain the position information of the pin mark at the current position after each step movement in each arrangement direction; The actual physical spacing of the chip array is determined based on the distance between the reference point and the pin marks obtained after the movement.

8. The wafer positioning method according to claim 7, characterized in that, The step of performing at least one step movement along each arrangement direction of the chip array, and obtaining the position information of the ejector pin mark at the current position after each step movement in each arrangement direction, includes: The chip array is moved M times along the first direction and N times along the second direction, and the position information of the pin mark at the current position is obtained after each step movement; where M and N are both positive integers greater than or equal to 1. Determining the actual physical spacing of the chip array based on the distance between the reference point and the pin marks obtained after the movement includes: The first total distance between the reference point and the ejector pin mark after the Mth step movement along the first direction is determined, and the second total distance between the reference point and the ejector pin mark after the Nth step movement along the second direction is determined, wherein the first direction is the lateral arrangement direction of the chip array, the second direction is the longitudinal arrangement direction of the chip array, and the first direction and the second direction are perpendicular to each other. Based on the ratio of the first total distance to the number of step movements M, and the ratio of the second total distance to the number of step movements N, the corresponding actual physical distance in the first direction and the actual physical distance in the second direction are determined.

9. The wafer positioning method according to claim 8, characterized in that, Before performing M and N step movements along the first and second directions of the chip array, respectively, the method further includes: Obtain the theoretical dimensions of the chip, including the theoretical dimensions of the chip's lateral and vertical dimensions; The theoretical step size for a single step in the first direction is determined based on the theoretical lateral dimension. The theoretical step size for a single step in the second direction is determined based on the aforementioned longitudinal theoretical dimension; The M-step and N-step movements along the first and second directions of the chip array, respectively, include: M steps are taken in the first direction according to the theoretical step size in the first direction, and N steps are taken in the second direction according to the theoretical step size in the second direction.

10. The wafer positioning method according to claim 8, characterized in that, The step of determining the actual coordinate position of each chip in the chip array based on the reference point as the origin and the actual physical spacing includes: Using the reference point as the origin of the coordinate system, and taking the actual physical spacing in the first direction and the actual physical spacing in the second direction as the unit step size in the horizontal and vertical directions respectively, a virtual grid distribution corresponding to the chip array is generated. The actual coordinate positions of each chip in the chip array are determined based on the virtual grid distribution.

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