Mask structure for monitoring multiple process parameters of SiC wafer chip and preparation method thereof

Abstract

The application belongs to the technical field of semiconductor process, and particularly relates to a mask structure for monitoring multiple process parameters of a SiC wafer chip and a preparation method thereof. The method comprises the following steps: forming a monitoring pattern mark for positioning and identification on the surface of a SiC wafer to obtain a first SiC wafer; forming a dielectric layer on the surface of the first SiC wafer; forming an injection area mask pattern and a non-injection area mask pattern on the dielectric layer to obtain a second SiC wafer; the injection area mask pattern comprises a surface roughness monitoring injection area pattern, a carrier activation concentration monitoring injection area pattern and an ohmic contact monitoring injection area pattern; forming a metal layer on the surface of the second SiC wafer; and forming a metal electrode mask pattern on the metal layer, wherein the metal electrode mask pattern comprises an ohmic contact test electrode pattern and a Hall test electrode pattern. The method realizes the simultaneous completion of the multiple-parameter monitoring of the surface roughness, the carrier activation concentration and the metal-semiconductor contact type after high-temperature annealing on the same SiC wafer.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor process technology, specifically a mask structure and preparation method for monitoring multiple process parameters of SiC wafer chips. Background Technology

[0002] Chips based on silicon carbide (SiC) wafers exhibit superior performance in high-temperature, high-frequency, and high-power applications due to their excellent physical and chemical properties. With continuous advancements in SiC material processing technology and the expansion of its application areas, the market prospects for SiC wafer substrate chips are increasingly promising. Demand for SiC wafer substrate chips continues to grow, particularly in automotive electronics and industrial semiconductors. Furthermore, as research into 8-inch SiC wafer fabrication and epitaxial applications deepens, the cost of SiC wafer substrate chips will further decrease, and production volume will further increase, providing a strong guarantee for the widespread application of SiC wafer substrate chips.

[0003] In existing technologies, ion implantation, high-temperature annealing, and ohmic contact processes are key technologies for achieving effective doping within SiC wafers during chip manufacturing. Typically, these processes are monitored individually. However, due to the high cost of SiC wafers, monitoring each process individually requires a large number of wafers, and only one parameter can be monitored on the same wafer, increasing costs in mass production. Summary of the Invention

[0004] The purpose of this invention is to provide a mask structure and fabrication method for monitoring multiple process parameters of SiC wafer chips, so as to solve the problem of increased cost caused by consuming a large number of SiC wafers due to the use of single process monitoring in the prior art.

[0005] To achieve the above objectives, the present invention employs the following technical solution: In a first aspect, this application discloses a method for fabricating a mask structure for monitoring multiple process parameters of a SiC wafer chip, comprising: S1: A monitoring graphic mark for positioning and identification is formed on the surface of the SiC wafer to obtain the first SiC wafer; S2: A dielectric layer is formed on the surface of the first SiC wafer; S3: Form an injection region mask pattern and a non-injection region mask pattern on the dielectric layer to obtain a second SiC wafer; the injection region mask pattern includes a surface roughness monitoring injection region pattern, a carrier activation concentration monitoring injection region pattern, and an ohmic contact monitoring injection region pattern. S4: Form a metal layer on the surface of the second SiC wafer; S5: Form a metal electrode mask pattern on the metal layer, the metal electrode mask pattern including an ohmic contact test electrode pattern and a Hall test electrode pattern.

[0006] Optionally, the monitoring graphic markers in S1 include at least one of the following: Graphical markings of surface roughness in the injection area and the non-injection area used for surface roughness testing after high-temperature annealing; Graphical markings for different implantation conditions used in ion implantation distribution testing; Graphical markings for different injection conditions used in ohmic contact testing; Hall effect test graphic markers for monitoring carrier activation concentration.

[0007] Optionally, in S1, the monitoring pattern mark is formed by dry etching with an etching depth of 50 nm to 200 nm, and the size of the monitoring pattern mark is 100 μm × 50 μm to 200 μm × 100 μm.

[0008] Optionally, the dielectric layer in S2 is a silicon dioxide layer, and the thickness of the silicon dioxide layer is 800 nm to 2500 nm.

[0009] Optionally, in S3, the injection area mask pattern and the non-injection area mask pattern are formed on the dielectric layer by means of coating, photolithography and development, and the coating thickness is 1.0 μm to 1.7 μm.

[0010] Optionally, in S3: The size of the surface roughness monitoring injection area pattern is 20 μm × 20 μm to 200 μm × 200 μm; The size of the ohmic contact monitoring injection area pattern is 100 μm × 1500 μm to 200 μm × 3000 μm; The size of the carrier activation concentration monitoring injection region pattern is 5 mm × 5 mm to 10 mm × 10 mm.

[0011] Optionally, the metal layer in S4 is a Ni layer, and the thickness of the Ni layer is 100 nm to 300 nm.

[0012] Alternatively, in S5: The ohmic contact test electrode pattern includes 6 to 8 electrodes, with the spacing between adjacent electrodes increasing at equal intervals, the increment being 10 μm to 30 μm, and the size of the ohmic contact test electrode being 50 μm × 50 μm to 200 μm × 200 μm. The Hall test electrode pattern comprises four electrodes, and the size of the Hall test electrode is 500 μm × 500 μm to 1000 μm × 1000 μm.

[0013] Optionally, the monitoring pattern markers, the injection region mask pattern, the non-injection region mask pattern, and the metal electrode mask pattern together constitute a test unit. The test units are distributed at intervals on the SiC wafer, with the interval between adjacent test units being 50 μm to 100 μm.

[0014] Secondly, this application discloses a mask structure for monitoring multiple process parameters of SiC wafer chips, which is prepared by the method described above for preparing a mask structure for monitoring manufacturing parameters of SiC wafer chips.

[0015] Compared with the prior art, the present invention has the following beneficial effects: This application achieves simultaneous monitoring of multiple parameters—surface roughness, carrier activation concentration, and metal-semiconductor contact type—on a single SiC wafer by sequentially forming monitoring pattern markers, a dielectric layer, implantation region mask patterns, non-implantation region mask patterns, a metal layer, and a metal electrode mask pattern on the surface of a SiC wafer. Specifically, by integrating surface roughness monitoring implantation region patterns, carrier activation concentration monitoring implantation region patterns, ohmic contact monitoring implantation region patterns, and corresponding ohmic contact test electrode patterns and Hall effect test electrode patterns on the same wafer, it effectively avoids the cost increase caused by consuming a large number of wafers for monitoring a single process in existing technologies, significantly reducing wafer monitoring costs. Furthermore, since multiple monitoring pattern markers, implantation region mask patterns, and metal electrode mask patterns can be distributed at intervals in each test unit of the same wafer, the monitoring of multiple process parameters can be completed synchronously in the same process flow. This facilitates timely reflection of fluctuations in each process stage, thereby effectively ensuring the overall stability of the multi-process flow.

[0016] Furthermore, by specifically setting the monitoring graphic markers as surface roughness graphic markers for the implanted area and the non-implanted area, the subsequent atomic force microscope can accurately scan and test the implanted and non-implanted areas on the same wafer. By comparing and analyzing the surface roughness data of the two, the influence of the high-temperature annealing process itself on the surface morphology can be accurately isolated, thereby achieving independent monitoring of the quality of the high-temperature annealing process. At the same time, by setting graphic markers for different implantation conditions and graphic markers for ohmic contact testing and Hall testing, a precise positioning benchmark is provided for subsequent ion implantation distribution testing, ohmic contact testing, and Hall testing, enabling each test to be accurately performed within a predetermined area of ​​the same wafer, ensuring the feasibility and accuracy of multi-parameter monitoring. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 For surface roughness monitoring mask structure; Figure 2 The mask structure is used for monitoring ion implantation distribution. Figure 3 Mask structure for ohmic contact test injection region; Figure 4 Hall test mask structure for monitoring carrier activation concentration; Figure 5 Metal electrode mask structure for ohmic contact testing and Hall effect testing; Figure 6 This is to test the distribution of cells in the wafer.

[0019] Among them, 1-Hall test mask structure for monitoring carrier activation concentration; 2-Ion implantation distribution monitoring test mask structure; 3-Ohmic contact monitoring test mask structure; 4-Surface roughness monitoring mask structure; 5-Second test unit; 6-First test unit; 7-Third test unit; 8-SiC wafer; 9-Test unit spacing; 10-Impplanted region; 11-Non-implanted region; 12-Ion implantation distribution test region; 13-Ohmic contact implanted region; 14-Hall test implanted region; 15-Hall test electrode; 16-Ohmic contact test electrode. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0021] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0022] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0023] In the description of the embodiments of the present invention, it should be noted that if terms such as "upper," "lower," "horizontal," or "inner" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of the invention is in use, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. Furthermore, terms such as "first" and "second" are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0024] Furthermore, the use of the term "horizontal" does not imply that the component must be absolutely horizontal, but rather that it can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal than "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0025] In the description of the embodiments of the present invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in the present invention according to the specific circumstances.

[0026] The present invention will now be described in further detail with reference to the accompanying drawings: This application discloses a method for fabricating a mask structure for monitoring multiple process parameters of a SiC wafer chip, including: S1: A monitoring graphic mark for positioning and identification is formed on the surface of the SiC wafer to obtain the first SiC wafer; S2: A dielectric layer is formed on the surface of the first SiC wafer; S3, forming an injection region mask pattern and a non-injection region mask pattern on the dielectric layer to obtain a second SiC wafer; the injection region mask pattern includes a surface roughness monitoring injection region pattern, a carrier activation concentration monitoring injection region pattern, and an ohmic contact monitoring injection region pattern. S4, a metal layer is formed on the surface of the second SiC wafer; S5, forming a metal electrode mask pattern on the metal layer, the metal electrode mask pattern including an ohmic contact test electrode pattern and a Hall test electrode pattern.

[0027] By sequentially forming monitoring pattern markers, dielectric layers, implantation region mask patterns containing multiple monitoring areas, metal layers, and metal electrode mask patterns containing multiple test electrodes on the same SiC wafer, a single wafer can simultaneously integrate monitoring functions for surface roughness, carrier activation concentration, and ohmic contact characteristics after undergoing a complete process sequence. This directly avoids the need to occupy multiple wafers to monitor different process parameters, significantly reducing wafer consumption and monitoring costs in mass production. Furthermore, because each monitoring pattern shares the same process environment, it can more realistically reflect the collaborative stability of multiple process flows.

[0028] In some embodiments, the monitoring graphic markers in S1 include at least one of the following: Graphical markings of surface roughness in the injection area and the non-injection area used for surface roughness testing after high-temperature annealing; Graphical markings for different implantation conditions used in ion implantation distribution testing; Graphical markings for different injection conditions used in ohmic contact testing; Hall effect test graphic markers for monitoring carrier activation concentration.

[0029] In some embodiments, the monitoring pattern mark is formed by dry etching in S1, with an etching depth of 50 nm to 200 nm and a size of 100 μm × 50 μm to 200 μm × 100 μm. By using dry etching to form the monitoring pattern mark and controlling the etching depth between 50 nm and 200 nm and the mark size between 100 μm × 50 μm and 200 μm × 100 μm, it is ensured that the mark pattern has sufficient etching depth to be clearly identified and located after subsequent multilayer processes (including dielectric deposition, photolithography, metal deposition, etc.), while avoiding excessive etching that could cause excessive damage to the SiC wafer surface and affect the electrical performance of subsequent epitaxy or the active region of the device. At the same time, this size range is moderate, which can meet the recognition accuracy requirements of optical alignment equipment without crowding out the effective layout space of the test unit on the wafer due to the mark area being too large.

[0030] In some embodiments, the dielectric layer in S2 is a silicon dioxide layer with a thickness of 800 nm to 2500 nm. On the one hand, this thickness range is sufficient to serve as an effective implantation barrier layer in subsequent ion implantation processes, preventing implanted ions from penetrating the dielectric layer and entering the wafer surface in the non-implanted area, thereby ensuring a clear demarcation between the implanted and non-implanted areas. On the other hand, this dielectric layer can protect the wafer surface during high-temperature annealing, reducing thermal damage to the wafer surface caused by high temperatures. Furthermore, silicon dioxide layers within this thickness range have good process compatibility during subsequent removal, and will not cause additional contamination or damage to the wafer surface.

[0031] In some embodiments, in step S3, a mask pattern for the implantation region and a mask pattern for the non-implantation region are formed on the dielectric layer using a process of photoresist coating, photolithography, and development. The photoresist coating thickness is 1.0 μm to 1.7 μm. This range of coating thickness ensures that the photoresist layer has sufficient thickness to effectively protect the dielectric layer in the non-implantation region from damage during subsequent etching or ion implantation. On the other hand, it avoids the problems of decreased photolithographic pattern resolution and insufficient development caused by excessively thick photoresist layers. This ensures the edge steepness and dimensional accuracy of the implantation region window, thereby making the actual shape and size of the implantation region highly consistent with the design pattern, improving the repeatability of the implantation process and the comparability of test results.

[0032] In some embodiments, in S3: The size of the surface roughness monitoring injection area pattern is 20 μm×20 μm to 200 μm×200 μm; this size range matches the conventional scanning range of the atomic force microscope, which can provide sufficient scanning area to ensure the representativeness of surface roughness statistics and adapt to the testing requirements at different magnifications. The size of the ohmic contact monitoring injection area pattern is 100 μm×1500 μm~200 μm×3000 μm; it provides a transmission line region of sufficient length for linear transmission line model testing, so that the resistance difference between electrodes with different spacings can be accurately measured, thereby ensuring the accuracy of the specific contact resistance value calculation. The size of the carrier activation concentration monitoring injection region pattern is 5 mm × 5 mm to 10 mm × 10 mm. This area is sufficient to meet the arrangement requirements of current and voltage probes in Hall effect testing, and at the same time, it can obtain a Hall voltage signal with sufficient strength to ensure the testing accuracy of carrier concentration and mobility.

[0033] In some embodiments, the metal layer in S4 is a Ni layer, and the thickness of the Ni layer is 100 nm to 300 nm. Ni is one of the most commonly used ohmic contact metals in the SiC material system. Within this thickness range, it can form good nickel silicide with the SiC substrate after high-temperature annealing, thereby achieving a low specific contact resistance. Simultaneously, this thickness range ensures that the metal electrode has sufficient conductivity and mechanical strength to withstand multiple probe insertions, while preventing excessive metal layer thickness from causing difficulties in photolithography lift-off or excessive internal stress that could affect the adhesion between the electrode and SiC.

[0034] In some embodiments, S5: The ohmic contact test electrode pattern comprises 6 to 8 electrodes, with the spacing between adjacent electrodes increasing arithmetically in increments of 10 μm to 30 μm. This spacing arrangement provides ample test data points for fitting a linear transmission line model. The arithmetically increasing spacing design ensures a linear relationship between the resistance value and the spacing, facilitating accurate extraction of the specific contact resistance value through linear regression. The ohmic contact test electrode has dimensions ranging from 50 μm × 50 μm to 200 μm × 200 μm, which is sufficient to ensure that the test probe can accurately penetrate the electrode surface without deviation, while also preventing the effective transmission line length from being shortened due to excessive electrode size. The Hall test electrode pattern includes four electrodes, each with a size of 500 μm × 500 μm to 1000 μm × 1000 μm. The configuration of the four electrodes conforms to the standard van der Burg method requirements for Hall effect testing. The larger electrode size reduces the positional accuracy requirements of the probe insertion, facilitates rapid testing, and ensures the stability of the test signal.

[0035] In some embodiments, the monitoring pattern markers, implantation region mask patterns, non-implantation region mask patterns, and metal electrode mask patterns collectively constitute a test unit. These test units are spaced apart on the SiC wafer, with an interval of 50 μm to 100 μm between adjacent test units. Multiple test units can be arranged on the same wafer, each containing complete monitoring pattern markers, implantation region mask patterns, and metal electrode mask patterns, thereby achieving simultaneous multi-parameter monitoring at multiple locations on a single wafer. The uniform distribution design allows each test unit to cover different radial positions on the wafer. By comparing data from test units at different locations, the distribution of processes such as ion implantation uniformity, annealing temperature uniformity, and metal deposition uniformity across the entire wafer can be reflected, providing comprehensive data support for process optimization and process stability assessment.

[0036] This application also discloses a mask structure for monitoring multiple process parameters of SiC wafer chips, which is prepared by the method described above for preparing a mask structure for monitoring manufacturing parameters of SiC wafer chips.

[0037]

Example

[0038] This invention provides a mask structure for monitoring multiple process parameters of SiC wafer chips. Different mask patterns can be used to simultaneously monitor surface roughness, carrier activation concentration, ion implantation distribution, and metal-semiconductor contact type on a single wafer after high-temperature annealing.

[0039] To achieve the above objectives, the present invention employs the following technical solution: A mask structure for monitoring multiple process parameters of a SiC wafer chip is characterized by simultaneously monitoring surface roughness, carrier activation concentration, ion implantation distribution, and metal-semiconductor contact type after high-temperature annealing using different mask patterns on a single wafer. Its fabrication method includes the following steps: S1, dry etching is used to etch the monitoring mask pattern marking on the surface of the SiC wafer. S2, SiO2 deposition on SiC wafer S3, on the obtained S2 wafer, uses coating, photolithography, and development methods to realize surface roughness monitoring mask patterns for the injection and non-injection regions, carrier activation concentration monitoring mask patterns for the injection region, and ohmic contact mask patterns for the injection region.

[0040] S4, depositing metal on the wafer surface; S5, a metal electrode mask structure is realized on the obtained S4 wafer by means of coating, photolithography and development.

[0041] In S1, the monitoring graphic markers include surface roughness tests after high-temperature annealing. The surface roughness graphic marker for the injection area is AFM1, represented by a solid line box; the surface roughness graphic marker for the non-injection area is AFM0, represented by a dashed line box. (See attached...) Figure 1 .

[0042] In S1, the monitoring graphic markers include ion implantation distribution testing. Different implantation conditions are marked as SIMS1, SIMS2, SIMS3, etc., represented by solid-line boxes. (See attached image.) Figure 2 . In S1, the monitoring graphic markers include ohmic contact tests, and different injection conditions are marked with TLM1, TLM2, TLM3, etc., represented by solid line boxes. (See attached image) Figure 3 .

[0043] In S1, the monitoring graphical markers include Hall tests, with different injection conditions marked as Hall1, Hall2, Hall3, etc. (See attached image.) Figure 4 .

[0044] In S4, metal electrodes are used for ohmic contact TLM testing and Hall effect testing, with the spacing between the ohmic contact TLM testing electrodes increasing proportionally. (See attached image) Figure 5 .

[0045] In S4, the relative positions of the metal electrode and the implantation region are shown in the attached figure. Figure 5 .

[0046] The test patterns formed by S1, S3, and S5 are collectively called test cells, which are evenly distributed throughout the wafer. (See attached image.) Figure 6 .

[0047]

Example 2

[0048] S2, depositing SiO2 on a SiC wafer. Preferably, the thickness of the deposited SiO2 is between 800 nm and 2500 nm.

[0049] S3, on the obtained S2 wafer, uses coating, photolithography and development to realize the monitoring mask structure of the implanted and non-implanted areas.

[0050] Preferably, the adhesive coating thickness is 1.0 μm to 1.0 μm. The injection area size for surface roughness monitoring is 20 μm × 20 μm to 200 μm × 200 μm. The injection area size for ohmic contact testing is 100 μm × 1500 μm to 200 μm × 3000 μm. The injection area size for Hall effect testing is 5 mm × 5 mm to 10 mm × 10 mm.

[0051] S4, depositing metal on the wafer surface Preferably, metallic Ni is deposited with a deposition thickness of 100 nm to 300 nm.

[0052] S5, a metal electrode mask structure is realized on the obtained S4 wafer by means of coating, photolithography and development.

[0053] Preferably, each ohmic contact test area has 6 to 8 TLM electrodes, with an increase in distance Δd between each electrode of 10 μm to 30 μm. The electrode size is 50 μm × 50 μm to 200 μm × 200 μm. There are 4 Hall test electrodes, with electrode sizes of 500 μm × 500 μm to 1000 μm × 1000 μm. The test units are uniformly distributed in the wafer with a spacing of 50 μm to 100 μm.

[0054] Example 3 S1 uses dry etching to etch monitoring pattern markings on the surface of SiC wafers, with an etching depth of 200nm and a marking pattern size of 200μm×100μm.

[0055] S2, depositing SiO2 on a SiC wafer with a SiO2 thickness of 2000nm.

[0056] S3, on the obtained S2 wafer, employs a coating, photolithography, and development process to create monitoring mask structures for both implanted and non-implanted regions. The coating thickness is 1.7 μm. The implanted region size for surface roughness monitoring is 100 μm × 100 μm. The implanted region size for ohmic contact testing is 160 μm × 1300 μm. The implanted region size for Hall effect testing is 10 mm × 10 mm.

[0057] S4, depositing metal Ni on the wafer surface, with a deposition thickness of 300 nm.

[0058] S5, a metal electrode mask structure is realized on the obtained S4 wafer by means of coating, photolithography and development.

[0059] Each ohmic contact test area has 6 TLM electrodes, with an increase in distance Δd of 20 μm per electrode. The electrode size is 150 μm × 150 μm. There are 4 Hall effect test electrodes, each with a size of 1000 μm × 1000 μm. The test cells are uniformly distributed 80 μm apart on the wafer. The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for fabricating a mask structure for monitoring multiple process parameters of a SiC wafer chip, characterized in that, include: S1: A monitoring graphic mark for positioning and identification is formed on the surface of the SiC wafer to obtain the first SiC wafer; S2: A dielectric layer is formed on the surface of the first SiC wafer; S3: Form an injection region mask pattern and a non-injection region mask pattern on the dielectric layer to obtain a second SiC wafer; the injection region mask pattern includes a surface roughness monitoring injection region pattern, a carrier activation concentration monitoring injection region pattern, and an ohmic contact monitoring injection region pattern. S4: Form a metal layer on the surface of the second SiC wafer; S5: Form a metal electrode mask pattern on the metal layer, the metal electrode mask pattern including an ohmic contact test electrode pattern and a Hall test electrode pattern.

2. The method for fabricating a mask structure for monitoring multiple process parameters of a SiC wafer chip according to claim 1, characterized in that, The monitoring graphic markers mentioned in S1 include at least one of the following: Graphical markings of surface roughness in the injection area and the non-injection area used for surface roughness testing after high-temperature annealing; Graphical markings for different implantation conditions used in ion implantation distribution testing; Graphical markings for different injection conditions used in ohmic contact testing; Hall effect test graphic markers for monitoring carrier activation concentration.

3. The method for fabricating a mask structure for monitoring multiple process parameters of a SiC wafer chip according to claim 1, characterized in that, The monitoring pattern mark is formed by dry etching in S1, with an etching depth of 50 nm to 200 nm and a size of 100 μm × 50 μm to 200 μm × 100 μm.

4. The method for fabricating a mask structure for monitoring multiple process parameters of a SiC wafer chip according to claim 1, characterized in that, The dielectric layer in S2 is a silicon dioxide layer, and the thickness of the silicon dioxide layer is 800 nm to 2500 nm.

5. The method for fabricating a mask structure for monitoring multiple process parameters of a SiC wafer chip according to claim 1, characterized in that, In S3, the injection area mask pattern and the non-injection area mask pattern are formed on the dielectric layer by means of coating, photolithography and development, and the coating thickness is 1.0 μm to 1.7 μm.

6. The method for fabricating a mask structure for monitoring multiple process parameters of a SiC wafer chip according to claim 1, characterized in that, In S3: The size of the surface roughness monitoring injection area pattern is 20 μm × 20 μm to 200 μm × 200 μm; The size of the ohmic contact monitoring injection area pattern is 100 μm × 1500 μm to 200 μm × 3000 μm; The size of the carrier activation concentration monitoring injection region pattern is 5 mm × 5 mm to 10 mm × 10 mm.

7. The method for fabricating a mask structure for monitoring multiple process parameters of a SiC wafer chip according to claim 1, characterized in that, The metal layer mentioned in S4 is a Ni metal layer, and the thickness of the Ni metal layer is 100 nm to 300 nm.

8. The method for fabricating a mask structure for monitoring multiple process parameters of a SiC wafer chip according to claim 1, characterized in that, In S5: The ohmic contact test electrode pattern includes 6 to 8 electrodes, with the spacing between adjacent electrodes increasing at equal intervals, the increment being 10 μm to 30 μm, and the size of the ohmic contact test electrode being 50 μm × 50 μm to 200 μm × 200 μm. The Hall test electrode pattern comprises four electrodes, and the size of the Hall test electrode is 500 μm × 500 μm to 1000 μm × 1000 μm.

9. The method for fabricating a mask structure for monitoring multiple process parameters of a SiC wafer chip according to claim 1, characterized in that, The monitoring pattern markers, the injection region mask pattern, the non-injection region mask pattern, and the metal electrode mask pattern together constitute a test unit. The test units are distributed at intervals on the SiC wafer, with an interval of 50 μm to 100 μm between adjacent test units.

10. A mask structure for monitoring multiple process parameters of a SiC wafer chip, characterized in that, The mask structure for monitoring SiC wafer chip manufacturing parameters is prepared using any one of the methods described in claims 1 to 9.

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