Packaging structure and electronic device

Abstract

Provided are a packaging structure and an electronic device, and relate to the technical field of semiconductor packaging. The packaging structure comprises a chip, a conversion board, a substrate, a first connecting structure, and a second connecting structure. The conversion board is connected to one side of the chip. The substrate is located on the side of the conversion board away from the chip; the side of the substrate facing the conversion board comprises a first connecting area and a second connecting area. The conversion board and the first connecting area are connected by the first connecting structure which has a large size; the first connecting structure has characteristics such as a large upper limit current and strong stress bearing capacity; the conversion board and the second connecting area are connected by the second connecting structure which has a small size; the second connecting structure has characteristics such as a fast signal transmission rate. In this way, the aforementioned packaging structure has high-bandwidth transmission, good reliability, and good power supply capacity.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and more particularly to packaging structures and electronic devices. Background Technology

[0002] With the continuous advancement of technology, electronic devices are developing towards higher performance, more multifunctionality, and miniaturization. To achieve these functions, higher requirements are placed on the interconnect bandwidth of the packaging structure in electronic devices.

[0003] Currently, while improving the interconnect bandwidth of the packaging structure, it is difficult to simultaneously achieve superior reliability and power supply capability, which restricts the large-scale use of the packaging structure. Summary of the Invention

[0004] Embodiments of this application provide a packaging structure and an electronic device that combines high bandwidth transmission, superior reliability, and superior power supply capability, which is conducive to the large-scale use of the packaging structure.

[0005] In a first aspect, a packaging structure is provided. The packaging structure includes: a chip, an adapter board, a substrate, a first connection structure, and a second connection structure. The adapter board is connected to one side of the chip. The substrate is located on the side of the adapter board facing away from the chip. The side of the substrate facing the adapter board includes a first connection area and a second connection area. The adapter board and the first connection area are connected via the first connection structure, and the adapter board and the second connection area are connected via the second connection structure. Along the direction towards the chip, the size of the first connection structure is larger than the size of the second connection structure.

[0006] In the aforementioned packaging structure, a first connection structure is used to connect the adapter board and the first connection area. The first connection structure has a larger size, so its resistance is smaller and the upper limit current through the first connection structure is higher, which can improve the power supply capacity of the packaging structure. At the same time, the larger size of the first connection structure has better stress resistance and is less prone to fatigue fracture, which can improve the reliability of the packaging structure.

[0007] A smaller second connection structure is used to connect the adapter board and the second connection area. Due to the smaller size of the second connection structure, more second connection structures can be set between the second connection area and the adapter board, which can increase the density of electrical connection points between the second connection area and the adapter board, and is conducive to achieving high bandwidth interconnection of the package structure. At the same time, due to the smaller size of the second connection structure, the signal transmission path through the second connection structure is shorter, which is further conducive to achieving high bandwidth interconnection of the package structure.

[0008] In summary, the packaging structure provided in this application combines high bandwidth transmission, superior reliability, and excellent power supply capability. Furthermore, it requires minimal design work on the packaging structure, is compatible with existing manufacturing processes, and is easily industrialized.

[0009] In one possible implementation, the adapter board includes a first line with a larger cross-sectional area and a second line with a smaller cross-sectional area, the first line being connected to a first connection structure and the second line being connected to a second connection structure.

[0010] The cross-sectional area of ​​a circuit is generally directly proportional to the magnitude of the current. If the cross-sectional area of ​​the first circuit is larger than that of the second circuit, the current transmitted through the first circuit will be greater than that transmitted through the second circuit. When the materials are similar or identical, the size of a connection structure is generally inversely proportional to its resistance. Along the direction towards the chip, the size of the first connection structure is larger than that of the second connection structure, meaning the resistance of the first connection structure is less than that of the second connection structure. The larger current output from the first circuit is transmitted through the first connection structure with lower resistance, while the smaller current output from the second circuit is transmitted through the second connection structure with higher resistance. This minimizes current loss and improves the power supply capability of the package structure.

[0011] In one possible implementation, the orthographic projection of the chip onto the substrate (referred to as the first orthographic projection) overlaps with the first connection area. Alternatively, it can be understood that there is at least partial overlap between the area of ​​the substrate directly opposite the chip (referred to as the first opposite area) and the first connection area.

[0012] The first orthographic projection and the first connection area overlap, and the first connection area and the adapter board are connected by the first connection structure. That is, the first opposing area can be connected to the adapter board through the first connection structure. The first opposing area belongs to the area with high current transmission requirements, high reliability requirements, and non-high-speed signal transmission. Since the first connection structure has advantages such as a large upper limit current and strong stress resistance, connecting the first opposing area to the adapter board through the first connection structure can well meet the connection requirements of this area.

[0013] In one possible implementation, the other regions of the substrate besides the first orthographic projection (referred to as the first non-orthographic projection) and the second connection region overlap. Alternatively, it can be understood that there is at least partial overlap between the other regions of the substrate besides the region facing the chip (referred to as the first non-facing region) and the second connection region.

[0014] The first non-orthographic projection and the second connection area overlap, and the second connection area and the adapter board are connected by a second connection structure. That is, the first non-orthographic area is connected to the adapter board through the second connection structure. The first non-orthographic area belongs to the area with lower current transmission requirements, lower reliability requirements, and high-speed signal transmission. Since the second connection structure has advantages such as faster signal transmission rate, connecting the first non-orthographic area to the adapter board through the second connection structure can better meet the connection requirements of this area.

[0015] In one possible implementation, the first connection area faces the edge of the adapter plate, and the edges of the substrate and the adapter plate are connected by a first connection structure in the first connection area. Since the edge of the adapter plate is a critical location for the connection between the substrate and the adapter plate, it is highly susceptible to loosening and detachment under external forces such as vibration or impact. Using the first connection structure to connect the edges of the substrate and the adapter plate provides superior stress resistance and a larger contact area between the first connection structure and the substrate / adapter plate, thus improving the connection effect between the substrate and the adapter plate and ultimately enhancing the reliability of the packaging structure.

[0016] In one possible implementation, the first connection area is provided with a first groove, the bottom wall of which is connected to the adapter plate via a first connection structure.

[0017] In one possible implementation, the package structure further includes a first electronic device, such as a capacitor, inductor, or resistor. The first electronic device is located between the first recess and the adapter plate, and is connected to the adapter plate. Since the space between the first recess and the adapter plate is relatively large, it can accommodate the first electronic device. Thus, by incorporating the first electronic device, the integration density of the package structure can be improved, and different first electronic devices can give the package structure different functions.

[0018] In one possible implementation, the adapter plate has a second groove in the area opposite the first groove; the bottom walls of the first and second grooves are connected by a first connecting structure. Alternatively, the first electronic device can be located in the area between the bottom walls of the first and second grooves.

[0019] In one possible implementation, along the direction toward the chip, the first connection structure has a size of L1, and the second connection structure has a size of L2, with the ratio of L1 to L2 being (1.2-3):1. Thus, the sizes of the first and second connection structures are moderate, and the package structure combines high bandwidth transmission, superior reliability, and excellent power supply capability.

[0020] In one possible implementation, along a direction perpendicular to the chip, the average cross-sectional area of ​​the first connection structure is S1, and the average cross-sectional area of ​​the second connection structure is S2, where S1 is larger than S2. The larger average cross-sectional area of ​​the first connection structure results in a smaller resistance; conversely, the smaller average cross-sectional area results in a larger resistance. This allows larger currents to be transmitted through the lower-resistance first connection structure, and smaller currents through the higher-resistance second connection structure, minimizing current loss and improving the power supply capability of the package structure.

[0021] In one possible implementation, the ratio of S1 to S2 is (1.2-3):1. Thus, the average cross-sectional area of ​​the first connection structure and the average cross-sectional area of ​​the second connection structure are moderate, and the packaging structure combines high bandwidth transmission, superior reliability, and superior power supply capability.

[0022] In one possible implementation, the first connection structure and the second connection structure include at least one of solder balls and metal pillars. Thus, the first and second connection structures possess excellent electrical and mechanical properties, which is beneficial for improving the high-speed signal transmission and reliability of the package structure.

[0023] In one possible implementation, the first and second connecting structures are made of the same material. This allows for the simple and easy fabrication of both structures, reducing the manufacturing cost of the encapsulation structure.

[0024] In a second aspect, an electronic device is provided. The electronic device includes a circuit board and a packaging structure as described in any possible implementation of the first aspect; a substrate in the packaging structure is connected to the circuit board.

[0025] In one possible implementation, a third connection area and a fourth connection area are provided on the side of the circuit board facing the substrate. The electronic device also includes a third connection structure and a fourth connection structure, with the substrate and the third connection area connected via the third connection structure, and the substrate and the fourth connection area connected via the fourth connection structure. Specifically, along the direction towards the substrate, the size of the third connection structure is larger than the size of the fourth connection structure.

[0026] In the aforementioned electronic devices, the third connection structure is characterized by a larger upper limit current, stronger stress resistance, and lower signal transmission rate, while the fourth connection structure is characterized by a smaller upper limit current, weaker stress resistance, and faster signal transmission rate. The third connection structure is used to connect the substrate and the third connection area, and the fourth connection structure is used to connect the substrate and the fourth connection area, thus enabling the electronic device to possess high bandwidth transmission, superior reliability, and better power supply capability.

[0027] In one possible implementation, the orthographic projection of the chip on the circuit board (referred to as the second orthographic projection) and the third connection area overlap. Alternatively, it can be understood that there is at least partial overlap between the area of ​​the circuit board directly opposite the chip (referred to as the second opposite area) and the third connection area.

[0028] The second orthographic projection and the third connection area overlap, and the third connection area is connected to the substrate through the third connection structure. That is, the second orthographic projection area can be connected to the substrate through the third connection structure. The second orthographic projection area is a region with high current transmission requirements, high reliability requirements, and non-high-speed signal transmission. Since the third connection structure has advantages such as a large upper limit current and strong stress resistance, connecting the second orthographic projection area to the substrate through the third connection structure can well meet the connection requirements of this region.

[0029] In one possible implementation, the other areas of the circuit board besides the second orthographic projection (referred to as the second non-orthographic projection) overlap with the fourth connection area. This can also be understood as the other areas of the circuit board besides the area directly opposite the chip (referred to as the second non-opposite area), where there is at least partial overlap between the second non-opposite area and the fourth connection area.

[0030] The second non-orthographic projection and the fourth connection area overlap, and the fourth connection area and the substrate are connected through the fourth connection structure. That is, part or all of the second non-orthographic projection area is connected to the substrate through the fourth connection structure. The second non-orthographic projection area belongs to the area with low current transmission requirements, low reliability requirements, and high-speed signal transmission. Since the fourth connection structure has advantages such as high signal transmission rate, connecting part or all of the second non-orthographic projection area to the substrate through the fourth connection structure can better meet the connection requirements of this area.

[0031] In one possible implementation, the third connection area faces the edge of the substrate; the edges of the circuit board and the substrate are connected by the third connection structure. This improves the connection between the circuit board and the substrate, thereby enhancing the reliability of the electronic device.

[0032] In one possible implementation, the third connection area is provided with a third groove, the bottom wall of which is connected to the substrate by a third connection structure.

[0033] In one possible implementation, the electronic device further includes a second electronic component, such as a capacitor, inductor, or resistor. This second electronic component is located between the third recess and the substrate, and is connected to the substrate. Because the space between the third recess and the substrate is relatively large, it can accommodate the second electronic component. Thus, by incorporating the second electronic component, the integration level of the electronic device can be improved, and different second electronic components can endow the electronic device with different functions.

[0034] In one possible implementation, a fourth groove is provided in the area of ​​the substrate opposite the third groove; the bottom wall of the third groove and the bottom wall of the fourth groove are connected by a third connecting structure. Of course, the second electronic device can also be disposed in the area between the bottom walls of the third groove and the bottom walls of the fourth groove.

[0035] Thirdly, a circuit board is provided. The circuit board includes a first side and a second side disposed opposite to each other, the first side of the circuit board being used for connection with a package structure. The first side of the circuit board includes a fifth connection area and a sixth connection area, the fifth connection area being provided with a first pad and the sixth connection area being provided with a second pad. The distance between the first pad and the second side is less than the distance between the second pad and the second side. The cross-sectional area of ​​the line connecting the first pad is greater than the cross-sectional area of ​​the line connecting the second pad.

[0036] The cross-sectional area of ​​the trace connecting the first pad is larger than that of the trace connecting the second pad. Traces with larger cross-sectional areas typically carry larger currents, while those with smaller cross-sectional areas typically carry smaller currents. Therefore, the current entering the first pad is greater than the current entering the second pad. Consequently, when this circuit board is connected to the package structure, the larger current is transmitted through the first pad and the larger connection structure, while the smaller current is transmitted through the second pad and the smaller connection structure, minimizing current loss.

[0037] Fourthly, another electronic device is provided. This electronic device includes: a package structure, a fifth connection structure, a sixth connection structure, and a circuit board as described in any possible implementation of the third aspect. The fifth connection area in the package structure and the circuit board is connected via a first pad, and the sixth connection area in the package structure and the circuit board is connected via a second pad. Along the direction toward the package structure, the size of the fifth connection structure is larger than the size of the sixth connection structure.

[0038] As analyzed in the third aspect above, the current entering the first pad is greater than the current entering the second pad. By connecting the larger fifth connection structure to the first pad and the smaller sixth connection structure to the second pad, the larger current will be transmitted through the first pad and the fifth connection structure, while the smaller current will be transmitted through the second pad and the sixth connection structure, thus minimizing current loss. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 These are schematic diagrams of the structures of some electronic devices;

[0041] Figure 2 Here are schematic diagrams of the structures of other electronic devices;

[0042] Figure 3 Here are some structural diagrams of electronic devices;

[0043] Figure 4 Here are some structural diagrams of electronic devices;

[0044] Figure 5 Here are some schematic diagrams of packaging structures;

[0045] Figure 6 Schematic diagrams of some packaging structures provided in the embodiments of this application;

[0046] Figure 7 Schematic diagrams of other packaging structures provided in the embodiments of this application;

[0047] Figure 8 This is a schematic diagram of some other packaging structures provided in the embodiments of this application;

[0048] Figure 9 This is a schematic diagram of some other packaging structures provided in the embodiments of this application;

[0049] Figure 10 Some positional relationship diagrams of the substrate, the first connection structure, and the second connection structure provided in the embodiments of this application;

[0050] Figure 11 This is a schematic diagram of some other packaging structures provided in the embodiments of this application;

[0051] Figure 12 This is a schematic diagram of some other packaging structures provided in the embodiments of this application;

[0052] Figure 13 This is a schematic diagram of some other packaging structures provided in the embodiments of this application;

[0053] Figure 14 Schematic diagrams of the structures of some electronic devices provided in the embodiments of this application;

[0054] Figure 15 Schematic diagrams of other electronic devices provided in the embodiments of this application;

[0055] Figure 16 Schematic diagrams of some circuit boards provided in the embodiments of this application;

[0056] Figure 17Schematic diagrams of the structures of some other electronic devices provided in the embodiments of this application;

[0057] Figure 18 Schematic diagrams of the structures of some other electronic devices provided in the embodiments of this application;

[0058] Figure 19 Schematic diagrams of the structures of some other electronic devices provided in the embodiments of this application;

[0059] Figure 20 Schematic diagrams of the structures of some other electronic devices provided in the embodiments of this application;

[0060] Figure 21 Schematic diagrams of the structures of some other electronic devices provided in the embodiments of this application;

[0061] Figure 22 Schematic diagrams of the structures of some other electronic devices provided in the embodiments of this application;

[0062] Figure 23 This is a bandwidth distribution diagram of different electronic devices provided in the embodiments of this application.

[0063] Figure label:

[0064] 1-Electronic device; 10-Packaging structure; 20-Circuit board; 21-First pad; 22-Second pad.

[0065] 100 - Chip; 200 - Substrate; 300 - Adapter board; 310 - Metal circuit; 320 - Conductive post; 330 - Dielectric material; 410A - First connection structure; 410B - Second connection structure; 420A - Third connection structure; 420B - Fourth connection structure; 430A - Fifth connection structure; 430B - Sixth connection structure; 510 - First electronic device; 520 - Second electronic device; 530 - Third electronic device.

[0066] Area A1 - First Connecting Area; Area A2 - Second Connecting Area; Area B1 - Third Connecting Area; Area B2 - Fourth Connecting Area; Area C1 - Fifth Connecting Area; Area C2 - Sixth Connecting Area. Detailed Implementation

[0067] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the embodiments of this application, and not all embodiments.

[0068] In the following, the terms "first," "second," etc., are used only for descriptive purposes to distinguish identical or similar items that have substantially the same function and effect, and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the embodiments of this application, the term "connection" should be interpreted broadly; unless otherwise explicitly specified and limited, "connection" can be a direct connection or an indirect connection through an intermediate medium.

[0069] To facilitate understanding of the packaging structure provided in the embodiments of this application, the application devices of the packaging structure are described below.

[0070] Packaging structures are widely used in various electronic devices, such as servers, cloud computing electronic devices, AI electronic devices, optical communication devices, mobile phones, tablet personal computers, laptop computers, personal digital assistants (PDAs), cameras, personal computers, laptops, automotive equipment, wearable devices, augmented reality (AR) glasses, AR headsets, virtual reality (VR) glasses, or VR headsets, and other devices that require data processing / storage / transmission and reception.

[0071] Figures 1 to 4 This is a schematic diagram of the structure of some electronic devices 1.

[0072] refer to Figure 1 Electronic device 1 includes a circuit board 20, and a package structure 10 is connected to the circuit board 20, enabling signal transmission between the package structure 10 and the circuit board 20. In some examples, the circuit board 20 can be a printed circuit board (PCB). As a key structure in electronic device 1, the package structure 10 protects the electronic components (such as chips) within the electronic device 1, improving its security and reliability. Furthermore, the package structure 10 can also be used to establish communication with the outside world and improve the transmission efficiency of circuit signals within the electronic device 1.

[0073] The package structure 10 in electronic device 1 may include various components. The following explains the various different components of the package structure 10:

[0074] refer to Figure 1 and Figure 2The packaging structure 10 includes a chip 100 and a substrate 200 stacked together, interconnected, and the substrate 200 can also be interconnected with other electronic devices (such as a circuit board 20). In short, Figure 2 The adapter board 300 is not included in the package structure 10 shown.

[0075] In some examples, reference Figure 2 Chip 100 and substrate 200 are interconnected via connection structure C1. In some examples, refer to Figure 2 The substrate 200 and the circuit board 20 are interconnected through the connection structure C2.

[0076] refer to Figure 1 and Figure 3 The package structure 10 includes stacked chips 100 and an adapter board 300. The adapter board 300 can be used to interconnect different chips 100, and also to interconnect chips 100 with other electronic devices (such as circuit board 20). The package structure 10 can be an integrated fan-out (Info) package, where the adapter board 300 replaces the substrate 200 for signal transmission, eliminating the need for the substrate 200 and effectively reducing the package height of the package structure 10. In short, Figure 3 The package structure 10 shown does not include the substrate 200.

[0077] In some examples, reference Figure 3 Chip 100 and adapter board 300 are interconnected via connection structure C1. In some examples, refer to... Figure 3 The adapter board 300 and the circuit board 20 are interconnected through the connection structure C2.

[0078] refer to Figure 1 and Figure 4 The packaging structure 10 includes a chip 100, an adapter board 300, and a substrate 200 stacked sequentially. The adapter board 300 can be used to interconnect different chips 100, and also to interconnect chips 100 and substrate 200. In some examples, refer to... Figure 4The adapter board 300 includes conductive elements and dielectric material 330 disposed around the conductive elements. The conductive elements can be one or more of metal lines 310 and conductive posts 320 disposed in through holes. Depending on the conductive elements, the packaging structure 10 can be packaged in either CoWoS-R (chip on wafer on substrate - RDL interposer) or CoWoS-L (chip on wafer on substrate - LocalSilicon Interconnect and RDL Interposer).

[0079] In some examples, reference Figure 4 Chip 100 and adapter board 300 are interconnected via connection structure C1. In some examples, refer to... Figure 4 The adapter board 300 and the base plate 200 are interconnected via the connection structure C3. In some examples, refer to... Figure 4 The substrate 200 and the circuit board 20 are interconnected through the connection structure C2.

[0080] In some examples, reference Figures 2 to 4 The connection structure C1 can be a micro bump (uBump) or a controlled collapse chip connection. In some examples, connection structures C1 and C2 can be a ball grid array (BGA) or multiple arrays of copper pillar bumps (CPB).

[0081] Figures 2 to 4 The encapsulation structure 10 in this application does not constitute a specific limitation on the encapsulation structure 10 described in the embodiments of this application. The encapsulation structure 10 may also include more or fewer components, combinations of certain components, certain split components, arrangements of different components, etc. The embodiments of this application do not make specific limitations in this regard.

[0082] With the continuous advancement of technology, electronic devices 1 are developing towards high performance, multifunctionality, and miniaturization. To achieve these functions, higher requirements are placed on the interconnect bandwidth of the package structure 10 in electronic devices 1. For example, in the field of high-speed serial interface interconnection, high-speed serializers / deserializers (SerDes) or high-speed analog-to-digital / digital-analog converters all require package structure 10 for high bandwidth transmission.

[0083] Figure 5 This is a schematic diagram of some packaging structures 10.

[0084] In some examples, extremely small connection structures or multiple connection structures with very small spacing are used to connect different components in the package structure 10, thereby improving the interconnect bandwidth of the package structure 10. For example, to achieve high-bandwidth transmission of the serializer / deserializer at a rate of 448Gbps, the diameter of the connection structure C3 (such as solder balls) is typically less than 0.3 mm, and the spacing between adjacent connection structures C3 (such as solder balls) is less than 0.5 mm. However, this approach has the following problem: the stress resistance of small-sized connection structures is generally poor, affecting the reliability of the package structure 10. In other examples, refer to Figure 5 A silicon-based or glass-based interconnect bridge structure is provided between the chip 100 and the substrate 200. The interconnect bridge structure contains conductive components that enable the connection between the chip 100 and the substrate 200. However, this solution has the following problems: the fabrication process of the interconnect bridge structure is complex and costly, and it requires precise alignment and connection of one end of the conductive component to the chip 100 and the other end of the conductive component to the substrate 200, placing extremely high demands on the assembly of the interconnect bridge structure.

[0085] In summary, the current packaging structure 10 is difficult to simultaneously achieve high bandwidth transmission, superior reliability, and superior power supply capability. It also suffers from problems such as complex manufacturing process and high manufacturing cost, which restrict the large-scale use of the packaging structure 10.

[0086] Based on this, embodiments of this application propose a packaging structure 10 and an electronic device 1, which combines high bandwidth transmission, superior reliability, and superior power supply capability. Furthermore, the packaging structure 10 requires minimal design work, is compatible with existing manufacturing processes, and is easily industrialized.

[0087] Figure 6 and Figure 7 This is a schematic diagram of some packaging structures 10 provided in the embodiments of this application.

[0088] This application provides a packaging structure 10. (See reference...) Figure 6 and Figure 7 The packaging structure 10 includes a chip 100, a substrate 200, an adapter board 300, a first connection structure 410A, and a second connection structure 410B.

[0089] Chip 100 can be a single bare die or a multi-chip assembly.

[0090] In some examples, the multi-chip assembly can be a structure consisting of multiple bare chips arranged side-by-side along a direction perpendicular to the thickness of the substrate 200. For example, see reference... Figure 6A multi-chip assembly is a structure consisting of multiple chips 100 arranged side-by-side along a direction perpendicular to the thickness of the substrate 200. In other examples, a multi-chip assembly can be a structure consisting of multiple bare chips stacked along the thickness of the substrate 200, for example, a high bandwidth memory (HBM).

[0091] Adapter board 300 is connected to one side of chip 100.

[0092] In some examples, chip 100 and adapter board 300 are interconnected via connection structure C1. The description of connection structure C1 can be found in the previous examples and will not be repeated here. In some examples, an underfill may be provided around connection structure C1. This underfill fills the gap between chip 100 and adapter board 300, enhancing the connection strength and providing mechanical protection.

[0093] In some examples, the adapter board 300 includes conductive elements and a dielectric material 330 disposed around the conductive elements. The conductive elements can be metal lines 310 or conductive posts 320 disposed in through-holes. The metal lines 310 can enable signal transmission between different chips 100, and also enable signal transmission between different chips 100 and the substrate 200; the conductive posts 320 can enable signal transmission between different chips 100 and the substrate 200. The dielectric material 330 can include one or more of polyimide (PI), epoxy resin, ceramic, or glass.

[0094] The substrate 200 is located on the side of the adapter plate 300 facing away from the chip 100. The chip 100, adapter plate 300, and substrate 200 are stacked sequentially. The side of the substrate 200 facing the adapter plate 300 includes a first connection area A1 and a second connection area A2. The vertical distance between the first connection area A1 and the adapter plate 300 is greater than the vertical distance between the second connection area A2 and the adapter plate 300. Due to the presence of the first connection area A1 and the second connection area A2, the side of the substrate 200 facing the adapter plate 300 generally exhibits a stepped structure.

[0095] In some examples, substrate 200 can be a flip chip ball grid array (FCBGA) package substrate, which can be used for high-density integrated circuits in flip chip ball grid array packaging.

[0096] The first connecting structure 410A is located between the first connecting area A1 and the adapter plate 300, and the first connecting area A1 and the adapter plate 300 are connected by the first connecting structure 410A. Because the vertical distance between the first connecting area A1 and the adapter plate 300 is large, the size of the first connecting structure 410A is large.

[0097] In this embodiment, the first connection area A1 and the adapter board 300 are connected by a first connection structure 410A. This means that the lines in the first connection area A1 and the lines in the adapter board 300 are connected by the first connection structure 410A. For example, when the first connection structure 410A is a solder ball, the first connection area A1 is provided with solder pads, and the adapter board 300 is also provided with solder pads, one end of the solder ball is connected to the solder pad on the first connection area A1, and the other end of the solder ball is connected to the solder pad on the adapter board 300.

[0098] The second connection structure 410B is located between the second connection area A2 and the adapter board 300, and the second connection area A2 and the adapter board 300 are connected by the second connection structure 410B. Because the vertical distance between the second connection area A2 and the adapter board 300 is small, the size of the second connection structure 410B is smaller. In other words, along the direction towards the chip 100, the size of the first connection structure 410A is larger than the size of the second connection structure 410B. Of course, the volume of the first connection structure 410A is also generally larger than that of the second connection structure 410B.

[0099] In this embodiment, the second connection area A2 and the adapter board 300 are connected by the second connection structure 410B. This means that the lines in the second connection area A2 and the lines in the adapter board 300 are connected through the second connection structure 410B. For example, when the second connection structure 410B is a solder ball, the second connection area A2 is provided with solder pads, and the adapter board 300 is also provided with solder pads, one end of the solder ball is connected to the solder pad on the second connection area A2, and the other end of the solder ball is connected to the solder pad on the adapter board 300.

[0100] The beneficial effects of the packaging structure 10 provided in the embodiments of this application are described in detail below:

[0101] When materials are similar or identical, smaller dimensions mean a smaller cross-sectional area. According to the resistance formula, the first connection structure 410A has a larger dimension and a larger cross-sectional area, thus exhibiting lower resistance. According to Joule's law, under the same current, the lower resistance of the first connection structure 410A results in less heat generation. In other words, while ensuring the safety of the package structure 10 (i.e., with a fixed local heat load), a higher upper limit current through the first connection structure 410A is beneficial for improving the power supply capability of the package structure 10.

[0102] When the materials are similar or the same, the size of the connection structure and the stress-bearing capacity of the connection structure are roughly proportional. The first connection structure 410A has a larger size, so the first connection structure 410A has a better stress-bearing capacity.

[0103] Within the same installation space, a larger size means fewer connection structures, and the number of connection structures directly affects the density of electrical connection points, thus affecting the interconnect bandwidth of the package structure 10. Because the second connection structure 410B is smaller, there are more second connection structures 410B within the same installation space, therefore the area where the second connection structure 410B is installed has a faster interconnect speed.

[0104] When signal strengths are similar or identical, the length of the signal transmission path affects the interconnect bandwidth of the package structure 10. Because the second connection structure 410B is smaller, the area where the second connection structure 410B is located has a faster interconnect speed.

[0105] In the packaging structure 10 provided in this application embodiment, a larger first connection structure 410A is used to connect the first connection area A1 and the adapter board 300. The higher upper limit current of the first connection structure 410A improves the power supply capability of the packaging structure 10. Simultaneously, the first connection structure 410A has superior stress resistance, making it less prone to fatigue fracture and improving the reliability of the packaging structure 10. A smaller second connection structure 410B is used to connect the adapter board 300 and the second connection area A2. The second connection area A2 can accommodate more second connection structures 410B, resulting in more electrical connection points. Furthermore, the signal transmission path through the smaller second connection structure 410B is shorter, and the area with the second connection structure 410B has a faster interconnection rate, enabling high-bandwidth interconnection of the packaging structure 10. In summary, the packaging structure 10 provided in this application embodiment combines high-bandwidth transmission, superior reliability, and superior power supply capability. Moreover, it requires minimal design work, is compatible with existing manufacturing processes, and is easily industrialized.

[0106] For chips that achieve high-speed interconnection using high-speed differential signals, such as AI chips (e.g., high-speed serializers / deserializers, high-speed analog-to-digital / digital-to-analog converters, etc.) and network chips, the continuous development of technology and the resulting increase in chip computing power lead to a continuous increase in power consumption. This places higher demands on the signal transmission rate, reliability, and power supply capabilities of the packaged structures containing these chips. The packaged structure 10 provided in this application embodiment combines high bandwidth transmission, superior reliability, and superior power supply capabilities, effectively meeting the needs of such chips.

[0107] In some embodiments, reference Figure 6 and Figure 7 The first connecting area A1 is provided with a first groove, and the bottom wall of the first groove and the adapter plate 300 are connected by a first connecting structure 410A. The shape of the first groove can be cylindrical or cubic, etc., and this embodiment does not limit it.

[0108] In some examples, the bottom wall of the first groove is provided with pads (not shown in the figure), and the adapter plate 300 is also provided with pads. One end of the first connecting structure 410A is connected to the pads on the bottom wall of the first groove, and the other end of the first connecting structure 410A is connected to the pads on the adapter plate 300. In some examples, the second connecting area A2 may also be provided with pads (not shown in the figure). One end of the second connecting structure 410B is connected to the pads on the second connecting area A2, and the other end of the second connecting structure 410B is connected to the pads on the adapter plate 300.

[0109] In some embodiments, reference Figure 6 The second connection area A2 is a planar area, and the planar area and the adapter plate 300 are connected by the second connection structure 410B. In other embodiments, refer to Figure 7 The second connection area A2 is provided with a groove, and the bottom wall of the groove and the adapter plate 300 are connected by the second connection structure 410B.

[0110] Figure 8 This is a schematic diagram of some packaging structures 10 provided in the embodiments of this application.

[0111] In some embodiments, reference Figure 8 The packaging structure 10 also includes a first electronic device 510, which is located between the first recess and the adapter plate 300 and is connected to the adapter plate 300. The space between the first recess and the adapter plate 300 is large enough to accommodate the first electronic device 510. In this way, by setting the first electronic device 510, the integration of the packaging structure 10 can be improved, and different first electronic devices 510 can also give the packaging structure 10 different functions.

[0112] In some examples, the first electronic device 510 includes devices such as capacitors, inductors, or resistors. The first electronic device 510 can be connected to the adapter board 300 by means of adhesive bonding or other methods.

[0113] For example, when the first electronic device 510 is a capacitor, the capacitor has the characteristic of storing and releasing charge, which can stabilize the voltage output from the power supply to the chip 100, alleviate or avoid excessive voltage fluctuations, and allow the chip 100 to always operate under a stable voltage, thus improving the robustness of the power supply network. In addition, the capacitor has a filtering effect, which can filter out high-frequency noise in the power supply and reduce unnecessary circuit switching and power consumption caused by noise; especially for some high-speed digital circuits, signal jitter is easily caused by power supply noise, which in turn consumes too much energy, and the filtering effect of the capacitor can effectively reduce the occurrence of such situations.

[0114] In some embodiments, a plurality of first connection regions A1 are provided on the substrate 200, and at least a portion of the first connection regions A1 are provided with first grooves. One or more first connection structures 410A and one or more first electronic devices 510 may be provided within a single first groove. For example, all the first grooves in the plurality of first connection regions A1 are provided with both a first connection structure 410A and a first electronic device 510. As another example, a portion of the first grooves in the plurality of first connection regions A1 are provided with both a first connection structure 410A and a first electronic device 510, while another portion of the first grooves in the plurality of first connection regions A1 are provided with only a first connection structure 410A.

[0115] In other embodiments, the space between the substrate 200 and the adapter plate 300 is relatively large, and the substrate 200 and the adapter plate 300 are connected using a relatively large first connection structure 410A. This can easily lead to at least one of the following problems:

[0116] First, within the same set space, a larger connection structure means a smaller number of connection structures. The use of a relatively large first connection structure 410A between the substrate 200 and the adapter board 300 results in a smaller number of first connection structures 410A, leading to a lower density of electrical connection points between the substrate 200 and the adapter board 300, making it difficult to achieve high-bandwidth transmission in the package structure. This is especially true for chips requiring high-speed differential signal interconnection, such as A1 chips and network chips, which have extremely high interconnection rate requirements. The low density of electrical connection points between the substrate 200 and the adapter board 300 limits the improvement of interconnection rate and makes it difficult to achieve high-bandwidth transmission in the package structure 10.

[0117] Second, when signal strengths are similar or the same, the distance of the signal transmission path affects the interconnect bandwidth of the package structure 10. Because the second connection structure 410B is larger, the signal transmission path through the second connection structure 410B is longer, resulting in a slower interconnect rate in the area where the first connection structure 410A is located. This further limits the improvement of the interconnect rate and makes it difficult to achieve high bandwidth transmission in the package structure 10.

[0118] In other embodiments, the space between the substrate 200 and the adapter plate 300 is smaller, and the substrate 200 and the adapter plate 300 are connected using a smaller second connection structure 410B. This can lead to at least one of the following problems:

[0119] First, the connection between the substrate 200 and the adapter board 300 is achieved using a relatively small second connection structure 410B. This results in a small space between the substrate 200 and the adapter board 300, making it difficult to place a first electronic device 510 of a certain size between them. Taking an AI chip or a switching chip as an example, these chips 100 have logic power supplies with large power consumption and large fluctuations. The current demand changes continuously during operation, and the fluctuations in the logic power supply also generate high-frequency noise. If a capacitor is not placed on the surface of the adapter board 300 facing away from the chip 100, the performance and stability of the chip 100 will be severely affected.

[0120] Secondly, given a fixed material, a smaller size means a smaller cross-sectional area. According to the resistance formula, the smaller size and cross-sectional area of ​​the second connection structure 410B result in a larger resistance and thus a larger heat generation. Under the premise of ensuring the safety of the package structure 10, i.e., with a fixed local heat load on the package structure 10, the upper limit current through the second connection structure 410B is relatively low. As the computing power of the chip 100 continues to increase, its power consumption also continues to rise, placing higher demands on the power supply capacity of the package structure 10. Connecting the substrate 200 and the adapter board 300 through the smaller second connection structure 410B is insufficient to meet the ever-increasing power supply requirements of the package structure 10.

[0121] Third, given a fixed material, a smaller size implies a poorer stress-bearing capacity. Due to the differences in the coefficients of thermal expansion between different components, thermal stress is easily generated between them. The smaller size of the second connection structure 410B results in a poorer stress-bearing capacity and a greater risk of fatigue fracture, thus leading to poorer reliability of the packaging structure 10.

[0122] Figure 9 Schematic diagrams of some other packaging structures 10 provided in the embodiments of this application; Figure 10 A diagram showing the positional relationship of the substrate 200, the first connection structure 410A, and the second connection structure 410B provided in the embodiments of this application.

[0123] In some embodiments, reference Figure 9 and Figure 10The adapter board 300 includes a first line and a second line, the cross-sectional area of ​​the first line is larger than that of the second line; the first line is connected to the first connection structure 410A, and the second line is connected to the second connection structure 410B.

[0124] The cross-sectional area of ​​a circuit is generally directly proportional to the magnitude of the current. The cross-sectional area of ​​the first circuit is larger than that of the second circuit, resulting in a greater current transmitted through the first circuit than through the second. When materials are similar or identical, the size of a connection structure is generally inversely proportional to its resistance. Along the direction towards the chip, the size of the first connection structure 410A is larger than that of the second connection structure 410B, meaning the resistance of the first connection structure 410A is less than that of the second connection structure 410B. The larger current output from the first circuit is transmitted through the lower-resistance first connection structure 410A, while the smaller current output from the second circuit is transmitted through the higher-resistance second connection structure 410B. This minimizes current loss and improves the power supply capability of the package structure 10.

[0125] In some embodiments, the orthographic projection of the chip 100 onto the substrate 200 (referred to as the first orthographic projection) overlaps with the first connection region A1. It can also be understood that there is at least partial overlap between the area of ​​the substrate 200 directly opposite the chip 100 (referred to as the first opposite area) and the first connection region A1.

[0126] Since high-current paths are typically concentrated in the first facing region, this region has high requirements for current transmission and is primarily used for transmitting non-high-speed signals. Furthermore, chip 100 is susceptible to various external forces during operation, such as vibration and impact, making it prone to fatigue fracture. Therefore, the first facing region requires high reliability. In summary, the first facing region is characterized by high current transmission requirements, high reliability requirements, and is used for non-high-speed signal transmission.

[0127] The first orthographic projection and the first connection area A1 overlap, and the first connection area A1 and the adapter plate 300 are connected by the first connection structure 410A. That is, the first opposing area can be connected to the adapter plate 300 through the first connection structure 410A. Since the first connection structure 410A has advantages such as a large upper limit current and strong stress resistance, connecting the first opposing area to the adapter plate 300 through the first connection structure 410A can well meet the connection requirements of this area.

[0128] In some examples, the first opposing region can completely overlap with the first connecting region A1, meaning that the first opposing regions are all connected to the adapter plate 300 using the first connecting structure 410A. See the example for reference. Figure 9In some examples, a portion of the first facing region of the substrate 200 coincides with the first connection region A1, and another portion of the first facing region coincides with the second connection region A2.

[0129] In some embodiments, the other regions of the substrate 200 other than the first orthographic projection (referred to as the first non-orthographic projection) and the second connection region A2 overlap. It can also be understood that, apart from the region facing the chip 100, the other regions of the substrate 200 (referred to as the first non-facing region) and the second connection region A2 have at least a partial overlap.

[0130] Since the pins and wiring areas used for signal transmission are typically concentrated in the first non-aligned area, as the integration density of the chip increases, the number of signals that need to be transmitted also increases. To achieve high-density signal wiring within a limited space, a smaller second connection structure 410B can be used to arrange more pins, thereby meeting the needs of more signal transmission. In summary, the first non-aligned area is an area with lower current transmission requirements, lower reliability requirements, and high-speed signal transmission.

[0131] The first non-orthographic projection and the second connection area A2 overlap. The second connection area A2 and the adapter board 300 are connected by the second connection structure 410B. That is, the first non-orthographic area is connected to the adapter board 300 through the second connection structure 410B. Since the second connection structure 410B has advantages such as a faster signal transmission rate, connecting the first non-orthographic area to the adapter board 300 through the second connection structure 410B can better meet the connection requirements of this area.

[0132] In some examples, the first non-aligned area can completely overlap with the second connecting area A2, meaning that the first non-aligned area is connected to the adapter plate 300 using the second connecting structure 410B. In other examples, a portion of the first non-aligned area overlaps with the first connecting area A1, and another portion of the first non-aligned area overlaps with the second connecting area A2. See examples for reference. Figure 9 The first non-directly facing area is simultaneously provided with a first connecting area A1 and a second connecting area A2.

[0133] In some embodiments, reference Figure 9 and Figure 10 The first connection area A1 is directly opposite the edge of the adapter plate 300, and the edges of the substrate 200 and the adapter plate 300 are connected by the first connection structure 410A in the first connection area A1.

[0134] Since the edge of the adapter plate 300 is a critical location for the connection between the substrate 200 and the adapter plate 300, it is highly susceptible to loosening and separation between the edges of the substrate 200 and the adapter plate 300 under external forces such as vibration or impact. The first connection structure 410A is used to connect the edges of the substrate 200 and the adapter plate 300. The first connection structure 410A has better stress resistance and a larger contact area with the substrate 200 and the adapter plate 300, which can improve the connection effect between the substrate 200 and the adapter plate 300, thereby improving the reliability of the packaging structure 10.

[0135] In some examples, the first connection region A1 may be located in part or all of the edge region of the substrate 200. For example, see reference. Figure 10 The first connection area A1 is mainly located in the four corner edge areas of the substrate 200.

[0136] In some embodiments, reference Figure 9 Along the direction toward chip 100, the first connection structure 410A has a size of L1, and the second connection structure 410B has a size of L2. The ratio of L1 to L2 is (1.2-3):1. For example, it can be 1.2:1, 1.5:1, 2:1, 2.5:1, or 3:1.

[0137] By limiting the ratio of L1 to L2 within the aforementioned range, the dimensions of both the first connection structure 410A and the second connection structure 410B are moderate, and the package structure 10 combines high bandwidth transmission, superior reliability, and superior power supply capability. Furthermore, it can mitigate or avoid an excessively large ratio of L1 to L2, which would cause the size of the first connection structure 410A to be much larger than the size of the second connection structure 410B, resulting in poor signal transmission performance of the first connection structure 410A and affecting high-speed signal transmission in the package structure 10. Conversely, it can mitigate or avoid an excessively small ratio of L1 to L2, which would cause the size of the first connection structure 410A to be close to the size of the second connection structure 410B, making it difficult to meet the different connection requirements of different areas of the adapter board 300 and the substrate 200, and resulting in poor reliability of the package structure 10.

[0138] In some embodiments, along a direction perpendicular to the chip 100, the average cross-sectional area of ​​the first connection structure 410A is S1, and the average cross-sectional area of ​​the second connection structure 410B is S2, where S1 is greater than S2.

[0139] The cross-sectional area of ​​a connection structure is generally inversely proportional to its resistance. The first connection structure 410A has a larger average cross-sectional area, therefore its resistance is smaller; conversely, the first connection structure 410A has a smaller average cross-sectional area, therefore its resistance is larger. In this way, larger currents are transmitted through the smaller-resistance first connection structure 410A, while smaller currents are transmitted through the larger-resistance second connection structure 410B, minimizing current loss and improving the power supply capability of the package structure 10.

[0140] In some embodiments, the ratio of S1 to S2 is (1.2-3):1. For example, it can be 1.2:1, 1.5:1, 2:1, 2.5:1, or 3:1. Thus, the average cross-sectional area of ​​the first connection structure 410A and the average cross-sectional area of ​​the second connection structure 410B are moderate, and the packaging structure 10 combines high bandwidth transmission, superior reliability, and superior power supply capability.

[0141] Figure 11 and Figure 12 This is a schematic diagram of another packaging structure 10 provided in the embodiments of this application.

[0142] In some embodiments, the first connection structure 410A and the second connection structure 410B each independently include at least one of a solder ball and a metal pillar (also referred to as a direct pad-to-pad connection). Thus, the first connection structure 410A and the second connection structure 410B possess excellent electrical and mechanical properties, which is beneficial for improving the high-speed signal transmission and reliability of the package structure 10.

[0143] Example, reference Figure 9 Both the first connection structure 410A and the second connection structure 410B are solder balls. For another example, see [reference needed]. Figure 11 and Figure 12 The first connecting structure 410A is a solder ball, and the second connecting structure 410B is a metal pillar.

[0144] In some embodiments, the materials of the first connection structure 410A and the second connection structure 410B include one or more of tin, silver and copper.

[0145] In some examples, the first connection structure 410A and the second connection structure 410B are made of the same material. Thus, the first connection structure 410A and the second connection structure 410B can be fabricated in a simple and easy manner, which helps to reduce the fabrication cost of the encapsulation structure 10.

[0146] In some embodiments, the first connection structure 410A is connected to the substrate 200 and the adapter plate 300 by welding. Of course, the second connection structure 410B can also be connected to the substrate 200 and the adapter plate 300 by welding.

[0147] In some embodiments, reference Figure 12 The adapter plate 300 has a second groove in the area opposite the first groove; the bottom wall of the first groove and the bottom wall of the second groove are connected by a first connecting structure 410A. Of course, the first electronic device 510 can also be disposed in the area between the bottom wall of the first groove and the bottom wall of the second groove.

[0148] Figures 13 to 15 This is a schematic diagram of the structure of some electronic devices 1 provided in the embodiments of this application. To better illustrate the reference numerals for each component, Figures 13 to 15 The reference numerals for the first connection area A1 and the second connection area A2 are not shown in the attached drawings. Please refer to [the provided text]. Figure 7 and Figure 9 The annotation.

[0149] This application provides an electronic device 1. (See reference...) Figure 13 The electronic device 1 includes a circuit board 20 and a packaging structure 10 as described in the foregoing embodiments; the substrate 200 in the packaging structure 10 is connected to the circuit board 20. The beneficial effects of the electronic device 1 can be found in the description of the beneficial effects of the packaging structure 10 in the foregoing embodiments, and will not be repeated here.

[0150] In some embodiments, reference Figure 14 The circuit board 20 includes a third connection area B1 and a fourth connection area B2 on the side facing the substrate 200; the electronic device 1 also includes a third connection structure 420A and a fourth connection structure 420B, the substrate 200 and the third connection area B1 are connected by the third connection structure 420A, and the substrate 200 and the fourth connection area B2 are connected by the fourth connection structure 420B; wherein, along the direction toward the chip, the size of the third connection structure 420A is larger than the size of the fourth connection structure 420B.

[0151] In the aforementioned electronic device 1, a larger third connection structure 420A is used to connect the substrate 200 and the third connection region B1, while a smaller fourth connection structure 420B is used to connect the substrate 200 and the fourth connection region B2. The third connection structure 420A is similar to the first connection structure 410A in the aforementioned embodiments, and has advantages such as a larger upper limit current and stronger stress resistance. The fourth connection structure 420B is similar to the second connection structure 410B in the aforementioned embodiments, and has advantages such as a faster signal transmission rate. The electronic device 1 provided in this application embodiment combines high bandwidth transmission, superior reliability, and superior power supply capability.

[0152] In some embodiments, reference Figure 14 The orthographic projection of chip 100 on circuit board 20 (referred to as the second orthographic projection) overlaps with the third connection area B1. Alternatively, it can be understood that there is at least partial overlap between the area of ​​circuit board 20 directly facing chip 100 (referred to as the second facing area) and the third connection area B1.

[0153] The second orthographic projection and the third connection area B1 overlap, and the third connection area B1 and the substrate 200 are connected through the third connection structure 420A. That is, the second opposing area can be connected to the substrate 200 through the third connection structure 420A. The second opposing area is an area with high current transmission requirements, high reliability requirements, and is not a high-speed signal transmission area. Since the third connection structure 420A has advantages such as a large upper limit current and strong stress resistance, connecting the second opposing area to the substrate 200 through the third connection structure 420A can well meet the connection requirements of this area.

[0154] In some embodiments, reference Figure 14 The other areas of the circuit board 20, excluding the second orthographic projection (referred to as the second non-orthographic projection), overlap with the fourth connection area B2. Alternatively, it can be understood that, excluding the area directly opposite the chip 100, the other areas of the circuit board 20 (referred to as the second non-orthographic area) and the fourth connection area B2 have at least partial overlap.

[0155] The second non-orthographic projection and the fourth connection area B2 overlap, and the fourth connection area B2 and the substrate 200 are connected by the fourth connection structure 420B. That is, part or all of the second non-orthographic projection area is connected to the substrate 200 through the fourth connection structure 420B. The second non-orthographic projection area belongs to the area with low current transmission requirements, low reliability requirements, and high-speed signal transmission. Since the fourth connection structure 420B has advantages such as high signal transmission rate, connecting part or all of the second non-orthographic projection area to the substrate 200 through the fourth connection structure 420B can better meet the connection requirements of this area.

[0156] In some embodiments, reference Figure 14 The third connection area B1 is directly opposite the edge of the substrate 200; the edges of the circuit board 20 and the substrate 200 are connected by the third connection structure 420A. Thus, since the third connection structure 420A has superior stress-bearing capacity, connecting the edges of the circuit board 20 and the substrate 200 through the third connection structure 420A improves the connection effect between the circuit board 20 and the substrate 200, thereby improving the reliability of the electronic device 1.

[0157] In some embodiments, reference Figure 14 The electronic device 1 also includes a second electronic component 520, which includes devices such as capacitors, inductors, or resistors. The second electronic component 520 is located between the third recess and the substrate 200, and is connected to the substrate 200. Because the space between the third recess and the substrate 200 is relatively large, it can accommodate the second electronic component 520. Thus, by incorporating the second electronic component 520, the integration level of the electronic device 1 can be improved, and different second electronic components 520 can give the electronic device 1 different functions.

[0158] The description of the second electronic device 520 can be referred to the first electronic device 510 in the foregoing embodiments; the description of the third connection structure 420A and the fourth connection structure 420B can be referred to the first connection structure 410A and the second connection structure 410B in the foregoing embodiments, and will not be repeated here.

[0159] In some embodiments, reference Figure 15 The substrate 200 has a fourth groove in the area opposite the third groove; the bottom wall of the third groove and the bottom wall of the fourth groove are connected by a third connecting structure 420A. Of course, the second electronic device 520 can also be disposed in the area between the bottom wall of the third groove and the bottom wall of the fourth groove.

[0160] Figure 16 The following are schematic diagrams of the structure of some circuit boards 20 provided in the embodiments of this application.

[0161] This application provides a circuit board 20. (See reference...) Figure 16 The circuit board 20 includes a first side and a second side disposed opposite to each other. The first side of the circuit board 20 is used for connection with the package structure 10. The first side of the circuit board 20 includes a fifth connection area C1 and a sixth connection area C2. A first pad 21 is provided in the fifth connection area C1, and a second pad 22 is provided in the sixth connection area C2. The distance between the first pad 21 and the second side is less than the distance between the second pad 22 and the second side. The cross-sectional area of ​​the line connecting the first pad 21 is greater than the cross-sectional area of ​​the line connecting the second pad 22.

[0162] The distance between the first pad 21 and the second side is less than the distance between the second pad 22 and the second side. In other words, the distance between the first pad 21 and the package structure 10 is greater than the distance between the second pad 22 and the package structure 10. Therefore, a larger connection structure is needed to connect the first pad 21 and the package structure 10, and a smaller connection structure is needed to connect the second pad 22 and the package structure 10.

[0163] The cross-sectional area of ​​the line connecting the first pad 21 is larger than that of the line connecting the second pad 22. Lines with larger cross-sectional areas typically carry larger currents, while lines with smaller cross-sectional areas typically carry smaller currents. Therefore, the current entering the first pad 21 is greater than the current entering the second pad 22. Consequently, when the circuit board 20 is connected to the package structure 10, the larger current is transmitted through the first pad 21 and the larger connection structure, while the smaller current is transmitted through the second pad 22 and the smaller connection structure, minimizing current loss.

[0164] Figures 17 to 22 This is a schematic diagram of the structure of some electronic devices 1 provided in the embodiments of this application.

[0165] This application provides another electronic device 1. (See also...) Figures 17 to 22 The electronic device 1 includes a package structure 10, a fifth connection structure 430A, a sixth connection structure 430B, and a circuit board 20 as described in the previous embodiment. The first pad 21 in the package structure 10 and the circuit board 20 is connected via the fifth connection structure 430A, and the second pad 22 in the package structure 10 and the circuit board 20 is connected via the sixth connection structure 430B. Along the direction toward the package structure 10, the size of the fifth connection structure 430A is larger than the size of the sixth connection structure 430B.

[0166] In the aforementioned electronic device 1, a larger fifth connection structure 430A is used to connect the substrate 200 and the first pad 21, while a smaller sixth connection structure 430B is used to connect the substrate 200 and the second pad 22. The fifth connection structure 430A is similar to the first connection structure 410A in the aforementioned embodiment, and has advantages such as a larger upper limit current and stronger stress resistance. The sixth connection structure 430B is similar to the second connection structure 410B in the aforementioned embodiment, and has advantages such as a faster signal transmission rate. The electronic device 1 provided in this application embodiment combines high bandwidth transmission, superior reliability, and superior power supply capability.

[0167] In some embodiments, reference Figures 17 to 22 The electronic device 1 also includes a third electronic component 530, which includes devices such as capacitors, inductors, or resistors. The third electronic component 530 is located between the first pad 21 and the substrate 200, and is connected to the substrate 200. Because the space between the first pad 21 and the substrate 200 is relatively large, it can accommodate the third electronic component 530. Thus, by incorporating the third electronic component 530, the integration density of the electronic device 1 can be improved, and different third electronic components 530 can give the electronic device 1 different functions.

[0168] In some examples, reference Figures 17 to 22Along the direction toward chip 100, the fifth connection structure 430A has a size of 0.2 mm to 0.6 mm. For example, it can be 0.2 mm, 0.3 mm, 0.4 mm, 0.5 mm or 0.6 mm.

[0169] By limiting the size of the fifth connection structure 430A within the aforementioned range, the fifth connection structure 430A has a moderate size, low resistance, and a high upper limit current, resulting in high power supply capability for electronic device 1 and enabling high-speed signal transmission. Furthermore, the fifth connection structure 430A's moderate size, superior stress resistance, and resistance to fatigue fracture contribute to the superior reliability of electronic device 1.

[0170] In some examples, reference Figures 17 to 22 Along the direction toward chip 100, the sixth connection structure 430B has a size of 0.2 mm to 0.35 mm. For example, it can be 0.2 mm, 0.25 mm, 0.3 mm or 0.35 mm.

[0171] The size of the sixth connection structure 430B is limited to the aforementioned range. The size of the sixth connection structure 430B is moderate, and the area where the sixth connection structure 430B is provided has a faster interconnection rate, which is conducive to realizing high broadband interconnection of electronic device 1.

[0172] In some examples, reference Figures 17 to 22 The electronic device 1 includes a plurality of fifth connection structures 430A, with the spacing between adjacent fifth connection structures 430A ranging from 0.5 mm to 1.5 mm, for example, 0.5 mm, 0.7 mm, 0.9 mm, 1.0 mm, 1.3 mm, or 1.5 mm. In some examples, refer to... Figure 10 The electronic device 1 has a plurality of sixth connection structures 430B, and the spacing between adjacent sixth connection structures 430B is 0.2 mm to 0.8 mm, for example, 0.2 mm, 0.4 mm, 0.6 mm, or 0.8 mm. In some examples, the spacing between adjacent sixth connection structures 430B is greater than the spacing between adjacent fifth connection structures 430A.

[0173] By limiting the spacing between adjacent fifth connection structures 430A within the aforementioned range, and ensuring a moderate spacing, there are more electrical connection points between the circuit board 20 and the substrate 200, which can provide better signal transmission performance. Furthermore, this spacing can alleviate or prevent stress on the electronic device 1 that could cause adjacent fifth connection structures 430A to connect, reducing or avoiding short circuits and improving the safety of the electronic device 1. The effects of the sixth connection structure 430B are similar to those of the fifth connection structure 430A, and will not be described further here.

[0174] It should be noted that when the aforementioned connection structures (such as the fifth connection structure 430A) are used as solder, the dimensions of the aforementioned connection structures are the dimensions after reflow soldering (ball height after reflow).

[0175] The different components of electronic device 1 are explained below:

[0176] In some examples, reference Figure 17 The electronic device 1 includes a chip 100, a substrate 200, a fifth connection structure 430A, a sixth connection structure 430B, and a circuit board 20 as described in the previous embodiment. The substrate 200 is connected to one side of the chip 100. The first pad 21 in the substrate 200 and the circuit board 20 are connected via the fifth connection structure 430A, and the second pad 22 in the substrate 200 and the circuit board 20 are connected via the sixth connection structure 430B. Along the direction toward the package structure 10, the size of the fifth connection structure 430A is larger than the size of the sixth connection structure 430B. The beneficial effects produced by this electronic device 1 can be referred to the aforementioned beneficial effects, and will not be repeated here.

[0177] In other examples, refer to Figure 19 The electronic device 1 includes a chip 100, an adapter board 300, a fifth connection structure 430A, a sixth connection structure 430B, and a circuit board 20 as described in the previous embodiment. The adapter board 300 is connected to one side of the chip 100. The adapter board 300 and the first pad 21 in the circuit board 20 are connected via the fifth connection structure 430A, and the adapter board 300 and the second pad 22 in the circuit board 20 are connected via the sixth connection structure 430B. Along the direction toward the package structure 10, the size of the fifth connection structure 430A is larger than the size of the sixth connection structure 430B. The beneficial effects produced by this electronic device 1 can be referred to the aforementioned beneficial effects, and will not be repeated here.

[0178] In yet another example, refer to Figure 21The electronic device 1 includes: a chip 100, an adapter board 300, a substrate 200, a fifth connection structure 430A, a sixth connection structure 430B, and a circuit board 20 as described in the previous embodiment. The adapter board 300 is connected to one side of the chip 100. The substrate 200 is located on the side of the adapter board 300 facing away from the chip 100. The substrate 200 and the first pad 21 in the circuit board 20 are connected via the fifth connection structure 430A, and the substrate 200 and the second pad 22 in the circuit board 20 are connected via the sixth connection structure 430B. Along the direction toward the package structure 10, the size of the fifth connection structure 430A is larger than the size of the sixth connection structure 430B. The beneficial effects produced by this electronic device 1 can be referred to the aforementioned beneficial effects, and will not be repeated here.

[0179] In some embodiments, reference Figures 17 to 22 The fifth connection area C1 of the circuit board 20 is provided with a fifth groove, and the bottom wall of the fifth groove is connected to the substrate 200 through the fifth connection structure 430A.

[0180] In some embodiments, reference Figure 18 , Figure 20 and Figure 22 The substrate 200 has a sixth groove in the area opposite the fifth groove; the bottom wall of the fifth groove and the bottom wall of the sixth groove are connected by a fifth connecting structure 430A. Of course, the third electronic device 530 can also be disposed in the area between the bottom wall of the fifth groove and the bottom wall of the sixth groove.

[0181] Figure 23 This is a bandwidth distribution diagram of different electronic devices provided in the embodiments of this application.

[0182] In some embodiments, the following three examples are provided for testing the electronic device 1 provided in the embodiments of this application:

[0183] Example 1 provides a method such as Figure 17 The dimensions of the components in the electronic device 1 shown below are explained:

[0184] Both the fifth connection structure 430A and the sixth connection structure 430B are solder balls;

[0185] In the fifth connection region C1, along the direction toward chip 100, the size of the fifth connection structure 430A (solder ball) before reflow soldering is 600 micrometers, and the size of the fifth connection structure 430A (solder ball) after reflow soldering is 400 micrometers; the center-to-center distance of the fifth connection structure 430A (i.e., the distance between adjacent fifth connection structures 430A, ball pitch) is 900 micrometers.

[0186] In the sixth connection region C2, along the direction toward chip 100, the size of the sixth connection structure 430B (solder ball) before reflow soldering is 300 micrometers, and the size of the sixth connection structure 430B (solder ball) after reflow soldering is 240 micrometers; the center-to-center distance of the sixth connection structure 430B (i.e., the distance between adjacent sixth connection structures 430B, ball pitch) is 500 micrometers.

[0187] Example 2: The fifth connection structure 430A is a solder ball; the sixth connection structure 430B is a metal pillar.

[0188] In the fifth connection region C1, along the direction toward chip 100, the size of the fifth connection structure 430A (solder ball) before reflow soldering is 600 micrometers, and the size of the fifth connection structure 430A (solder ball) after reflow soldering is 400 micrometers; the center-to-center distance of the fifth connection structure 430A (i.e., the distance between adjacent fifth connection structures 430A, ball pitch) is 900 micrometers.

[0189] In the sixth connection region C2, along the direction toward chip 100, the pin height of the sixth connection structure 430B (metal pillar) is 50 micrometers, and the center pitch of the fifth connection structure 430A is 500 micrometers.

[0190] Example 3, the difference between Example 3 and Example 1 is:

[0191] The circuit board 20 does not have a fifth connection area C1, and the circuit board 20 and the substrate 200 are connected by a uniform array of solder balls;

[0192] Along the direction toward chip 100, the size of the solder balls before reflow soldering is 600 micrometers, and the size of the solder balls after reflow soldering is 400 micrometers; the center-to-center distance between the solder balls is 900 micrometers. That is, the size of the solder balls in Example 3 is the same as the size of the fifth connection structure 430A in Example 1.

[0193] Electrical interconnection simulations were performed on electronic devices 1 in Examples 1 to 3. Table 1 shows the bandwidth requirements of the current serializer / deserializer under different modulation methods.

[0194] Table 1

[0195]

[0196] Figure 23 This is a bandwidth distribution diagram of different electronic devices provided in the embodiments of this application. Figure 23 The bandwidth in the figure is the passive channel bandwidth estimated based on 1.2 times the Nyquist frequency.

[0197] refer to Figure 23Example 1 has a bandwidth of 125GHz, which is significantly higher than 108GHz under PAM6 and slightly less than 134GHz under PAM4. Therefore, it supports inter-chip electrical interconnection of serializer / deserializer at a rate of 448Gbps under PAM6 encoding.

[0198] Example 2 has a bandwidth of 142 GHz, which is significantly higher than 108 GHz under PAM6 and 134 GHz under PAM4, thus supporting inter-chip electrical interconnection at a rate of 448 Gbps under both PAM6 and PAM4 encoding.

[0199] Example 3 has a bandwidth of 92 GHz, which is significantly lower than 108 GHz under PAM6 and 134 GHz under PAM4, making it difficult to support inter-chip electrical interconnection at a rate of 448 Gbps under both PAM6 and PAM4 encoding. This demonstrates that the electronic device provided in the embodiments of this application can achieve high bandwidth transmission.

[0200] Although this application has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made thereto without departing from the spirit and scope of this application. Accordingly, this specification and drawings are merely exemplary illustrations of this application as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of this application. Clearly, those skilled in the art can make various alterations and modifications to this application without departing from the spirit and scope of this application. Thus, if such modifications and modifications of this application fall within the scope of the claims of this application and their equivalents, this application is also intended to include such modifications and modifications.

Claims

1. A packaging structure, characterized in that, include: chip; An adapter board is connected to one side of the chip; The substrate is located on the side of the adapter plate opposite to the chip; The side of the substrate facing the adapter plate includes a first connection area and a second connection area; A first connection structure is provided, wherein the adapter plate and the first connection area are connected through the first connection structure. The second connection structure connects the adapter board and the second connection area; wherein, along the direction toward the chip, the size of the first connection structure is larger than the size of the second connection structure.

2. The packaging structure according to claim 1, characterized in that, The adapter board includes a first line and a second line, wherein the cross-sectional area of ​​the first line is larger than the cross-sectional area of ​​the second line. The first line is connected to the first connection structure, and the second line is connected to the second connection structure.

3. The packaging structure according to claim 1 or 2, characterized in that, The orthographic projection of the chip on the substrate overlaps with the first connection area.

4. The packaging structure according to any one of claims 1-3, characterized in that, The first connection area is directly opposite the edge of the adapter plate; the edges of the substrate and the adapter plate are connected by the first connection structure.

5. The packaging structure according to any one of claims 1-4, characterized in that, The first connection area is provided with a first groove, and the bottom wall of the first groove and the adapter plate are connected through the first connection structure.

6. The packaging structure according to claim 5, characterized in that, The packaging structure further includes a first electronic device; the first electronic device is located between the first groove and the adapter plate, and is connected to the adapter plate.

7. The packaging structure according to claim 5 or 6, characterized in that, The adapter plate has a second groove in the area opposite to the first groove; the bottom wall of the first groove and the bottom wall of the second groove are connected by the first connecting structure.

8. The packaging structure according to any one of claims 1-7, characterized in that, Along the direction toward the chip, the size of the first connection structure is L1, the size of the second connection structure is L2, and the ratio of L1 to L2 is (1.2-3):

1.

9. The packaging structure according to any one of claims 1-8, characterized in that, Along a direction perpendicular to the chip, the average cross-sectional area of ​​the first connection structure is S1, and the average cross-sectional area of ​​the second connection structure is S2, where S1 is greater than S2.

10. The packaging structure according to claim 9, characterized in that, The ratio of S1 to S2 is (1.2-3):

1.

11. An electronic device, characterized in that, It includes a circuit board and a packaging structure according to any one of claims 1-10; the substrate in the packaging structure is connected to the circuit board.

12. The electronic device according to claim 11, characterized in that, The circuit board has a third connection area and a fourth connection area on the side facing the substrate; The electronic device further includes a third connection structure and a fourth connection structure, wherein the substrate and the third connection area are connected through the third connection structure, and the substrate and the fourth connection area are connected through the fourth connection structure; In the direction toward the substrate, the size of the third connection structure is larger than the size of the fourth connection structure.

13. A circuit board, characterized in that, The circuit board includes a first side and a second side that are disposed opposite to each other; The first side of the circuit board includes a fifth connection area and a sixth connection area. The fifth connection area is provided with a first pad, and the sixth connection area is provided with a second pad. The distance between the first pad and the second side is less than the distance between the second pad and the second side; The cross-sectional area of ​​the line connecting the first pad is greater than the cross-sectional area of ​​the line connecting the second pad.

14. An electronic device, characterized in that, Includes a packaging structure, a fifth connection structure, a sixth connection structure, and the circuit board as described in claim 13; The packaging structure and the first pad in the circuit board are connected by the fifth connection structure, and the packaging structure and the second pad in the circuit board are connected by the sixth connection structure. Along the direction toward the packaging structure, the size of the fifth connection structure is larger than the size of the sixth connection structure.

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