A power module

Abstract

The application discloses a power module, relates to the field of power modules, and discloses a power module, wherein a semiconductor chip is arranged on the upper surface of a ceramic substrate; a laminated conductive assembly comprises a first conductive member and a second conductive member which are arranged in a laminated and insulated manner in the height direction and are spaced apart; the first conductive member and the second conductive member are electrically connected with the semiconductor chip and the ceramic substrate respectively to form a laminated current loop; a composite heat dissipation substrate comprises a copper layer and a graphene layer; the graphene layer is connected with the copper layer in a composite manner, and the ceramic substrate is arranged on the composite heat dissipation substrate. The application can reduce the stray inductance of the power module, improve the current-carrying capacity and long-term reliability of electrical interconnection, and greatly reduce the thermal resistance of the power module, thereby improving the overall heat dissipation performance.

Description

Technical Field

[0001] This application relates to the field of power modules, and in particular to a power module. Background Technology

[0002] With the rapid development of electric vehicles, rail transportation, new energy power generation, and industrial frequency conversion, the performance requirements for power modules (such as IGBTs, SiC MOSFETs, and other power semiconductor modules) are becoming increasingly stringent. Modern high-performance power modules are evolving towards high power density, high reliability, low stray inductance (low switching losses), and excellent thermal management. However, traditional power module packaging architectures are gradually becoming bottlenecks restricting performance improvement at the two core levels of electrical interconnection and thermal conduction.

[0003] Currently, conventional power module packaging typically employs the following two traditional structures: (1) In terms of electrical interconnection, traditional power modules generally use surface-bonded metal wires (such as aluminum or copper wires) to achieve electrical interconnection between the chip and external terminals. This wire-based connection method has the following obvious limitations: First, the wires are "point contacts" or "line contacts", with relatively large contact resistance and limited current carrying capacity, making it difficult to cope with the ever-increasing demand for ultra-high current density; Second, the loop formed by the wires in space will introduce a large parasitic inductance, which is very easy to generate severe switching overvoltage spikes and additional switching losses when the device performs high-frequency switching operations, limiting the improvement of the module's operating frequency; Finally, due to the mismatch between the coefficient of thermal expansion (CTE) of the wire material and the surface metal layer of the chip, the root of the wire is very prone to thermomechanical fatigue or even detachment under long-term power cycling and thermal stress shock. This is one of the main reasons for the failure of traditional power modules, which seriously affects the long-term reliability of the module.

[0004] (2) In terms of thermal management, traditional power modules typically employ a single and lengthy heat dissipation path: “chip-soldering layer-ceramic substrate-soldering layer-copper base plate-thermal grease-external heat sink.” This multi-layered stacked heat dissipation structure has the following drawbacks: Firstly, the multi-layered material stacking introduces multiple solid-solid contact interfaces, and the thermal conductivity of each layer (especially the solder layer and thermal grease) is limited, resulting in significant interfacial thermal resistance. Secondly, due to the limited in-plane thermal diffusion capacity of traditional metal materials such as the copper base plate, heat tends to accumulate directly beneath the chip during vertical downward conduction. These factors collectively lead to a generally high junction-to-case thermal resistance in traditional modules (typically greater than 0.5 K / W), making it difficult to meet the heat dissipation requirements under ultra-high power density, easily forming hot spots in localized areas of the chip, thereby limiting the full utilization of chip performance and the lifespan of the module.

[0005] Therefore, there is an urgent need in this field for a novel power module packaging architecture to fundamentally reduce the stray inductance of power modules, improve the current carrying capacity and long-term reliability of electrical interconnects, and at the same time significantly reduce the thermal resistance of power modules and improve overall heat dissipation performance. Summary of the Invention

[0006] The purpose of this application is to provide a power module that can reduce stray inductance, improve the current carrying capacity and long-term reliability of electrical interconnects, and significantly reduce thermal resistance of the power module, thereby improving overall heat dissipation performance.

[0007] To achieve the above objectives, this application provides the following solution: In a first aspect, this application provides a power module, including: a ceramic substrate, a semiconductor chip, a stacked conductive component, and a composite heat dissipation substrate; The semiconductor chip is disposed on the upper surface of the ceramic substrate; The stacked conductive assembly includes a first conductive element and a second conductive element that are spaced apart in the height direction and arranged in an insulated stacked layer; the first conductive element and the second conductive element are respectively electrically connected to the semiconductor chip and the ceramic substrate to form a stacked current loop; The composite heat dissipation substrate includes a copper layer and a graphene layer; the graphene layer and the copper layer are compositely connected, and the ceramic substrate is disposed on the composite heat dissipation substrate.

[0008] According to the specific embodiments provided in this application, this application has the following technical effects: This application provides a power module that uses stacked conductive components—specifically, a first conductive element and a second conductive element spaced apart and insulated in the height direction—to form a stacked current loop electrically connected to a semiconductor chip and a ceramic substrate, minimizing the path length of the main power loop. When current flows in opposite or symmetrical directions between the upper and lower stacked conductive elements, a significant magnetic flux cancellation effect is generated, thereby drastically reducing the module's stray inductance (Ls) to an extremely low level. This effectively suppresses overvoltage spikes and additional switching losses generated during high-frequency switching, allowing the device to operate stably at higher switching frequencies, significantly improving the overall system efficiency and power density. The use of stacked conductive components (such as clip-like / strip structures) to replace traditional, easily failing bonded aluminum wires upgrades traditional point or line contacts to large-area "surface contacts," significantly reducing connection resistance and local current density, and greatly improving the module's ability to handle ultra-high current densities. Meanwhile, its robust mechanical connection method can better withstand the thermomechanical stress caused by long-term power cycling and mechanical vibration, fundamentally avoiding the problem of thermal fatigue and detachment caused by the mismatch of thermal expansion coefficients in traditional bonding wires. This increases the power cycle life by an order of magnitude, fully meeting the high reliability requirements of demanding applications such as electric vehicles and rail transportation. The composite heat dissipation substrate, which is connected by a copper layer and a graphene layer, utilizes the anisotropic advantage of material thermal conduction. The copper layer is responsible for efficiently transferring the heat conducted by the ceramic substrate downwards in the vertical direction (Z-axis); while the graphene layer, with its ultra-high in-plane thermal conductivity, can rapidly diffuse the heat received from the copper layer over a large area in the horizontal direction (X / Y plane). The synergistic heat dissipation mechanism of vertical conduction + horizontal diffusion in this application effectively breaks through the bottleneck of the limited heat diffusion capacity of traditional single copper base plates, eliminates local hot spots that are easy to accumulate directly under the chip, and significantly reduces the junction-to-case thermal resistance of the module and the maximum junction temperature of the chip, thereby further releasing the performance potential of the chip and extending the service life of the module. The application achieves low stray inductance, high current carrying capacity, high reliability, and excellent heat dissipation performance through a dual-layer reconstruction of electrical interconnect architecture (stacked conductive circuits) and thermal management materials (copper-graphene composite substrate), providing a highly valuable system solution for the packaging of high power density and high performance power modules. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a schematic diagram of a power module structure in one embodiment of this application; Figure 2 A schematic diagram of the traditional IGBT power device packaging architecture; Figure 3 This is a schematic diagram of the structure of the first conductive element (upper conductive clip); Figure 4 This is a schematic diagram of the structure of the second conductive element (lower conductive clip); Figure 5 This is a schematic diagram of a stacked converter circuit; Figure 6 This is a schematic diagram of the power terminals; Figure 7 This is a schematic diagram of the current path in a tandem converter circuit. Figure 8 This is an analytical diagram of a power module structure according to an embodiment of this application; Figure 9 This is a schematic diagram of the composite heat dissipation substrate structure. Detailed Implementation

[0011] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0012] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0013] In one exemplary embodiment, such as Figure 1 As shown, a power module is provided, which includes a ceramic substrate 5, a semiconductor chip 12, a stacked conductive component 2, and a composite heat dissipation substrate 14. The semiconductor chip 12 is disposed on the upper surface of the ceramic substrate 5; The stacked conductive assembly 2 includes a first conductive element 8 and a second conductive element 11 that are spaced apart in the height direction and arranged in an insulated stacked layer; the first conductive element 8 and the second conductive element 11 are respectively electrically connected to the semiconductor chip 12 and the ceramic substrate 5 to form a stacked current loop. The composite heat dissipation substrate 14 includes a copper layer and a graphene layer 16; the graphene layer 16 is compositely connected to the copper layer, and the ceramic substrate 5 is disposed on the composite heat dissipation substrate 14.

[0014] As a specific embodiment, the stacked conductive component 2 is a stacked clip (sheet or strip) structure; the semiconductor chip 12 is specifically an IGBT / MOSFET chip; and the ceramic substrate 5 is an AMB (Active Metal Brazing) / DBC (Direct Copper Clad) copper-clad ceramic substrate. As a specific example, such as Figure 3 and Figure 4 As shown, both the first conductive element 8 and the second conductive element 11 include: a chip connection portion, a substrate connection portion, and a stacked conductive busbar; The chip connection portion is connected to the surface of the semiconductor chip 12; The substrate connecting portion is connected to the surface of the ceramic substrate 5; The stacked conductive busbars are respectively connected to the chip connection portion and the substrate connection portion; The projected portions of the stacked conductive busbars of the first conductive element 8 and the stacked conductive busbars of the second conductive element 11 on the horizontal plane overlap. The overlapping area determines the degree to which current loop stray inductance is reduced. Specifically, the chip connection portion consists of chip soldering pins 6 and 9, and the substrate connection portion consists of soldering pins 7 and 10 on the AMB / DBC copper-clad ceramic substrate. Further, chip soldering pins 6 and 9 are soldered to the surface of the IGBT / MOSFET chip on the AMB / DBC copper-clad ceramic substrate, forming an electrical circuit. Soldering pins 7 and 10 on the AMB / DBC copper-clad ceramic substrate are soldered to connect the multilayer conductive component 2 to the copper layer of the AMB / DBC copper-clad ceramic substrate, forming an electrical circuit, allowing the current path to... Figure 7 The flow in the converter loop shown is as follows; As a specific embodiment, the semiconductor chip 12 includes an upper transistor chip and a lower transistor chip; The first conductive element 8 is the upper conductive clip, and the second conductive element 11 is the lower conductive clip; like Figure 5 As shown, there is no direct mechanical contact or electrical connection between the upper conductive clip and the lower conductive clip. The vertical distance between them is H1, and the vertical distance between the upper conductive clip (top cu-clip) and the ceramic substrate 5 is H2. The smaller H2 is, the smaller the stacking effect and the lower the module stray inductance. H1 is the air gap between the upper conductive clip and the lower conductive clip, which is used to achieve electrical isolation. The smaller H1 is, the more significant the magnetic flux cancellation effect and the lower the module stray inductance. The upper conductive clip is connected to the upper transistor chip and the lower transistor chip to form the upper bridge arm power circuit; the lower conductive clip is connected to the upper transistor chip and the lower transistor chip to form the lower bridge arm power circuit.

[0015] The semiconductor chip 12 serves as the core switching device of the power module, enabling high-frequency conversion and regulation of electrical energy. The upper surface of the semiconductor chip 12 typically consists of gate and source / emitter pads, which are connected to the chip solder pads of the multilayer conductive assembly 2 via bonding wires or direct connection. The lower surface of the semiconductor chip 12 consists of drain / collector electrodes, which are connected to the multilayer conductive assembly 2 and solder 13 via the upper and lower surfaces, respectively, forming a complete thermally and electrically conductive interface.

[0016] Solder 13 forms the following solder layer, which enables mechanical fixation, electrical connection, and thermal conduction between the semiconductor and the copper-clad ceramic substrate. Typically, high thermal conductivity, low melting point lead-free solder 13 (such as SnAgCu alloy) or high-temperature resistant materials such as sintered silver are selected.

[0017] Specifically, as a particular embodiment, this application also includes DC busbar terminal 1 and AC busbar terminal 3, such as... Figure 6 As shown; The DC bus terminal 1 includes a DC+ terminal and a DC- terminal; the DC+ terminal is electrically connected to the first conductive element 8 or the ceramic substrate 5; the DC- terminal is electrically connected to the second conductive element 11 or the ceramic substrate 5. The AC busbar terminal 3 is electrically connected to the output terminal of the lower tube chip or the ceramic substrate 5. The DC+ terminal, the first conductive element 8, the upper transistor chip, the lower transistor chip, the second conductive element 11, and the DC- terminal constitute a stacked converter circuit.

[0018] Among them, DC bus terminal 1 is used to connect to the external DC bus voltage and serve as the DC power input interface of the module; DC bus terminal 1 is fixed to the corresponding pad or copper layer on the ceramic substrate 5 by soldering or ultrasonic welding, and forms a low-impedance stacked current path with the stacked conductive component 2. like Figure 5 As shown, the current entering the DC+ bus terminal 1 directly enters the upper IGBT / MOSFET chip, passes through the chip to the surface-mounted clip, then enters the copper layer of the lower chip, and flows out through the AC bus terminal 3. The AC bus terminal 3 flows into the lower chip, passes through the chip to the surface-mounted clip, enters the copper layer where the DC- bus terminal 1 is located, and then flows out through the DC- bus terminal 1. From the perspective of the stacked conductive components 2 and the layout, the above DC+ bus to DC- bus current loops form a multi-path large-area stack or symmetrical structure. Due to the magnetic flux cancellation, the effect of reducing stray inductance is obvious.

[0019] AC busbar terminal 3 is used to output the AC current inverted internally to an external load (such as a motor winding), and is the AC output interface of the power module. This terminal is connected to... Figure 5The output terminal of the lower transistor chip shown (e.g., the source / emitter of the lower transistor IGBT / MOSFET) or the copper layer of the corresponding ceramic substrate 5 are electrically connected.

[0020] Specifically, the AC busbar terminal 3 is fixedly connected to the AC output copper layer on the ceramic substrate 5 by soldering or ultrasonic welding. The AC output copper layer of AC busbar terminal 3 is connected to the internal circuit ( Figure 7 The self-designed current path shown is connected to the source / emitter pads of the lower transistor chip, and at the same time forms an electrical path with the stacked conductive component 2 (lower clip or corresponding output clip) soldered to the lower transistor chip. As a specific embodiment, in the DCM (upper arm power circuit and lower arm power circuit) topology, AC bus terminal 3 is connected to Figure 5 The diagram shows the intermediate electrical node between the upper and lower transistor chips, that is, the node where the source / emitter of the upper transistor chip is connected to the drain / collector of the lower transistor chip. like Figure 5 As shown, the current from the lower transistor chip flows through the lower clip (second conductive element 11) or the copper layer (CU) of the ceramic substrate 5 to the AC bus terminal 3, and is finally output to the external load.

[0021] As a specific embodiment, the composite heat dissipation substrate 14 is a copper-graphene-copper sandwich structure or a copper-graphene composite structure; When it is a copper-graphene-copper sandwich structure, the graphene layer 16 is sandwiched between two copper layers. When it is a copper-graphene composite structure, the graphene layer 16 is disposed on the side of the copper layer away from the ceramic substrate 5.

[0022] The composite heat dissipation substrate 14 serves as a heat diffusion layer and structural support layer, rapidly diffusing heat from the ceramic substrate 5 laterally and transferring it downwards to the graphene layer 16. Simultaneously, the copper layer acts as a mechanical base plate for the module, providing mounting strength.

[0023] As a specific example, such as Figure 9 As shown, the composite heat dissipation substrate 14 includes multiple layers of copper foil and graphene film stacked alternately.

[0024] Graphene is one of the materials with the highest known thermal conductivity, with a theoretical in-plane thermal conductivity exceeding 5300 W / (m·K). High-quality graphene films actually prepared can reach over 1500 W / (m·K), which is more than four times that of pure copper. At the same time, since graphene has a single-layer atomic structure, it has excellent high thermal conductivity in the X and Y planes, but does not have this characteristic in the Z direction. This application describes a Cu-graphene hybrid sandwich method to regulate the chip junction temperature, effectively reducing the chip junction temperature and improving the module power density.

[0025] As a specific embodiment, the graphene layer 16 is grown directly on the surface of the copper layer using a chemical vapor deposition process; or, the graphene layer 16 is compositely connected to the copper layer via a thermally conductive adhesive layer. The lower surface of the graphene layer 16 can be coated with thermally conductive silicone grease or directly contact an external heat sink. Preferably, multiple layers of graphene film and multiple layers of copper foil can be alternately laminated to form a "copper-graphene-copper-graphene" composite structure, further improving the overall heat dissipation performance.

[0026] Utilizing the ultra-high thermal conductivity of graphene in the planar direction (X / Y axis) (actually ≥1500 W / (m·K)), heat from the upper copper layer is rapidly distributed horizontally, eliminating local hot spots and significantly reducing the chip junction temperature. Graphene layer 16 has relatively weak thermal conductivity in the vertical direction (Z axis), therefore a copper-graphene sandwich structure is employed, combining the vertical thermal conductivity of copper with the horizontal thermal conductivity of graphene.

[0027] The composite heat dissipation substrate 14 is located at the bottom of the entire stacked structure, that is, below the copper layer of the heat dissipation substrate, and directly faces the external heat sink or cooling medium.

[0028] By utilizing multilayer graphene in an X / Y plane and chip-vertical design, and taking full advantage of graphene's anisotropic heat dissipation properties, a graphene-copper-graphene composite substrate can be formed by directly growing or combining graphene layers 16 on the surface of a copper substrate. This significantly improves the substrate's thermal diffusion capability, allowing the heat generated by the chip to be dissipated more effectively through the graphene layers 16. Furthermore, high-performance graphene heat dissipation substrates can be fabricated according to different chip locations, scenarios, and applications.

[0029] As a specific example, such as Figure 1 As shown, signal drive terminal 4 is used to receive gate control signals (such as PWM pulses) generated by an external drive circuit and transmit these signals to the gate (G) and Kelvin source / emitter (if applicable) of the semiconductor chip 12 inside the module, thereby controlling the switching state of the semiconductor chip 12. Signal drive terminal 4 typically includes multiple pins, corresponding to the gate and source (or Kelvin source) of the upper and lower transistor chips, as well as auxiliary function pins such as temperature detection and current detection.

[0030] The signal driving terminal 4 is connected to the signal pad on the ceramic substrate 5 via a lead wire (bonding wire, i.e., aluminum wire or copper wire) or a lead frame. The signal pad is connected to the gate and source pads (or Kelvin source pads) of the semiconductor chip 12 via a bonding wire. For the upper-side chip, the drive signal usually needs to be level shifted or pass through an isolation transformer (if the drive circuit is external). However, in this application, the signal drive terminal 4 is only responsible for introducing the external drive signal into the module and does not include a level shifting circuit. The signal drive terminal 4 and the power terminal maintain a preset electrical clearance and creepage distance to meet safety insulation requirements; the power terminal includes a DC busbar terminal 1 and an AC busbar terminal 3.

[0031] like Figure 8 As shown in the illustration, in a specific embodiment, this application also includes a molding compound 15; The molding compound 15 encapsulates the semiconductor chip 12, the multilayer conductive component 2, and the ceramic substrate 5. The semiconductor chip 12 is connected to the ceramic substrate 5 via a solder layer 13 or a sintered silver layer; The stacked conductive component 2 is connected to the ceramic substrate 5 by soldering or ultrasonic welding.

[0032] The molding compound 15 spatially isolates the semiconductor chip 12, the stacked conductive components 2, and the ceramic substrate 5 from each other, thus avoiding strong electrical interference. As a specific embodiment, the ceramic substrate 5 includes a ceramic insulating layer and an upper copper layer and a lower copper layer respectively coated on the upper and lower surfaces of the ceramic insulating layer; The semiconductor chip 12 and the stacked conductive component 2 are both connected to the upper copper layer, and the lower copper layer is connected to the composite heat dissipation substrate 14.

[0033] Specifically, the upper copper layer of the ceramic substrate 5 is connected to the semiconductor chip 12 via solder 13; the lower copper layer is connected to the copper layer of the heat dissipation substrate via another layer of solder 13 or a direct composite process (or composited with the graphene layer 16). The ceramic substrate 5 provides electrical insulation (ceramic layer), mechanical support, and conductive copper layers on the upper and lower surfaces. It also serves as an intermediate layer in the main heat dissipation path, transferring the heat from the semiconductor chip 12 downwards to the heat dissipation substrate (composite heat dissipation substrate 14). This application is compared to, Figure 2 The IGBT module packaging architecture shown integrates low-hyper-inductance stacked clip interconnects with a graphene high-heat-dissipation substrate, reconstructing high-performance IGBT modules from the two most fundamental levels of electrical interconnection and thermal conduction, and has the following specific advantages: (1) The easily failed bonding wires are abandoned, and a clip (sheet or strip structure) is used for surface contact connection. This directly upgrades the traditional point contact (bonding point) to a large area surface contact, which significantly reduces the connection resistance and local current density; (2) The stacked structure significantly reduces the parasitic inductance of the module: The stacked structure design, through the optimization of the three-dimensional layout of the clip, can shorten the path of the main power circuit to the maximum extent, and reduce the stray inductance (Ls) of the module to an extremely low level (Ls<3nH), which is more than 60% lower than the stray inductance of the current conventional automotive-grade power modules. This can effectively suppress switching overvoltage, allow the device to operate at a higher switching frequency, and significantly improve system efficiency and power density. (3) Superior reliability: The multilayer clip has a much better current carrying capacity and thermal conductivity than aluminum wire. Its robust mechanical connection can better withstand the stress caused by power cycling and mechanical vibration, increasing the power cycle life by an order of magnitude (from tens of thousands of times to more than one hundred thousand times), fully meeting the stringent application requirements of automotive electronics and other applications.

[0034] (4) High heat dissipation substrate prepared with graphene: The core lies in using graphene to prepare or enhance the heat dissipation substrate. Graphene is one of the known high thermal conductivity materials. Its theoretical in-plane thermal conductivity exceeds 5300W / (m·K), and the actual high-quality graphene film prepared can reach 1500W / (m·K), which is more than 4 times that of pure copper. This provides a revolutionary material solution for solving the heat dissipation bottleneck of the module core.

[0035] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0036] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A power module, characterized in that, include: Ceramic substrates, semiconductor chips, multilayer conductive components, and composite heat dissipation substrates; The semiconductor chip is disposed on the upper surface of the ceramic substrate; The stacked conductive assembly includes a first conductive element and a second conductive element that are spaced apart in the height direction and arranged in an insulated stacked layer; the first conductive element and the second conductive element are respectively electrically connected to the semiconductor chip and the ceramic substrate to form a stacked current loop; The composite heat dissipation substrate includes a copper layer and a graphene layer; the graphene layer and the copper layer are compositely connected, and the ceramic substrate is disposed on the composite heat dissipation substrate.

2. The power module according to claim 1, characterized in that, Both the first conductive element and the second conductive element include: a chip connection portion, a substrate connection portion, and a stacked conductive busbar; The chip connection portion is connected to the surface of the semiconductor chip; The substrate connection portion is connected to the surface of the ceramic substrate; The stacked conductive busbars are respectively connected to the chip connection portion and the substrate connection portion; The projected portions of the stacked conductive busbars of the first conductive element and the stacked conductive busbars of the second conductive element overlap on the horizontal plane.

3. The power module according to claim 1, characterized in that, The semiconductor chip includes an upper-side chip and a lower-side chip; The first conductive element is the upper conductive clip, and the second conductive element is the lower conductive clip; The vertical distance between the upper conductive clip and the lower conductive clip is H1, and the vertical distance between the upper conductive clip and the ceramic substrate is H2. The upper conductive clip is connected to the upper transistor chip and the lower transistor chip to form the upper bridge arm power circuit; the lower conductive clip is connected to the upper transistor chip and the lower transistor chip to form the lower bridge arm power circuit.

4. The power module according to claim 3, characterized in that, It also includes DC busbar terminals and AC busbar terminals; The DC bus terminal includes a DC+ terminal and a DC- terminal; the DC+ terminal is electrically connected to the first conductive element or the ceramic substrate; the DC- terminal is electrically connected to the second conductive element or the ceramic substrate. The AC busbar terminals are electrically connected to the output terminal of the lower tube chip or the ceramic substrate. The DC+ terminal, the first conductive element, the upper transistor chip, the lower transistor chip, the second conductive element, and the DC- terminal constitute a stacked converter circuit.

5. The power module according to claim 1, characterized in that, The composite heat dissipation substrate is a copper-graphene-copper sandwich structure or a copper-graphene composite structure. When it is a copper-graphene-copper sandwich structure, the graphene layer is sandwiched between two copper layers. When it is a copper-graphene composite structure, the graphene layer is disposed on the side of the copper layer away from the ceramic substrate.

6. The power module according to claim 5, characterized in that, The composite heat dissipation substrate comprises multiple layers of copper foil and graphene film stacked alternately.

7. The power module according to claim 1 or claim 5, characterized in that, The graphene layer is grown directly on the surface of the copper layer using a chemical vapor deposition process; or, the graphene layer is compositely connected to the copper layer through a thermally conductive adhesive layer.

8. The power module according to claim 4, characterized in that, It also includes signal drive terminals; The signal driving terminal is connected to the signal pad on the ceramic substrate via a lead or lead frame, and the signal pad is connected to the gate and source pads of the semiconductor chip via bonding wires. The signal drive terminal and the power terminal maintain a preset electrical clearance and creepage distance. The power terminal includes a DC busbar terminal and an AC busbar terminal.

9. The power module according to claim 1, characterized in that, It also includes the encapsulated body; The molding compound encapsulates the semiconductor chip, the multilayer conductive components, and the ceramic substrate; The semiconductor chip is connected to the ceramic substrate via a solder layer or a sintered silver layer; The multilayer conductive components are connected to the ceramic substrate by soldering or ultrasonic welding.

10. The power module according to claim 1, characterized in that, The ceramic substrate includes a ceramic insulating layer and an upper copper layer and a lower copper layer respectively coated on the upper and lower surfaces of the ceramic insulating layer; The semiconductor chip and the stacked conductive components are both connected to the upper copper layer, and the lower copper layer is connected to the composite heat dissipation substrate.

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