An integrated package and method of packaging

Abstract

The application discloses an integrated board-level package and a packaging method. The packaging method comprises the following steps: providing a first carrier plate, mounting a chip on the surface of the first carrier plate with the front face of the chip facing downward, and forming a plastic package layer by plastic packaging; removing the first carrier plate, temporarily bonding the side of the plastic package layer opposite to the front face of the chip to a second carrier plate; forming a through hole and a conductive column on the plastic package layer; forming a rewiring layer and a passivation layer on the front face side of the chip, and interconnecting the rewiring layer with the chip pad and the conductive column; removing the second carrier plate, mounting a passive element on the side of the plastic package layer opposite to the front face of the chip, and electrically connecting the passive element with the conductive column; and cutting to form a single package. The single-layer integrated board-level package structure is formed by arranging the chip and the passive element on the two sides of the plastic package layer and interconnecting the chip and the passive element through the conductive column, so that the packaging area is reduced, the high-frequency performance is improved, the process flow is simplified, and the manufacturing cost is reduced.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor packaging technology, specifically relating to an integrated board-level package and a packaging method. Background Technology

[0002] As electronic devices rapidly evolve towards miniaturization, multifunctionality, and high performance, semiconductor packaging technology faces increasingly stringent integration requirements. System-in-Package (SiP), by integrating multiple chips and passive components into a single package module, has become a crucial technological path for achieving heterogeneous integration. Fan-out board-level packaging (FOPLP), as a technological extension of fan-out wafer-level packaging, redistributes chips across a large-size panel for interconnection, enabling the integration of multiple chips, passive components, and interconnects within a single package. It holds great promise in fields such as AIoT, 5G, and autonomous driving.

[0003] Currently, the board-level packaging of chips and passive components mainly adopts the following process: first, solder paste is printed on the substrate; then, the chip and passive component are mounted on their corresponding positions on the substrate; electrical connection is achieved through reflow soldering; and finally, plastic encapsulation is applied for protection. However, this traditional packaging method has the following prominent problems: (i) Large packaging area. Chips and passive components are usually laid flat on the substrate surface. When there are many passive components (such as dozens or even hundreds of passive components in RF modules), they will occupy a large amount of substrate area, which limits the further improvement of packaging density.

[0004] (ii) Complex process and high reliability risk. Traditional methods require numerous high-precision placement operations to position all components before molding, resulting in slow production speed and high cost. After the molding layer is formed, if a secondary reflow or other heat treatment process is required, the solder paste will melt again and can easily flow into the gap between the two external electrodes of the passive components, causing a short circuit and reducing product yield. In addition, to protect the chip and passive components, multiple molding processes are often required, increasing the overall package thickness.

[0005] (iii) Limited high-frequency performance. Traditional organic substrates suffer from high loss and severe frequency deviation when transmitting signals at high frequencies, making it difficult to meet the requirements of high-frequency applications such as radio frequency and microwave.

[0006] Therefore, there is an urgent need for a method that can integrate chips and passive components into a single package, which can reduce package size, simplify the process, improve reliability, and enhance high-frequency performance. Summary of the Invention

[0007] To address the aforementioned technical problems, the present invention aims to provide an integrated board-level package and packaging method. The present invention utilizes a single-layer, integrated board-level package structure in which the chip and passive components are placed on opposite sides of a molding compound and interconnected by through-through conductive pillars. This structure reduces the package area, improves high-frequency performance, simplifies the manufacturing process, and lowers manufacturing costs.

[0008] To achieve the above-mentioned technical objectives and effects, the present invention is implemented through the following technical solution: This invention provides an integrated board-level packaging method, comprising: A first substrate is provided, and the chip is mounted face down on the surface of the first substrate and encapsulated to form an encapsulation layer; After removing the first substrate, the side of the molding compound opposite to the front of the chip is temporarily bonded to the second substrate; Create through-holes and form conductive pillars on the molding layer; A redistribution layer and a passivation layer are fabricated on the front side of the chip, and the redistribution layer is interconnected with the chip pads and the conductive pillars. After removing the second carrier board, a passive component is mounted on the side of the molding layer opposite to the front of the chip and the passive component is electrically connected to the conductive post. Cut into individual packages.

[0009] Furthermore, during molding, the molding layer simultaneously covers the back side of the chip, so that the chip is completely embedded in the molding layer.

[0010] Furthermore, the through hole is formed using a laser drilling process.

[0011] Furthermore, the conductive pillar is formed by filling the through hole with copper through electroplating or chemical plating processes.

[0012] Further, the step of forming the redistribution layer includes: sputtering to form a seed layer on the front side of the chip, forming an opening in the seed layer to expose the chip pads and the ends of the conductive pillars, and then forming a metal wiring layer at the opening by electroplating.

[0013] Furthermore, external solder terminals are formed on the redistribution layer through an electroplating process.

[0014] Furthermore, before mounting the passive components, a protective film is first applied to the front side of the chip. After the passive components are mounted, the protective film is removed.

[0015] Another aspect of the present invention provides an integrated board-level package, comprising: Plastic sealant; At least one chip is embedded in the molding compound, with its front side exposed to a first surface of the molding compound; Conductive pillars are disposed through the encapsulation layer; A redistribution layer is disposed on the first surface of the first molding layer and electrically connected to the chip pads and the conductive pillars; A passivation layer is applied over the redistribution layer. And passive components, which are mounted on the second surface of the molding layer and electrically connected to the conductive pillar.

[0016] Furthermore, the redistribution layer is also provided with external solder terminals.

[0017] Furthermore, the number of redistribution layers is at least two.

[0018] The beneficial effects of this invention are as follows: This invention changes the space utilization method of traditional packaging by placing the chip and passive components on opposite sides of the molding compound and vertically interconnecting them with conductive pillars. Compared to traditional planar mounting solutions, this invention moves the passive components from the existing substrate surface to the back of the package, significantly reducing the substrate area occupied by the package and providing a structural foundation for higher-density system-level integration. Simultaneously, the fan-out board-level packaging, combined with a redistribution layer replacing the traditional organic substrate signal transmission scheme, and the short-path interconnect structure formed by the vertically penetrating conductive pillars, effectively shortens the signal transmission distance, reduces parasitic effects and transmission losses, resulting in a significant improvement in the high-frequency performance of the package.

[0019] This invention eliminates the need for prefabricated substrates or lead frames throughout the entire process. All redistribution layers are formed in situ on the surface of the molding compound, eliminating substrate prefabrication and testing processes and reducing production costs. Simultaneously, molding, photolithography, and copper pillar fabrication are completed continuously on the same board-level production line, reducing cross-line transfers and shortening the production cycle. Passive components are centrally mounted using single-sided SMT after all front-side processes are completed. This simplifies the placement process, reduces the risk of misalignment, and avoids the risk of short circuits due to secondary reflow soldering after simultaneous mounting of passive components and chips in traditional solutions, thus improving product yield. Furthermore, the dual-carrier process, which involves temporarily bonding a second carrier after removing the first carrier, effectively controls the risk of warpage and cracking of large-size molding compounds in subsequent processes, further ensuring process stability.

[0020] In summary, this invention effectively reduces the packaging area, improves high-frequency signal transmission performance, simplifies the process, reduces manufacturing costs, and improves packaging reliability. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of step one in the packaging method of the present invention.

[0022] Figure 2This is a schematic diagram of step two in the packaging method of the present invention.

[0023] Figure 3 This is a schematic diagram of step three in the packaging method of the present invention.

[0024] Figure 4 This is a schematic diagram of step four in the packaging method of the present invention.

[0025] Figure 5 This is a schematic diagram of step five in the packaging method of the present invention.

[0026] Figure 6 This is a schematic diagram of step six in the packaging method of the present invention.

[0027] Figure 7 This is a schematic diagram of step seven in the packaging method of the present invention.

[0028] Figure 8 This is a schematic diagram of step eight in the packaging method of the present invention.

[0029] Figure 9 This is a schematic diagram of step nine in the packaging method of the present invention.

[0030] Figure 10 This is a schematic diagram of step ten in the packaging method of the present invention.

[0031] In the diagram, 1: First carrier board; 2: Chip; 3: Molding layer; 4: Second carrier board; 5: Through-hole; 6: Conductive pillar; 7: Photosensitive polyimide layer; 8: Rewiring layer; 9: Passivation layer; 10: External solder terminal; 11: Protective film; 12: Passive component. Detailed Implementation

[0032] The technical solutions of the present invention will be clearly and completely described below with reference to specific embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0033] like Figures 1 to 10 As shown, this invention provides an integrated board-level packaging method and package, aiming to solve problems such as large area, poor high-frequency performance, complex process, and reliability risks of secondary recirculation short circuits caused by the flat laying of chips and passive components in traditional packaging. The specific steps are described in detail below.

[0034] Step 1: Chip mounting on the first carrier board like Figure 1As shown, a flat first carrier board 1 is provided, which is used to temporarily support the chip. Exemplarily, the first carrier board 1 can be any one of a glass carrier board, a silicon carrier board, or a metal carrier board, and its surface is cleaned to ensure subsequent mounting accuracy. Preferably, a temporary bonding adhesive or adhesion layer can be pre-formed on the surface of the first carrier board 1 to facilitate smooth peeling of the carrier board later. Subsequently, at least one chip 2 is mounted on the same surface of the first carrier board 1, with the front side of the chip 2 (i.e., the side with the bonding pads) facing the first carrier board 1. Exemplarily, the mounting of the chip 2 can be performed using a high-precision pick-and-place machine, and the mounting accuracy is preferably controlled within ±10μm. It is understood that when multiple chips 2 are mounted, the chips 2 can be arranged in an array according to design requirements.

[0035] Step 2: Forming the sealing layer like Figure 2 As shown, a molding compound 3 is formed on the first substrate 1, which at least covers the sidewalls of the chip 2. Preferably, the molding compound 3 also covers the back side of the chip 2 (i.e., the side opposite to the front side), so that the chip 2 is completely embedded in the molding compound 3. Exemplarily, the molding compound 3 can be made of epoxy resin molding compound (EMC) and formed by compression molding or transfer molding processes. The curing temperature of the molding compound 3 is preferably below 250°C to accommodate the temperature resistance requirements of chips 2 made of different materials. Through the above molding process, the chip 2 is firmly embedded inside the molding compound.

[0036] Step 3: Remove the first carrier board and bond the second carrier board. like Figure 3 As shown, the first carrier board 1 is removed, exposing the front pads of the chip 2. Exemplarily, the removal method can employ any of the following processes: mechanical peeling, laser peeling, or thermal bonding. After removing the first carrier board 1, a temporary bonding process is used to bond the molding compound to the second carrier board 4. This involves temporarily bonding the side of the molding compound 3 opposite to the front of the chip (i.e., the back side of the molding compound 3) to the second carrier board 4. This effectively controls the warping and deformation of the large-size molding compound during subsequent fabrication, avoids the risk of molding compound cracking, and ensures the alignment accuracy of subsequent photolithography, electroplating, and other processes.

[0037] Step 4: Create a through hole like Figure 4 As shown, through-holes 5 are formed in the molding compound 3 using a laser drilling device, penetrating the molding compound 3. These through-holes 5 provide a channel for subsequent electrical connections between the chip pads and the passive components 12 on the back. Preferably, the position and number of through-holes 5 are pre-designed according to the layout of the chip pads and the mounting position of the passive components 12. After forming the through-holes 5, plasma cleaning is performed on the through-holes 5 to remove dust and organic impurities generated during the drilling process, thereby improving the bonding strength between the subsequent conductive material and the inner wall of the through-holes 5.

[0038] Step 5: Forming conductive pillars like Figure 5 As shown, conductive material is filled into the through-hole 5 formed in step four through electroplating or chemical plating processes to form a conductive pillar 6. Preferably, copper is selected as the conductive material to form a conductive copper pillar.

[0039] Step 6: Form the redistribution layer and passivation layer like Figure 6 As shown, a redistribution layer 8 and a passivation layer 9 are sequentially formed on the exposed front side of the chip after the first carrier board 1 is removed. The redistribution layer 8 is used to realize electrical interconnections between chip pads and between chip pads and conductive pillars 6.

[0040] For example, the steps for forming the redistribution layer 8 specifically include: First, forming a seed layer covering the entire front side of the chip using a sputtering process; the seed layer material can be a titanium / copper (Ti / Cu) combination. Then, coating a photosensitive polyimide layer 7 (PI layer, with an exemplary thickness of 10 μm) onto the seed layer, and forming openings using photolithography processes such as pre-baking, exposure, and development. The openings are located at the ends of the chip pads and conductive pillars 6, exposing the seed layer at the bottom of the openings while the remaining areas are still covered by the PI layer. Next, forming metal lines within the openings using an electroplating process, and finally removing the PI layer and etching away the seed layer not covered by the metal lines to form the final redistribution layer 8. The redistribution layer 8 is electrically connected to the chip pads and conductive pillars 6; the redistribution layer 8 is preferably a copper layer with an exemplary thickness of 5~20 μm.

[0041] After the first redistribution layer 8 is formed, a passivation layer 9 is fabricated to cover and protect the redistribution layer 8. Exemplarily, the passivation layer 9 can be formed in one of two ways: Option 1: Coating a photosensitive polyimide passivation adhesive, exposing and developing it, creating windows, and then hard-baking it at approximately 150°C; Option 2: Laminating an ABF film (such as ABF-GX-T31R2), curing it at approximately 180°C for an appropriate time (such as 60 minutes), and then post-curing it, forming windows by laser drilling (the window diameter is exemplarily 40μm~80μm, and the depth is exemplarily 15μm~25μm). The positions of the windows on the passivation layer 9 correspond to the areas of the redistribution layer 8.

[0042] The number of layers in the redistribution layer 8 can be set to multiple layers according to the routing design requirements. Adjacent redistribution layers 8 are interconnected through windows on the passivation layer 9 between layers.

[0043] Step 7: Forming external solder terminals like Figure 7As shown, an external solder terminal 10 is fabricated on the outermost passivation layer 9 (i.e., above the outermost redistribution layer 8). Exemplarily, a seed layer (such as Ti / Cu) is formed on the passivation layer 9 using a sputtering process; then, a photosensitive polyimide layer 7 (PI layer, with an exemplary thickness of 30-60 μm) is coated on the seed layer. An opening is formed using photolithography processes such as spin coating, pre-baking, exposure, and development. The opening corresponds to the area of ​​the underlying redistribution layer 8, exposing the bottom seed layer while the remaining seed layer is still covered by the PI layer. Next, the external solder terminal 10 is formed within the opening using an electroplating process. Finally, the PI layer is removed, and the seed layer not covered by the external solder terminal 10 is etched away. Exemplarily, the solder terminal can adopt a copper-tin (Cu / Sn) structure, which can be formed sequentially by an electroplating process, with the copper layer thickness exemplary to be 10-20 μm and the tin layer thickness exemplary to be 10-20 μm.

[0044] Step 8: Remove the second carrier board like Figure 8 As shown, after the front-side packaging of the chip is completed (including the fabrication of the redistribution layer 8, passivation layer 9, and external solder terminals 10), the second substrate 4 is removed to expose the ends of the conductive posts 6 on the back side of the molding compound 3 for connection with the passive component 12. Preferably, the second substrate 4 is removed using a thermal bonding method.

[0045] Step 9: Mount passive components like Figure 9 As shown, before mounting the passive component 12, a protective film 11 is first applied to the front side of the chip (i.e., the side with the external solder terminals 10) to prevent the front terminals from being scratched or contaminated during the subsequent mounting of the passive component 12. Preferably, the protective film 11 can be a UV film. Then, using SMT (Surface Mount Technology), the passive component 12 is mounted on the designated area on the back of the molding compound 3 according to the designed layout, so that the passive component 12 corresponds to the end of the conductive post 6. After mounting, reflow soldering and FLUX cleaning are performed to achieve a stable electrical interconnection between the passive component 12 and the conductive post 6. Finally, the protective film 11 on the front side of the chip is removed by ultraviolet light irradiation.

[0046] Step 10: Cutting like Figure 10 As shown, according to the design dimensions, the entire package assembly, after completing all the above processes, is cut to form multiple individual integrated packages. For example, a diamond blade cutting process can be used, with a cutting width of 100~300μm. After cutting, each package can be visually inspected and its electrical performance tested to ensure product quality.

[0047] This completes the integrated board-level packaging of the chip and passive components. For example... Figure 10As shown, in the package obtained by the above method, chip 2 is embedded in molding compound 3, with its front side exposed on the first surface of molding compound 3; conductive post 6 is disposed through molding compound 3, one end of which is electrically connected to redistribution layer 8, and the other end extends to the second surface of molding compound 3; passive component 12 is mounted on the second surface of molding compound 3, and is electrically interconnected with chip 2 through conductive post 6. Chip 2 and passive component 12 are located on opposite sides of molding compound 3, forming an integrated board-level package structure.

[0048] The method and package provided by this invention have the following advantages: no separate packaging substrate is required, significantly reducing the packaging area; the redistribution layer 8 has a short interconnect path and excellent high-frequency performance; it eliminates the need for prefabrication substrates and multiple intermediate processes, simplifying the process flow and reducing manufacturing costs; simultaneously, since the passive components 12 are mounted only after the front-side process is completed, the risk of short circuits caused by secondary reflow is avoided, improving product reliability and yield. It is particularly suitable for applications requiring miniaturization and high-frequency performance, such as RF front-end modules and high-density system-in-package (SiP).

[0049] The present invention will be further described below through specific embodiments.

[0050] This embodiment illustrates the integrated board-level packaging method of the present invention by way of specific process parameters.

[0051] Step 1: Chip mounting like Figure 1 As shown, a flat first carrier plate 1 (a glass carrier plate is used in this embodiment) is provided, and its surface is cleaned and coated with temporary bonding adhesive. A high-precision pick-and-place machine is used to mount multiple chips 2 in an array on the surface of the first carrier plate 1, with the front side of the chips 2 facing the first carrier plate 1, and the mounting accuracy is controlled within ±10μm.

[0052] Step 2: Lamination like Figure 2 As shown, epoxy resin molding compound (EMC) is used to form a molding layer 3 on the first carrier board 1 through compression molding, so that the chip 2 is completely embedded in the molding layer 3. The curing temperature of the molding layer 3 is 230℃.

[0053] Step 3: Remove the first carrier board and bond the second carrier board. like Figure 3 As shown, the first substrate 1 is removed by mechanical peeling, exposing the pads on the front side of the chip 2. Then, the back side of the molding compound 3 is temporarily bonded to the second substrate 4.

[0054] Step 4: Create a through hole like Figure 4 As shown, a through hole 5 is made at the corresponding position on the plastic seal layer 3 using a laser drilling device. After the through hole 5 is made, it is plasma cleaned.

[0055] Step 5: Forming conductive pillars like Figure 5 As shown, copper is filled into the through hole 5 through an electroplating process to form a conductive pillar 6.

[0056] Step 6: Form the redistribution layer and passivation layer like Figure 6 As shown, a Ti / Cu seed layer covering the entire front side of the chip is formed using a sputtering process. Then, a photosensitive polyimide layer 7 (PI layer) with a thickness of 10 μm is spin-coated onto the seed layer. After exposure and development, openings are formed, exposing the seed layer at the ends of the chip pads and conductive pillars 6. Copper wiring with a thickness of 10 μm is formed within the openings using an electroplating process. The PI layer is removed, and the exposed seed layer is etched away, forming a redistribution layer 8. The redistribution layer 8 is electrically connected to the chip pads and conductive pillars 6.

[0057] An ABF film is laminated onto the redistribution layer 8, cured at 180°C for 60 minutes and then post-cured. A window with a diameter of 60 μm is formed by laser drilling, exposing part of the redistribution layer 8, thus obtaining the passivation layer 9.

[0058] Step 7: Forming external solder terminals like Figure 7 As shown, a Ti / Cu seed layer is sputtered onto the passivation layer 9, and a 40 μm thick photosensitive polyimide layer 7 is spin-coated. An opening is formed by photolithography, and the position of the opening corresponds to the area of ​​the redistribution layer 8 below. A copper layer (15 μm) and a tin layer (15 μm) are formed sequentially by electroplating. Then, the PI layer is removed and the exposed seed layer is etched away to obtain the external solder terminal 10 of the copper-tin structure.

[0059] Step 8: Remove the second carrier board like Figure 8 As shown, the second carrier plate 4 is removed by thermal debonding, exposing the end of the conductive post 6.

[0060] Step 9: Mount passive components like Figure 9 As shown, a protective film 11 (UV film) is attached to the front side of the chip. Passive components 12 are mounted on the back side of the molding layer 3 using SMT (Surface Mount Technology). After reflow soldering and FLUX cleaning, the passive components 12 are electrically connected to the conductive posts 6. Finally, the protective film 11 is removed by ultraviolet light irradiation.

[0061] Step 10: Cutting like Figure 10 As shown, diamond blades are used to cut along the kerf, with a kerf width of 200μm, forming multiple individual packages. After visual inspection and electrical performance testing, they become the finished products.

[0062] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within the present invention.

[0063] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. An integrated board-level packaging method, characterized in that, include: A first substrate is provided, and the chip is mounted face down on the surface of the first substrate and encapsulated to form an encapsulation layer; After removing the first substrate, the side of the molding compound opposite to the front of the chip is temporarily bonded to the second substrate; Create through-holes and form conductive pillars on the molding layer; A redistribution layer and a passivation layer are fabricated on the front side of the chip, and the redistribution layer is interconnected with the chip pads and the conductive pillars. After removing the second carrier board, a passive component is mounted on the side of the molding layer opposite to the front of the chip and the passive component is electrically connected to the conductive post. Cut into individual packages.

2. The integrated board-level packaging method according to claim 1, characterized in that, During molding, the molding layer also covers the back of the chip, so that the chip is completely embedded in the molding layer.

3. The integrated board-level packaging method according to claim 1, characterized in that, The through hole is formed using a laser drilling process.

4. The integrated board-level packaging method according to claim 1, characterized in that, The conductive pillar is formed by filling the through hole with copper through electroplating or chemical plating processes.

5. The integrated board-level packaging method according to claim 1, characterized in that, The steps of forming the redistribution layer include: sputtering a seed layer on the front side of the chip, forming an opening in the seed layer to expose the chip pads and the ends of the conductive pillars, and then forming a metal wiring layer at the opening by electroplating.

6. The integrated board-level packaging method according to claim 1, characterized in that, External solder terminals are formed on the redistribution layer through an electroplating process.

7. The integrated board-level packaging method according to claim 1 or 6, characterized in that, Before mounting the passive components, a protective film is first applied to the front side of the chip. After the passive components are mounted, the protective film is removed.

8. An integrated board-level package, characterized in that, include: Plastic sealant; At least one chip is embedded in the molding compound, with its front side exposed to a first surface of the molding compound; Conductive pillars are disposed through the encapsulation layer; A redistribution layer is disposed on the first surface of the first molding layer and electrically connected to the chip pads and the conductive pillars; A passivation layer is applied over the redistribution layer. And passive components, which are mounted on the second surface of the molding layer and electrically connected to the conductive pillar.

9. An integrated board-level package according to claim 8, characterized in that, The redistribution layer is also provided with external solder terminals.

10. An integrated board-level package according to claim 8, characterized in that, The number of redistribution layers is at least two.

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