Electronic device and method for digital pre-distortion

Abstract

According to an embodiment, a method performed by an electronic device can include acquiring a specified number of samples based on an input signal related to a power amplifier (PA) and an output signal related to the PA. The method can include identifying first gain information about the input signal with respect to the output signal. The method can include performing, for each of power levels of the output signal, a first process for averaging at least some of gain values within a specified power range in the first gain information. The method can include performing, for each of the power levels, a second process for estimating gain values outside the specified power range in the first gain information. The method can include changing configuration information about a digital pre-distortion (DPD) circuit of the electronic device based on second gain information about the input signal with respect to the output signal.

Description

Technical Field

[0001] This disclosure relates to wireless communication systems. More specifically, this disclosure relates to electronic devices and methods for digital predistortion (DPD) in wireless communication systems. Background Technology

[0002] In wireless communication systems, digitally modulated signals are amplified by radio frequency (RF) power amplifiers. To transmit signals without distortion, the power amplifier requires high linearity. To provide high linearity, digital predistortion (DPD) is used to modify the input signal so that the power amplifier's output approaches an ideal state.

[0003] To aid in understanding this disclosure, the above information may be provided as prior art. No argument or decision is made regarding whether anything described above is applicable as prior art in connection with this disclosure. Summary of the Invention

[0004] Technical solution According to an embodiment, an electronic device may include a digital predistortion (DPD) circuit, a digital-to-analog converter (DAC) coupled to the DPD circuit, a power amplifier (PA) coupled to the DAC, an analog-to-digital converter (ADC) coupled to the PA, at least one processor including processing circuitry, and a memory including one or more storage media storing instructions. When executed individually or jointly by the at least one processor, the instructions may cause the electronic device to: acquire a specified number of samples based on an input signal associated with the PA and an output signal associated with the PA. When executed individually or jointly by the at least one processor, the instructions may cause the electronic device to: identify first gain information of the input signal relative to the output signal based on the specified number of samples. When executed individually or jointly by the at least one processor, the instructions may cause the electronic device to: perform a first process with respect to each power level of the output signal to average at least a portion of the gain values ​​within a specified power range in the first gain information. When executed individually or jointly by the at least one processor, the instructions may cause the electronic device to: perform a second process with respect to each power level of the output signal to estimate a gain value outside the specified power range in the first gain information. When executed individually or jointly by the at least one processor, the instructions can cause the electronic device to: acquire second gain information of the input signal relative to the output signal based on the first processing and the second processing. When executed individually or jointly by the at least one processor, the instructions can cause the electronic device to: change the setting information of the DPD circuit according to the second gain information.

[0005] According to an embodiment, a method performed by an electronic device may include: acquiring a specified number of samples based on an input signal associated with a power amplifier (PA) of the electronic device and an output signal associated with the PA. The method may include: identifying first gain information of the input signal relative to the output signal based on the specified number of samples. The method may include: performing a first process for each power level of the output signal to average at least a portion of the gain values ​​within a specified power range in the first gain information. The method may include: performing a second process for each power level of the output signal to estimate gain values ​​outside the specified power range in the first gain information. The method may include: acquiring second gain information of the input signal relative to the output signal based on the first and second processes. The method may include: changing the setting information of a digital predistortion (DPD) circuit of the electronic device according to the second gain information.

[0006] According to an embodiment, an electronic device may include a digital predistortion (DPD) circuit, a digital-to-analog converter (DAC) coupled to the DPD circuit, a power amplifier (PA) coupled to the DAC, an analog-to-digital converter (ADC) coupled to the PA, and at least one processor. The at least one processor may be configured to: acquire a specified number of samples based on an input signal associated with the PA and an output signal associated with the PA. The at least one processor may be configured to: identify first gain information of the input signal relative to the output signal based on the specified number of samples. The at least one processor may be configured to: perform a first process for each power level of the output signal to average at least a portion of the gain values ​​within a specified power range in the first gain information. The at least one processor may be configured to: perform a second process for each power level of the output signal to estimate gain values ​​outside the specified power range in the first gain information. The at least one processor may be configured to: acquire second gain information of the input signal relative to the output signal based on the first and second processes. The at least one processor may be configured to: change the setting information of the DPD circuit according to the second gain information.

[0007] According to an embodiment, a non-transitory computer-readable storage medium may store one or more programs. The one or more programs may include instructions, when executed by a processor of an electronic device having digital predistortion (DPD) circuitry, a digital-to-analog converter (DAC) coupled to the DPD circuitry, a power amplifier (PA) coupled to the DAC, and an analog-to-digital converter (ADC) coupled to the PA, causing the electronic device to: acquire a specified number of samples based on an input signal associated with the PA and an output signal associated with the PA. The one or more programs may include instructions, when executed by the processor of the electronic device, causing the electronic device to: identify first gain information of the input signal relative to the output signal based on the specified number of samples. The one or more programs may include instructions, when executed by the processor of the electronic device, causing the electronic device to: perform a first process with respect to each power level of the output signal to average at least a portion of the gain values ​​within a specified power range of the first gain information. The one or more programs may include instructions, when executed by the processor of the electronic device, to cause the electronic device to: perform a second process for each power level of the output signal to estimate a gain value outside a specified power range in the first gain information. The one or more programs may include instructions, when executed by the processor of the electronic device, to cause the electronic device to: obtain second gain information of the input signal relative to the output signal based on the first process and the second process. The one or more programs may include instructions, when executed by the processor of the electronic device, to cause the electronic device to: change the setting information of the DPD circuit according to the second gain information. Attached Figure Description

[0008] Figure 1 A wireless communication system is shown.

[0009] Figure 2 This is a diagram used to describe the principle of digital predistortion (DPD).

[0010] Figure 3 An example of a transmitter circuit including a DPD circuit is shown.

[0011] Figure 4a An example of a GSM signal acquired through a capture block is shown.

[0012] Figure 4b An example of the power range of a GSM signal acquired through a capture block is shown.

[0013] Figure 5An example of a transmitter circuit including a DPD circuit is shown, which is used to perform DPD modeling on a signal with a narrow bandwidth.

[0014] Figure 6 This is a flowchart of the operation of an electronic device to change the setting information of the DPD circuit.

[0015] Figure 7 An example of a graph related to samples acquired based on input and output signals is shown.

[0016] Figure 8 It is a flowchart of the operation of an electronic device for identifying the gain value corresponding to each of a plurality of power levels.

[0017] Figure 9a This is a flowchart of the operation performed by the electronic device to execute the first process.

[0018] Figure 9b The variation of the gain value within a specified power range according to the first process is shown.

[0019] Figure 10a This is a flowchart of the operation of an electronic device to perform a second process.

[0020] Figure 10b The variation of the gain value outside the specified power range according to the second processing is shown.

[0021] Figure 11a The change in gain is shown when the first gain information is changed to the second gain information.

[0022] Figure 11b The diagram shows the phase change when the first gain information is changed to the second gain information.

[0023] Figure 12 The change in PA output is shown when the setting information of the DPD circuit is changed according to the second gain information.

[0024] Figure 13 The functional configuration of the electronic device, including the transmitting circuit, is shown. Detailed Implementation

[0025] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the scope of other embodiments. Singular expressions may include plural expressions unless the context clearly indicates otherwise. The terms used herein (including technical or scientific terms) may have the same meaning as commonly understood by one of ordinary skill in the art as described in this disclosure. Among the terminology used in this disclosure, terms defined in general dictionaries may be interpreted as having the same or similar meaning as in the context of related technologies, and should not be construed as having an idealized or over-formal meaning unless explicitly defined in this disclosure. In some cases, even terms defined in this disclosure should not be construed as excluding embodiments of this disclosure.

[0026] In the various embodiments of this disclosure described below, hardware-based methods will be used as examples. However, since the various embodiments of this disclosure include techniques using both hardware and software, software-based methods are not excluded.

[0027] The terms used in the following description that refer to signals (e.g., signal, signal stream, composite signal, digital signal, analog signal, modulated signal, distorted signal), resources (e.g., time, symbol, time slot, subframe, radio frame, subcarrier, resource element (RE), resource block (RB), bandwidth portion (BWP), timing), terms used for calculating states (e.g., step, operation, process), data (e.g., packet, user stream, information, bit, symbol, codeword), channels, network entities, and device components are listed for ease of description only. Therefore, this disclosure is not limited to the terms described below, and other terms with equivalent technical meanings may be used.

[0028] The terms used in the following description that refer to components of an electronic device (e.g., module, antenna, antenna element, circuit, processor, chip, assembly, device), terms that refer to circuits (e.g., combinational circuit, coupling circuit, split circuit, distribution circuit, PIMC circuit, harmonic suppression circuit), terms that refer to the shape of a component (e.g., structure, structural body, support, contact, protrusion), and terms that refer to circuits (e.g., printed circuit board (PCB), flexible printed circuit board (FPCB), signal line, feeder, data line, RF signal line, antenna line, RF path, RF module, RF circuit, power divider, distributor, coupler, combiner), etc., are listed for ease of description only. Therefore, this disclosure is not limited to the terms described below, and other terms with equivalent technical meanings may also be used. Furthermore, terms such as “...unit,” “...device,” “...object,” and “...structure” used below may refer to at least one shape structure or a unit of processing function.

[0029] Furthermore, in this disclosure, the terms "greater than" or "less than" can be used to determine whether a particular condition is met or achieved, but this is merely a description of examples and does not exclude descriptions of "greater than or equal to" or "less than or equal to". A condition described as "greater than or equal to" can be replaced with "greater than", a condition described as "less than or equal to" can be replaced with "less than", and a condition described as "greater than or equal to and less than" can be replaced with "greater than and less than or equal to". Additionally, in the following text, "A" to "B" refers to at least one element from A (inclusive) to B (inclusive).

[0030] This disclosure uses terminology used in some communication standards (e.g., 3GPP, xRAN, and ORAN) to describe various embodiments, but this is only for illustrative purposes. The various embodiments of this disclosure can be readily modified and applied to other communication systems.

[0031] Figure 1 A wireless communication system is shown.

[0032] refer to Figure 1 , Figure 1 Base station 110 and terminal 120 are shown as part of a node using a wireless channel in a wireless communication system. Although Figure 1 Only one base station is shown, but the wireless communication system may also include other base stations that are the same as or similar to base station 110.

[0033] Base station 110 is a network infrastructure that provides wireless access to terminal 120. Base station 110 has a coverage range defined based on the distance over which the signal can be transmitted. In addition to "base station", base station 110 may also be referred to as "access point (AP)", "eNodeB (eNB)", "fifth generation node", "next generation node B (gNB)", "wireless point", "transmit / receive point (TRP)" or another term with equivalent technical meaning.

[0034] Terminal 120, a device used by a user, communicates with base station 110 via a wireless channel. The link from base station 110 to terminal 120 is called the downlink (DL), and the link directly from terminal 120 to base station 110 is called the uplink (UL). Furthermore, although... Figure 1Not shown, but terminal 120 and another terminal can communicate with each other via a wireless channel. In this case, the link (device-to-device link, D2D) between terminal 120 and another terminal is called a side link, which can be used interchangeably with the PC5 interface. In some other embodiments, terminal 120 can operate without user intervention. According to an embodiment, terminal 120, as a device performing machine-type communication (MTC), may not be carried by a user. Additionally, according to an embodiment, terminal 120 may be a narrowband (NB)-Internet of Things (IoT) device.

[0035] In addition to the term "terminal", terminal 120 may also be referred to as "user equipment (UE)", "customer premises equipment (CPE)", "mobile station", "user station", "remote terminal", "wireless terminal", "electronic device", "user equipment" or other terms with equivalent technical meanings.

[0036] According to an embodiment, base station 110 can transmit signals with high power to transmit radio signals. Base station 110 may include a power amplifier (hereinafter, PA) for amplifying the power of the signal. The PA can be used to amplify the power of the input signal. However, as the power of the input signal to the power amplifier (PA) increases, the response of the power amplifier may indicate nonlinearity. Eventually, the response of the power amplifier may eventually reach a saturation point. This nonlinearity may cause distortion in the transmitted signal and lead to degradation of link quality. Therefore, linearity of the power amplifier is required. Typically, to achieve linearity, it may be necessary to have a limited power range input to the power amplifier. Digital predistortion can be used to increase the power range of the input signal for linearity.

[0037] Figure 2 This diagram illustrates the principle of digital predistortion (DPD). Predistortion can be performed in a DPD circuit. The DPD circuit compensates for distortion components due to the nonlinear characteristics of the PA by comparing the input and output signals of the PA. Since the input modulated signal, distorted by the DPD circuit, is input to the PA, the final modulated signal can be linearly amplified.

[0038] refer to Figure 2The DPD circuit 210 can output a DPD output signal 215 based on the input signal 205. The input signal 205 can be pre-distorted into the DPD output signal 215 by the DPD circuit 210. The PA 220 can output an amplifier output signal 225 based on the DPD output signal 215. The DPD output signal 215 can be input to the PA 220. Due to the nonlinear characteristics of the PA 220, the DPD output signal 215 is distorted. Due to the distortion caused by the PA 220, the amplifier output signal 225 is output. Although in Figure 2 It is not shown in the figure, but the DPD output signal 215 can be analog converted by a DAC and up-converted by a mixer.

[0039] Graph 251 shows the relationship between the amplitude of the input signal 205 and the amplitude of the DPD output signal 215. Graph 253 shows the relationship between the amplitude of the DPD output signal 215 and the amplitude of the amplifier output signal 225. Graph 255 shows the relationship between the amplitude of the input signal 205 and the amplitude of the amplifier output signal 225. Referring to graph 255, through the predistortion of the DPD circuit 210, the output (e.g., the amplifier output signal 225) relative to the input (e.g., the input signal 205) can be linear.

[0040] PA 220 may include transistors. Transistors generate harmonic components. Due to the nonlinearity of the low-frequency second harmonic component corresponding to the bandwidth (f2-f1) (f2 is the highest frequency, and f1 is the lowest frequency), a memory effect occurs. Because the low-frequency second harmonic component is relatively large, impedance removal is not easy. Therefore, the power amplifier exhibits a memory effect as the signal bandwidth increases. In cases where the modulated signal in a wireless communication system is used as a wide-bandwidth signal, the distortion components of the power amplifier may include distortion components not only due to nonlinear characteristics but also due to the memory effect. The memory effect means that a signal that was nonlinearly generated in the past can affect the current nonlinearity. That is, the power amplifier is a nonlinear system that utilizes memory.

[0041] Memory effects can be caused by the thermal constants of active devices or components of bias networks with frequency-dependent operation. As mentioned above, the distortion component due to memory effects increases proportionally to the signal bandwidth. To compensate for the nonlinear distortion components of the power amplifier and the distortion components due to memory effects, a memory-compensated DPD circuit is needed. In the following text, in Figure 3 The text describes a DPD circuit for memory compensation.

[0042] Figure 3An example of a transmitting circuit including a DPD circuit is shown. The DPD circuit according to the embodiment can compensate for memory effects. Memory effects refer to the fact that signals generated in the past can affect current nonlinearity.

[0043] refer to Figure 3 The DPD circuit 300 can use a finite impulse response (FIR) filter structure. For predistortion implementation, a polynomial FIR filter can be used. The DPD circuit 300 can include components according to the structure of an FIR filter. The DPD circuit 300 can include multiple DPD units, one or more delay elements, and a combiner 330. The multiple DPD units can include a first DPD unit 320-1, a second DPD unit 320-2, a third DPD unit 320-3, ..., and an i-th DPD unit 320-i. In each DPD unit, a function operation (e.g., coefficient multiplication) can be performed on the delayed signal. i can correspond to the length of the FIR filter. One or more delay elements can include a second delay element 310-2 connected to the second DPD unit 320-2, a third delay element 310-3 connected to the third DPD unit 320-3, a fourth delay element 310-4 connected to the fourth DPD unit 320-4, ..., and a delay element coupled to the Nth DPD unit. The output of each of the multiple DPD units can be provided to the combiner 330.

[0044] Combiner 330 can generate DPD output signal 335 by combining the outputs of multiple DPD units. DPD output signal 335 can be transmitted from combiner 330 to DAC 340. According to an embodiment, DPD output signal 335 can be provided to computation block 380. Computation block 380 refers to a function executed by a processor.

[0045] DAC 340 converts the DPD output signal 335 into an analog signal. DAC 340 then transmits the converted analog signal to PA 350. Although in Figure 3 Not shown, but the upconversion performed by the mixer can be performed between the DAC 340 and PA 350.

[0046] PA 350 amplifies the input signal. The signal 395 amplified by PA 350 can be transmitted via coupler 360 to a filter (not shown) (e.g., a bandpass filter (BPF)) and an antenna (not shown). The antenna can radiate the signal. PA 350 may also include a transistor. A transistor is an active element and inherently has nonlinear characteristics. Therefore, PA 350 can output a nonlinear amplifier output signal with respect to the input signal. The amplifier output signal is linearly proportional to the input signal amplitude in a certain region. However, in another region with respect to the input signal amplitude, PA 350 provides an output that is disproportionate to the input signal. In particular, as the bandwidth of the input signal to PA 350 increases, memory effects due to the second harmonic component of the input signal occur frequently. The harmonic impedance at the output of PA 350 may generate voltage components. These voltage components may be reflected by the bias line and re-input to PA 350. Therefore, memory effects may occur through the interaction between the current input signal and the re-input signal. To reduce performance delays caused by this memory effect, a DPD circuit 300 and a computation block 380 for controlling the DPD circuit 300 can be used.

[0047] The calculation block 380 may include a capture block 381 and a DPD circuit control block 382.

[0048] Capture block 381 can be used to acquire (or capture) input signal 305, DPD output signal 335, and ADC output signal 375. For example, input signal 305 can be a source signal before being input to DPD circuit 300. Input signal 305 can be referred to as DPD input. For example, DPD output signal 335 can be a signal output from DPD circuit 300. DPD output signal 335 can be a signal in which input signal 305 is distorted according to DPD. ADC output signal 375 can be a signal in which the output signal of PA350 is converted to this signal by ADC 370.

[0049] For example, capture block 381 can use at least one of input signal 305, DPD output signal 335, and ADC output signal 375 to acquire (or collect or capture) a specific number (e.g., 8192) of data samples for DPD modeling. The number of data samples to be acquired can be fixed.

[0050] DPD circuit control block 382 can control DPD circuit 300. For example, DPD circuit control block 382 can control DPD circuit 300 to predistort the nonlinear characteristics of PA 350. The operation corresponding to DPD circuit control block 382 (or calculation block 380) can be executed by a processor. That is, the processor of the electronic device can generate control signals for controlling DPD circuit 300.

[0051] According to an embodiment, the processor performing the operation corresponding to computation block 380 can determine, based on the bandwidth of the input signal, how much compensation is made to the nonlinear characteristics of PA 350 by DPD circuit 300. As the complexity of DPD circuit 300 increases, the degree of compensation for the nonlinear characteristics of PA 350 increases. The complexity of DPD circuit 300 depends on the number of activated DPD units. The number of activated DPD units can be referred to as the memory order.

[0052] According to an embodiment, the processor performing the operation corresponding to computation block 380 can determine control parameters for predistorting the nonlinear characteristics of PA 350 by comparing the input signal of PA 350 (e.g., DPD output signal 335) and the output signal of PA 350 (e.g., ADC output signal 375). Determining the control parameters can be referred to as DPD modeling. For example, DPD modeling can be performed by modeling the inverse function of PA 350 using data samples acquired through capture block 380. DPD modeling can be substantially equivalent to modeling a system where the output signal of PA 350 (e.g., ADC output signal 375) is set as the input, and the input signal of PA 350 (e.g., DPD output signal 335) is set as the output.

[0053] For example, a processor performing an operation corresponding to computation block 380 can acquire the input signal of DAC 340 (e.g., DPD output signal 335). The input signal to DAC 340 can correspond to the input signal of PA 350. The processor of computation block 380 can acquire the output signal of ADC 370. The output signal of ADC 370 (or ADC output signal 375) can correspond to the output signal of PA 350. Signal 365, isolated by coupler 360 coupled to PA 350, can pass through ADC 370 and be transmitted to computation block 380.

[0054] The results of DPD modeling can be stored in the DPD circuit 300 in the form of a lookup table (LUT) of a specified size and depth. The DPD modeling operation can be repeated to ensure DPD performance and adaptability to various environments (e.g., temperature and input signal characteristics).

[0055] According to an embodiment, the DPD circuit 300 can be configured based on the Long Term Evolution (LTE) standard and / or the New Radio (NR) standard. For example, the bandwidth of the radio signal according to the LTE and / or NR standard can be set from 5MHz to 20MHz or greater. Accordingly, the computing block 380 and / or the DPD circuit 300 can be configured to support signals with a bandwidth of 5MHz to 20MHz or greater.

[0056] When the signal bandwidth is relatively small compared to the sampling rate, computation block 380 may not be able to identify the characteristics of PA 350. For example, even if a specific number (e.g., 8192) of data samples are acquired in capture block 382, ​​computation block 380 may not be able to perform DPD modeling. For example, signals in Global System for Mobile Communications (GSM) bands (e.g., 850MHz, 900MHz, or 1800MHz bands) may have a bandwidth of 0.2MHz. The bandwidth of GSM band signals is narrower than that of LTE or NR standard signals. Therefore, DPD modeling may not be performed smoothly for GSM band signals.

[0057] In the following Figure 4a and Figure 4b In this section, regarding signals in the GSM band, examples of signals (or data samples) acquired in capture block 381 will be described. In the following text, signals in the GSM band may be referred to as GSM signals.

[0058] Figure 4a An example of a GSM signal acquired through a capture block is shown.

[0059] Figure 4b An example of the power range of a GSM signal acquired through a capture block is shown.

[0060] refer to Figure 4a Signal 401 indicates a GSM signal acquired (or captured) in capture block 381 during one sampling interval. Signal 402 indicates a GSM signal acquired (or captured) in capture block 381 according to multiple sampling intervals.

[0061] For example, if capture block 381 acquires GSM signals over multiple sampling intervals, then signal 402, which is similar to the GSM signal, can be acquired. However, if capture block 381 acquires GSM signals within one sampling interval, then signal 401, which is part of the GSM signal, can be acquired. Within one sampling interval, only the GSM signal at time interval 410 within time interval 420 can be acquired by capture block 381.

[0062] refer to Figure 4b Figure 431 shows the output signal (e.g., based on the amplitude (or power) of the input signal (e.g., GSM signal). Figure 4a The amplitude (or power) of the input signal (e.g., GSM signal 401). Graph 431 can be configured based on the signal captured during a sampling interval. Graph 432 represents the output signal (e.g., [missing information]) based on the amplitude (or power) of the input signal (e.g., GSM signal 401). Figure 4aThe amplitude (or power) of the signal 402. The curve 432 can be configured based on the signal captured over multiple sampling intervals. For example, the output signal could refer to the GSM signal acquired via capture block 381.

[0063] According to curves 431 and 432, if the capture block 381 acquires the GSM signal over multiple sampling intervals, a signal similar to the GSM signal can be acquired. However, if the capture block 381 acquires the GSM signal within one sampling interval, only a portion of the GSM signal can be acquired.

[0064] refer to Figure 4a and Figure 4b When the signal bandwidth is less than the reference bandwidth, it may not be possible to identify the characteristics of the PA for that signal using only data samples acquired in a single sampling interval. Furthermore, since the signal characteristics differ for each interval, performance may not be constant when the sampling intervals are set differently.

[0065] The technical features for improving the performance of DPD for signals with narrow bandwidth (e.g., GSM signals) will be described below in this specification.

[0066] Figure 5 An example of a transmitter circuit including a DPD circuit is shown, which is used to perform DPD modeling on a signal with a narrow bandwidth. Figure 5 The transmitting circuit can use Figure 3 The transmitting circuit. Figure 5 The computation block 580 may include Figure 3 At least a portion of the components (or blocks) of the computation block 380. Furthermore, terms such as “...unit,” “...device,” “...object,” “...body,” and “...block” used below may refer to at least one shape structure or unit used for processing functions. Figure 5 The transmitting circuit shown can be included in an electronic device.

[0067] refer to Figure 5 The DPD circuit 500 can use a finite impulse response (FIR) filter structure. The DPD circuit 500 may include multiple DPD units, one or more delay elements, one or more switches, and combiners (e.g., Figure 3 Combiner 330). For example, DPD circuit 500 can correspond to Figure 3 The DPD circuit 300.

[0068] DPD input signal 501 can be input to DPD circuit 500. DPD circuit 500 can generate DPD output signal 505 by combining the outputs of the plurality of DPD units. DPD circuit 500 can output DPD output signal 505. DPD output signal 505 can be sent to DAC 540. According to an embodiment, DPD input signal 501 and DPD output signal 505 can be provided to computing block 580. Computing block 580 can refer to a function performed by a processor of an electronic device including transmitting circuitry. Hereinafter, the operation of computing block 580 according to an embodiment can be understood as the operation of a processor.

[0069] DAC 540 converts the DPD output signal 505 into an analog signal 545. DAC 540 then transmits the analog signal 545 to PA 550. Although in Figure 5 Not shown, but the upconversion performed by the mixer can be performed between the DAC 540 and PA 550. The DAC 540 can correspond to... Figure 3 The DAC 530.

[0070] Analog signal 545 can be input to PA 550. PA 550 amplifies the input analog signal 545. PA 550 converts analog signal 545 into amplified signal 555. Amplified signal 555 can be passed to a filter (not shown) (e.g., a bandpass filter (BPF)) and an antenna (not shown) via coupler 560. The antenna can radiate the signal. PA 550 may also include a transistor. PA 550 may correspond to... Figure 3 PA 350. Coupler 560 can correspond to Figure 3 The coupler is 360.

[0071] An analog signal 565, isolated by coupler 560, can be input to ADC 570. ADC 570 converts the analog signal 565 into an ADC output signal 575. The ADC output signal 575 can be a digital signal. The ADC output signal 575 can be transmitted to computation block 580. The ADC output signal 575 can be referred to as the PA output signal. ADC 570 can correspond to... Figure 3 The ADC370.

[0072] The calculation block 580 may include a capture block 581, a sample accumulation block 582, a smoothing and extrapolation block 583, and a DPD circuit control block 584.

[0073] Capture block 581 can be used to acquire (or capture) DPD input signal 501, DPD output signal 505, and ADC output signal 575. For example, DPD input signal 501 can be a source signal before being input to DPD circuit 500. DPD input signal 501 can be referred to as DPD input. For example, DPD output signal 505 can be a signal output from DPD circuit 500. DPD output signal 505 can be a signal in which DPD input signal 501 is distorted according to DPD. ADC output signal 575 can be a signal in which the output signal of PA 550 is converted to this signal by ADC 570.

[0074] The capture block 581 can use at least one of the DPD input signal 501, the DPD output signal 505, and the ADC output signal 575 to acquire (or collect or capture) a specified number of data samples for DPD modeling.

[0075] Sample accumulation block 582 can accumulate samples acquired through multiple sampling intervals.

[0076] The smoothing and extrapolation block 583 can perform a first processing and / or a second processing, the first processing being used to average at least a portion of the gain values ​​within a specified power range, and the second processing being used to estimate the gain values ​​outside the specified power range.

[0077] DPD circuit control block 584 can control DPD circuit 500. For example, DPD circuit control block 584 can control DPD circuit 500 to predistort the nonlinear characteristics of PA 550. DPD circuit control block 584 can be referred to as DPD adaptive block.

[0078] According to an embodiment, the operation corresponding to the calculation block 580 can be performed by a processor. For example, the processor of the electronic device can generate control signals for controlling the DPD circuit 500. For example, the processor of the electronic device can use the capture block 581 to acquire at least one sample. Hereinafter, for ease of description, the operation (or calculation) associated with the calculation block 580 will be described as being performed by the processor of the electronic device.

[0079] According to an embodiment, in order to model the inverse function characteristics of PA 550, the processor can acquire an output signal (e.g., ADC output signal 575) associated with PA 550 and an input signal (e.g., DPD output signal 505) associated with PA 550. The processor can set the output signal associated with PA 550 as the input signal and set the input signal associated with PA 550 as the target signal. The processor can use the input signal and the target signal to configure a complex gain table. The complex gain table can be used for covariance matrix operations of the input signals required for modeling the inverse function characteristics of PA 550, as well as cross-correlation operations between the input signal and the target signal.

[0080] The processor can use the smoothing and extrapolation block 583 to perform the first and second processing in order to perform stable DPD modeling. The specific operations of the first and second processing will be described below.

[0081] Figure 6 This is a flowchart of the operations performed by an electronic device to change the setting information of the DPD circuit. The operations described below can be executed by the processor of the electronic device. The processor can use... Figure 5 The computation block 580 is used to execute operations 610 to 670.

[0082] refer to Figure 6 In operation 610, the processor can acquire a specified number of samples based on the input signal associated with the PA and the output signal associated with the PA. For example, the processor can perform sampling processing to acquire at least one sample within a sampling interval. The processor can repeatedly perform sampling processing until the specified number of samples have been acquired.

[0083] For example, a processor can repeat a sampling process a specified number of times (e.g., 11 times). Based on the specified number of times the sampling process has been repeated, the processor can identify that a specified number of samples have been acquired. Given that the sampling process has been executed a specified number of times, a specified number of samples can be acquired. For example, the operation used to acquire a specified number of samples can be referred to as cumulative processing.

[0084] In operation 620, the processor can identify first gain information of the input signal relative to the output signal. For example, the processor can identify the first gain information of the input signal relative to the output signal based on a specified number of samples.

[0085] For example, the processor can identify a reference power range for the output signal. The processor can identify multiple power levels corresponding to the reference power range of the output signal. As an example, the number of multiple power levels can be set to 256. The multiple power levels can be configured with integer values ​​greater than or equal to 0 and less than or equal to 255. In this disclosure, an example of multiple power levels configured with integer values ​​greater than or equal to 0 and less than or equal to 255 is described, but this is for ease of description and is not a limitation. The number and range of multiple power levels can be set in various ways.

[0086] The first gain information may include a gain value for each of a plurality of power levels of the output signal. For example, the processor may identify at least one sampled gain value for each of the plurality of power levels of the output signal. The processor may identify the average of the at least one sampled gain value as the gain value for each of the plurality of power levels. The processor may identify (or acquire) the first gain information by identifying the gain value for each of the plurality of power levels. The operation of identifying the first gain information may be referred to as normalization processing.

[0087] For example, the gain value can be configured as a complex number. The gain value can be referred to as a complex gain value. Examples of at least one sampled gain value for each of the multiple power levels of the output signal will be given below. Figure 7 The specific example of the operation to identify the first gain information will be described below. Figure 8 As described in the text.

[0088] In operation 630, the processor can identify whether the power level of the first gain information is within a specified power range. The processor can identify whether the power level of the first gain information is within the specified power range to perform one of the first and second processes.

[0089] In operation 640, if the power level of the first gain information is within a specified power range, the processor may perform a first process to average at least a portion of the gain values ​​within the specified power range in the first gain information. For example, with respect to each power level of the output signal, the processor may perform the first process to average at least a portion of the gain values ​​within the specified power range in the first gain information.

[0090] For example, the processor can use Figure 5 The smoothing and extrapolation block 583 is used to perform the first process. The first process can be referred to as the smoothing process. The specific operations of the first process will be explained below. Figure 9a and Figure 9b As described in the text.

[0091] In operation 650, if the power level of the first gain information is outside a specified power range, the processor may perform a second process to estimate the gain value outside the specified power range in the first gain information. For example, with respect to each power level of the output signal, the processor may perform the second process to estimate the gain value outside the specified power range in the first gain information. For example, the processor may use extrapolation to estimate the gain value outside the specified power range in the first gain information.

[0092] For example, the processor can use Figure 5 The smoothing and extrapolation block 583 is used to perform the second processing. This second processing can be referred to as extrapolation processing. The specific operations of the second processing will be explained below. Figure 10a and Figure 10b As described in the text.

[0093] In operation 660, the processor can acquire second gain information of the input signal relative to the output signal. For example, the processor can acquire the second gain information of the input signal relative to the output signal based on the first processing and the second processing. For example, the second gain information can be acquired based on correcting the first gain information according to the above operations.

[0094] According to an embodiment, the gain value for each of the plurality of power levels included in the first gain information can be configured discontinuously. As the first gain information is corrected to the second gain information, the gain value for each of the plurality of power levels can be configured continuously.

[0095] In operation 670, the processor can change the setting information of the DPD circuit. For example, the processor can change the setting information of the DPD circuit based on the second gain information. The processor can change the setting information of the DPD circuit by changing the control parameters associated with the DPD circuit based on the second gain information. For example, the processor can change the setting information of the DPD circuit by storing the second gain information in the DPD circuit. As an example, the second gain information may include a table configured with gain values ​​for each of a plurality of power levels. The processor can change the setting information of the DPD circuit by storing this table in the DPD circuit. This table may be referred to as a lookup table (LUT).

[0096] Figure 7 An example of a graph relating to samples acquired based on input and output signals is shown.

[0097] refer to Figure 7 The processor can acquire input signals related to the PA (e.g., Figure 5 The DPD output signal 505) and the PA-related output signals (e.g., Figure 5The ADC output signal is shown in graph 775. Graph 701 represents the output signal associated with the PA. Graph 702 represents the input signal associated with the PA. Although for ease of description, graphs 701 and 702 are shown as representing the amplitude of the signal over time, this is only for convenience, and graphs 701 and 702 could also represent the strength of the signal over frequency.

[0098] For example, to model the inverse function characteristics associated with PA, the processor can set the PA-related output signal as the input signal of the estimation model. Conversely, to model the inverse function characteristics associated with PA, the processor can set the PA-related input signal as the target signal.

[0099] The processor can acquire (or identify) first gain information of the input signal associated with the PA relative to the output signal associated with the PA. The processor can acquire samples for acquiring the first gain information. The processor can perform sampling processing to acquire at least one sample within a sampling interval 730.

[0100] For example, the processor can acquire at least one sample 710 based on the output signal. The processor can acquire at least one sample 720 based on the input signal. The processor can identify the gain value of at least one sample 720 relative to at least one sample 710. For example, sample 711 in at least one sample 710 can correspond to sample 721 in at least one sample 720. The processor can configure the signal identified based on sample 711 and the signal identified based on sample 721, as shown in the following equation.

[0101] Equation 1

[0102] Referring to Equation 1, the PA output identified by a single sample (e.g., sample 711) can refer to the output signal associated with the PA (e.g., Figure 5 The ADC output signal is 575. a and b are constants. i is the imaginary unit.

[0103] Equation 2

[0104] Referring to Equation 2, the DPD output identified by a single sample (e.g., sample 721) can refer to the input signal associated with the PA (e.g., Figure 5 The DPD output signal is 505. c and d are constants. i is the imaginary unit.

[0105] According to an embodiment, the processor can identify the magnitude of the power according to each of a plurality of power levels based on at least one sample 710. The processor can be configured with a scatter plot 703 representing the magnitude of the power according to each of the plurality of power levels.

[0106] For example, the processor can identify multiple power levels corresponding to a reference power range for the output signal associated with the PA. The processor can set a reference power range for the output signal associated with the PA. As an example, the processor can set the maximum value of multiple power levels to 255. The processor can set the minimum value of multiple power levels to 0. For example, the processor can perform quantization on the power of the output signal associated with the PA and identify it as one of a power level from 0 to 255. Figure 7 The following example is shown where multiple power levels are set to 256, but this disclosure is not limited thereto. The number of power levels can be set in various ways. For example, power level 255 can correspond to a power value of 750. According to an embodiment, power level 255 can correspond to the maximum power value of the output signal associated with the PA.

[0107] For example, the power of the output signal associated with the PA, based on the power level, can be configured as shown in the following equation.

[0108] Equation 3

[0109] In Equation 3, n is the power level. n is set to one of the levels greater than or equal to 0 and less than or equal to N. N is the power level corresponding to the maximum power of the output signal associated with PA. pwr[n] is the magnitude of the power of the output signal used for power level n. n is the power level of the output signal associated with PA quantized into N steps. Figure 7 The example shown is N set to 255, but it is not limited to this. The scatter plot 703 for at least one sample 710 can be configured according to Equation 3.

[0110] According to an embodiment, the processor may be configured with a scatter plot 704, which represents the number of each of a plurality of power levels identified using at least one sample 710.

[0111] According to an embodiment, the processor can use at least one sample 710 and at least one sample 720 to configure scatter plots 705 and 706 representing the gain of the input signal relative to the output signal. Scatter plot 705 can represent the real part gain value of the input signal relative to the output signal. Scatter plot 706 can represent the imaginary part gain value of the input signal relative to the output signal.

[0112] For example, the complex gain value of the input signal relative to the output signal can be configured as shown in the following equation.

[0113] Equation 4

[0114] Referring to Equation 4, complex gain[n] is the complex gain of the input signal relative to the output signal. pwr is configured as in Equation 3.

[0115] Equation 5

[0116] Equation 6

[0117] Referring to Equations 5 and 6, complex gain[n](i) represents the real part of the gain of the input signal relative to the output signal. Complex gain[n](q) represents the imaginary part of the gain of the input signal relative to the output signal.

[0118] Scatter plots 705 and 706 for at least one sample 710 can be configured according to Equations 5 and 6.

[0119] According to an embodiment, the processor can repeatedly perform the above sampling process. The processor can repeatedly perform the sampling process until a specified number of samples are acquired. Thereafter, the processor can identify (or acquire) first gain information by identifying the gain value corresponding to each of the plurality of power levels. To identify the first gain information, it will be explained below. Figure 8 The description specifies the operation of identifying the gain value corresponding to each of a plurality of power levels.

[0120] Figure 8 It is a flowchart of the operation of an electronic device for identifying the gain value corresponding to each power level in the power level.

[0121] refer to Figure 8 In operation 810, the processor can identify multiple power levels corresponding to a reference power range of the output signal associated with the PA. For example, the processor can set the reference power range. For instance, the maximum value of the reference power range can be set to the maximum value of the output signal associated with the PA. The minimum value of the reference power range can be set to 0. As an example, the processor can set the maximum value of the multiple power levels to 255. The processor can set the minimum value of the multiple power levels to 0. For example, the processor can quantize the magnitude of the power of the output signal associated with the PA and identify it as one of the power levels from 0 to 255.

[0122] In operation 820, the processor can identify the average of at least one sampled gain value for each of a plurality of power levels as a gain value for each of the plurality of power levels. For example, at least one sampled gain value can be identified using a specified number of samples.

[0123] According to an embodiment, the processor can identify the average value of at least one sampled gain value (e.g., a complex gain value) for each of a plurality of power levels based on a specified number of samples. The processor can identify the average value of at least one sampled gain value (e.g., a complex gain value) for each of the plurality of power levels as the gain value for each of the plurality of power levels.

[0124] For example, the processor can identify the average of at least one sampled real part gain value for each of a plurality of power levels as the real part gain value for each of the plurality of power levels. The processor can also identify the average of at least one sampled imaginary part gain value for each of the plurality of power levels as the imaginary part gain value for each of the plurality of power levels.

[0125] For example, at least one sampled gain value can be obtained with respect to a power level. The processor can identify the average of the at least one sampled gain value to identify a gain value with respect to that power level. The processor can identify the identified average as the gain value with respect to that power level. The processor can identify the gain value corresponding to each of the multiple power levels by performing the same operation on each of the multiple power levels. The operation of identifying the gain value corresponding to each of the multiple power levels can be referred to as normalization processing.

[0126] Figure 9a This is a flowchart of the operation performed by an electronic device to execute the first process.

[0127] Figure 9b The variation of the gain value within a specified power range according to the first process is shown.

[0128] refer to Figure 9a In operation 910, the processor can use a first power level from the power levels within the specified power range in the first gain information to identify a second power level less than the first power level and a third power level greater than the first power level.

[0129] According to an embodiment, the processor can determine a specified power range. The processor can identify power levels within the specified power range. For example, the processor can set a portion of multiple power levels as the specified power range. As an example, when multiple power levels are configured from 0 to 255, the specified power range can be set to a range greater than 25 and less than or equal to 220.

[0130] According to an embodiment, the processor can identify a second power level that is less than the first power level and a third power level that is greater than the first power level, centered on a first power level within a specified power range.

[0131] For example, a processor can identify a second power level that is less than a first power level. A processor can identify a third power level that is greater than the first power level. A processor can identify a second power level that is a specified level lower than the first power level. A processor can identify a third power level that is a specified level higher than the first power level. A processor can determine a specified power range based on the specified levels. As an example, with a first power level of 100, the processor can identify the second power level as 75 and the third power level as 125.

[0132] In operation 920, the processor can identify the average of the gain values ​​of the power levels between the second and third power levels as the gain value of the first power level.

[0133] For example, the processor can identify power levels between a second power level and a third power level. The processor can identify a gain value for each of the identified power levels. The processor can identify the average gain value for the identified power levels. The processor can then identify the average gain value as the gain value for the first power level.

[0134] For example, with the first power level at 100, the processor can identify the second power level as 75 and the third power level as 125. The processor can identify gain values ​​from power level 75 to power level 125. The processor can set the average of the identified gain values ​​as the gain value of the first power level.

[0135] For example, the operation of identifying the average gain value of the power level between the second and third power levels as the gain value of the first power level can be performed based on the following equation.

[0136] Equation 7

[0137] Referring to Equation 7, n can be within a range greater than 25 and less than or equal to N-25. In other words, the specified power range can be greater than 25 and less than or equal to N-25. n is the first power level. (n-25) is the second power level. (n+25) is the third power level.

[0138] According to an embodiment, the processor can perform the above operations with respect to each power level within a specified power range. The processor can perform the first processing based on performing the above operations with respect to each power level within the specified power range. An example of the change in gain value with respect to power levels within the specified power range based on the first processing will be provided later. Figure 9b As described in the text.

[0139] refer to Figure 9b The specified power range can be set to a range greater than 25 and less than or equal to 220. The processor can perform the first processing by performing the above operation with respect to each power level within the specified power range. Before performing the first processing, the gain value based on the power levels within the specified power range can be configured as shown in graph 931. After performing the first processing, the gain value with respect to the power levels within the specified power range can be configured as shown in graph 932.

[0140] According to an embodiment, the processor can use Figure 5 The smoothing and extrapolation block 583 performs the first processing (or smoothing processing) to smoothly change the gain value with respect to the power level within a specified power range.

[0141] Figure 10a This is a flowchart of the operation of an electronic device to perform a second process.

[0142] Figure 10b The variation of the gain value outside the specified power range according to the second processing is shown.

[0143] refer to Figure 10a In operation 1010, the processor can identify power levels outside the specified power range.

[0144] According to an embodiment, the processor can determine a specified power range. The processor can identify power levels outside the specified power range. For example, the processor can set a portion of multiple power levels as the specified power range. As an example, when multiple power levels are configured from 0 to 255, the specified power range can be set to a range greater than 25 and less than or equal to 220. Power levels outside the specified power range can include power levels from 0 to 25 and power levels from 221 to 225.

[0145] In operation 1020, the processor can estimate the gain value for power levels outside a specified power range. For example, the processor can estimate the gain value for power levels outside the specified power range by performing extrapolation using the first gain information.

[0146] For example, as an example, when multiple power levels are configured from 0 to 255, power levels outside the specified power range can include power levels from 0 to 25 and power levels from 221 to 225. Extrapolation can be performed on the gain values ​​(e.g., complex gain values) of the power levels from 0 to 25 according to Equation 8 below. Extrapolation can be performed on the gain values ​​(e.g., complex gain values) of the power levels from 221 to 225 according to Equation 9 below. The processor can estimate the gain value for each power level outside the specified power range by performing extrapolation.

[0147] Equation 8

[0148] Equation 9

[0149] Referring to Equations 8 and 9, Extrapolation_size is the value used to determine the extrapolation slope. For example, Extrapolation_size can be set to 12.

[0150] According to an embodiment, the processor can perform the above operation with respect to each power level outside the specified power range. The processor can perform a second process based on performing the above operation with respect to each power level outside the specified power range. Figure 10b The following example is described, in which a gain value is estimated with respect to a power level outside a specified power range according to a second process.

[0151] refer to Figure 10b The specified power range can be set to a range greater than 25 and less than or equal to 220. Power levels outside the specified power range can include power levels from 0 to 25 and power levels from 221 to 225.

[0152] The processor can perform the second processing by performing the above operations on each power level outside the specified power range. Before performing the second processing, the gain value for the power levels within the specified power range can be configured as shown in curve 1031. After performing the second processing, the estimated gain value for the power levels outside the specified power range can be configured as shown in curves 1032 and 1033.

[0153] According to an embodiment, the processor can use Figure 5 The smoothing and extrapolation block 583 performs a second process (or extrapolation process) to estimate the gain value based on the power level outside the specified power range.

[0154] Figure 11a The change in gain is shown when the first gain information is changed to the second gain information.

[0155] Figure 11b The diagram shows the phase change when the first gain information is changed to the second gain information.

[0156] Figure 12 The change in PA output is shown when the setting information of the DPD circuit is changed according to the second gain information.

[0157] refer to Figure 11a and Figure 11b Curves 1101 and 1102 represent gain changes according to power level. Curves 1111 and 1112 represent phase changes according to power level. Curves 1101 and 1111 can be configured based on first gain information. Curves 1102 and 1112 can be configured based on second gain information. Curves 1101 and 1111 may be discontinuous or not smoothly configured in signals with narrow bandwidth. Curves 1101 and 1111 may not be suitable for modeling the inverse function characteristics of the PA. The processor can use the first gain information to identify the second gain information. Curves 1102 and 1112 configured based on the second gain information can be configured continuously and smoothly even in signals with narrow bandwidth. Curves 1102 and 1112 may be suitable for modeling the inverse function characteristics of the PA.

[0158] refer to Figure 12 Graphs 1201 and 1202 represent the PA output according to frequency. Graph 1201 shows the output when applied... Figure 3 The PA output varies according to frequency in the case of the transmitting circuit shown. Graph 1202 illustrates the effect of applying... Figure 5 The PA output is based on the frequency in the case of the transmitting circuit shown. This is due to the application of... Figure 5 The transmitting circuit shown further improves the performance of the PA output.

[0159] According to the above embodiments, by accumulating a large number of samples, DPD modeling can be performed in one go, even for signals with narrow bandwidth. Furthermore, through the first processing (or smoothing processing) and the second processing (or extrapolation processing), discontinuously configured signals can be configured continuously and smoothly.

[0160] According to the above embodiments, signals can be captured at various time intervals, not only for specific intervals of signal power levels, but also for all power levels of the signal. Even for signals with narrow bandwidth, DPD modeling can be performed smoothly. Therefore, DPD performance can be improved.

[0161] Figure 13 The functional configuration of the electronic device, including the transmitting circuit, is shown.

[0162] Electronic device 1310 can be Figure 1 The base station 110 or the MMU of the base station 110. Meanwhile, unlike the illustration, this disclosure does not exclude the possibility that it can also be used in… Figure 1 The electronic device 1310 is implemented in the terminal 120. Through Figures 1 to 12 Not only the communication module associated with the transmitting circuit, but also the electronic device including the communication module are included in the embodiments of this disclosure.

[0163] refer to Figure 13 An exemplary functional configuration of electronic device 1310 is shown. Electronic device 1310 may include antenna unit 1311, filter unit 1312, radio frequency (RF) processing unit 1313, and processor 1314.

[0164] Antenna unit 1311 may include one or more antennas. The antennas perform the function of transmitting and receiving signals over a wireless channel. Antennas may include radiators made of conductors or conductive patterns formed on a substrate (e.g., a PCB). Antennas may radiate up-converted signals over the wireless channel or acquire signals radiated by another device. Each antenna may be referred to as an antenna element or antenna device. In some embodiments, antenna unit 1311 may include an antenna array of multiple antenna elements. Antenna unit 1311 may be electrically connected to filter unit 1312 via RF signal lines. Antenna unit 1311 may be mounted on a PCB including multiple antenna elements. The PCB may include multiple RF signal lines connecting each antenna element and a filter of filter unit 1312. These RF signal lines may be referred to as a feed network.

[0165] Antenna unit 1311 can provide received signals to filter unit 1312, or radiate signals provided by filter unit 1312 into the air. Filter unit 1312 can perform filtering to transmit signals of a desired frequency. Filter unit 1312 can selectively identify frequencies by forming a resonance. Filter unit 1312 may include at least one of a bandpass filter, a low-pass filter, a high-pass filter, or a band-stop filter. That is, filter unit 1312 may include RF circuitry for acquiring signals in a transmit band or a receive band. According to an embodiment, filter unit 1312 may be electrically connected to antenna unit 1311 and RF processing unit 1313.

[0166] RF processing unit 1313 may include multiple RF paths. An RF path can be a unit of the path traversed by a signal received by an antenna or a signal radiated by an antenna. At least one RF path may be referred to as an RF chain. An RF chain may include multiple RF elements. RF elements may include amplifiers, mixers, oscillators, DACs, ADCs, etc. For example, RF processing unit 1313 may include a mixer for up-converting a transmitted signal to a transmitted frequency. The transmitted path of RF processing unit 1313 may include a DAC, mixer, oscillator, and amplifier. The received path of RF processing unit 1313 may include an ADC, mixer, oscillator, and LNA. The transmitted path may also include a coupler (or combiner). Alternatively, for example, RF processing unit 1313 may include a mixer for down-converting an analog RF received signal to a digital frequency. The received path of RF processing unit 1313 may include a low-noise amplifier (LNA), mixer, oscillator, and ADC. The received path may also include a coupler or attenuator.

[0167] The RF components of the RF processing unit can be implemented on a PCB. The electronic device 1310 may include a structure in which the antenna unit 1311, the filter unit 1312, and the RF processing unit 1313 are stacked in that order. The antenna and the RF components of the RF processing unit can be implemented on a PCB, and the filter can be formed in multiple layers by repeatedly fastening it between PCBs.

[0168] Processor 1314 can control the overall operation of electronic device 1310. Processor 1314 may include various modules for performing communication. Although in Figure 13A processor is shown, but processor 1314 may also include multiple processors. Processor 1314 may include modules for digital signal processing. For example, processor 1314 may include components for controlling DPD circuitry (e.g., a baseband modem). As another example, processor 1314 may include components for operating DPD circuitry (e.g., a chip). When transmitting data, processor 1314 generates complex symbols by encoding and modulating the transmitted bit stream. Additionally, for example, when receiving data, processor 1314 recovers the received bit stream by demodulating and decoding the baseband signals. Processor 1314 can perform the functions of the protocol stack required by the communication standard.

[0169] exist Figure 13 In this context, the functional configuration of electronic device 1310 has been described as a device in which the antenna structure of this disclosure can be utilized. However, Figure 13 The examples shown are merely for the purpose of utilizing the information provided in this disclosure. Figures 1 to 12 The described antenna structure is an exemplary configuration, and the embodiments of this disclosure are not limited to those described herein. Figure 13 The components of the device shown. Therefore, an antenna module including an antenna structure, a communication device having another configuration, and the antenna structure itself can also be understood as embodiments of this disclosure.

[0170] According to an embodiment, the electronic device may include a digital predistortion (DPD) circuit, a digital-to-analog converter (DAC) coupled to the DPD circuit, a power amplifier (PA) coupled to the DAC, an analog-to-digital converter (ADC) coupled to the PA, at least one processor including processing circuitry, and a memory including one or more storage media storing instructions. When executed individually or jointly by the at least one processor, the instructions may cause the electronic device to: acquire a specified number of samples based on an input signal associated with the PA and an output signal associated with the PA. When executed individually or jointly by the at least one processor, the instructions may cause the electronic device to: identify first gain information of the input signal relative to the output signal based on the specified number of samples. When executed individually or jointly by the at least one processor, the instructions may cause the electronic device to: perform a first process with respect to each power level of the output signal to average at least a portion of the gain values ​​within a specified power range in the first gain information. When executed individually or jointly by the at least one processor, the instructions may cause the electronic device to: perform a second process with respect to each power level of the output signal to estimate gain values ​​outside the specified power range in the first gain information. When executed individually or jointly by the at least one processor, the instructions can cause the electronic device to: acquire second gain information of the input signal relative to the output signal based on the first processing and the second processing. When executed individually or jointly by the at least one processor, the instructions can cause the electronic device to: change the setting information of the DPD circuit according to the second gain information.

[0171] According to an embodiment, when executed individually or jointly by the at least one processor, the instructions can cause the electronic device to: perform sampling processing to acquire at least one sample within a sampling interval. When executed individually or jointly by the at least one processor, the instructions can also cause the electronic device to: repeatedly perform the sampling processing until a specified number of samples are acquired.

[0172] According to an embodiment, when executed individually or jointly by the at least one processor, the instructions can cause the electronic device to: identify a plurality of power levels corresponding to a reference power range of the output signal. When executed individually or jointly by the at least one processor, the instructions can cause the electronic device to: identify the average of at least one sampled gain value for each of the plurality of power levels as a gain value for each of the plurality of power levels. The at least one sampled gain value can be identified using a specified number of samples.

[0173] According to an embodiment, when the instructions are executed individually or jointly by the at least one processor, the electronic device can: identify a second power level less than the first power level and a third power level greater than the first power level using a first power level within a specified power range. When the instructions are executed individually or jointly by the at least one processor, the electronic device can: identify a gain value for the first power level by recognizing the average gain value of the power levels between the second and third power levels as a gain value for the first power level, and identify a gain value for the power levels within the specified power range. When the instructions are executed individually or jointly by the at least one processor, the electronic device can: perform a first process based on the identified gain value for the power levels within the specified power range.

[0174] According to an embodiment, when executed individually or jointly by the at least one processor, the instructions can cause the electronic device to: identify a power level outside a specified power range. When executed individually or jointly by the at least one processor, the instructions can cause the electronic device to: estimate a gain value for the power level outside the specified power range by performing extrapolation using first gain information. When executed individually or jointly by the at least one processor, the instructions can cause the electronic device to: perform a second process based on the estimated gain value for the power level outside the specified power range.

[0175] According to an embodiment, the output signal can be configured for use as a radio signal transmitted through the Global System for Mobile Communications (GSM) band.

[0176] According to an embodiment, the radio signal may have a bandwidth of 0.2 MHz.

[0177] According to an embodiment, the input signal associated with the PA may include a signal input to the PA via a DAC. The output signal associated with the PA may include a signal output from the PA via an ADC.

[0178] According to an embodiment, when the instructions are executed individually or jointly by the at least one processor, the electronic device can store second gain information in the DPD circuit.

[0179] According to an embodiment, the second gain information may include a table configured with gain values ​​for each of a plurality of power levels.

[0180] According to an embodiment, a method performed by an electronic device may include: acquiring a specified number of samples based on an input signal associated with a power amplifier (PA) of the electronic device and an output signal associated with the PA. The method may include: identifying first gain information of the input signal relative to the output signal based on the specified number of samples. The method may include: performing a first process for each power level of the output signal to average at least a portion of the gain values ​​within a specified power range in the first gain information. The method may include: performing a second process for each power level of the output signal to estimate gain values ​​outside the specified power range in the first gain information. The method may include: acquiring second gain information of the input signal relative to the output signal based on the first and second processes. The method may include: changing the setting information of a digital predistortion (DPD) circuit of the electronic device according to the second gain information.

[0181] According to an embodiment, the method may include: performing a sampling process to acquire at least one sample within a sampling interval. The method may also include: repeatedly performing the sampling process until a specified number of samples are acquired.

[0182] According to an embodiment, the method may include: identifying a plurality of power levels corresponding to a reference power range of the output signal. The method may include: identifying the average of at least one sampled gain value for each of the plurality of power levels as a gain value for each of the plurality of power levels. The at least one sampled gain value may be identified using a specified number of samples.

[0183] According to an embodiment, the method may include: using a first power level within a specified power range, identifying a second power level less than the first power level and a third power level greater than the first power level. The method may include: identifying a gain value for the power levels within the specified power range by identifying the average gain value of the power levels between the second and third power levels as a gain value for the first power level. The method may include: performing a first process based on the identified gain value for the power levels within the specified power range.

[0184] According to an embodiment, the method may include: identifying power levels outside a specified power range. The method may include: estimating a gain value for the power level outside the specified power range by performing extrapolation using first gain information. The method may include: performing a second process based on the estimated gain value for the power level outside the specified power range.

[0185] According to an embodiment, the output signal can be configured for use as a radio signal transmitted through the Global System for Mobile Communications (GSM) band.

[0186] According to an embodiment, the radio signal may have a bandwidth of 0.2 MHz.

[0187] According to an embodiment, the input signal associated with the PA may include a signal input to the PA via a DAC. The output signal associated with the PA may include a signal output from the PA via an ADC.

[0188] According to an embodiment, the method may include storing second gain information into a DPD circuit.

[0189] According to an embodiment, an electronic device may include a digital predistortion (DPD) circuit, a digital-to-analog converter (DAC) coupled to the DPD circuit, a power amplifier (PA) coupled to the DAC, an analog-to-digital converter (ADC) coupled to the PA, and at least one processor. The at least one processor may be configured to: acquire a specified number of samples based on an input signal associated with the PA and an output signal associated with the PA. The at least one processor may be configured to: identify first gain information of the input signal relative to the output signal based on the specified number of samples. The at least one processor may be configured to: perform a first process for each power level of the output signal to average at least a portion of the gain values ​​within a specified power range in the first gain information. The at least one processor may be configured to: perform a second process for each power level of the output signal to estimate gain values ​​outside the specified power range in the first gain information. The at least one processor may be configured to: acquire second gain information of the input signal relative to the output signal based on the first and second processes. The at least one processor may be configured to: change the setting information of the DPD circuit according to the second gain information.

[0190] According to an embodiment, a non-transitory computer-readable storage medium may store one or more programs. The one or more programs may include instructions, when executed by a processor of an electronic device having digital predistortion (DPD) circuitry, a digital-to-analog converter (DAC) coupled to the DPD circuitry, a power amplifier (PA) coupled to the DAC, and an analog-to-digital converter (ADC) coupled to the PA, causing the electronic device to: acquire a specified number of samples based on an input signal associated with the PA and an output signal associated with the PA. The one or more programs may include instructions, when executed by the processor of the electronic device, causing the electronic device to: identify first gain information of the input signal relative to the output signal based on the specified number of samples. The one or more programs may include instructions, when executed by the processor of the electronic device, causing the electronic device to: perform a first process with respect to each power level of the output signal to average at least a portion of the gain values ​​within a specified power range of the first gain information. The one or more programs may include instructions, when executed by the processor of the electronic device, to cause the electronic device to: perform a second process for each power level of the output signal to estimate a gain value outside a specified power range in the first gain information. The one or more programs may include instructions, when executed by the processor of the electronic device, to cause the electronic device to: obtain second gain information of the input signal relative to the output signal based on the first process and the second process. The one or more programs may include instructions, when executed by the processor of the electronic device, to cause the electronic device to: change the setting information of the DPD circuit according to the second gain information.

[0191] According to the above embodiments, in a wireless communication system, the DPD performance used for stable compensation of PA nonlinearity can be improved. When using existing general data acquisition schemes, DPD performance degradation occurs in signals with narrow bandwidths. According to the above embodiments, DPD modeling can be performed stably even in narrow communication bands such as the GSM band. According to the above embodiments, DPD modeling and / or amplifier (AMP) performance can be improved for all signals, regardless of bandwidth size.

[0192] The method according to the embodiments described in the claims or this disclosure can be implemented in hardware, software, or a combination of hardware and software.

[0193] In the case of a software implementation, a computer-readable storage medium may be provided for storing one or more programs (software modules). One or more programs stored in the computer-readable storage medium are configured to be executed by one or more processors in an electronic device. The one or more programs include instructions to cause the electronic device to perform a method according to the embodiments described in the claims or this disclosure.

[0194] Such programs (software modules, software) can be stored in random access memory, non-volatile memory including flash memory, read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), disk storage devices, optical storage devices (e.g., optical disc-ROM, digital versatile optical disc (DVD), or other formats), or magnetic tape cartridges. Alternatively, it can be stored in a memory configured with some or all of these. Furthermore, multiple configuration memories may be included.

[0195] Additionally, the program can be stored in an attachable storage device accessible via a communication network (e.g., the Internet, intranet, local area network (LAN), wide area network (WAN), or storage area network (SAN), or a combination thereof). Such a storage device can be connected to the device executing embodiments of this disclosure via an external port. Furthermore, a separate storage device on the communication network can also be connected to the device executing embodiments of this disclosure.

[0196] In the specific embodiments of this disclosure described above, the components included in this disclosure are expressed in a singular or plural form depending on the specific embodiments presented. However, the singular or plural form may be appropriately chosen for the purposes of illustration, and this disclosure is not limited to a singular or plural number of components; even components expressed in a plural form may be configured as singular, or components expressed in a singular form may be configured as plural.

[0197] Furthermore, specific embodiments have been described in the detailed description of this disclosure, and various modifications can be made without departing from the scope of this disclosure.

Claims

1. An electronic device, the electronic device comprising: Digital predistortion (DPD) circuit; A digital-to-analog converter (DAC), wherein the DAC is coupled to the DPD circuit; A power amplifier PA, which is coupled to the DAC; Analog-to-digital converter (ADC), the ADC being coupled to the PA; At least one processor, the at least one processor including processing circuitry; and The memory, comprising one or more storage media, stores instructions. Wherein, when the instructions are executed individually or jointly by the at least one processor, the electronic device: Based on the input signal and the output signal associated with the PA, a specified number of samples are obtained; Based on the specified number of samples, identify first gain information of the input signal relative to the output signal; For each power level of the output signal, a first process is performed to average at least a portion of the gain values ​​within a specified power range in the first gain information; For each of the power levels, a second process is performed to estimate a gain value outside the specified power range in the first gain information; Based on the first processing and the second processing, second gain information of the input signal relative to the output signal is obtained; and The setting information of the DPD circuit is changed according to the second gain information.

2. The electronic device according to claim 1, wherein, When the instructions are executed individually or jointly by the at least one processor, the electronic device also causes: Perform sampling processing to acquire at least one sample within the sampling interval; and Repeat the sampling process until the specified number of samples are acquired.

3. The electronic device according to claim 1, wherein, When the instructions are executed individually or jointly by the at least one processor, the electronic device also causes: Identify multiple power levels corresponding to a reference power range of the output signal; and The average of at least one sampled gain value for each of the plurality of power levels is identified as the gain value for each of the plurality of power levels, and The at least one sampling gain value is identified using the specified number of samples.

4. The electronic device according to claim 1, wherein, When the instructions are executed individually or jointly by the at least one processor, the electronic device also causes: Using a first power level within the specified power range, identify a second power level less than the first power level and a third power level greater than the first power level; Gain values ​​for power levels within the specified power range are identified by recognizing the average gain value of the power levels between the second power level and the third power level as the gain value for the first power level. as well as The first process is performed based on the identified gain value for the power level within the specified power range.

5. The electronic device according to claim 1, wherein, When the instructions are executed individually or jointly by the at least one processor, the electronic device also causes: Identify power levels outside the specified power range; Gain values ​​for power levels outside the specified power range are estimated by performing extrapolation using the first gain information; as well as The second process is performed based on the estimated gain value for power levels outside the specified power range.

6. The electronic device according to claim 1, wherein, The output signal is configured to be used as a radio signal transmitted via the GSM band of the Global System for Mobile Communications (GSM).

7. The electronic device according to claim 6, wherein, The radio signal has a bandwidth of 0.2 MHz.

8. The electronic device according to claim 1, wherein, The input signals associated with the PA include signals input to the PA via the DAC, and The output signal associated with the PA includes the signal output from the PA via the ADC.

9. The electronic device according to claim 1, wherein, When the instruction is executed individually or jointly by the at least one processor, it also causes the electronic device to store the second gain information into the DPD circuit.

10. The electronic device according to claim 9, wherein, The second gain information includes a table configured with gain values ​​for each of the plurality of power levels.

11. A method performed by an electronic device, the method comprising: Based on the input signal associated with the power amplifier PA of the electronic device and the output signal associated with the PA, a specified number of samples are obtained; Based on the specified number of samples, identify first gain information of the input signal relative to the output signal; For each power level of the output signal, a first process is performed to average at least a portion of the gain values ​​within a specified power range in the first gain information; For each power level of the output signal, a second process is performed to estimate a gain value outside the specified power range in the first gain information; Based on the first processing and the second processing, second gain information of the input signal relative to the output signal is obtained; as well as The setting information of the digital predistortion (DPD) circuit of the electronic device is changed according to the second gain information.

12. The method of claim 11, wherein, The method further includes: Perform sampling processing to acquire at least one sample within the sampling interval; and Repeat the sampling process until the specified number of samples are acquired.

13. The method of claim 11, wherein, The method further includes: Identify multiple power levels corresponding to a reference power range of the output signal; and The average of at least one sampled gain value for each of the plurality of power levels is identified as the gain value for each of the plurality of power levels. The at least one sampling gain value is identified using the specified number of samples.

14. The method according to claim 11, wherein, The method further includes: Using a first power level within the specified power range, identify a second power level less than the first power level and a third power level greater than the first power level; Gain values ​​for power levels within the specified power range are identified by recognizing the average gain value of the power levels between the second power level and the third power level as the gain value for the first power level; and The first process is performed based on the identified gain value for the power level within the specified power range.

15. A non-transitory computer-readable storage medium storing one or more programs, the one or more programs comprising instructions that, when executed by a processor of an electronic device, the electronic device has a digital predistortion (DPD) circuit, a digital-to-analog converter (DAC) coupled to the DPD circuit, a power amplifier (PA) coupled to the DAC, and an analog-to-digital converter (ADC) coupled to the PA, such that the electronic device: Based on the input signal and the output signal associated with the PA, a specified number of samples are obtained; Based on the specified number of samples, identify first gain information of the input signal relative to the output signal; For each power level of the output signal, a first process is performed to average at least a portion of the gain values ​​within a specified power range in the first gain information; For each power level of the output signal, a second process is performed to estimate a gain value outside the specified power range in the first gain information; Based on the first processing and the second processing, second gain information of the input signal relative to the output signal is obtained; as well as The setting information of the DPD circuit is changed according to the second gain information.

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