Phased array transmitter

Abstract

A phase shifter, the phase shifter comprising: a quadrature generator configured to generate an in-phase (I) signal and a quadrature (Q) signal from an input signal; an in-phase vector modulator (VM_I) configured to receive the I signal and a quadrature vector modulator (VM_Q) configured to receive the Q signal; and an auxiliary VM_I connected to the VM_I and an auxiliary VM_Q connected to the VM_Q, the auxiliary VM_I configured to receive the I signal, the auxiliary VM_Q configured to receive the Q signal, the auxiliary VM_I and the auxiliary VM_Q configured to receive a bias signal, and configured to adjust an in-phase amplitude output of the VM_I and a quadrature amplitude output of the VM_Q in response to the bias signal.

Description

Technical Field

[0001] This disclosure relates generally to electronic devices, and more specifically to transmitters in transceivers. Background Technology

[0002] Wireless communication devices and technologies are becoming increasingly prevalent as communication systems operate at millimeter-wave (mmW) frequencies and near-mmW or higher frequencies. Next-generation millimeter-wave (mmW) power amplifiers (PAs) must support multi-standard communication systems with wide bandwidth, complex modulation, and high energy efficiency. To support transmissions using high-order modulation (64-QAM / 256-QAM), high linearity and superior noise performance are required to meet error vector magnitude (EVM) requirements at both maximum power (Pmax) and near minimum power (Pmin).

[0003] Amplitude modulation (AM)-AM distortion is generally easy to compensate for, but AM-phase modulation (PM) distortion presents an additional challenge because AM-PM distortion occurs when changes in the amplitude of the power amplifier (PA) input signal cause a phase change at the PA output. AM-PM distortion can limit the EVM in the Pmax region. In the past, AM-PM distortion was compensated for by adding a varactor diode at the input of the power amplifier. However, this comes at the cost of an additional load at the PA input and a decrease in PA gain, and still does not completely eliminate AM-PM distortion. Furthermore, the lack of robust millimeter-wave (or shorter-wave) phase-invariant gain control solutions also limits the EVM to near Pmin, because at lower power, the intermediate frequency (IF) gain, rather than the millimeter-wave gain, decreases, thus limiting the overall noise performance of the transmitter.

[0004] Therefore, an effective phase-invariant gain control solution and a solution that minimizes AM-PM distortion are desired. Summary of the Invention

[0005] The various embodiments of the systems, methods, and apparatuses within the scope of the appended claims each have several aspects, none of which individually fully encompasses the desired properties described herein. Certain prominent features are described herein without limiting the scope of the appended claims.

[0006] Details of one or more specific embodiments of the subject matter described in this specification are set forth in the accompanying drawings and the following description. Other features, aspects, and advantages will become apparent from the description, drawings, and claims. It should be noted that the relative dimensions in the following drawings may not be drawn to scale.

[0007] One aspect of this disclosure provides a phase shifter comprising: a quadrature generator configured to generate an in-phase (I) signal and a quadrature (Q) signal from an input signal; an in-phase vector modulator (VM_I) configured to receive the I signal and a quadrature vector modulator (VM_Q) configured to receive the Q signal; and an auxiliary VM_I connected to VM_I and an auxiliary VM_Q connected to VM_Q, the auxiliary VM_I being configured to receive the I signal and the auxiliary VM_Q being configured to receive the Q signal, the auxiliary VM_I and the auxiliary VM_Q being configured to receive a bias signal and being configured to adjust the in-phase amplitude output of VM_I and the quadrature amplitude output of VM_Q in response to the bias signal.

[0008] Another aspect of this disclosure provides a method for signal transmission, the method comprising: generating an in-phase (I) amplitude and a quadrature (Q) amplitude based on an input signal; generating an auxiliary in-phase amplitude and an auxiliary quadrature amplitude based on the input signal and a gain signal; and adjusting the in-phase amplitude using the auxiliary in-phase amplitude and adjusting the quadrature amplitude using the auxiliary quadrature amplitude.

[0009] Another aspect of this disclosure provides an apparatus comprising: components for generating in-phase (I) amplitude and quadrature (Q) amplitude based on an input signal; components for generating auxiliary in-phase amplitude and auxiliary quadrature amplitude based on the input signal and a gain signal; and components for adjusting the in-phase amplitude using the auxiliary in-phase amplitude and adjusting the quadrature amplitude using the auxiliary quadrature amplitude. Attached Figure Description

[0010] In the accompanying drawings, unless otherwise indicated, similar reference numerals are used throughout the various views to refer to similar parts. For reference numerals with letter characters, such as "102a" or "102b", the letter characters distinguish two similar parts or elements in the same drawing. When the aim is to have the reference numerals cover all parts with the same reference numerals in all drawings, the letter characters of the reference numerals may be omitted.

[0011] Figure 1 This is a diagram illustrating communication between a wireless device and a wireless communication system.

[0012] Figure 2A This is a block diagram illustrating a wireless device in which exemplary technologies of this disclosure may be implemented.

[0013] Figure 2B This is a block diagram illustrating a wireless device in which exemplary technologies of this disclosure may be implemented.

[0014] Figure 2C This is a block diagram illustrating a wireless device in which exemplary technologies of this disclosure may be implemented.

[0015] Figure 3A schematic diagram of a portion of a transmitting circuit according to an exemplary embodiment of the present disclosure is shown.

[0016] Figure 4 This is a schematic diagram of an example (slice) of a variable gain amplifier (VGA) according to an exemplary embodiment of the present disclosure.

[0017] Figure 5 It is shown as Figure 3 and Figure 4 A schematic diagram of an example of an adaptive bias circuit, which can be used to bias auxiliary VM_I 324 and auxiliary VM_Q 326.

[0018] Figure 6 It is shown as Figure 3 A series of graphs illustrating exemplary phase changes resulting from the operation of auxiliary VM_I 324 and auxiliary VM_Q 326.

[0019] Figure 7 This is a schematic diagram of a phase shifter according to an exemplary embodiment of the present disclosure.

[0020] Figure 8 This is a flowchart illustrating an example of the operation of a method for signal transmission.

[0021] Figure 9 This is a functional block diagram of a device used for signal transmission. Detailed Implementation

[0022] The word “exemplary” is used in this document to mean “serving as an example, instance, or illustration.” Any aspect described as “exemplary” in this document is not necessarily to be construed as preferred or superior to other aspects.

[0023] In an exemplary embodiment, the phased array transmitter includes a vector modulator and an auxiliary vector modulator. The auxiliary vector modulator can be configured to receive a bias signal and can be configured to adjust the output of the vector modulator in response to the bias signal.

[0024] In an exemplary embodiment, the bias signal provided to the auxiliary vector modulator may be responsive to the input signal level provided to both the vector modulator and the auxiliary vector modulator.

[0025] In an exemplary implementation, the auxiliary vector modulator compensates for AM-PM distortion in response to the input signal level.

[0026] Figure 1This diagram illustrates communication between wireless device 110 and wireless communication system 120. Wireless communication system 120 can be a Long Term Evolution (LTE) system, a Code Division Multiple Access (CDMA) system, a Global System for Mobile Communications (GSM) system, a Wireless Local Area Network (WLAN) system, a 5G NR (New Radio) system, or some other wireless system. The CDMA system can implement Wideband CDMA (WCDMA), CDMA 1X, Evolved Data Optimized (EVDO), Time Division Synchronous CDMA (TD-SCDMA), or some other version of CDMA. For simplicity, Figure 1 A wireless communication system 120 is shown, comprising two base stations 130 and 132 and a system controller 140. Generally, a wireless communication system may include any number of base stations and any set of network entities.

[0027] Wireless device 110 may also be referred to as user equipment (UE), mobile station, terminal, access terminal, subscriber unit, station, etc. Wireless device 110 may be a cellular phone, smartphone, tablet device, wireless modem, personal digital assistant (PDA), handheld device, laptop computer, smartbook, netbook, tablet computer, cordless phone, medical device, automotive device, device configured to connect to one or more other devices (e.g., via the Internet of Things), wireless local loop (WLL) station, Bluetooth device, etc. Wireless device 110 can communicate with wireless communication system 120. Wireless device 110 can also receive signals from broadcast stations (e.g., broadcast station 134) and / or from satellites (e.g., satellites 150, etc., in one or more Global Navigation Satellite Systems (GNSS)). Wireless device 110 may support one or more radio technologies for wireless communication, such as LTE, WCDMA, CDMA 1X, EVDO, TD-SCDMA, GSM, 802.11, 802.15, 5G, Sub6 5G, 6G, Ultra Wideband (UWB), etc.

[0028] Wireless device 110 can operate in various communication frequency bands, including those used by LTE, WiFi, 5G, or other communication frequency bands within a wide frequency range. Wireless device 110 can also communicate directly with other wireless devices without communicating through a network.

[0029] Wireless device 110 may support carrier aggregation, for example, as described in one or more LTE or 5G standards. In some implementations, carrier aggregation is used to transmit a single data stream on multiple carriers, as opposed to separate carriers used for each data stream. Generally, carrier aggregation (CA) can be classified into two types: intra-band CA and inter-band CA. Intra-band CA refers to operation on multiple carriers within the same frequency band. Inter-band CA refers to operation on multiple carriers in different frequency bands.

[0030] Figure 2A This is a block diagram illustrating a wireless device 200 in which exemplary technologies of the present disclosure may be implemented. The wireless device 200 may be, for example, Figure 1 The illustrated implementation scheme of wireless device 110.

[0031] Figure 2A An example of a transceiver 220 with a transmitter 230 and a receiver 250 is shown. Generally, the conditioning of the signals in the transmitter 230 and receiver 250 can be performed by one or more stages such as amplifiers, filters, up-converters, down-converters, etc. These circuit blocks can be connected to… Figure 2A The configurations shown are arranged differently. Furthermore, Figure 2A Other circuit blocks, not shown, can also be used to regulate the signals in transmitter 230 and receiver 250, such as phase shifters as discussed further below. Unless otherwise indicated, Figure 2A Any signal in any of the other diagrams in the accompanying drawings may be a single-ended signal or a differential signal. Figure 2A Some circuit blocks in the code can also be omitted.

[0032] exist Figure 2A In the example shown, wireless device 200 typically includes a transceiver 220 and a data processor 210. Data processor 210 may include a processor 296 operatively coupled to memory 298. Memory 298 may be configured to store data and program code, generally shown using reference numeral 299, and may typically include analog and / or digital processing components. Transceiver 220 includes a transmitter 230 and a receiver 250 supporting bidirectional communication. Generally, wireless device 200 may include any number of transmitters and / or receivers for any number of communication systems and frequency bands. All or part of transceiver 220 may be implemented on one or more analog integrated circuits (ICs), RF ICs (RFICs), mixed-signal ICs, etc.

[0033] Transmitters or receivers can be implemented using either a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal undergoes multiple stages of frequency conversion between radio frequency (RF) and baseband; for example, for a receiver, this might involve switching from RF to intermediate frequency (IF) in one stage and then from IF to baseband in another. In a direct conversion architecture, the signal is converted between RF and baseband in a single stage. Superheterodyne and direct conversion architectures can utilize different circuit blocks and / or have different requirements. Figure 2A In the example shown, transmitter 230 and receiver 250 are implemented using a direct conversion architecture.

[0034] In the transmission path, data processor 210 processes the data to be transmitted and provides in-phase (I) and quadrature (Q) analog output signals to transmitter 230. In an exemplary embodiment, data processor 210 includes digital-to-analog converters (DACs) 214a and 214b for converting digital signals generated by data processor 210 into I analog output signals and Q analog output signals (e.g., I output current and Q output current) for further processing. In other embodiments, DACs 214a and 214b are included in transceiver 220, and data processor 210 provides data (e.g., for I and Q) digitally to transceiver 220.

[0035] Within transmitter 230, low-pass filters 232a and 232b filter the I and Q analog transmit signals, respectively, to remove unwanted image frequencies caused by the preceding digital-to-analog conversion. Amplifiers (Amp) 234a and 234b amplify the signals from low-pass filters 232a and 232b, respectively, providing the I baseband and Q baseband signals. Upconverter 240, with upconverters 241a and 241b, utilizes the I TX LO and Q TX LO signals from transmit (TX) local oscillator (LO) signal generator 290 to upconvert the I baseband and Q baseband signals, providing the upconverted signals. Filter 242 filters the upconverted signals to remove unwanted images caused by frequency upconversion and noise in the receive band. Power amplifier (PA) 244 amplifies the signal from filter 242 to obtain the desired output power level and provide the transmit RF signal. The transmitted RF signal is routed via a duplexer or switch 246 and transmitted through antenna 248, or alternatively, the transmitted RF signal can be transmitted to a separate transmit antenna different from the separate receive antenna. Although the examples discussed herein utilize I and Q signals, those skilled in the art will understand that transceiver components can be configured to utilize polarity modulation.

[0036] In the receiving path, antenna 248 receives the communication signal and provides the received RF signal, which can be routed via a duplexer or switch 246 and provided to a low-noise amplifier (LNA) 252. Duplexer 246 is designed to operate with specific RX and TX duplexer frequencies, thus isolating the RX and TX signals. Alternatively, separate transmit and receive antennas as mentioned above can exist, in which case RX and TX isolation can be achieved through limited coupling between the two antennas. In the case of separate RX and TX antennas, the RX antenna can be directly coupled to LNA 252. The received RF signal is amplified by LNA 252 and filtered by filter 254 to obtain the desired RF input signal. Downconverters 261a and 261b in downconverter 260 mix the output of filter 254 with the I RX LO and Q RX LO signals (i.e., LO_I and LO_Q) from receive (RX) LO signal generator 280 to generate I baseband and Q baseband signals. The I-baseband signal and Q-baseband signal are amplified by amplifiers 262a and 262b and further filtered by low-pass filters 264a and 264b to obtain the I-analog input signal and Q-analog input signal, which are provided to the data processor 210. In the illustrated exemplary embodiment, the data processor 210 includes analog-to-digital converters (ADCs) 216a and 216b for converting the analog input signals into digital signals to be further processed by the data processor 210. In some embodiments, ADCs 216a and 216b are included in transceiver 220 and provide data digitally to the data processor 210.

[0037] exist Figure 2A In this configuration, TX LO signal generator 290 generates I TX LO and Q TX LO signals for up-conversion, while RX LO signal generator 280 generates I RX LO and Q RX LO signals for down-conversion. Each LO signal is a periodic signal with a specific base frequency. Phase-locked loop (PLL) 292 receives timing information from data processor 210 and generates control signals for adjusting the frequency and / or phase of the TX LO signals from LO signal generator 290. Similarly, PLL 282 receives timing information from data processor 210 and generates control signals for adjusting the frequency and / or phase of the RX LO signals from LO signal generator 280.

[0038] In an exemplary embodiment, RX PLL 282, TX PLL 292, RX LO signal generator 280, and TX LO signal generator 290 may alternatively be combined into a single LO generator circuit 295, which may include common or shared LO signal generator circuitry to provide TX LO and RX LO signals. Alternatively, separate LO generator circuitry may be used to generate TX LO and RX LO signals.

[0039] The wireless device 200 may support carrier aggregation (CA) and may (i) receive multiple downlink signals transmitted by one or more cells on multiple downlink carriers at different frequencies, and / or (ii) transmit multiple uplink signals to one or more cells on multiple uplink carriers. However, those skilled in the art will understand that the aspects described herein may be implemented in systems, devices, and / or architectures that do not support carrier aggregation.

[0040] Figure 2A The transceiver 220 is functionally illustrated in the text, and the illustrated configuration may or may not represent the physical device configuration in certain specific implementations. For example, as described above, the transceiver 220 may be implemented in various integrated circuits (ICs), RF ICs (RFICs), mixed-signal ICs, etc. In some embodiments, the transceiver 220 is implemented on a substrate or board (such as a printed circuit board (PCB)) having various modules, chips, and / or components. For example, the power amplifier 244, filter 242, and duplexer 246 may be implemented in separate modules or as discrete components, while the remaining components illustrated in the transceiver 220 may be implemented in a single transceiver chip.

[0041] Power amplifier 244 may include one or more stages, such as driver stages, power amplifier stages, or other components that may be configured to amplify communication signals at one or more frequencies, in one or more frequency bands, and at one or more power levels. Depending on various factors, power amplifier 244 may be configured to operate using one or more driver stages, one or more power amplifier stages, one or more impedance matching networks, and may be configured to provide good linearity, efficiency, or a combination of good linearity and efficiency.

[0042] In an exemplary implementation of the superheterodyne architecture, filter 242, PA 244, LNA 252, and filter 254 can be implemented separately from other components in transmitter 230 and receiver 250, and can be implemented on a millimeter-wave integrated circuit. Figure 2B The example superheterodyne architecture is illustrated in the figure.

[0043] Figure 2BThis is a block diagram illustrating a wireless device in which exemplary technologies of this disclosure may be implemented. Figure 2B Certain components of the wireless device 200a (e.g., those indicated by the same reference numerals) may be similar to... Figure 2A The components in the wireless device 200 shown are configured, and there will be no duplicate configuration. Figure 2B Descriptions of items with the same number in the table.

[0044] Wireless device 200a is an example of a heterodyne (or superheterodyne) architecture, in which upconverter 240 and downconverter 260 are configured to process communication signals between baseband and intermediate frequency (IF). For example, upconverter 240 may be configured to provide an IF signal to upconverter 275. In an exemplary embodiment, upconverter 275 may include upconverter mixer 276. Summation function 278 of upconverter 240 combines the I output and Q output and provides the combined signal to mixer 276. The combined signal may be single-ended or differential. Mixer 276 is configured to receive the IF signal from upconverter 240 and the TX RF LO signal from TXRF LO signal generator 277, and provide the upconverted RF signal to phase shift circuit 281. Although PLL 292 is in Figure 2B The PLL is exemplified as being shared by signal generators 290 and 277, but a corresponding PLL can be implemented for each signal generator.

[0045] In an exemplary embodiment, the components in the phase shift circuit 281 may include one or more adjustable or variable phased array elements, and may receive one or more control signals from the data processor 210 via connection 294, and operate the adjustable or variable phased array elements based on the received control signals.

[0046] In an exemplary embodiment, phase shift circuit 281 includes phase shifter 283 and phased array element 287. Although three phase shifters 283 and three phased array elements 287 are shown for illustrative purposes, phase shift circuit 281 may include more or fewer phase shifters 283 and phased array elements 287.

[0047] Each phase shifter 283 can be configured to receive an RF transmission signal from the upconverter 275, change its phase by an amount, and provide an RF signal to a corresponding phased array element 287. Each phased array element 287 may include transmitting and receiving circuitry, including one or more filters, amplifiers, driver amplifiers, and power amplifiers. In some embodiments, the phase shifter 283 may be incorporated into the corresponding phased array element 287. Exemplary embodiments of the phased array transmitter described herein can be implemented in the phased array element 287.

[0048] The output of phase shift circuit 281 is provided to antenna array 248. In an exemplary embodiment, antenna array 248 includes a plurality of antennas, typically corresponding to the number of phase shifters 283 and phased array elements 287, such that each antenna element is coupled to a corresponding phased array element 287. In an exemplary embodiment, phase shift circuit 281 and antenna array 248 may be referred to as a phased array.

[0049] In the receiving direction, the output of phase shift circuit 281 is provided to downconverter 285. In an exemplary embodiment, downconverter 285 may include downconverter mixer 286. In an exemplary embodiment, mixer 286 downconverts the received RF signal provided by phase shift circuit 281 to an IF signal based on the RX RF LO signal provided by RX RF LO signal generator 279. I / Q generation function 291 of downconverter 260 receives the IF signal from mixer 286 and generates I and Q signals in downconverter 260, which downconverts the IF signal to baseband, as described above. Although PLL 282 is in Figure 2B The PLL is exemplified as being shared by signal generators 280 and 279, but a corresponding PLL can be implemented for each signal generator.

[0050] In some embodiments, the upconverter 275, downconverter 285, and phase shift circuit 281 are implemented on a common IC. In some embodiments, although the summation function 278 and the I / Q generation function 291 are implemented separately from mixers 276 and 286, such that mixers 276, 286, and phase shift circuit 281 are implemented on a common IC, the summation function 278 and the I / Q generation function 291 are not implemented on the common IC (e.g., the summation function 278 and the I / Q generation function 291 are implemented in another IC coupled to the IC having mixers 276, 286). In some embodiments, LO signal generators 277, 279 are included in a common IC. In some embodiments where the phase shift circuit is implemented on a common IC having 276, 286, 277, 278, 279, and / or 291, the common IC and antenna array 248 are included in a module that can be coupled to other components of transceiver 220 via connectors. In some implementations, the phase shift circuit 281 (e.g., a chip on which the phase shift circuit 281 is implemented) is coupled to the antenna array 248 via interconnects. For example, components of the antenna array 248 may be implemented on a substrate and coupled to an integrated circuit implementing the phase shift circuit 281 via a flexible printed circuit board, or the chip may be mounted on the substrate.

[0051] In some implementation schemes, Figure 2A The illustrated architecture and Figure 2B The illustrated architecture is implemented within the same device. For example, wireless devices 110 or 200 can be configured to use... Figure 2A The architecture illustrated communicates with signals having frequencies below approximately 7 GHz (e.g., the FR1 band) and uses... Figure 2B The architecture illustrated communicates with signals at frequencies higher than approximately 24 GHz. In devices implementing these two architectures, Figure 2A and Figure 2B One or more components with the same number can be shared between the two architectures. For example, a signal that has been directly down-converted from RF to baseband and a signal that has been down-converted from RF to baseband by an IF stage can both be filtered by the same baseband filter 264. In other embodiments, a first version of filter 264 is included in the device implementation. Figure 2A In the architecture section, and the second version of filter 264 is included in the device implementation. Figure 2B In the architecture of the part.

[0052] Figure 2C This is a block diagram illustrating a wireless device in which exemplary technologies of this disclosure may be implemented. Figure 2C Certain components of the wireless device 200b (e.g., indicated by the same reference numerals) can be configured with... Figure 2A The wireless device 200 and / or shown Figure 2B The components in the wireless device 200a shown are similar, and Figure 2C Component items with the same number will not be described again.

[0053] Figure 2C The wireless device 200b incorporates a phase shift circuit 281 in its direct conversion architecture. Figure 2B As shown in the diagram, the mmW transmit signal undergoes up-conversion and down-conversion between baseband and RF without the need for intermediate frequency (IF) signal conversion. This type of architecture can be referred to as a low-IF (LIF) or zero-IF (ZIF) architecture. For example, Figure 2C The LO signal in the architecture can include a signal with a frequency of tens of GHz. In other examples, the LO signal can be a single digital or low dual-digit GHz frequency (e.g., when wireless device 200b is configured to be used with signals in the FR3 band) or hundreds of GHz (e.g., when wireless device 200b is configured to be used with signals in the sub-THz band).

[0054] In some embodiments, upconverter 240, downconverter 260, and phase shift circuit 281 are implemented on a common IC. In some embodiments, LO signal generators 280 and 290 are included in the common IC. In some embodiments, the common IC and antenna array 248 are included in a module that can be coupled to other components of transceiver 220 via connectors. In some embodiments, phase shift circuit 281 (e.g., a chip on which phase shift circuit 281 is implemented) is coupled to antenna array 248 via interconnects, or both are mounted on a substrate. For example, components of antenna array 248 may be implemented on the substrate and coupled to the integrated circuit implementing phase shift circuit 281 via flexible printed circuitry, or the integrated circuit may be mounted on the other side of the substrate. In some embodiments, upconverter 240 and downconverter 260 may be iterated multiple times to process multiple signals in different frequency bands.

[0055] Figure 3 A schematic diagram of a portion of a transmitting circuit 300 according to an exemplary embodiment of the present disclosure is shown. The transmitting circuit 300 may be implemented wholly or partially in a phased array element 287. The transmitting circuit 300 includes a vector modulator driver (VMDR) 304 configured to receive differential input signals via differential connections 302a and 302b. The differential input signals on differential connections 302a and 302b may include modulation information signals to be transmitted. The amplified differential output of the VMDR 304 is provided to a quadrature generator 306 via differential connections 305a and 305b. In an exemplary embodiment, the quadrature generator 306 is configured to generate in-phase (I) signals I-, I+ and quadrature (Q) signals Q-, Q+ from the amplified differential input signals on connections 305a and 305b. In an exemplary embodiment, differential I- and I+ signals are provided to in-phase vector modulator (VM_I) 308 via connections 307a and 307b, and differential Q- and Q+ signals are provided to quadrature vector modulator (VM_Q) 310 via connections 309a and 309b. In another exemplary embodiment, VM_I 308 and VM_Q 310 adjust (or set) the amplitudes of the input I-, I+, Q-, and Q+ signals, respectively, and provide amplitude-adjusted I- and I+ signals to magnetic circuit 315 via connections 312a and 312b, and amplitude-adjusted Q- and Q+ signals to magnetic circuit 315 via connections 314a and 314b.

[0056] In an exemplary embodiment, magnetic circuit 315 may include an input or primary element 316 and an output or secondary element 317. Magnetic circuit 315 combines the I- and I+ signals connected to 312a and 312b with the Q- and Q+ signals connected to 314a and 314b, and provides the combined signal as an input to driver amplifier 318.

[0057] With the amplitudes of the signals connected to 312a and 312b and to 314a and 314b being equal (i.e., the I signal and Q signal are precisely offset by 90 degrees), the output of magnetic circuit 315 represents a vector 342 appearing at exactly 45 degrees relative to the I-axis, as shown in graph 340. Point 344 represents the combination of the I- and I+ signals and the Q- and Q+ signals at secondary element 317.

[0058] The driver amplifier 318 preamplifies the signal, and the power amplifier 319 provides the amplified transmitted signal to the antenna or antenna array 248. Figure 2A , 2B 、2C).

[0059] In an exemplary embodiment, the transmitting circuitry 300 includes an auxiliary vector modulator 322 having an auxiliary in-phase vector modulator (auxiliary VM_I) 324 and an auxiliary quadrature vector modulator (auxiliary VM_Q) 326 connected to the output of the quadrature generator 306. In an exemplary embodiment, auxiliary VM_I 324 may include one or more additional circuit instances (sometimes referred to as slices) of VM_I 308, and auxiliary VM_Q 326 may include one or more additional instances (or slices) of VM_Q 310. Depending on the specific implementation, auxiliary VM_I 324 and auxiliary VM_Q 326 may be configured as single (a single instance or slice of VGA circuitry) or multi-bit (multiple instances or slices of VGA circuitry).

[0060] In an exemplary embodiment, the transmitting circuit 300 further includes an adaptive bias circuit 320 configured to adaptively bias auxiliary VM_I 324 and auxiliary VM_Q 326 in response to the amplitude of the differential signals on connections 305a and 305b. The bias signals are provided to auxiliary VM_I 324 and auxiliary VM_Q 326 via connection 321. The differential I- and I+ outputs of auxiliary VM_I 324 are connected to connections 312a and 312b, and the differential Q- and Q+ outputs of auxiliary VM_Q 326 are connected to connections 314a and 314b. In an exemplary embodiment, in response to the amplitude of the input signals on connections 305a and 305b and in response to the gain applied by auxiliary VM_I 324 and auxiliary VM_Q 326, auxiliary VM_I 324 adjusts the output of VM_I 308 on connections 312a and 312b, and auxiliary VM_Q 326 adjusts the output of VM_Q 310 on connections 314a and 314b.

[0061] Depending on the amplitude of the signals at connections 305a and 305b and the gain applied by auxiliary VM_I 324 and auxiliary VM_Q 326, the adaptive bias circuit 320 can cause auxiliary VM_I 324 and auxiliary VM_Q 326 to adjust the amplitude of the I signal at connections 312a and 312b and the Q signal at connections 314a and 314b, such that point 344 moves toward the Q-axis (as shown in point 346) or toward the I-axis (as shown in point 348). For example, as the amplitude of the signals at connections 305a and 305b increases, the amplitude of the outputs of auxiliary VM_I 324 and auxiliary VM_Q 326 also increases proportionally, which, together with the adjustment of the gain applied by auxiliary VM_I 324 and auxiliary VM_Q 326, causes a resulting change in the phase of the signal at the input of the driver amplifier 318, indicated by point 346. Similarly, as the amplitude of the signals on connections 305a and 305b decreases, the amplitude of the outputs of auxiliary VM_I 324 and auxiliary VM_Q 326 also decreases proportionally. This, together with the adjustment of the gain applied by auxiliary VM_I 324 and auxiliary VM_Q 326, causes a change in the phase of the signal at the input of the driver amplifier 318, indicated by point 348.

[0062] Figure 4 This is a schematic diagram of an example (slice) of a variable gain amplifier (VGA) according to an exemplary embodiment of this disclosure. Circuit 400 represents... Figure 3 An instance of VM_I 308 or VM_Q 310 and Figure 3 An instance of auxiliary VM_I 324 or auxiliary VM_Q 326. Figure 4 An instance of VM_I 308 is shown for illustrative purposes only; it should be understood that instances of VM_Q 310 also exist. Similarly, Figure 4 An instance of auxiliary VM_I 324 is shown for illustrative purposes only; it should be understood that instances of auxiliary VM_Q 326 also exist.

[0063] In an exemplary embodiment, VM_I 308 may include transistors 456, 458, 414, 416, 417, and 418. In an exemplary embodiment, transistors 456, 458, 414, 416, 417, and 418 may include N-type transistors. However, transistors 456, 458, 414, 416, 417, and 418 may include P-type transistors or devices manufactured using other processes.

[0064] In an exemplary embodiment, transistors 456 and 458 may be configured to receive differential input signals on connections 307a and 307b and a fixed gate bias through resistors 481 and 482. Transistors 414, 416, 417, and 418 may be arranged relative to transistors 456 and 458 in a cascode architecture. In an exemplary embodiment, transistors 414 and 418 may be configured to receive a gate bias signal B. <n>Furthermore, transistors 416 and 417 can be configured to receive complementary gate bias signal B'. <n>Bias signal B <n>and B' <n>The flow of current through transistors 414, 416, 417 and 418 is controlled to allow the gain of VM_I 308 to be changed, thereby adjusting the phase of the output of VM_I 308 connected to 312a and 312b.

[0065] In an exemplary embodiment, the auxiliary VM_I 324 may include transistors 452, 454, 464, 466, 467, and 468. In an exemplary embodiment, transistors 452, 454, 464, 466, 467, and 468 may include N-type transistors. However, transistors 452, 454, 464, 466, 467, and 468 may include P-type transistors or devices manufactured using other processes.

[0066] In an exemplary embodiment, transistors 452 and 454 may be configured to receive an adaptive gate bias signal from adaptive bias circuitry 320, and transistors 464, 466, 467, and 468 may be arranged relative to transistors 452 and 454 in a cascode architecture. In an exemplary embodiment, transistors 464 and 468 may be configured to receive gate bias signal C. <n>Furthermore, transistors 466 and 467 can be configured to receive a complementary gate bias signal C'. <n>Bias signal C <n>and C' <n>The value and polarity control of the current flow through transistors 464, 466, 467 and 468, and allow for the desired polarity and amount of adaptive AM-PM distortion compensation provided by auxiliary VM_I 324 to the signals connected to 312a and 312b.

[0067] In an exemplary embodiment, circuit 450 represents Figure 3 An example of the auxiliary VM_I 324. The adaptive bias circuit 320 is based on the connection of 305a and 305b ( Figure 3 The amplitude of the signal on 305a and 305b provides a bias signal to transistors 452 and 454 in the auxiliary VM_I 324. The output of the auxiliary VM_I 324 on connections 312a and 312b is combined with the output of VM_I 308 to change the amplitude of the signal on connections 312a and 312b in response to the amplitude of the signal on connections 305a and 305b. The auxiliary VM_I 324 can be unitary (in this case, a single instance (or slice) of the auxiliary VM_I 324 will be as follows). Figure 4 The implementation shown is either a single instance (or slice) or it can be a multi-level implementation (in which case multiple instances (or slices) will be implemented as shown by the dashed lines).

[0068] In an exemplary embodiment, auxiliary VM_I 324 (and auxiliary VM_Q 326) do not affect the beamforming provided by VM_I 308. The auxiliary amplitude correction provided by auxiliary VM_I 324 (and auxiliary VM_Q 326) is applied equally to all elements of the phased array, therefore it does not affect the beamforming performed by a beamforming array (not shown), which will include transmit circuitry 300 (…). Figure 3 Multiple instances of at least some parts of ).

[0069] Beamforming arrays may include multiple transmitting circuits ( Figure 3 Multiple phase shifters in a phased array (e.g., in a 300). For example, multiple phase shifters can be arranged in a phased array (e.g., in a 300). Figure 2B / Figure 2C In the phase shifting circuit 281), the IVGA and QVGA of each phase shifter are configured to provide a phase shift relative to the signals provided by the IVGA and QVGA of the other phase shifters, while the auxiliary VM_I and auxiliary VM_Q of each phase shifter provide the same phase shift relative to the signals provided by the auxiliary VM_I and auxiliary VM_Q of the other phase shifters.

[0070] In an exemplary embodiment, the auxiliary VM_I / VM_Q 324 is adaptively biased by the adaptive bias circuit 320, while the VM_I / VM_Q 308 has a fixed gate bias applied to transistors 456 and 458. As a result, the amplitude-dependent phase (depending on the amplitude of the input signals connected to 305a and 305b) is generated by the auxiliary VM_I / VM_Q 324 using a weighted sum of the currents through transistors 464, 466, 467, and 468, which can compensate for the bias caused by the power amplifier 319 ( Figure 3 It introduces AM-PM distortion (phase lead / phase lag) in any direction without adding any additional load to the PA 319 input.

[0071] In an exemplary embodiment, the bias applied to transistors 452 and 454 in auxiliary VM_I 324 is fixed, and auxiliary VM_I 324 provides a fixed phase offset on connections 312a and 312b, which can be applied to all phase shifters in the phased array, thereby allowing phase-invariant gain control without affecting beam steering provided by VM_I 308 (and VM_Q 310).

[0072] The cascode arrangement 460 can be implemented in the auxiliary VM_I 324 to control the output of the auxiliary VM_I 324, in this example, to determine whether the amplitude of the I signal (or the Q signal of VM_Q 326 and the auxiliary VM_Q 326) is affected by the output of the auxiliary VM_I 324. For example, if it is desired that only the Q signal is affected, the cascode arrangement 460 can be turned off so that the auxiliary VM_I 324 does not affect the signals on connections 312a and 312b. Furthermore, the cascode arrangement 460 also allows for full 360-degree output phase control, such that only the I+ (in this example) or I- (in this example) output can be provided from the auxiliary VM_I 324 to the signals on connections 312a and 312b.

[0073] Figure 5 It is shown as Figure 3 and Figure 4 A schematic diagram of circuit 500, an example of an adaptive biasing circuit 320, is shown. This circuit can be used to bias auxiliary VM_I 324 and auxiliary VM_Q 326. In an exemplary embodiment, circuit 500 includes transistors 502 and 504, each transistor having a source connected to the system voltage Vdd. The drain of transistor 504 is connected to transistors 452 and 454 (…). Figure 4 The gate of ).

[0074] Circuit 500 also includes transistor 508, amplifier 506, transistors 512 and 514, transistor 516, and amplifier 518. The drain of transistor 502 is connected to the drain of transistor 508. The source of transistor 508 is connected to the drains of transistors 512 and 514. The differential input signal on connections 305a and 305b is applied to the gates of transistors 512 and 514. The sources of transistors 512 and 514 are connected together and connected to the source of transistor 516. The drain of transistor 516 is connected to system ground. Capacitor 522 is connected between the drains and sources of transistors 512 and 514.

[0075] Transistors 512 and 514 act as a square circuit for the input inp / inm signal, followed by low-pass filtering provided by capacitor 522. In this way, a current I proportional to the envelope of the inp / inm signal amplitude is generated. This envelope current I is mirrored to transistor 504, which generates an adaptive voltage proportional to the signal envelope at connection 321 and can be used to bias auxiliary VM_I 324 ( Figure 4 Transistors 452 and 454.

[0076] To ensure reliable operation of the square transistors 512 and 514, a fixed voltage and low impedance can be provided at the source node of transistor 508. This can be achieved by placing transistor 508 in negative feedback using amplifier 506. This helps to set the source node of transistor 508 to be the same as the reference voltage Vref provided at the input 507 of amplifier 506. Since AM-PM distortion typically occurs at high voltage swings, adaptive bias voltages can be avoided for input signals (inp / inm) supplied to amplifier 518 at connection 521 that are below a certain threshold voltage Vtrig. This is achieved by placing transistor 516 in negative feedback using amplifier 518 and appropriately selecting the trigger voltage Vtrig.

[0077] Figure 6 It is shown as Figure 3 A series of graphs illustrating exemplary phase changes as a result of the operation of auxiliary VM_I 324 and auxiliary VM_Q 326. Trace 610 shows the change in the adaptive bias signal in response to the amplitude of the input signal. Trace 620 shows the phase hysteresis (e.g., point 348) caused by the output of auxiliary VM_I 324 adjusting the signals on connections 312a and 312b and the output of auxiliary VM_Q 326 adjusting the signals on connections 314a and 314b. Figure 3 And trace 630 shows the phase lead (e.g., point 346) caused by the output adjustment of auxiliary VM_I 324 on the signals connected to 312a and 312b and the output adjustment of auxiliary VM_Q 326 on the signals connected to 314a and 314b. Figure 3 Phase adjustment compensation PA (319, provided by auxiliary VM_I 324 and auxiliary VM_Q 326) Figure 3 The phase change can be configured such that it does not introduce any additional load at the input of PA 319 and provides phase-invariant gain control adjustment only in response to the input signal amplitude. In an exemplary embodiment, auxiliary VM_I 324 and auxiliary VM_Q 326 can be configured to provide a relatively small phase adjustment, such as approximately 5 degrees, to the signals on connections 312a and 312b and connections 314a and 314b. Other phase adjustment amounts are possible.

[0078] In exemplary embodiments, at low power, it is desirable to have a way to adjust the gain so that current consumption can be minimized. However, changing the gain also changes the phase, which is undesirable. In such embodiments, multiple auxiliary VM_I 324 and auxiliary VM_Q 326 can be implemented to correct the phase shift caused by gain control.

[0079] Figure 7 This is a schematic diagram of a phase shifter circuit according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, the phase shifter circuit 700 includes an in-phase (I) quadrature (Q) (I / Q) generator 306, VM_I 308, auxiliary VM_I 324, VM_Q 310, auxiliary VM_Q 326, and a combinational circuit 315. For ease of illustration, Figure 7 Details of the auxiliary VM_I 324 and auxiliary VM_Q 326 are omitted. Each of VM_I 308, VM_Q 310, auxiliary VM_I 324, and auxiliary VM_Q 326 uses binary weighted device slicing to generate a weighted sum of the I and Q signals. Binary weighting is an example, and other weightings may be used in other specific implementations. The number of bits used for VM_I 308 and VM_Q 310 may differ from the number of bits used for auxiliary VM_I 324 and auxiliary VM_Q 326. The resolution of VM_I 308 and VM_Q 310 determines the phased array beam steering resolution, and 5 bits may be used in an exemplary embodiment. The number of bits used for the resolution of auxiliary VM_I 324 and auxiliary VM_Q 326 depends on how many degrees of AMPM correction are applied to the PA, and in an exemplary embodiment, this number of bits may be three or one.

[0080] In an exemplary embodiment, the I / Q generator 306 may receive differential input signals at connections 305a and 305b. In an exemplary embodiment, the in-phase positive component (Iin+ or Iinp) of the differential signal may be provided at connection 307a, and the in-phase negative component (Iin- or Iinn) of the differential signal may be provided at connection 307b.

[0081] In an exemplary embodiment, the quadrature positive components (Qin+ or Qinp) of the differential signal can be provided on connection 309a, and the quadrature negative components (Qin- or Qinn) of the differential signal can be provided on connection 309b.

[0082] In other embodiments, a single-ended signal can be provided to the I / Q generator 306, and a differential signal can be generated using, for example, a balun (not shown). The signals connected to 305a and 305b can come from the output of the balun or another component, such as an amplifier like a VGA.

[0083] In an exemplary implementation, the I / Q generator 306 may be implemented using a polyphase filter, an orthogonal hybrid coupler, a Lange coupler, or other lumped element equivalents at millimeter-wave to sub-THz frequencies.

[0084] In an exemplary embodiment, VM_I 308 includes transistors 456, 458, 414, 416, 417, and 418. In the exemplary embodiment, transistors 414 and 418 may be referred to as "through" transistors, and transistors 416 and 417 may be referred to as "crossover" transistors. Figure 7 In the example shown, transistors 456, 458, 414, 416, 417, and 418 are all N-type field-effect transistors (N-FETs). However, transistors 456, 458, 414, 416, 417, and 418 may alternatively be P-type FETs, or may be fabricated using other manufacturing techniques and processes.

[0085] The drain of transistor 414 is connected to the drain of transistor 417, and the drains of both transistors are connected to node 426 and connection 312a. The drain of transistor 416 is connected to the drain of transistor 418, and the drains of both transistors are connected to node 428 and connection 312b.

[0086] The sources of transistors 414 and 416 are connected together and then connected to the drain of transistor 456. The source of transistor 456 is connected to system ground. The sources of transistors 417 and 418 are connected together and then connected to the drain of transistor 458. The source of transistor 458 is connected to system ground.

[0087] In an exemplary embodiment, VM_Q 310 includes transistors 442, 444, 434, 436, 437, and 438. In the exemplary embodiment, transistors 434 and 438 may be referred to as "through" transistors, and transistors 436 and 437 may be referred to as "crossover" transistors. Figure 7 In the example shown, transistors 442, 444, 434, 436, 437, and 438 are all N-type field-effect transistors (N-FETs). However, transistors 442, 444, 434, 436, 437, and 438 may alternatively be P-type FETs, or may be fabricated using other manufacturing techniques and processes.

[0088] The drain of transistor 434 is connected to the drain of transistor 437, and the drains of both transistors are connected to node 446 and connection 314a. The drain of transistor 436 is connected to the drain of transistor 438, and the drains of both transistors are connected to node 448 and connection 314b.

[0089] The sources of transistors 434 and 436 are connected together and then connected to the drain of transistor 442. The source of transistor 442 is connected to system ground. The sources of transistors 437 and 438 are connected together and then connected to the drain of transistor 444. The source of transistor 444 is connected to system ground.

[0090] The Iout+ output of VM_I 308 is provided to node 786 via connection 312a, and the Iout- output of VM_I 308 is provided to node 787 via connection 312b. The Qout+ output of VM_Q 310 is provided to node 786 via connection 314a, and the Qout- output of VM_Q 310 is provided to node 787 via connection 314b.

[0091] The adaptive bias circuit 320 is configured to receive the differential input signal via connections 305a and 305b, and to provide an adaptive bias signal to the auxiliary VM_I 324 via connection 321. The Iout+ output of the auxiliary VM_I 324 is provided to node 786 via connection 312a. The Iout- output of the auxiliary VM_I 324 is provided to node 787 via connection 312b. For ease of illustration, Figure 7 Details of the auxiliary VM_I 324 are omitted.

[0092] The adaptive bias circuit 320 is configured to receive the differential input signal via connections 305a and 305b, and to provide an adaptive bias signal to the auxiliary VM_Q 326 via connection 321. The Qout+ output of the auxiliary VM_Q 326 is provided to node 786 via connection 314a. The Qout- output of the auxiliary VM_Q 326 is provided to node 787 via connection 314b. For ease of illustration, Figure 7 Details of the auxiliary VM_Q 326 are omitted.

[0093] In an exemplary embodiment, the combinational circuit 315 further includes a first winding 316 and a second winding 317. The Iout+ output on connection 312a and the Qout+ output on connection 314a are provided to node 786, which is connected to one side of the first winding 316. The Iout- output on connection 312b and the Qout- output on connection 314b are provided to node 787, which is connected to the other side of the first winding 316. The center tap of the first winding 316 is connected to the system voltage V. DD .

[0094] For illustrative purposes only, combinational circuit 315 is illustrated as a transformer. Combinatorial circuits can be implemented in other ways, such as by using a Wilkinson combiner or other circuits.

[0095] The output of the combinational circuit 315 is provided from the second winding 317 to, for example... Figure 3 The driver amplifier 318.

[0096] Figure 8 This is a flowchart 800 illustrating an example of the operation of a method for signal transmission. The blocks in method 800 may be executed in the order shown or not, and in some embodiments, may be executed at least partially in parallel.

[0097] In block 802, in-phase and quadrature amplitudes are generated by a vector modulator. For example, VM_I 308 can generate in-phase amplitudes Iout+ and Iout- on connections 312a and 312b, and VM_Q 310 can generate quadrature amplitudes Qout+ and Qout- on connections 314a and 314b.

[0098] In block 804, auxiliary in-phase amplitude and auxiliary quadrature amplitude are generated by auxiliary vector modulators. For example, auxiliary VM_I 324 can generate auxiliary in-phase amplitude on connections 312a and 312b, and auxiliary VM_Q 326 can generate auxiliary quadrature amplitude on connections 314a and 314b.

[0099] In block 806, the outputs of the auxiliary in-phase vector modulator auxiliary VM_I and the auxiliary quadrature vector modulator auxiliary VM_Q are used to adjust the in-phase and quadrature amplitudes. For example, the output of auxiliary VM_I 324 adjusts the amplitude of the output of VM_I 308 connected to 312a and 312b, and the output of auxiliary VM_Q 326 adjusts the amplitude of the output of VM_Q 310 connected to 31a and 314b.

[0100] Figure 9 This is a functional block diagram of a device 900 for signal transmission. Device 900 includes components 902 for generating in-phase and quadrature amplitudes. In some embodiments, components 902 for generating in-phase and quadrature amplitudes may be configured to perform method 800. Figure 8 The function described in operation block 802 is one or more of the functions described in the example implementation. In an exemplary embodiment, component 902 for generating in-phase and quadrature amplitudes may include VM_I 308 configured to generate in-phase amplitudes Iout+ and Iout- on connections 314a and 312b, and VM_Q 310 configured to generate quadrature amplitudes Qout+ and Qout- on connections 312a and 314b.

[0101] The apparatus 900 may further include components 904 for generating auxiliary in-phase and auxiliary quadrature amplitudes. In some embodiments, components 904 for generating auxiliary in-phase and auxiliary quadrature amplitudes may be configured to perform method 800. Figure 8 The function may be one or more of the functions described in operation block 804. In an exemplary embodiment, component 904 for generating auxiliary in-phase and auxiliary quadrature amplitudes may include auxiliary VM_I 324 configured to generate auxiliary in-phase amplitudes on connections 312a and 312b and auxiliary VM_Q 326 configured to generate auxiliary quadrature amplitudes on connections 314a and 314b.

[0102] The apparatus 900 may further include a component 906 for adjusting the in-phase and quadrature amplitudes. In some embodiments, the component 906 for adjusting the in-phase and quadrature amplitudes may be configured to perform method 800. Figure 8 The function may be one or more of the functions described in operation block 806. In an exemplary embodiment, component 906 for adjusting in-phase and quadrature amplitudes may include the outputs of auxiliary VM_I 324 and VM_I 308 coupled on connections 312a and 312b, and the outputs of auxiliary VM_Q 326 and VM_Q 310 coupled on connections 314a and 314b.

[0103] Specific implementation examples are described in the following numbered clauses:

[0104] 1. A phase shifter comprising: a quadrature generator configured to generate an in-phase (I) signal and a quadrature (Q) signal from an input signal; an in-phase vector modulator (VM_I) configured to receive the I signal and a quadrature vector modulator (VM_Q) configured to receive the Q signal; and an auxiliary VM_I connected to the VM_I and an auxiliary VM_Q connected to the VM_Q, the auxiliary VM_I being configured to receive the I signal and the auxiliary VM_Q being configured to receive the Q signal, the auxiliary VM_I and the auxiliary VM_Q being configured to receive a bias signal and being configured to adjust the in-phase amplitude output of the VM_I and the quadrature amplitude output of the VM_Q in response to the bias signal.

[0105] 2. The phase shifter according to Clause 1, wherein the bias signal is a fixed bias signal.

[0106] 3. The phase shifter according to Clause 1, wherein the bias signal is an adaptive bias signal responsive to the level of the input signal.

[0107] 4. The phase shifter according to any one of clauses 1 to 3, wherein the auxiliary VM_I and the auxiliary VM_Q comprise cascode devices configured to adjust the direction of phase rotation of the combined output of the VM_I and the VM_Q.

[0108] 5. The phase shifter according to any one of clauses 1 to 4, wherein the auxiliary VM_I and the auxiliary VM_Q comprise a unit architecture.

[0109] 6. The phase shifter according to any one of clauses 1 to 5, wherein the auxiliary VM_I and the auxiliary VM_Q comprise a multi-bit architecture.

[0110] 7. A phase shifter according to any one of claims 1 to 6, wherein the phase shifters are arranged in a phased array comprising a plurality of phase shifters, and the VM_I and VM_Q of each phase shifter are configured to provide a phase shift relative to the signals provided by the VM_I and VM_Q of the other phase shifters, while the auxiliary VM_I and auxiliary VM_Q of each phase shifter provide the same phase shift relative to the signals provided by the auxiliary VM_I and auxiliary VM_Q of the other phase shifters.

[0111] 8. The phase shifter according to any one of Clauses 3 to 7, wherein the adaptive bias signal compensates for amplitude modulation (AM)-phase modulation (PM) distortion of the power amplifier.

[0112] 9. The phase shifter according to any one of clauses 3 to 7, wherein the adaptive bias signal is generated by a bias circuit in response to an input signal of the bias circuit being higher than a threshold voltage.

[0113] 10. The phase shifter according to any one of clauses 1 to 9, wherein the phase shifter further comprises a vector modulator driver amplifier configured to receive the input signal.

[0114] 11. The phase shifter according to any one of clauses 1 to 10, the phase shifter further comprising combination circuitry configured to combine the adjusted output of the VM_I and the adjusted output of the VM_Q.

[0115] 12. A method for transmitting a signal, the method comprising: generating an in-phase (I) amplitude and a quadrature (Q) amplitude based on an input signal; generating an auxiliary in-phase amplitude and an auxiliary quadrature amplitude based on the input signal and a gain signal; and adjusting the in-phase amplitude using the auxiliary in-phase amplitude and adjusting the quadrature amplitude using the auxiliary quadrature amplitude.

[0116] 13. The method according to Clause 12, the method further comprising: adjusting the in-phase amplitude and adjusting the quadrature amplitude in response to a bias signal.

[0117] 14. The method according to Clause 13, wherein the bias signal is fixed.

[0118] 15. The method according to Clause 13, wherein the bias signal is adaptive in response to the level of the differential input signal.

[0119] 16. The method according to Clause 15, the method further comprising: adjusting the in-phase amplitude and adjusting the quadrature amplitude to become one of a lead vector or a lag vector associated with the in-phase amplitude and the quadrature amplitude.

[0120] 17. The method according to any one of clauses 12 to 16, the method further comprising: using a unit architecture to generate the auxiliary in-phase amplitude and the auxiliary quadrature amplitude.

[0121] 18. The method according to any one of clauses 12 to 16, the method further comprising: using a multi-bit architecture to generate the auxiliary in-phase amplitude and the auxiliary quadrature amplitude.

[0122] 19. An apparatus comprising: means for generating an in-phase (I) amplitude and a quadrature (Q) amplitude based on an input signal; means for generating an auxiliary in-phase amplitude and an auxiliary quadrature amplitude based on the input signal and a gain signal; and means for adjusting the in-phase amplitude using the auxiliary in-phase amplitude and adjusting the quadrature amplitude using the auxiliary quadrature amplitude.

[0123] 20. The apparatus according to Clause 19, the apparatus further comprising components for adjusting the in-phase amplitude and the quadrature amplitude in response to a bias signal.

[0124] 21. The device according to Clause 20, wherein the bias signal is fixed.

[0125] 22. The device according to Clause 20, wherein the bias signal is adaptive in response to the level of the differential input signal.

[0126] 23. The apparatus according to Clause 22, the apparatus further comprising components for adjusting the in-phase amplitude to be one of a lead vector or a lag vector associated with the in-phase amplitude and the quadrature amplitude, and components for adjusting the quadrature amplitude to be one of a lead vector or a lag vector associated with the in-phase amplitude and the quadrature amplitude.

[0127] 24. A transmitting circuit comprising: a vector modulator driver amplifier configured to receive a differential input signal; a quadrature generator configured to generate a differential in-phase (I) signal and a differential quadrature (Q) signal from the differential input signal; an in-phase vector modulator (VM_I) configured to receive the differential I signal and a quadrature vector modulator (VM_Q) configured to receive the differential Q signal; an auxiliary VM_I connected to the VM_I and an auxiliary VM_Q connected to the VM_Q, the auxiliary VM_I configured to receive the differential I signal and the auxiliary VM_Q configured to receive the differential Q signal, the auxiliary VM_I and the auxiliary VM_Q configured to receive a bias signal and configured to adjust the in-phase output of the VM_I and the quadrature output of the VM_Q in response to the bias signal; and a combination circuit configured to combine the adjusted output of the VM_I and the adjusted output of the VM_Q.

[0128] 25. The transmitting circuit according to Clause 24, wherein the bias signal is a fixed bias signal.

[0129] 26. The transmitting circuit according to Clause 24, wherein the bias signal is an adaptive bias signal responsive to the level of the differential input signal.

[0130] 27. The transmitting circuit according to any one of clauses 24 to 26, wherein the auxiliary VM_I and the auxiliary VM_Q comprise cascode devices configured to adjust the direction of phase rotation of the combined adjusted output of the VM_I and the VM_Q.

[0131] 28. The transmitting circuit according to any one of clauses 24 to 27, wherein the auxiliary VM_I and the auxiliary VM_Q comprise a unit architecture.

[0132] 29. The transmitting circuit according to any one of clauses 24 to 27, wherein the auxiliary VM_I and the auxiliary VM_Q comprise a multi-bit architecture.

[0133] 30. The transmitting circuit according to Clause 26, wherein the adaptive bias signal compensates for amplitude modulation (AM) to phase modulation (PM) distortion of the power amplifier.

[0134] 31. The transmitting circuit according to Clause 26, wherein the adaptive bias signal is generated by the bias circuit in response to an input signal of the bias circuit being higher than a threshold voltage.

[0135] 32. A phase shifter comprising: a quadrature generator configured to generate an in-phase (I) signal and a quadrature (Q) signal from an input signal; a first in-phase vector modulator configured to receive the I signal and a first quadrature vector modulator configured to receive the Q signal, wherein the first in-phase vector modulator and the first quadrature vector modulator are coupled to a fixed bias; and a second in-phase vector modulator configured to receive the I signal and a second quadrature vector modulator configured to receive the Q signal, wherein the second in-phase vector modulator and the second quadrature vector modulator are coupled to an adaptive bias.

[0136] 33. The phase shifter according to Clause 32, wherein the outputs of the first in-phase vector modulator and the second in-phase vector modulator are connected together, and the outputs of the first quadrature vector modulator and the second quadrature vector modulator are connected together.

[0137] 34. The phase shifter according to Clause 32, wherein the adaptive bias varies based on the amplitude of the input signal.

[0138] 35. A phased array comprising a plurality of phase shifters configured to be coupled to an input signal and a corresponding antenna, each of the phase shifters comprising a first vector modulator configured to receive the input signal and generate an output signal having a phase difference relative to output signals from other phase shifters in the phased array; and a second vector modulator configured to receive the input signal and generate an output signal having the same phase as other output signals from the other phase shifters in the phased array.

[0139] 36. The phase shifter according to Clause 35, wherein the second vector modulator is coupled to an adaptive bias.

[0140] 37. The phase shifter according to Clause 36, wherein the adaptive bias varies based on the amplitude of the input signal.

[0141] 38. The phase shifter according to Clause 35, wherein the second vector modulator is coupled to a fixed bias.

[0142] The circuit architecture described in this article can be implemented on one or more ICs, analog ICs, RFICs, mixed-signal ICs, ASICs, printed circuit boards (PCBs), electronic devices, etc. The circuit architecture described in this article can also be manufactured using various IC process technologies, such as complementary metal-oxide-semiconductor (CMOS), N-channel MOS (NMOS), P-channel MOS (PMOS), bipolar junction transistors (BJTs), bipolar CMOS (BiCMOS), silicon-germanium (SiGe), gallium arsenide (GaAs), heterojunction bipolar transistors (HBTs), high electron mobility transistors (HEMTs), silicon-on-insulator (SOI), etc.

[0143] The apparatus for implementing the circuit described herein may be a standalone device or part of a larger device. The device may be (i) a standalone IC, (ii) a collection of one or more ICs that may include memory ICs for storing data and / or instructions, (iii) an RF IC such as an RF receiver (RFR) or an RF transmitter / receiver (RTR), (iv) an ASIC such as a mobile station modem (MSM), (v) a module that may be embedded in other devices, (vi) a receiver, a cellular phone, a wireless device, a mobile phone or mobile unit, (vii) and so on.

[0144] While selected aspects have been illustrated and described in detail, it should be understood that various substitutions and modifications may be made therein without departing from the spirit and scope of the invention, as defined in the appended claims.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A phase shifter, the phase shifter comprising: An orthogonal generator configured to generate in-phase (I) and quadrature (Q) signals from an input signal; A non-inverting vector modulator (VM_I) configured to receive the I signal and a quadrature vector modulator (VM_Q) configured to receive the Q signal. and An auxiliary VM_I connected to the VM_I and an auxiliary VM_Q connected to the VM_Q, the auxiliary VM_I being configured to receive the I signal and the auxiliary VM_Q being configured to receive the Q signal, the auxiliary VM_I and the auxiliary VM_Q being configured to receive a bias signal and being configured to adjust the in-phase amplitude output of the VM_I and the quadrature amplitude output of the VM_Q in response to the bias signal.

2. The phase shifter according to claim 1, wherein the bias signal is a fixed bias signal.

3. The phase shifter of claim 1, wherein the bias signal is an adaptive bias signal responsive to the level of the input signal.

4. The phase shifter of claim 1, wherein the auxiliary VM_I and the auxiliary VM_Q comprise cascode devices configured to adjust the direction of phase rotation of the combined output of the VM_I and the VM_Q.

5. The phase shifter of claim 1, wherein the auxiliary VM_I and the auxiliary VM_Q comprise a unit architecture.

6. The phase shifter of claim 1, wherein the auxiliary VM_I and the auxiliary VM_Q comprise a multi-bit architecture.

7. The phase shifter of claim 1, wherein the phase shifters are arranged in a phased array comprising a plurality of phase shifters, and the VM_I and VM_Q of each phase shifter are configured to provide a phase shift relative to the signals provided by the VM_I and VM_Q of the other phase shifters, while the auxiliary VM_I and auxiliary VM_Q of each phase shifter provide the same phase shift relative to the signals provided by the auxiliary VM_I and auxiliary VM_Q of the other phase shifters.

8. The phase shifter of claim 3, wherein the adaptive bias signal compensates for amplitude modulation (AM)-phase modulation (PM) distortion of the power amplifier.

9. The phase shifter of claim 3, wherein the adaptive bias signal is generated by the bias circuit in response to an input signal of the bias circuit being higher than a threshold voltage.

10. The phase shifter of claim 1, further comprising a vector modulator driver amplifier configured to receive the input signal.

11. The phase shifter of claim 1, further comprising combination circuitry configured to combine the adjusted output of VM_I and the adjusted output of VM_Q.

12. A method for transmitting a signal, the method comprising: Generate in-phase (I) amplitude and quadrature (Q) amplitude based on the input signal; Based on the input signal and the gain signal, auxiliary in-phase amplitude and auxiliary quadrature amplitude are generated; as well as The in-phase amplitude is adjusted using the auxiliary in-phase amplitude, and the quadrature amplitude is adjusted using the auxiliary quadrature amplitude.

13. The method according to claim 12, further comprising: The in-phase amplitude and the quadrature amplitude are adjusted in response to the bias signal.

14. The method of claim 13, wherein the bias signal is fixed.

15. The method of claim 13, wherein the bias signal is adaptive in response to the level of the differential input signal.

16. The method of claim 15, further comprising: Adjust the in-phase amplitude and the quadrature amplitude to make them one of the lead or lag vectors associated with the in-phase amplitude and the quadrature amplitude.

17. The method according to claim 12, further comprising: The unit architecture is used to generate the auxiliary in-phase amplitude and the auxiliary quadrature amplitude.

18. The method according to claim 12, further comprising: A multi-bit architecture is used to generate the auxiliary in-phase amplitude and the auxiliary quadrature amplitude.

19. An apparatus, the apparatus comprising: A component used to generate in-phase (I) amplitude and quadrature (Q) amplitude based on the input signal; Components for generating auxiliary in-phase amplitude and auxiliary quadrature amplitude based on the input signal and gain signal; and A component for adjusting the in-phase amplitude using the auxiliary in-phase amplitude and adjusting the quadrature amplitude using the auxiliary quadrature amplitude.

20. The apparatus of claim 19, further comprising components for adjusting the in-phase amplitude and the quadrature amplitude in response to a bias signal.

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