Decoupling capacitor element

Abstract

A decoupling capacitor element (100) includes: an n-type well region (11n) and a p-type well region (11p); a power supply wiring (31) and a ground wiring (32) extending in an X-axis direction; a first n-type impurity region (21n) and a first p-type impurity region (21p) formed in the n-type well region (11n); and a second n-type impurity region (22n) and a second p-type impurity region (22p) formed in the p-type well region (11p). In a plan view, the n-type well region (11n) and the p-type well region (11p) are disposed adjacent to each other in a region between the power supply wiring (31) and the ground wiring (32). The power supply wiring (31) is electrically connected to the first n-type impurity region (21n) and the second n-type impurity region (22n), and the ground wiring (32) is electrically connected to the first p-type impurity region (21p) and the second p-type impurity region (22p).

Description

Technical Field

[0001] This disclosure relates to decoupling capacitor elements. Background Technology

[0002] In semiconductor integrated circuit devices (hereinafter also referred to as "semiconductor devices"), decoupling capacitor units are known to be used as noise countermeasures. For example, Patent Document 1 discloses a semiconductor device having a decoupling capacitor utilizing a MOS capacitor. Furthermore, Patent Document 2 discloses a decoupling capacitor utilizing a MOS transistor.

[0003] (Existing technical documents) (Patent Documents) Patent Document 1: Japanese Patent Application Publication No. 2007-299860 Patent Document 2: Japanese Patent Application Publication No. 2007-273846 Summary of the Invention

[0004] The problem that the invention aims to solve For example, decoupling capacitor elements, which utilize cells formed on a semiconductor substrate, may experience reduced reliability due to the miniaturization of semiconductor processes, such as increased leakage current and decreased breakdown voltage of the gate insulating film.

[0005] In Patent Document 1, two MOS capacitors are connected in series to suppress the breakdown of the gate insulating film of the MOS capacitor. However, with further miniaturization of semiconductor processes, the effect of suppressing gate insulating film breakdown is not sufficient. In addition, as semiconductor processes become smaller, the gate insulating film becomes thinner, and the leakage current itself becomes larger. Therefore, even if two MOS capacitors are connected in series, the effect of reducing leakage current is very low.

[0006] Furthermore, in Patent Document 2, a MOS transistor used as a resistive element is provided between the gate of the MOS transistor used as a capacitor element and the power supply wiring to suppress the breakdown of the gate insulating film of the MOS transistor used as a capacitor element. However, since the MOS transistor used as a resistive element increases the resistive component, the response to high frequencies deteriorates, thus reducing the effectiveness of the noise countermeasure originally intended.

[0007] Therefore, this disclosure provides a highly reliable decoupling capacitor element.

[0008] Methods for solving problems One aspect of this disclosure relates to a decoupling capacitor element comprising: an n-type well region and a p-type well region formed on a semiconductor substrate; a power supply wiring and a ground wiring located above the semiconductor substrate and extending along a first direction orthogonal to the thickness direction of the semiconductor substrate, wherein, in a plan view of the semiconductor substrate, the power supply wiring and the ground wiring are arranged along a second direction orthogonal to the first direction and the thickness direction of the semiconductor substrate; a first n-type impurity region and a first p-type impurity region formed in the n-type well region; and a second n-type impurity region and a second p-type impurity region formed in the p-type well region, wherein, in the plan view, the n-type well region and the p-type well region are adjacent to each other in the region between the power supply wiring and the ground wiring, the power supply wiring being electrically connected to the first n-type impurity region and the second n-type impurity region, and the ground wiring being electrically connected to the first p-type impurity region and the second p-type impurity region.

[0009] Invention Effects This disclosure enables the provision of highly reliable decoupling capacitor components. Attached Figure Description

[0010] Figure 1 This is a plan view illustrating an example of the decoupling capacitor element involved in the embodiment.

[0011] Figure 2 yes Figure 1 The cross-sectional view at line II-II shown.

[0012] Figure 3 yes Figure 1 The cross-sectional view at line III-III shown.

[0013] Figure 4 This is a circuit diagram of the decoupling capacitor element involved in the implementation method.

[0014] Figure 5 This is a plan view showing an example of a decoupling capacitor element according to a variation of embodiment 1.

[0015] Figure 6 This is a plan view showing an example of a decoupling capacitor element according to a modified example 2 of the embodiment.

[0016] Figure 7 yes Figure 6 The cross-sectional view at line VII-VII shown.

[0017] Figure 8 yes Figure 6 The cross-sectional view at line VIII-VIII shown.

[0018] Figure 9This is a plan view showing an example of the decoupling capacitor element involved in variation 3 of the embodiment.

[0019] Figure 10 This is a plan view showing an example of the decoupling capacitor element involved in variation 4 of the embodiment.

[0020] Figure 11 This is a plan view showing an example of the decoupling capacitor element involved in variation 5 of the embodiment.

[0021] Figure 12 This is a plan view showing another example of the decoupling capacitor element involved in variation 5 of the embodiment.

[0022] Figure 13 This is a plan view showing an example of the decoupling capacitor element involved in variation 6 of the embodiment.

[0023] Figure 14 This is a plan view showing an example of the decoupling capacitor element involved in variation 7 of the embodiment.

[0024] Figure 15 This is a plan view showing another example of the decoupling capacitor element involved in variation 7 of the embodiment.

[0025] Figure 16 This is a plan view showing an example of the decoupling capacitor element involved in variation 8 of the embodiment. Detailed Implementation

[0026] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0027] Furthermore, the embodiments described below are all general or specific examples. The numerical values, shapes, constituent elements, arrangement and connection patterns of constituent elements, steps, and order of steps shown in the following embodiments are merely examples and are not intended to limit this disclosure. Furthermore, in the constituent elements of this embodiment described below, constituent elements not described in the independent technical solution will be described as arbitrary constituent elements. In addition, all figures are schematic diagrams and are not necessarily strict illustrations. Furthermore, in all figures, substantially identical structures are labeled with the same reference numerals, and repeated descriptions will be omitted or simplified.

[0028] Furthermore, in this specification, terms indicating relationships between elements such as orthogonal, parallel, or consistent, terms indicating the shape of elements such as circular or rectangular, and numerical ranges are not merely expressions with a strict meaning, but rather imply that they also include substantially equivalent ranges, such as expressions that include differences of a few percent. Additionally, the term "same length" means substantially the same, including differences such as manufacturing errors.

[0029] Furthermore, in this specification, the terms "above" and "below" do not refer to the upward (vertically above) and downward (vertically below) directions in absolute spatial identification, but are used as terms defined by relative positional relationships. The terms "above" and "below" are only used to specify the mutual arrangement between constituent elements and are not intended to limit the orientation of the decoupling capacitor element. Similarly, the terms "lower surface" and "upper surface" do not refer to the upper and lower surfaces in absolute spatial identification. Moreover, the terms "above" and "below" apply not only to situations where two constituent elements are arranged apart from each other and other constituent elements are present between them, but also to situations where two constituent elements are arranged in close contact with each other.

[0030] Furthermore, in this specification, "plan view" refers to a plan view relative to the semiconductor substrate, that is, a view viewed from a direction perpendicular to the main surface of the semiconductor substrate, in other words, from the thickness direction of the semiconductor substrate.

[0031] Furthermore, in this specification and accompanying drawings, the X-axis, Y-axis, and Z-axis represent the three axes of a three-dimensional Cartesian coordinate system. In the following text, the Z-axis direction is defined as the thickness direction of the semiconductor substrate. Additionally, the negative side of the Z-axis is designated "below," and the positive side of the Z-axis is designated "above."

[0032] Furthermore, in this specification, ordinal numbers such as "first" and "second" do not indicate the quantity or order of constituent elements, unless otherwise stated, but are used to distinguish them in order to avoid confusion among similar constituent elements.

[0033] (Implementation Method) The decoupling capacitor element of this embodiment will be described below.

[0034] [structure] First, refer to Figures 1 to 4 The structure of the decoupling capacitor element in this embodiment will be described. Figure 1 This is a plan view showing an example of the decoupling capacitor element involved in this embodiment. Figure 2 yes Figure 1 The cross-sectional view at line II-II shown. Figure 3 yes Figure 1 The cross-sectional view at line III-III shown. Figure 4 This is a circuit diagram of the decoupling capacitor element in this embodiment. Figure 1 A plan view of the decoupling capacitor element 100 is shown when viewed from the positive side in the Z-axis direction.

[0035] exist Figure 1 For ease of observation, the first n-type impurity region 21n, the second n-type impurity region 22n, the first p-type impurity region 21p, the second p-type impurity region 22p, and the dummy gate electrode 51 are labeled with the symbols corresponding to the impurity regions 21n, 22n, 21p, 22p, and 51. Figure 2and Figure 3 The same section lines are shown in the cross-sectional view. Furthermore, in... Figure 1 In the diagram, the outline of the portion of the structure covered by the first wiring 41 and other wiring is represented by dashed lines. Furthermore, in... Figure 1 In the diagram, the boundary between the n-type well region 11n and the p-type well region 11p is also represented by a dashed line. Furthermore, in... Figure 1 The illustration of insulating layer 15 is omitted in the text. Furthermore, in... Figure 2 and Figure 3 For ease of observation, the cross-sectional lines representing the n-type well region 11n, the p-type well region 11p, and the insulating layer 15 have been omitted. Furthermore, in... Figure 2 and Figure 3 In the figures, electrical connections implemented by the n-type well region 11n and electrical connections implemented by the p-type well region 11p are schematically represented by thick solid lines. These also apply to the subsequent figures.

[0036] The decoupling capacitor element 100 in this embodiment is composed of a capacitor cell 80. The capacitor cell 80 includes: an n-type well region 11n and a p-type well region 11p formed in the semiconductor substrate 10; a power supply wiring 31 and a ground wiring 32; a first n-type impurity region 21n and a first p-type impurity region 21p formed in the n-type well region 11n; a second n-type impurity region 22n and a second p-type impurity region 22p formed in the p-type well region 11p; a first wiring 41; a second wiring 42; an insulating region 50; and a dummy gate electrode 51. Details will be described later. A diode is formed in the capacitor cell 80, but no transistor is present.

[0037] In this embodiment, the capacitor unit 80 is, for example, one of a plurality of standard units disposed in a semiconductor device. That is, the height of the capacitor unit 80 is the same as the height of the other standard units disposed around it. The width of the capacitor unit 80 may be the same as or different from the width of the other standard units disposed around it. In this specification, the width is the length in the X-axis direction, for example, a first direction. Furthermore, the height is the length in the Y-axis direction, for example, a second direction orthogonal to the first direction and the thickness direction of the semiconductor substrate 10. Figure 1 In the diagram, the area corresponding to capacitor unit 80 is represented by a rectangle with double-dotted lines. For example... Figure 1 As shown, the length of capacitor unit 80 in the Y-axis direction is from the center of power supply wiring 31 to the center of ground wiring 32 in the Y-axis direction.

[0038] In a semiconductor device, one or more capacitor cells 80 are provided. The capacitor cells 80 are, for example, arranged adjacent to other standard cells. The capacitor cells 80 are, for example, arranged near high-drive cells through which large currents flow, which are noise sources. Furthermore, the capacitor cells 80 are, for example, arranged near noise-sensitive circuits, such as clock cells or high-precision analog core circuits. Additionally, the capacitor cells 80 are, for example, arranged in blank areas of modules containing a large number of standard cells to stabilize the power supply.

[0039] The semiconductor substrate 10 is, for example, a p-type or n-type silicon substrate. The n-type well region 11n is, for example, a well formed by implanting n-type impurities into the semiconductor substrate 10. The p-type well region 11p is a well formed by implanting p-type impurities into the semiconductor substrate 10. Furthermore, in the case where the semiconductor substrate 10 is a p-type silicon substrate or similar semiconductor substrate containing p-type impurities, where regions that can become p-type wells are pre-formed, the p-type well region 11p can also be a region directly used on the semiconductor substrate 10. Similarly, in the case where the semiconductor substrate 10 is an n-type silicon substrate or similar semiconductor substrate containing n-type impurities, where regions that can become n-type wells are pre-formed (for example), the n-type well region 11n can also be a region directly used on the semiconductor substrate 10.

[0040] The first n-type impurity region 21n, the first p-type impurity region 21p, the second n-type impurity region 22n, the second p-type impurity region 22p, and the insulating region 50 are each regions extending from the upper surface of the semiconductor substrate 10 to a predetermined depth.

[0041] The first n-type impurity region 21n is, for example, an impurity diffusion region formed by implanting n-type impurities into the n-type well region 11n, and its impurity concentration is higher than that of the n-type well region 11n. The first n-type impurity region 21n is electrically connected to the power supply wiring 31. A power supply voltage VDD is applied to the first n-type impurity region 21n through the power supply wiring 31. The first n-type impurity region 21n serves as a substrate contact region for providing the power supply voltage VDD to the n-type well region 11n. That is, the capacitor unit 80 also serves as a substrate contact unit for stabilizing the potential of the n-type well region 11n. Thus, without the need to add additional units for substrate contact, the layout area efficiency of the semiconductor device in which the capacitor unit 80 is provided can be improved.

[0042] The first p-type impurity region 21p is, for example, an impurity diffusion region formed by injecting p-type impurities into the n-type well region 11n, and its impurity concentration is higher than that of the p-type well region 11p. The first p-type impurity region 21p is electrically connected to the ground wiring 32. A ground level voltage VSS is applied to the first p-type impurity region 21p through the ground wiring 32.

[0043] The second n-type impurity region 22n is, for example, an impurity diffusion region formed by injecting n-type impurities into the p-type well region 11p, and its impurity concentration is higher than that of the n-type well region 11n. The second n-type impurity region 22n is electrically connected to the power supply wiring 31. A power supply voltage VDD is applied to the second n-type impurity region 22n through the power supply wiring 31.

[0044] The second p-type impurity region 22p is, for example, an impurity diffusion region formed by implanting p-type impurities into the p-type well region 11p, and its impurity concentration is higher than that of the p-type well region 11p. The second p-type impurity region 22p is electrically connected to the ground wiring 32. A voltage VSS is applied to the second p-type impurity region 22p through the ground wiring 32. The second p-type impurity region 22p serves as a substrate contact region for providing the voltage VSS to the p-type well region 11p. That is, the capacitor unit 80 also serves as a substrate contact unit for stabilizing the potential of the p-type well region 11p. As a result, the layout area efficiency of the semiconductor device in which the capacitor unit 80 is provided can be improved.

[0045] An insulating region 50 is formed in the semiconductor substrate 10 to electrically isolate the first n-type impurity region 21n, the first p-type impurity region 21p, the second n-type impurity region 22n, and the second p-type impurity region 22p from each other. In a plan view, the insulating region 50 is configured to surround each of the first n-type impurity region 21n, the first p-type impurity region 21p, the second n-type impurity region 22n, and the second p-type impurity region 22p. The insulating region 50 is made of an insulating material such as silicon oxide. The insulating region 50 is, for example, a shallow trench isolation (STI) formed in the semiconductor substrate 10.

[0046] Power supply wiring 31 and ground wiring 32 are wirings located above the semiconductor substrate 10 and extending along the X-axis. Power supply wiring 31 and ground wiring 32 are opposite to the semiconductor substrate 10 through insulating layer 15. Although in Figure 2 and Figure 3 Not shown in the diagram, but an insulating layer and wiring layer may be further configured above the power supply wiring 31 and the ground wiring 32. The power supply wiring 31 and the ground wiring 32 are, for example, located in the wiring layer closest to the semiconductor substrate 10 among more than one wiring layer formed above the semiconductor substrate 10. The power supply wiring 31 and the ground wiring 32 are parallel to each other and are arranged along the Y-axis direction in a plan view.

[0047] A power supply voltage VDD is applied to power supply wiring 31. In capacitor cell 80, power supply wiring 31 overlaps with n-type well region 11n in plan view. A voltage VSS is applied to ground wiring 32. In capacitor cell 80, ground wiring 32 overlaps with p-type well region 11p in plan view. Power supply wiring 31 and ground wiring 32 are, for example, a power trunk shared by cells arranged along the X-axis direction.

[0048] The first wiring 41 electrically connects the power wiring 31 to the second n-type impurity region 22n. Figures 1 to 3 In the example shown, the first wiring 41 also electrically connects the power wiring 31 to the first n-type impurity region 21n. Figures 1 to 3 In the example shown, the first wiring 41 is directly connected to the power wiring 31, and the first wiring 41 is connected to the first n-type impurity region 21n and the second n-type impurity region 22n via a connector 45 formed of metal or doped polysilicon, etc. Figure 1 (Not shown in the diagram) Connection. The first wiring 41 extends along the Y-axis from the connection with the power wiring 31 toward the ground wiring 32.

[0049] The second wiring 42 electrically connects the grounding wiring 32 to the first p-type impurity region 21p. Figures 1 to 3 In the example shown, the second wiring 42 also electrically connects the ground wiring 32 to the second p-type impurity region 22p. Figures 1 to 3 In the example shown, the second wiring 42 is directly connected to the ground wiring 32, and the second wiring 42 is connected to the first p-type impurity region 21p and the second p-type impurity region 22p via a plug 45. The second wiring 42 extends along the Y-axis from the connection with the ground wiring 32 toward the power wiring 31.

[0050] The first wiring 41 and the second wiring 42 are located above the semiconductor substrate 10. The first wiring 41 and the second wiring 42 are opposite to the semiconductor substrate 10 through an insulating layer 15. The first wiring 41 and the second wiring 42 are arranged along the X-axis direction. The first wiring 41 and the second wiring 42 are adjacent to each other through the insulating layer 15. As a result, an inter-wiring capacitance is formed between the first wiring 41 and the second wiring 42, thereby increasing the capacitance value of the decoupling capacitor element 100.

[0051] Power supply wiring 31, ground wiring 32, first wiring 41, and second wiring 42 are disposed, for example, in the same wiring layer among one or more wiring layers stacked above the semiconductor substrate 10. Power supply wiring 31, ground wiring 32, first wiring 41, and second wiring 42 are formed, for example, by a conductor such as metal.

[0052] A dummy gate electrode 51 is disposed on the insulating region 50. The dummy gate electrode 51 is a dummy electrode that mimics the gate electrode. The dummy gate electrode 51 is electrically insulated from any one of the n-type well region 11n, the p-type well region 11p, the first n-type impurity region 21n, the first p-type impurity region 21p, the second n-type impurity region 22n, and the second p-type impurity region 22p. The surface of the dummy gate electrode 51, except for the surface on the insulating region 50 side, is covered by an insulating layer 15. The dummy gate electrode 51 is formed, for example, from polysilicon doped with impurities. By forming a dummy gate electrode 51 that mimics the gate electrode, it is ensured that the gate electrode area within the semiconductor device reaches a predetermined value or higher, thereby improving the accuracy of the gate length and gate width of the gate electrode of transistors formed in cells other than the capacitor cell 80. Furthermore, an insulating film (not shown) that mimics the gate insulating film may also be formed between the dummy gate electrode 51 and the insulating region 50.

[0053] In a plan view, the capacitor cell 80 includes: a dummy gate electrode 51 located between a first n-type impurity region 21n and a first p-type impurity region 21p; and a dummy gate electrode 51 located between a second n-type impurity region 22n and a second p-type impurity region 22p. Each dummy gate electrode 51 is an elongated shape extending along the Y-axis in the plan view.

[0054] like Figure 4 As shown, in the decoupling capacitor element 100, the n-type well region 11n and the first p-type impurity region 21p constitute a diode, and the p-type well region 11p and the second n-type impurity region 22n constitute a diode. Figure 4 In this circuit, the combination of two sets of p-type well regions 11p and the second n-type impurity region 22n is represented by a diode circuit symbol. Furthermore, in the decoupling capacitor element 100, a reverse bias voltage is applied to these diodes through power supply wiring 31 and ground wiring 32. Therefore, as... Figure 2 As schematically shown, a junction capacitance is generated at the pn junction of the n-type well region 11n and the first p-type impurity region 21p. Furthermore, as... Figure 3 As schematically shown, junction capacitances are generated at the pn junction of the p-type well region 11p and the second n-type impurity region 22n. In the decoupling capacitor element 100, these junction capacitances serve as decoupling capacitors to reduce noise. In the decoupling capacitor element 100, since a gate insulating film that would cause a decrease in breakdown voltage is not used as a capacitor, damage caused by electrostatic discharge (ESD) and other factors is suppressed. Furthermore, the leakage current in the reverse bias direction is very small in the pn junction, thus reducing leakage current in the decoupling capacitor element 100. Therefore, a highly reliable decoupling capacitor element 100 is achieved.

[0055] [Floor plan layout] Next, refer to Figure 1 This section describes the planar layout details of the decoupling capacitor element 100 (capacitor unit 80).

[0056] First, the planar layout of the n-type well region 11n, the p-type well region 11p, the first n-type impurity region 21n, the first p-type impurity region 21p, the second n-type impurity region 22n, and the second p-type impurity region 22p is described.

[0057] The n-type well region 11n and the p-type well region 11p are located adjacent to each other in the plan view between the power supply wiring 31 and the ground wiring 32. The n-type well region 11n and the p-type well region 11p are arranged along the Y-axis in the region between the power supply wiring 31 and the ground wiring 32. Therefore, a diode used as a decoupling capacitor can be formed using the region between the power supply wiring 31 and the ground wiring 32. Here, the region between the power supply wiring 31 and the ground wiring 32 refers to the region that also includes the areas overlapping with the power supply wiring 31 and the ground wiring 32 in the plan view. That is, in the Y-axis direction, the region between the power supply wiring 31 and the ground wiring 32 extends from the positive Y-axis end of the power supply wiring 31 to the negative Y-axis end of the ground wiring 32.

[0058] The capacitor cell 80 includes two first n-type impurity regions 21n, one first p-type impurity region 21p, two second n-type impurity regions 22n, and one second p-type impurity region 22p. In the capacitor cell 80, the number of first n-type impurity regions 21n is the same as the number of second n-type impurity regions 22n, and the number of first p-type impurity regions 21p is the same as the number of second p-type impurity regions 22p. In a plan view, the first n-type impurity regions 21n and the first p-type impurity regions 21p are arranged alternately along the X-axis. Furthermore, in a plan view, the second n-type impurity regions 22n and the second p-type impurity regions 22p are arranged alternately along the X-axis.

[0059] Furthermore, in the plan view, the first n-type impurity region 21n and the second n-type impurity region 22n are arranged along the Y-axis. Also, in the plan view, the first p-type impurity region 21p and the second p-type impurity region 22p are arranged along the Y-axis. This simplifies the electrical connection path between the power supply wiring 31 and the first n-type impurity region 21n and the second n-type impurity region 22n, as well as the electrical connection path between the ground wiring 32 and the first p-type impurity region 21p and the second p-type impurity region 22p. Furthermore, the length of the first n-type impurity region 21n in the X-axis direction is the same as the length of the second n-type impurity region 22n in the X-axis direction. Furthermore, the length of the first p-type impurity region 21p in the X-axis direction is the same as the length of the second p-type impurity region 22p in the X-axis direction. This makes it easier to widen the wiring width for the electrical connection path between the power supply wiring 31 and the first n-type impurity region 21n and the second n-type impurity region 22n, as well as the electrical connection path between the ground wiring 32 and the first p-type impurity region 21p and the second p-type impurity region 22p. Figure 1In the example shown, the position of the first n-type impurity region 21n in the X-axis direction is aligned with the position of the second n-type impurity region 22n in the X-axis direction. Furthermore, the position of the first p-type impurity region 21p in the X-axis direction is aligned with the position of the second p-type impurity region 22p in the X-axis direction.

[0060] Next, the planar layout of the first wiring 41 and the second wiring 42 will be described.

[0061] The capacitor cell 80 includes two first wirings 41 and one second wiring 42. In the capacitor cell 80, the number of first wirings 41 is the same as the number of first n-type impurity regions 21n and the number of second n-type impurity regions 22n. Furthermore, the number of second wirings 42 is the same as the number of first p-type impurity regions 21p and the number of second p-type impurity regions 22p.

[0062] In capacitor cell 80, the first wiring 41 and the second wiring 42 are opposite to each other between power supply wiring 31 and ground wiring 32, and are arranged adjacent to each other on the same plane. Furthermore, there are two first wirings 41, and the first wirings 41 and the second wirings 42 are arranged alternately along the X-axis. This increases the amount of inter-wiring capacitance between the first wirings 41 and the second wirings 42 formed in capacitor cell 80.

[0063] The spacing between the first wiring 41 and the second wiring 42 can be the minimum width of the wiring spacing design rules for a semiconductor device in which the capacitor unit 80 is provided. This increases the inter-wiring capacitance between the first wiring 41 and the second wiring 42. However, in other locations of the semiconductor device in which the capacitor unit 80 is provided, where an inter-wiring capacitor element, typically referred to as an MOM (Metal-Oxide-Metal) capacitor element, exists, the spacing between the first wiring 41 and the second wiring 42 may not be narrower than the wiring spacing of that inter-wiring capacitor element.

[0064] In capacitor cell 80, in plan view, the first wiring 41 completely overlaps with the first n-type impurity region 21n and the second n-type impurity region 22n. Furthermore, in plan view, the second wiring 42 completely overlaps with the first p-type impurity region 21p and the second p-type impurity region 22p.

[0065] (Modifications of the implementation method) Next, variations of the implementation method will be described. Furthermore, in the following description of the variations, the focus will be on the differences between the implementation method and the various variations of the implementation method, while omitting or simplifying the description of commonalities.

[0066] [Variation Example 1] First, the decoupling capacitor element involved in the modified example 1 of the implementation will be described. Figure 5 This is a plan view showing an example of the decoupling capacitor element involved in this variation. Figure 5 A plan view of the decoupling capacitor element 101 is shown when viewed from the front side in the Z-axis direction.

[0067] like Figure 5 As shown, the decoupling capacitor element 101 involved in this modified example is composed of a capacitor unit 81. The main difference between the capacitor unit 81 and the capacitor unit 80 described above is that the areas of the first n-type impurity region 21n, the first p-type impurity region 21p, the second n-type impurity region 22n, and the second p-type impurity region 22p are different.

[0068] exist Figure 5 In the example shown, the length of capacitor cell 81 in the X-axis direction is longer than its length in the Y-axis direction. Capacitor cell 81 includes two first n-type impurity regions 21n, one first p-type impurity region 21p, two second n-type impurity regions 22n, and one second p-type impurity region 22p. In the plan view, the first n-type impurity regions 21n and the first p-type impurity regions 21p are arranged alternately along the X-axis. Furthermore, in the plan view, the second n-type impurity regions 22n and the second p-type impurity regions 22p are arranged alternately along the X-axis.

[0069] In capacitor cell 81, in plan view, the area of ​​one first p-type impurity region 21p is greater than the total area of ​​two first n-type impurity regions 21n. Furthermore, in capacitor cell 81, in plan view, the total area of ​​two second n-type impurity regions 22n is greater than the area of ​​one second p-type impurity region 22p. Therefore, the pn junction of the first p-type impurity region 21p and the n-type well region 11n, and the pn junction of the second n-type impurity region 22n and the p-type well region 11p that generate the junction capacitance, can be increased, thereby increasing the capacitance value of decoupling capacitor element 101.

[0070] [Modification Example 2] Next, the decoupling capacitor element of the modified example 2 involved in the implementation will be described. Figure 6 This is a plan view showing an example of the decoupling capacitor element involved in this variation. Figure 7 yes Figure 6 The cross-sectional view at line VII-VII shown. Figure 8 yes Figure 6 The cross-sectional view at line VIII-VIII shown. Figure 6 A plan view of the decoupling capacitor element 102 is shown when viewed from the front side in the Z-axis direction.

[0071] like Figure 6As shown, the decoupling capacitor element 102 involved in this modified example is composed of a capacitor unit 82. The main difference between capacitor unit 82 and capacitor unit 81 is that the number of first n-type impurity region 21n, first p-type impurity region 21p, second n-type impurity region 22n, and second p-type impurity region 22p is greater.

[0072] exist Figure 6 In the example shown, the length of capacitor cell 82 in the X-axis direction is longer than its length in the Y-axis direction. Capacitor cell 82 includes: three first n-type impurity regions 21n, two first p-type impurity regions 21p, three second n-type impurity regions 22n, and two second p-type impurity regions 22p. In the plan view, the first n-type impurity regions 21n and the first p-type impurity regions 21p are arranged alternately along the X-axis direction. Furthermore, in the plan view, the second n-type impurity regions 22n and the second p-type impurity regions 22p are arranged alternately along the X-axis direction.

[0073] In capacitor cell 82, in plan view, the total area of ​​the two first p-type impurity regions 21p is greater than the total area of ​​the three first n-type impurity regions 21n. Furthermore, in capacitor cell 82, in plan view, the total area of ​​the three second n-type impurity regions 22n is greater than the total area of ​​the two second p-type impurity regions 22p.

[0074] In capacitor cell 82, the first p-type impurity region 21p, which forms a pn junction together with the n-type well region 11n, is divided into multiple parts by the above structure. Therefore, the length of each first p-type impurity region 21p in the X-axis direction can be shortened. Furthermore, in capacitor cell 82, the second n-type impurity region 22n, which forms a pn junction together with the p-type well region 11p, is divided into multiple parts by the above structure. Therefore, the length of each second n-type impurity region 22n in the X-axis direction can be shortened. As a result, as... Figure 7 As shown, this shortens the conductive path within the n-type well region 11n between the center of the first p-type impurity region 21p and the first n-type impurity region 21n. Furthermore, as... Figure 8 As shown, the conductive path within the p-type well region 11p between the center of the second n-type impurity region 22n and the second p-type impurity region 22p can be shortened. Since a longer conductive path within the well leads to an increase in resistance, shortening the conductive path within the well can reduce the series resistance component in the decoupling capacitor element 102. The lengths of each first p-type impurity region 21p and each second n-type impurity region 22n in the X-axis direction are, for example, shorter than the length of the capacitor unit 82 in the Y-axis direction.

[0075] [Modification Example 3] Next, the decoupling capacitor element involved in the modified example 3 of the embodiment will be described. Figure 9This is a plan view showing an example of the decoupling capacitor element involved in this variation. Figure 9 A plan view of the decoupling capacitor element 103 is shown when viewed from the front side in the Z-axis direction.

[0076] like Figure 9 As shown, the decoupling capacitor element 103 involved in this modified example is composed of a capacitor unit 83. The main difference between the capacitor unit 83 and the capacitor unit 81 described above is that the number of the first n-type impurity region 21n, the first p-type impurity region 21p, the second n-type impurity region 22n, and the second p-type impurity region 22p is one each.

[0077] exist Figure 9 In the example shown, the length of capacitor cell 83 in the X-axis direction is shorter than its length in the Y-axis direction. Capacitor cell 83 includes a first n-type impurity region 21n, a first p-type impurity region 21p, a second n-type impurity region 22n, and a second p-type impurity region 22p. In the plan view, the first n-type impurity region 21n and the first p-type impurity region 21p are arranged along the X-axis direction. Furthermore, in the plan view, the second n-type impurity region 22n and the second p-type impurity region 22p are arranged along the X-axis direction.

[0078] In capacitor cell 83, since there is only one each of the first n-type impurity region 21n, the first p-type impurity region 21p, the second n-type impurity region 22n, and the second p-type impurity region 22p, the area of ​​the insulating regions 50 existing between the first n-type impurity region 21n and the first p-type impurity region 21p, and between the second n-type impurity region 22n and the second p-type impurity region 22p, can be reduced. Therefore, even though capacitor cell 83 is relatively short in the X-axis direction, the area utilization efficiency of capacitor cell 83 can be improved.

[0079] exist Figure 9 In the example shown, in the plan view, the area of ​​a first p-type impurity region 21p is larger than the area of ​​a first n-type impurity region 21n. Furthermore, in the plan view, the area of ​​a second n-type impurity region 22n is larger than the area of ​​a second p-type impurity region 22p.

[0080] [Variation Example 4] Next, the decoupling capacitor element involved in the modified example 4 of the embodiment will be described. Figure 10 This is a plan view showing an example of the decoupling capacitor element involved in this variation. Figure 10 A plan view of the decoupling capacitor element 104 is shown when viewed from the front side in the Z-axis direction.

[0081] like Figure 10 As shown, the decoupling capacitor element 104 involved in this modified example differs from the decoupling capacitor element 103 described above in that it is composed of multiple capacitor units 83.

[0082] Multiple capacitor cells 83 are arranged along the X-axis and configured adjacent to each other. Thus, the diodes in adjacent capacitor cells 83 are connected in parallel, thereby increasing the capacitance of the decoupling capacitor element 104.

[0083] Furthermore, in the decoupling capacitor element 104, each of the plurality of capacitor cells 83 includes both a first n-type impurity region 21n and a first p-type impurity region 21p, but is not limited thereto. As long as both the first n-type impurity region 21n and the first p-type impurity region 21p are formed in the entirety of the plurality of capacitor cells 83, at least one of the plurality of capacitor cells 83 may also include only one of the first n-type impurity region 21n and the first p-type impurity region 21p. Similarly, as long as both the second n-type impurity region 22n and the second p-type impurity region 22p are formed in the entirety of the plurality of capacitor cells 83, at least one of the plurality of capacitor cells 83 may also include only one of the second n-type impurity region 22n and the second p-type impurity region 22p. For example, capacitor cells including only the first n-type impurity region 21n and the second n-type impurity region 22n, and capacitor cells including only the first p-type impurity region 21p and the second p-type impurity region 22p, may be arranged alternately along the X-axis direction.

[0084] Alternatively, instead of capacitor unit 83, capacitor units involved in embodiments or variations other than embodiment 4 can be arranged adjacent to each other.

[0085] [Variation Example 5] Next, the decoupling capacitor element involved in the modified example 5 of the embodiment will be described. Figure 11 This is a plan view showing an example of the decoupling capacitor element involved in this variation. Figure 11 A plan view of the decoupling capacitor element 105 is shown when viewed from the front side in the Z-axis direction.

[0086] like Figure 11 As shown, the decoupling capacitor element 105 involved in this modified example is composed of a capacitor unit 85. The main difference between the capacitor unit 85 and the capacitor unit 81 described above is that, in the plan view, the first n-type impurity region 21n, the first p-type impurity region 21p, the second n-type impurity region 22n, and the second p-type impurity region 22p are arranged along the Y-axis direction.

[0087] The capacitor cell 85 includes a first n-type impurity region 21n, a first p-type impurity region 21p, a second n-type impurity region 22n, and a second p-type impurity region 22p. In a plan view, the first n-type impurity region 21n and the first p-type impurity region 21p are arranged along the Y-axis. Furthermore, in a plan view, the second n-type impurity region 22n and the second p-type impurity region 22p are arranged along the Y-axis.

[0088] In a plan view, capacitor cell 85 includes a dummy gate electrode 51 extending along the X-axis and a dummy gate electrode 51 extending along the Y-axis.

[0089] exist Figure 11 In the example shown, the first n-type impurity region 21n, the first p-type impurity region 21p, the second n-type impurity region 22n, and the second p-type impurity region 22p each have the same length in the X-axis direction. Furthermore, the positions of the first n-type impurity region 21n, the first p-type impurity region 21p, the second n-type impurity region 22n, and the second p-type impurity region 22p are aligned in the X-axis direction.

[0090] In capacitor cell 85, the orientation of the first n-type impurity region 21n and the first p-type impurity region 21p, and the orientation of the second n-type impurity region 22n and the second p-type impurity region 22p, are along the Y-axis. Therefore, the lengths of the first n-type impurity region 21n, the first p-type impurity region 21p, the second n-type impurity region 22n, and the second p-type impurity region 22p in the X-axis direction can be increased. Furthermore, even if the lengths of the first n-type impurity region 21n, the first p-type impurity region 21p, the second n-type impurity region 22n, and the second p-type impurity region 22p in the X-axis direction increase, the conductive path within the n-type well region 11n between the center of the first p-type impurity region 21p and the first n-type impurity region 21n, and the conductive path within the p-type well region 11p between the center of the second n-type impurity region 22n and the second p-type impurity region 22p will not increase. Therefore, without increasing the series resistance component in the decoupling capacitor element 105, the lengths of the first n-type impurity region 21n, the first p-type impurity region 21p, the second n-type impurity region 22n, and the second p-type impurity region 22p in the X-axis direction can be increased, thereby increasing the capacitance value.

[0091] exist Figure 11 In the example shown, in the plan view, the area of ​​a first p-type impurity region 21p is larger than the area of ​​a first n-type impurity region 21n. Furthermore, in the plan view, the area of ​​a second n-type impurity region 22n is larger than the area of ​​a second p-type impurity region 22p. Additionally, in the plan view, the area of ​​a first p-type impurity region 21p may also be the same as the area of ​​a first n-type impurity region 21n. Furthermore, in the plan view, the area of ​​a second n-type impurity region 22n may also be the same as the area of ​​a second p-type impurity region 22p.

[0092] In capacitor cell 85, the first n-type impurity region 21n, the first p-type impurity region 21p, the second n-type impurity region 22n, and the second p-type impurity region 22p are each elongated shapes with a length in the X-axis direction longer than their length in the Y-axis direction. Furthermore, as described above, the first n-type impurity region 21n, the first p-type impurity region 21p, the second n-type impurity region 22n, and the second p-type impurity region 22p are arranged along the Y-axis direction. Therefore, it is possible to easily design a planar layout of capacitor cell 85 that varies the number of first wirings 41 and second wirings 42. For example, the number of first wirings 41 and second wirings 42 can be one or more. The number of first wirings 41 and second wirings 42 can, for example, be as follows: Figure 12 Make the changes as shown. Figure 12 This is a plan view showing another example of the decoupling capacitor element involved in this variation. Figure 12 A plan view of the decoupling capacitor element 105A is shown when viewed from the front side along the Z-axis.

[0093] like Figure 12 As shown, the decoupling capacitor element 105A is composed of a capacitor unit 85A. The capacitor unit 85A includes a plurality of first wirings 41 and a plurality of second wirings 42. In the capacitor unit 85A, the number of first wirings 41 is greater than the number of first n-type impurity regions 21n and second n-type impurity regions 22n. Furthermore, the number of second wirings 42 is greater than the number of first p-type impurity regions 21p and second p-type impurity regions 22p. In the capacitor unit 85A, the first wirings 41 and second wirings 42 are arranged alternately along the X-axis direction. This increases the inter-wiring capacitance between the first wirings 41 and the second wirings 42. Figure 12 In the example shown, the number of first wiring 41 and the number of second wiring 42 are both 4, but there are no special restrictions. For example, the number of first wiring 41 and the number of second wiring 42 can be more than 2 and less than 5.

[0094] [Variation Example 6] Next, the decoupling capacitor element involved in the modified example 6 of the embodiment will be described. Figure 13 This is a plan view showing an example of the decoupling capacitor element involved in this variation. Figure 13 A plan view of the decoupling capacitor element 106 is shown when viewed from the front side in the Z-axis direction.

[0095] like Figure 13 As shown, the decoupling capacitor element 106 involved in this variation is composed of a capacitor unit 86. The main difference between capacitor unit 86 and capacitor unit 85 described above is that, in the plan view, the power supply wiring 31 overlaps with the first n-type impurity region 21n, and the ground wiring 32 overlaps with the second p-type impurity region 22p.

[0096] In capacitor cell 86, power supply wiring 31 is connected to the first n-type impurity region 21n via a plug (not shown) without passing through the first wiring 41. Furthermore, ground wiring 32 is connected to the second p-type impurity region 22p via a plug (not shown) without passing through the second wiring 42.

[0097] exist Figure 13 In the example shown, in the plan view, the power supply wiring 31 completely overlaps with the first n-type impurity region 21n. The power supply wiring 31 may also overlap with a portion of the first n-type impurity region 21n. Furthermore, in the plan view, the ground wiring 32 completely overlaps with the second p-type impurity region 22p. The ground wiring 32 may also overlap with a portion of the second p-type impurity region 22p.

[0098] In capacitor cell 86, since power supply wiring 31 overlaps with the first n-type impurity region 21n and ground wiring 32 overlaps with the second p-type impurity region 22p, the area of ​​capacitor cell 86 in the plan view can be utilized efficiently, thereby improving the capacitance efficiency relative to the area of ​​capacitor cell 86.

[0099] [Modification Example 7] Next, the decoupling capacitor element involved in the modified example 7 of the embodiment will be described. Figure 14 This is a plan view showing an example of the decoupling capacitor element involved in this variation. Figure 14 A plan view of the decoupling capacitor element 107 is shown when viewed from the front side in the Z-axis direction.

[0100] like Figure 14 As shown, the decoupling capacitor element 107 involved in this modification is composed of a capacitor unit 87. The capacitor unit 87 has a structure that combines the planar arrangement of the first n-type impurity region 21n and the first p-type impurity region 21p in the capacitor unit 81 with the planar arrangement of the second n-type impurity region 22n and the second p-type impurity region 22p in the capacitor unit 85. Therefore, in the capacitor unit 87, the directions of the impurity regions arranged in the n-type well region 11n and the directions of the impurity regions arranged in the p-type well region 11p are the X-axis direction and the Y-axis direction, respectively, and are different from each other.

[0101] Furthermore, the direction of the impurity region arrangement in the n-type well region 11n and the direction of the impurity region arrangement in the p-type well region 11p can also be the Y-axis direction and the X-axis direction, respectively. Figure 15 This is a plan view showing another example of the decoupling capacitor element involved in this variation. Figure 15 A plan view of the decoupling capacitor element 107A is shown when viewed from the front side along the Z-axis.

[0102] like Figure 15As shown, the decoupling capacitor element 107A is composed of a capacitor unit 87A. The capacitor unit 87A has a structure that combines the planar arrangement of the first n-type impurity region 21n and the first p-type impurity region 21p in the capacitor unit 85 with the planar arrangement of the second n-type impurity region 22n and the second p-type impurity region 22p in the capacitor unit 81. Therefore, in the capacitor unit 87A, the direction of the impurity region arrangement in the n-type well region 11n and the direction of the impurity region arrangement in the p-type well region 11p are the Y-axis direction and the X-axis direction, respectively.

[0103] [Variation Example 8] Next, the decoupling capacitor element involved in the modified example 8 of the embodiment will be described. Figure 16 This is a plan view showing an example of the decoupling capacitor element involved in this variation. Figure 16 A plan view of the decoupling capacitor element 108 is shown when viewed from the front side in the Z-axis direction.

[0104] like Figure 16 As shown, the decoupling capacitor element 108 has a structure in which a plurality of the aforementioned capacitor cells 85 are arranged along the X-axis direction, and the first n-type impurity region 21n, the first p-type impurity region 21p, the second n-type impurity region 22n, and the second p-type impurity region 22p of adjacent capacitor cells 85 are respectively connected by removing the dummy gate electrode 51. Specifically, the decoupling capacitor element 108 includes capacitor cells 88A and 88B arranged along the X-axis direction, wherein capacitor cell 88A is the terminal cell located at the end of the X-axis direction, and capacitor cell 88B is the adjacent cell located outside the end of the X-axis direction.

[0105] Capacitor cell 88A is a cell adjacent to capacitor cell 88B on one side of the X-axis direction. On the other side of capacitor cell 88A in the X-axis direction, for example, another standard cell is arranged adjacent to it. Figure 16 The image shows capacitor cell 88A adjacent to capacitor cell 88B on the positive side in the X-axis direction. Although Figure 16 Not shown in the diagram, but a capacitor unit 88A is disposed at the end of the decoupling capacitor element 108 on the negative side of the X-axis direction, and its layout is similar to... Figure 16 The layout shown is reversed in the X-axis direction. Capacitor unit 88B is a unit that is not disposed at the X-axis end of the decoupling capacitor element 108. Furthermore, the decoupling capacitor element 108 may not include capacitor unit 88B, for example, it may be composed of capacitor unit 88A located at the positive end in the X-axis direction and capacitor unit 88A located at the negative end in the X-axis direction.

[0106] In addition, Figure 16In the example shown, two capacitor cells 88A are adjacent to each other in the Y-axis direction and share a ground wiring 32. Similarly, two capacitor cells 88B are adjacent to each other in the Y-axis direction and share a ground wiring 32. Furthermore, in the decoupling capacitor element 108, the number of capacitor cells 88A and 88B arranged along the Y-axis direction can be one.

[0107] In capacitor cells 88A and 88B, the first n-type impurity region 21n, the first p-type impurity region 21p, the second n-type impurity region 22n, and the second p-type impurity region 22p are respectively connected to the first n-type impurity region 21n, the first p-type impurity region 21p, the second n-type impurity region 22n, and the second p-type impurity region 22p of the capacitor cells 88A or 88B adjacent to each other in the X-axis direction. Therefore, the first n-type impurity region 21n, the first p-type impurity region 21p, the second n-type impurity region 22n, and the second p-type impurity region 22p can be arranged at the boundaries of adjacent capacitor cells. Thus, the capacitance efficiency relative to the area of ​​the decoupling capacitor element 108 can be improved.

[0108] In addition, Figure 16 In the example shown, the decoupling capacitor element 108 has a structure in which a plurality of the above-described capacitor cells 85 are arranged along the X-axis direction, and the first n-type impurity region 21n, the first p-type impurity region 21p, the second n-type impurity region 22n, and the second p-type impurity region 22p of adjacent capacitor cells 85 are respectively connected, but it is not limited thereto. The above structure can also be applied to capacitor cells 85A, 86, 87, or 87A instead of capacitor cells 85.

[0109] (other) The decoupling capacitor element involved in one or more embodiments of this disclosure has been described above based on implementation methods and variations, but this disclosure is not limited to the embodiments. Various modifications to the embodiments that can be conceived by those skilled in the art without departing from the spirit of this disclosure, as well as forms that combine the constituent elements of different embodiments and variations, may also be included within the scope of one or more embodiments of this disclosure.

[0110] For example, in the above embodiments and variations, the capacitor unit is a standard unit, but it is not limited to this. The capacitor unit may also be a unit of a different size than the standard unit.

[0111] Furthermore, the planar layout of the first n-type impurity region 21n, the first p-type impurity region 21p, the second n-type impurity region 22n, and the second p-type impurity region 22p described in the above embodiments and variations is only one example and is not particularly limited. It can be arbitrarily changed according to the structure of wiring, etc.

[0112] Furthermore, in the above embodiments and modifications, the power supply wiring 31, ground wiring 32, first wiring 41, and second wiring 42 are arranged in the same wiring layer, but this is not a limitation. At least two of the power supply wiring 31, ground wiring 32, first wiring 41, and second wiring 42 may also be arranged in different wiring layers. Furthermore, the power supply wiring 31, ground wiring 32, first wiring 41, and second wiring 42 may also be formed across multiple wiring layers.

[0113] The following are examples of decoupling capacitor elements according to the present disclosure based on the embodiments described above. The decoupling capacitor elements according to the present disclosure are not limited to the examples shown below.

[0114] For example, the decoupling capacitor element according to the first aspect of this disclosure includes: an n-type well region and a p-type well region formed on a semiconductor substrate; a power supply wiring and a ground wiring located above the semiconductor substrate and extending along a first direction orthogonal to the thickness direction of the semiconductor substrate, and in a plan view of the semiconductor substrate, the power supply wiring and the ground wiring are arranged along a second direction orthogonal to the first direction and the thickness direction of the semiconductor substrate; a first n-type impurity region and a first p-type impurity region formed in the n-type well region; and a second n-type impurity region and a second p-type impurity region formed in the p-type well region, wherein in the plan view, the n-type well region and the p-type well region are adjacent to each other in the region between the power supply wiring and the ground wiring, the power supply wiring is electrically connected to the first n-type impurity region and the second n-type impurity region, and the ground wiring is electrically connected to the first p-type impurity region and the second p-type impurity region.

[0115] Therefore, the n-type well region and the first p-type impurity region constitute a diode, and the p-type well region and the second n-type impurity region constitute a diode. Furthermore, a reverse bias voltage is applied to these diodes through power supply and ground wiring. Therefore, as decoupling capacitors, junction capacitances are generated at the pn junction of the n-type well region and the first p-type impurity region, and at the pn junction of the p-type well region and the second n-type impurity region. In the decoupling capacitor element according to this aspect, since a gate insulating film that would cause a decrease in breakdown voltage is not used as a capacitor, damage caused by static electricity, etc., is suppressed. Furthermore, the leakage current in the reverse bias direction is very small in the pn junction, so the leakage current can be reduced in the decoupling capacitor element according to this method. Therefore, a highly reliable decoupling capacitor element is realized.

[0116] Furthermore, the first n-type impurity region and the second p-type impurity region serve as substrate contact regions for providing voltage to the n-type well region and the p-type well region, respectively. Therefore, for example, the layout area efficiency of semiconductor devices with decoupling capacitor elements can be improved without the need for additional cells for substrate contacts.

[0117] Furthermore, for example, the decoupling capacitor element according to the second aspect of this disclosure is based on the decoupling capacitor element according to the first aspect, wherein, in the plan view, the first n-type impurity region and the second n-type impurity region are arranged along the second direction, and the first p-type impurity region and the second p-type impurity region are arranged along the second direction.

[0118] This simplifies the electrical connection path between the power supply wiring and the first n-type impurity region and the second n-type impurity region, as well as the electrical connection path between the ground wiring and the first p-type impurity region and the second p-type impurity region.

[0119] Furthermore, for example, the decoupling capacitor element according to the third aspect of this disclosure is based on the decoupling capacitor element according to the second aspect. In the plan view, the n-type well region and the p-type well region are arranged along the second direction, the first n-type impurity region and the first p-type impurity region are arranged along the first direction, the second n-type impurity region and the second p-type impurity region are arranged along the first direction, the length of the first n-type impurity region in the first direction is the same as the length of the second n-type impurity region in the first direction, and the length of the first p-type impurity region in the first direction is the same as the length of the second p-type impurity region in the first direction.

[0120] Therefore, it becomes easy to widen the wiring that serves as the electrical connection path between the power supply wiring and the first n-type impurity region and the second n-type impurity region, as well as the electrical connection path between the ground wiring and the first p-type impurity region and the second p-type impurity region.

[0121] Furthermore, for example, the decoupling capacitor element according to the fourth aspect of this disclosure is based on the decoupling capacitor element according to the first or second aspect, wherein, in the plan view, the n-type well region and the p-type well region are arranged along the second direction, and at least one of the directions in which the first n-type impurity region and the first p-type impurity region are arranged, and the directions in which the second n-type impurity region and the second p-type impurity region are arranged, is the second direction.

[0122] Therefore, the lengths of the first n-type impurity region, the first p-type impurity region, the second n-type impurity region, and the second p-type impurity region in the first direction can be increased. Furthermore, even if the lengths of the first n-type impurity region, the first p-type impurity region, the second n-type impurity region, and the second p-type impurity region in the first direction increase, the conductive paths within the n-type well region between the center of the first p-type impurity region and the first n-type impurity region, and the conductive paths within the p-type well region between the center of the second n-type impurity region and the second p-type impurity region, will not increase. Therefore, the lengths of the first n-type impurity region, the first p-type impurity region, the second n-type impurity region, and the second p-type impurity region in the first direction can be increased without increasing the series resistance component in the decoupling capacitor element, thereby increasing the capacitance value.

[0123] Furthermore, for example, the decoupling capacitor element involved in the fifth aspect of this disclosure is based on the decoupling capacitor element involved in any one of the first, second, and fourth aspects, wherein there is at least one first n-type impurity region, a first p-type impurity region, a second n-type impurity region, and a second p-type impurity region, and in the plan view, the total area of ​​at least one first p-type impurity region is greater than the total area of ​​at least one first n-type impurity region, and the total area of ​​at least one second n-type impurity region is greater than the total area of ​​at least one second p-type impurity region.

[0124] This increases the pn junction between the first p-type impurity region and the n-type well region, as well as the pn junction between the second n-type impurity region and the p-type well region, thereby increasing the capacitance value of the decoupling capacitor element.

[0125] Furthermore, for example, the decoupling capacitor element according to the sixth aspect of this disclosure is based on the decoupling capacitor element according to the fifth aspect, wherein there are multiple first p-type impurity regions and multiple second n-type impurity regions, and in the plan view, the first n-type impurity regions and the first p-type impurity regions are arranged alternately, and the second n-type impurity regions and the second p-type impurity regions are arranged alternately.

[0126] Therefore, the first p-type impurity region, which forms a pn junction together with the n-type well region, is divided into multiple segments. This shortens the length of each first p-type impurity region in the first direction. Furthermore, the second n-type impurity region, which forms a pn junction together with the p-type well region, is also divided into multiple segments. This shortens the length of each second n-type impurity region in the first direction. Consequently, the conductive paths within the n-type well region between the center of the first p-type impurity region and the first n-type impurity region, as well as the conductive paths within the p-type well region between the center of the second n-type impurity region and the second p-type impurity region, are shortened. As a result, the series resistance component in the decoupling capacitor element is reduced.

[0127] Furthermore, for example, the decoupling capacitor element involved in the seventh aspect of this disclosure is based on the decoupling capacitor element involved in any one of the first to sixth aspects, the decoupling capacitor element comprising: a first wiring electrically connecting the power supply wiring to the second n-type impurity region; and a second wiring electrically connecting the ground wiring to the first p-type impurity region, the first wiring and the second wiring being arranged along the first direction.

[0128] This creates an inter-wire capacitance between the first and second wiring, thereby increasing the capacitance value of the decoupling capacitor element.

[0129] Furthermore, for example, the decoupling capacitor element involved in the eighth aspect of this disclosure is based on the decoupling capacitor element involved in the seventh aspect, wherein the decoupling capacitor element is disposed in a semiconductor device, and regarding the spacing between the first wiring and the second wiring, (i) in the case where an inter-wiring capacitor element is present in the semiconductor device, the spacing between the first wiring and the second wiring is not narrower than the wiring spacing of the inter-wiring capacitor element, and (ii) in the case where an inter-wiring capacitor element is not present in the semiconductor device, the spacing between the first wiring and the second wiring is the minimum width of the wiring spacing design rule of the semiconductor device.

[0130] This increases the inter-wire capacitance between the first and second wiring.

[0131] Furthermore, for example, the decoupling capacitor element involved in the ninth aspect of this disclosure is based on the decoupling capacitor element involved in the seventh or eighth aspect, wherein at least one of the first wiring and the second wiring is multiple in the decoupling capacitor element, and the first wiring and the second wiring are alternately arranged along the first direction.

[0132] This increases the amount of inter-wire capacitance between the first and second wires formed in the decoupling capacitor element.

[0133] Furthermore, for example, the decoupling capacitor element according to the 10th aspect of this disclosure is based on the decoupling capacitor element according to any one of the 1st to 9th aspects, the decoupling capacitor element comprising: an insulating region formed on the semiconductor substrate, and a dummy gate electrode disposed on the insulating region, the insulating region electrically isolating the first n-type impurity region, the first p-type impurity region, the second n-type impurity region, and the second p-type impurity region from each other.

[0134] This allows for an increase in the electrode area on the semiconductor substrate, for example, improving the accuracy of the gate length and gate width of the gate electrode of the transistor formed around the decoupling capacitor element.

[0135] Furthermore, for example, the decoupling capacitor element involved in the 11th aspect of this disclosure is based on the decoupling capacitor element involved in any of the 1st to 10th aspects, wherein, in the plan view, the power supply wiring overlaps with the first n-type impurity region and the ground wiring overlaps with the second p-type impurity region.

[0136] Therefore, the area of ​​the decoupling capacitor element in the planar diagram can be used efficiently, thereby improving the capacitance efficiency relative to the area of ​​the decoupling capacitor element.

[0137] Industrial availability The decoupling capacitor element disclosed herein can be used to reduce noise in semiconductor devices and the like.

[0138] Explanation of reference numerals in the attached figures 10: Semiconductor substrate 11n: n-type well region 11p: p-type well region 15: Insulation layer 21n: First n-type impurity region 21p: First p-type impurity region 22n: Second n-type impurity region 22p: Second p-type impurity region 31: Power wiring 32: Grounding wiring 41: First wiring 42: Second wiring 45: Plug 50: Insulation area 51: Pseudo-gate electrode 80, 81, 82, 83, 85, 85A, 86, 87, 87A, 88A, 88B: Capacitor Units 100, 101, 102, 103, 104, 105, 105A, 106, 107, 107A, 108: Decoupling capacitors.

Claims

1. A decoupling capacitor element, The decoupling capacitor element includes: n-type well regions and p-type well regions are formed on the semiconductor substrate; Power and ground wirings are located above the semiconductor substrate and extend along a first direction orthogonal to the thickness direction of the semiconductor substrate. In a plan view of the semiconductor substrate, the power and ground wirings are arranged along a second direction orthogonal to the first direction and the thickness direction of the semiconductor substrate. A first n-type impurity region and a first p-type impurity region are formed in the n-type well region; as well as The second n-type impurity region and the second p-type impurity region are formed in the p-type well region. In the plan view, the n-type well region and the p-type well region are positioned adjacent to each other in the region between the power supply wiring and the ground wiring. The power supply wiring is electrically connected to the first n-type impurity region and the second n-type impurity region. The grounding wiring is electrically connected to the first p-type impurity region and the second p-type impurity region.

2. The decoupling capacitor element as described in claim 1, In the plan view, The first n-type impurity region and the second n-type impurity region are arranged along the second direction. The first p-type impurity region and the second p-type impurity region are arranged along the second direction.

3. The decoupling capacitor element as described in claim 2, In the plan view, The n-type well region and the p-type well region are arranged along the second direction. The first n-type impurity region and the first p-type impurity region are arranged along the first direction. The second n-type impurity region and the second p-type impurity region are arranged along the first direction. The length of the first n-type impurity region in the first direction is the same as the length of the second n-type impurity region in the first direction. The length of the first p-type impurity region in the first direction is the same as the length of the second p-type impurity region in the first direction.

4. The decoupling capacitor element as described in claim 1 or 2, In the plan view, The n-type well region and the p-type well region are arranged along the second direction. The direction in which the first n-type impurity region and the first p-type impurity region are arranged, and the direction in which the second n-type impurity region and the second p-type impurity region are arranged, are at least one of the second direction.

5. The decoupling capacitor element as described in any one of claims 1, 2, and 4, In the decoupling capacitor element, there is at least one of each of the first n-type impurity region, the first p-type impurity region, the second n-type impurity region, and the second p-type impurity region. In the plan view, The total area of ​​at least one of the first p-type impurity regions is greater than the total area of ​​at least one of the first n-type impurity regions. The total area of ​​at least one of the second n-type impurity regions is greater than the total area of ​​at least one of the second p-type impurity regions.

6. The decoupling capacitor element as described in claim 5, In the decoupling capacitor element, there are multiple first p-type impurity regions and multiple second n-type impurity regions. In the plan view, the first n-type impurity region and the first p-type impurity region are arranged alternately, and the second n-type impurity region and the second p-type impurity region are arranged alternately.

7. The decoupling capacitor element as described in any one of claims 1 to 6, The decoupling capacitor element includes: The first wiring electrically connects the power supply wiring to the second n-type impurity region; as well as The second wiring is electrically connected to the grounding wiring and the first p-type impurity region. The first wiring and the second wiring are arranged along the first direction.

8. The decoupling capacitor element as described in claim 7, The decoupling capacitor element is disposed in the semiconductor device. Regarding the spacing between the first wiring and the second wiring, (i) in the case where there is an inter-wiring capacitor element in the semiconductor device, the spacing between the first wiring and the second wiring is not narrower than the wiring spacing of the inter-wiring capacitor element, and (ii) in the case where there is no inter-wiring capacitor element in the semiconductor device, the spacing between the first wiring and the second wiring is the minimum width of the wiring spacing design rule of the semiconductor device.

9. The decoupling capacitor element as described in claim 7 or 8, At least one of the first wiring and the second wiring is multiple in the decoupling capacitor element. The first wiring and the second wiring are arranged alternately along the first direction.

10. The decoupling capacitor element as described in any one of claims 1 to 9, The decoupling capacitor element includes: An insulating region is formed on the semiconductor substrate, and a dummy gate electrode is disposed on the insulating region. The insulating region electrically isolates the first n-type impurity region, the first p-type impurity region, the second n-type impurity region, and the second p-type impurity region from each other.

11. The decoupling capacitor element as described in any one of claims 1 to 10, In the plan view, The power supply wiring overlaps with the first n-type impurity region. The grounding wiring overlaps with the second p-type impurity region.

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