Silicon carbide semiconductor device

Abstract

A silicon carbide semiconductor device has a silicon carbide substrate having a first main surface and a second main surface opposite thereto, and has a drift region having a first conductivity type, a body region provided over the drift region and having a second conductivity type, and a source region provided over the body region and having the first conductivity type, the first main surface being provided with a gate trench defined by a side surface penetrating through the source region and the body region and reaching the drift region and a bottom surface connected to the side surface, the gate trench extending along a first axis parallel to the first main surface, the substrate further having a contact region having the second conductivity type, interposed between the side surface and the source region and in contact with the body region, a first electric field relaxation region having the second conductivity type, provided between the bottom surface and the second main surface and overlapping the gate trench in a plan view perpendicular to the first main surface, and a second electric field relaxation region having the second conductivity type, provided between the body region and the second main surface and overlapping the contact region in the plan view perpendicular to the first main surface, the first and second electric field relaxation regions being arranged side by side along the first axis.

Description

Technical Field

[0001] This invention relates to a silicon carbide semiconductor device.

[0002] This application claims priority based on Japanese Patent Application No. 2024-035031, filed on March 7, 2024, and all contents set forth in the aforementioned Japanese Patent Application are incorporated herein by reference. Background Technology

[0003] As one type of silicon carbide semiconductor device, a trench gate MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is disclosed. The trench gate MOSFET has a gate trench formed in a silicon carbide substrate, and an electric field relief region arranged in a stripe pattern to intersect with the gate trench.

[0004] Existing technical documents Patent documents Patent document 1: Japanese Patent Application Publication No. 2012-169386. Summary of the Invention

[0005] The silicon carbide semiconductor device of the present invention includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface. The silicon carbide substrate has: a drift region having a first conductivity type; a body region disposed on the drift region and having a second conductivity type; and a source region disposed on the body region and having the first conductivity type. The first main surface has a gate trench defined by a side surface penetrating the source region and the body region and reaching the drift region, and a bottom surface connected to the side surface. The gate trench extends along a first axis parallel to the first main surface. The silicon substrate further comprises: a contact region sandwiching the source region between itself and the side surface, contacting the body region and having the second conductivity type; a first electric field mitigation region overlapping the gate trench in a top view perpendicular to the first main surface, disposed between the bottom surface and the second main surface and having the second conductivity type; and a second electric field mitigation region overlapping the contact region in a top view perpendicular to the first main surface, disposed between the body region and the second main surface and having the second conductivity type, wherein the first electric field mitigation region and the second electric field mitigation region are arranged side by side along the first axis. Attached Figure Description

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Figure 1

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Figure 2

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Figure 3

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Figure 4

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Figure 5

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Figure 6

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Figure 7

[0013] [The problem to be solved by this invention] Silicon carbide semiconductor devices have an active region and a termination region surrounding the active region. The area of ​​the termination region is smaller than that of the active region. In silicon carbide semiconductor devices, by designing the breakdown voltage of the active region to be lower than that of the termination region, avalanche current can be uniformly distributed in the relatively large active region, thereby improving avalanche tolerance.

[0014] In conventional silicon carbide semiconductor devices, the electric field strength applied to the gate insulating film is reduced by decreasing the spacing between adjacent electric field mitigation regions. In this case, the voltage difference between the active region and the terminal region decreases, and avalanche current tends to flow to the relatively smaller terminal region. Therefore, avalanche tolerance is reduced.

[0015] The purpose of this invention is to provide a silicon carbide semiconductor device that can reduce the electric field strength applied to the gate insulating film while maintaining avalanche tolerance.

[0016] [Effects of the Invention] According to the present invention, a silicon carbide semiconductor device can be provided that can reduce the electric field strength applied to the gate insulating film while maintaining avalanche tolerance. Detailed Implementation

[0017] The specific implementation method will be described below.

[0018] [Description of embodiments of the present invention] First, embodiments of the present invention will be listed and described. In the following description, the same or corresponding elements will be given the same reference numerals, and their identical descriptions will not be repeated. In the following description, an XYZ orthogonal coordinate system is used, but this coordinate system is provided for ease of explanation and does not limit the orientation of the semiconductor device. The XY top view is referred to as the top view; from any point, the +Z direction is sometimes referred to as above, upper side, or up, and the -Z direction is sometimes referred to as below, lower side, or down.

[0019] [1] One aspect of the present invention relates to a silicon carbide semiconductor device comprising a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, the silicon carbide substrate having: a drift region having a first conductivity type; a body region disposed on the drift region and having a second conductivity type; and a source region disposed on the body region and having the first conductivity type, the first main surface having a gate trench defined by a side surface penetrating the source region and the body region and reaching the drift region and a bottom surface connected to the side surface, the gate trench extending along a first axis parallel to the first main surface, the... The silicon carbide substrate further comprises: a contact region sandwiching the source region between itself and the side surface, contacting the body region, and having the second conductivity type; a first electric field mitigation region overlapping the gate trench in a top view perpendicular to the first main surface, disposed between the bottom surface and the second main surface, and having the second conductivity type; and a second electric field mitigation region overlapping the contact region in a top view perpendicular to the first main surface, disposed between the body region and the second main surface, and having the second conductivity type, wherein the first electric field mitigation region and the second electric field mitigation region are arranged side by side along the first axis. In this configuration, the electric field strength applied to the gate insulating film can be reduced while maintaining avalanche tolerance.

[0020] [2] Another aspect of the present invention relates to a silicon carbide semiconductor device comprising a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, the silicon carbide substrate comprising: a drift region having a first conductivity type; a body region disposed on the drift region and having a second conductivity type; and a source region disposed on the body region and having the first conductivity type, the first main surface having a gate trench defined by a side surface penetrating the source region and the body region and reaching the drift region and a bottom surface connected to the side surface, the gate trench extending along a first axis parallel to the first main surface, the silicon carbide substrate further comprising: The device comprises: a contact region sandwiching the source region between the side surface and the body region, contacting the body region and having the second conductivity type; a first electric field mitigation region having a portion overlapping the bottom surface of the gate trench in a top view perpendicular to the first main surface, disposed between the bottom surface and the second main surface and having the second conductivity type; and a second electric field mitigation region having a portion overlapping the contact region in a top view perpendicular to the first main surface, disposed between the body region and the second main surface and having the second conductivity type, wherein the first electric field mitigation region and the second electric field mitigation region are arranged side by side along the first axis. In this configuration, the electric field strength applied to the gate insulating film can be reduced while maintaining avalanche tolerance.

[0021] [3] In [1] or [2], the first electric field relief region and the second electric field relief region can be arranged alternately and repeatedly along the first axis. In this case, the deviation between the area through which current flows and the area through which it does not flow during avalanche breakdown becomes smaller. Therefore, it is easier to homogenize the heat distribution during avalanche breakdown within the chip.

[0022] [4] In [1] to [3], the first electric field relief region may be connected to the second electric field relief region adjacent to the first axis. In this case, the feedback capacitance can be reduced, thereby shortening the switching time.

[0023] [5] In [4], the first electric field mitigation region has a first length along a second axis parallel to the first main surface and perpendicular to the first axis, and the second electric field mitigation region has a second length along the second axis, wherein the first length may be shorter than the second length. In this case, the avalanche current is more likely to flow directly below the first electric field mitigation region compared to the terminal region. Therefore, the avalanche tolerance is improved.

[0024] [6] In [5], the first length may be shorter than the third length along the first axis of the portion where the first electric field relief region connects to the second electric field relief region. In this case, the avalanche current flows more easily to the direct below the first electric field relief region compared to the terminal region. Therefore, the avalanche tolerance is improved.

[0025] [7] In [1] to [6], the concentration of the first type of impurity in the drift region can be reduced from the first main surface toward the second main surface. In this case, the withstand voltage can be increased while reducing the on-resistance.

[0026] [8] In [1] to [7], a connection region may be provided that electrically connects the body region to the first electric field relief region. In this case, the feedback capacitance can be reduced, thereby shortening the switching time.

[0027] [Details of the embodiments of the present invention] The embodiments of the present invention will be described in detail below, but the present invention is not limited thereto.

[0028] [First Implementation] The first embodiment relates to a so-called trench-gate MOSFET using silicon carbide (SiC). A trench-gate MOSFET is an example of a silicon carbide semiconductor device. Figure 1 This is a diagram showing the arrangement of the electric field mitigation region included in the silicon carbide semiconductor device according to the first embodiment. Figure 2 and Figure 3 This is a cross-sectional view showing a silicon carbide semiconductor device according to the first embodiment. Figure 2 Equivalent to along Figure 1 Cross-sectional view of line II-II. Figure 3 Equivalent to along Figure 1 Cross-sectional view of line III-III.

[0029] like Figures 1 to 3 As shown, the silicon carbide semiconductor device 100 according to the first embodiment includes a silicon carbide substrate 10, a gate insulating film 81, a gate electrode 82, an interlayer insulating film 83, a source electrode 60, a drain electrode 70, and a barrier metal film 84.

[0030] The silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The first main surface 1 and the second main surface 2 are parallel to the XY plane. The silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40 located on the silicon carbide single crystal substrate 50. The silicon carbide epitaxial layer 40 includes the first main surface 1, and the silicon carbide single crystal substrate 50 includes the second main surface 2. The silicon carbide single crystal substrate 50 and the silicon carbide epitaxial layer 40, for example, contain 4H polytype hexagonal silicon carbide. The silicon carbide single crystal substrate 50 contains, for example, n-type impurities such as nitrogen (N) and has an n-type conductivity type (first conductivity type).

[0031] The silicon carbide epitaxial layer 40 has a drift region 11, a bulk region 12, a source region 13, a current diffusion region 14, an electric field mitigation region 16, and a contact region 18.

[0032] Drift region 11 contains n-type impurities such as nitrogen or phosphorus (P) and has an n-type conductivity type. The effective concentration of n-type impurities in drift region 11 can be reduced from the first main surface 1 toward the second main surface 2. Drift region 11 is disposed on silicon carbide single crystal substrate 50. Drift region 11 has a first region 11A, a second region 11B, and a third region 11C. The first region 11A, the second region 11B, and the third region 11C will be described later.

[0033] The body region 12 contains p-type impurities such as aluminum (Al) and has a p-type conductivity type (second conductivity type). The body region 12 is disposed above the drift region 11.

[0034] Source region 13 contains n-type impurities such as nitrogen or phosphorus and has an n-type conductivity type. Source region 13 is disposed on top of body region 12. Source region 13 is separated from drift region 11 by body region 12. Source region 13 includes a first main surface 1.

[0035] The first main surface 1 has a plurality of gate trenches 5 defined by a side surface 3 and a bottom surface 4. Each gate trench 5 extends, for example, along the Y-axis. The Y-axis is an example of a first axis. The plurality of gate trenches 5 are arranged at a certain interval along the X-axis. The X-axis is an example of a second axis. The side surface 3 penetrates the source region 13, the body region 12, the current diffusion region 14, and a portion of the drift region 11, and reaches the drift region 11. The bottom surface 4 is connected to the side surface 3. The bottom surface 4 is located in the drift region 11. The bottom surface 4 is, for example, parallel to the first main surface 1 and the second main surface 2. The side surface 3 is inclined relative to the plane containing the bottom surface 4.

[0036] The current diffusion region 14 contains n-type impurities such as phosphorus and has an n-type conductivity type. The current diffusion region 14 is disposed above the drift region 11. The current diffusion region 14 is disposed between the drift region 11 and the body region 12. The current diffusion region 14 is in contact with the drift region 11 and the body region 12.

[0037] Contact region 18 contains p-type impurities such as aluminum and has p-type conductivity. Contact region 18 extends through source region 13 and body region 12 and contacts current diffusion region 14. Contact region 18 includes a first main surface 1. In a top view perpendicular to the first main surface 1, contact region 18 is located between adjacent gate trenches 5 along the X-axis.

[0038] The electric field mitigation region 16 contains p-type impurities such as aluminum and has a p-type conductivity type. The electric field mitigation region 16 has a first electric field mitigation region 16A and a second electric field mitigation region 16B.

[0039] The first electric field relief region 16A is located within the drift region 11. The first electric field relief region 16A is located directly below the gate trench 5. In a top view perpendicular to the first main surface 1, the first electric field relief region 16A is positioned overlapping with the gate trench 5. In a top view perpendicular to the first main surface 1, the first electric field relief region 16A may have a portion overlapping with the bottom surface 4 of the gate trench 5. In a top view perpendicular to the first main surface 1, the first electric field relief region 16A may have a portion overlapping with the side surface 3 of the gate trench 5. At the position overlapping with the gate trench 5, the first electric field relief region 16A and the drift region 11 may be alternately arranged along the Y-axis. At the position overlapping with the gate trench 5, the first electric field relief region 16A may be discontinuously arranged along the Y-axis. In this case, compared to the case where the first electric field relief region 16A is continuously arranged along the Y-axis, the withstand voltage of the active region decreases. Therefore, the difference between the withstand voltage of the active region and the withstand voltage of the terminal region increases, making it less likely for avalanche current to flow to the terminal region. The first electric field relief region 16A is located between the bottom surface 4 and the second main surface 2. In this case, the electric field strength applied to the gate insulating film 81 can be reduced. The upper end surface of the first electric field relief region 16A can be separated from the bottom surface 4. In this case, the on-resistance is easily reduced. The upper end surface of the first electric field relief region 16A can be in contact with the bottom surface 4.

[0040] The second electric field mitigation region 16B is located within the drift region 11. A portion of the second electric field mitigation region 16B may also be located within the current diffusion region 14. The second electric field mitigation region 16B is located directly below the contact region 18. In a top view perpendicular to the first main surface 1, the second electric field mitigation region 16B is located between adjacent gate trenches 5 along the X-axis. In a top view perpendicular to the first main surface 1, the second electric field mitigation region 16B is positioned overlapping with the contact region 18. In a top view perpendicular to the first main surface 1, the second electric field mitigation region 16B may have a portion overlapping with the contact region 18. In a top view perpendicular to the first main surface 1, the second electric field mitigation region 16B may have a portion overlapping with the source region 13. Between two adjacent gate trenches 5 along the X-axis, the second electric field mitigation region 16B and the drift region 11 may be alternately arranged along the Y-axis. Between two adjacent gate trenches 5 along the X-axis, the second electric field mitigation region 16B may be discontinuously arranged along the Y-axis. The upper surface of the second electric field relief region 16B can contact and be electrically connected to the body region 12. The upper surface of the second electric field relief region 16B can also contact and be electrically connected to the contact region 18. In this case, it is easier to reduce the feedback capacitance, thereby shortening the switching time.

[0041] The first electric field relief region 16A and the second electric field relief region 16B are arranged side by side along the Y-axis. The first electric field relief region 16A and the second electric field relief region 16B can also be arranged alternately along the Y-axis. The first electric field relief region 16A can be connected to the adjacent second electric field relief region 16B along the Y-axis.

[0042] The first length L1 of the first electric field mitigation region 16A along the X-axis can be shorter than the second length L2 of the second electric field mitigation region 16B along the X-axis. In this case, the avalanche current flows more easily to the direct below the first electric field mitigation region 16A compared to the terminal region. Therefore, the avalanche tolerance is improved. The first length L1 can also be shorter than the third length L3 along the Y-axis connecting the first electric field mitigation region 16A and the second electric field mitigation region 16B. In this case, the avalanche current flows more easily to the direct below the first electric field mitigation region 16A compared to the terminal region. Therefore, the avalanche tolerance is improved.

[0043] The first region 11A is located between the current diffusion region 14 and the first electric field relief region 16A. The upper surface of the first region 11A is in contact with the current diffusion region 14, the lower surface is in contact with the first electric field relief region 16A, and the side is in contact with the second electric field relief region 16B.

[0044] The second region 11B is closer to the second main surface 2 than the first region 11A. The second region 11B is connected to the first region 11A. The upper surface of the second region 11B is in contact with the first region 11A, the lower surface is in contact with the third region 11C, and the side is in contact with the first electric field relief region 16A and the second electric field relief region 16B.

[0045] The third region 11C is closer to the second main surface 2 than the second region 11B. The third region 11C is connected to the second region 11B. The upper surface of the third region 11C is in contact with the first electric field relief region 16A, the second electric field relief region 16B and the second region 11B, and the lower surface is in contact with the silicon carbide single crystal substrate 50.

[0046] The gate insulating film 81 is, for example, an oxide film. The gate insulating film 81 may contain, for example, silicon dioxide. The gate insulating film 81 is in contact with the side surface 3 and the bottom surface 4. The gate insulating film 81 is in contact with the drift region 11 at the bottom surface 4. The gate insulating film 81 is in contact with the source region 13, the body region 12, the current diffusion region 14, and the drift region 11 at the side surface 3. The gate insulating film 81 may be in contact with the source region 13 at the first main surface 1.

[0047] A gate electrode 82 is disposed on a gate insulating film 81. The gate electrode 82 may comprise, for example, polysilicon. The polysilicon may contain conductive impurities. The gate electrode 82 is disposed inside a gate trench 5. The gate electrode 82 is opposite to the side surface 3 and the bottom surface 4. A portion of the gate electrode 82 may be opposite to a first main surface 1. The gate electrode 82 extends along the Y-axis. In a top view perpendicular to the first main surface 1, the gate electrode 82 may overlap with a plurality of gate trenches 5.

[0048] An interlayer insulating film 83 covers the gate electrode 82. The interlayer insulating film 83 is in contact with both the gate electrode 82 and the gate insulating film 81. The interlayer insulating film 83 is, for example, an oxide film. The interlayer insulating film 83 may contain, for example, silicon dioxide. The interlayer insulating film 83 electrically insulates the gate electrode 82 and the source electrode 60 from each other. A portion of the interlayer insulating film 83 may be disposed inside the gate trench 5.

[0049] Contact holes 90 are provided at certain intervals along the X-axis in the interlayer insulating film 83 and the gate insulating film 81. The contact holes 90 are configured such that the gate trench 5 is located between adjacent contact holes 90 along the X-axis. The contact holes 90 extend along the Y-axis. Through the contact holes 90, the source region 13 and the contact region 18 are exposed from the interlayer insulating film 83 and the gate insulating film 81.

[0050] A barrier metal film 84 covers the upper surface of the interlayer insulating film 83 and the side surface of the gate insulating film 81. The barrier metal film 84 is in contact with the interlayer insulating film 83 and the gate insulating film 81. The barrier metal film 84 may contain, for example, titanium nitride (TiN).

[0051] The source electrode 60 is in contact with the first main surface 1. The source electrode 60 has a contact electrode 61 and a source wiring 62.

[0052] A contact electrode 61 is disposed within a contact hole 90. The contact electrode 61 contacts the source region 13 and the contact region 18 at the first main surface 1. The contact electrode 61 may contain, for example, nickel silicide (NiSi). The contact electrode 61 may also contain titanium (Ti), aluminum, or silicon (Si). The contact electrode 61 forms an ohmic contact with the source region 13 and the contact region 18.

[0053] Source wiring 62 covers the upper and side surfaces of the barrier metal film 84 and the upper surface of the contact electrode 61. Source wiring 62 is in contact with both the barrier metal film 84 and the contact electrode 61. Source wiring 62 may contain, for example, aluminum. In this case, source wiring 62 can be easily connected to the contact electrode 61.

[0054] The drain electrode 70 is in contact with the second main surface 2. The drain electrode 70 is in contact with the silicon carbide single-crystal substrate 50 at the second main surface 2. The drain electrode 70 is electrically connected to the drift region 11. The drain electrode 70 may, for example, comprise nickel silicide. The drain electrode 70 may also comprise titanium, aluminum, and silicon. The drain electrode 70 forms an ohmic contact with the silicon carbide single-crystal substrate 50.

[0055] The effective concentration of n-type impurities in Zone 11A is, for example, 1 × 10⁻⁶. 16 cm -3 Above and 1×10 18 cm -3 The effective concentration of n-type impurities in Zone 11B can be lower than that in Zone 11A. For example, the effective concentration of n-type impurities in Zone 11B is 1 × 10⁻⁶.16 cm -3 Above and 1×10 18 cm -3 The effective concentration of n-type impurities in Zone 11C can be lower than that in Zone 11B. For example, the effective concentration of n-type impurities in Zone 11C is 2 × 10⁻⁶. 15 cm -3 Above and 5×10 16 cm -3 the following.

[0056] The effective concentration of n-type impurities in current diffusion region 14 can be higher than that in the first region 11A. For example, the effective concentration of n-type impurities in current diffusion region 14 is 2 × 10⁻⁶. 16 cm -3 Above and 4×10 18 cm -3 the following.

[0057] In this invention, the effective concentration of the first conductivity type impurity is the concentration obtained by subtracting the concentration of the second conductivity type impurity from the concentration of the first conductivity type impurity. Similarly, the effective concentration of the second conductivity type impurity is the concentration obtained by subtracting the concentration of the first conductivity type impurity from the concentration of the second conductivity type impurity. The effective concentration can be measured, for example, using scanning capacitance microscopy (SCM) or secondary ion mass spectrometry (SIMS).

[0058] Next, the manufacturing method of the silicon carbide semiconductor device 100 will be described.

[0059] First, a silicon carbide single-crystal substrate 50 is prepared. Next, a silicon carbide epitaxial layer 40 is formed on the silicon carbide single-crystal substrate 50. For example, the silicon carbide single-crystal substrate 50 contains n-type impurities such as nitrogen and has an n-type conductivity type. For example, the silicon carbide epitaxial layer 40 can be formed by epitaxial growth with the addition of n-type impurities such as nitrogen.

[0060] Next, an electric field relief region 16 is formed by ion implantation into the silicon carbide epitaxial layer 40. In the ion implantation used to form the electric field relief region 16, for example, channel implantation of p-type impurities such as aluminum is performed. At this time, the upper surface of the electric field relief region 16 must be separated from the upper surface of the silicon carbide epitaxial layer 40.

[0061] Next, ion implantation is performed on the silicon carbide epitaxial layer 40 to form a body region 12, a source region 13, a current diffusion region 14, and a contact region 18. The remaining portion of the silicon carbide epitaxial layer 40 becomes a drift region 11. Next, a plurality of gate trenches 5 are formed. Then, a gate insulating film 81, a gate electrode 82, an interlayer insulating film 83, a barrier metal film 84, a source electrode 60, and a drain electrode 70 are formed (see reference). Figure 2 and Figure 3 ).

[0062] Through the above steps, a silicon carbide semiconductor device 100 can be manufactured.

[0063] In the silicon carbide semiconductor device 100, as described above, the first electric field relief region 16A and the second electric field relief region 16B are arranged side by side along the Y-axis. The first electric field relief region 16A is located directly below the gate trench 5, and the second electric field relief region 16B is located directly below the contact region 18. In this configuration, the electric field strength applied to the gate insulating film 81 can be reduced while maintaining avalanche tolerance.

[0064] The first electric field relief region 16A and the second electric field relief region 16B can be arranged alternately and repeatedly along the Y-axis. In this case, the deviation between the area through which the current flows and the area through which it does not flow during avalanche breakdown becomes smaller, thus making it easier to uniformize the heat distribution during avalanche breakdown within the chip.

[0065] The first electric field relief region 16A can be connected to the adjacent second electric field relief region 16B along the Y-axis. In this case, it is easy to reduce the feedback capacitance, thereby shortening the switching time.

[0066] The first length L1 of the first electric field mitigation region 16A along the X-axis can be shorter than the second length L2 of the second electric field mitigation region 16B along the X-axis. In this case, the avalanche current flows more easily to the area directly below the first electric field mitigation region 16A compared to the terminal region. Therefore, the avalanche tolerance is improved.

[0067] The first length L1 can be shorter than the third length L3 along the Y-axis of the portion where the first electric field relief region 16A and the second electric field relief region 16B are connected. In this case, the avalanche current flows more easily to the area directly below the first electric field relief region 16A compared to the terminal region. Therefore, the avalanche tolerance is improved.

[0068] The effective concentration of n-type impurities in drift region 11 can be reduced from the first main surface 1 toward the second main surface 2. In this case, the withstand voltage can be increased while reducing the on-resistance.

[0069] [Second Implementation] The second embodiment is described below. The difference between the second embodiment and the first embodiment is that it has a connection region that electrically connects the body region and the first electric field relief region. Figure 4This is a diagram showing the arrangement of the electric field mitigation region included in the silicon carbide semiconductor device according to the second embodiment. Figure 5 This is a cross-sectional view showing a silicon carbide semiconductor device according to the second embodiment. Figure 5 Equivalent to along Figure 4 Cross-sectional view of the VV line.

[0070] like Figure 4 and Figure 5 As shown, the silicon carbide semiconductor device 200 according to the second embodiment has a connection region 17.

[0071] The connection region 17 contains p-type impurities such as aluminum and has a p-type conductivity type. In a top view perpendicular to the first main surface 1, the connection region 17 is positioned to overlap with the gate trench 5. In a top view perpendicular to the first main surface 1, the connection region 17 may have a portion overlapping with the bottom surface 4 of the gate trench 5. In a top view perpendicular to the first main surface 1, the connection region 17 may have a portion overlapping with the side surface 3 of the gate trench 5. At the position overlapping with the gate trench 5, the connection region 17 may be discontinuously positioned along the Y-axis. In a top view perpendicular to the first main surface 1, the connection region 17 overlaps with a portion of the first electric field relief region 16A. In a top view perpendicular to the first main surface 1, the connection region 17 may be positioned at the midpoint of the first electric field relief region 16A along the Y-axis. The connection region 17 is located between the body region 12 and the first electric field relief region 16A. The connection region 17 is in contact with both the body region 12 and the first electric field relief region 16A. The connecting region 17 electrically connects the body region 12 to the first electric field relief region 16A. The upper surface of the connecting region 17 can contact the bottom surface 4. In a top view perpendicular to the first main surface 1, the length of the connecting region 17 along the X-axis can be the same as that of the first electric field relief region 16A.

[0072] Except for the connection area 17, the rest is the same as in the first embodiment.

[0073] The silicon carbide semiconductor device 200 can be manufactured in the following manner: In the manufacturing method of the silicon carbide semiconductor device 100, after forming the electric field relief region 16, a connection region 17 is formed by ion implantation into the silicon carbide epitaxial layer 40. In the ion implantation used to form the connection region 17, for example, channel implantation of p-type impurities such as aluminum is performed. At this time, the upper surface of the connection region 17 is separated from the upper surface of the silicon carbide epitaxial layer 40.

[0074] The silicon carbide semiconductor device 200 of the second embodiment can also achieve the same effect as the first embodiment.

[0075] The silicon carbide semiconductor device 200 has a connection region 17 that electrically connects the body region 12 to the first electric field relief region 16A. In this case, the feedback capacitance can be reduced, thereby shortening the switching time.

[0076] [Third Implementation Method] The third embodiment is described below. The difference between the third embodiment and the second embodiment is that the connecting region electrically connects the body region and the contact region to the first electric field mitigation region. Figure 6 This is a diagram showing the arrangement of the electric field mitigation region included in the silicon carbide semiconductor device according to the third embodiment. Figure 7 This is a cross-sectional view showing a silicon carbide semiconductor device according to a third embodiment. Figure 7 Equivalent to along Figure 6 Cross-sectional view of line VII-VII in the middle.

[0077] like Figure 6 and Figure 7 As shown, in the silicon carbide semiconductor device 300 of the third embodiment, the upper end surface of the connection region 17 contacts the body region 12 and the contact region 18. The connection region 17 electrically connects the body region 12 and the contact region 18 to the first electric field relief region 16A. The connection region 17 extends along the X-axis. The length of the connection region 17 along the X-axis is longer than the length of the first electric field relief region 16A along the X-axis.

[0078] Except for the connection area 17, the rest is the same as in the second embodiment.

[0079] The silicon carbide semiconductor device 300 can be manufactured using the same method as the silicon carbide semiconductor device 200.

[0080] The silicon carbide semiconductor device 300 of the third embodiment can also achieve the same effect as the first embodiment.

[0081] The silicon carbide semiconductor device 300 has a connection region 17 that electrically connects the body region 12 to the first electric field relief region 16A. In this case, the feedback capacitance can be reduced, thereby shortening the switching time.

[0082] Connection region 17 electrically connects contact region 18 to the first electric field mitigation region 16A. In this case, the grounding of the first electric field mitigation region 16A is more secure.

[0083] The embodiments have been described in detail above, but the present invention is not limited to the specific embodiments. Various modifications and alterations can be made within the scope of the claims.

[0084] Explanation of reference numerals in the attached figures 1 First Main Face 2 Second Main Face 3. Side view 4 bottom 5 Gate trench 10 Silicon carbide substrate 11 Drift Zone 11A First District 11B Second Zone 11C Third District 12 body areas 13 source regions 14 Current diffusion region 16 Electric Field Relief Region 16A First Electric Field Relief Region 16B Second Electric Field Relief Region 17 Connection Area 18 Contact Area 40 Silicon carbide epitaxial layer 50 Silicon carbide single crystal substrate 60 source electrodes 61 Contact Electrode 62 Source wiring 70 Drain electrode 81 Gate insulating film 82 gate electrode 83 interlayer insulating film 84 Barrier Metal Film 90 contact hole 100 Silicon Carbide Semiconductor Device 200 Silicon Carbide Semiconductor Device 300 Silicon Carbide Semiconductor Device L1 First Length L2 Second Length L3 Third Length

Claims

1. A silicon carbide semiconductor device comprising a silicon carbide substrate, the silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface. The silicon carbide substrate has: Drift region with first conductivity type Above the drift region, there is a body region having a second conductivity type, and A source region of the first conductivity type is disposed above the body region. The first main surface is provided with a gate trench defined by a side surface that extends through the source region and the body region to the drift region and a bottom surface connected to the side surface. The gate trench extends along a first axis parallel to the first main surface. The silicon carbide substrate also has: The contact area, which sandwiches the source region between itself and the side surface, contacts the body region and has the second conductivity type. A first electric field mitigation region, which overlaps with the gate trench when viewed from above perpendicular to the first main surface, is located between the bottom surface and the second main surface, and has the second conductivity type. A second electric field mitigation region, which overlaps with the contact region when viewed from above perpendicular to the first main surface, is located between the body region and the second main surface, and has the second conductivity type. The first electric field relief region and the second electric field relief region are arranged side by side along the first axis.

2. A silicon carbide semiconductor device comprising a silicon carbide substrate, the silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface. The silicon carbide substrate has: Drift region with first conductivity type Above the drift region, there is a body region having a second conductivity type, and A source region of the first conductivity type is disposed above the body region. The first main surface is provided with a gate trench defined by a side surface that extends through the source region and the body region to the drift region and a bottom surface connected to the side surface. The gate trench extends along a first axis parallel to the first main surface. The silicon carbide substrate also has: The contact area, which sandwiches the source region between itself and the side surface, contacts the body region and has the second conductivity type. A first electric field mitigation region, which, when viewed from above perpendicular to the first main surface, has a portion overlapping the bottom surface of the gate trench, is disposed between the bottom surface and the second main surface, and has the second conductivity type. The second electric field mitigation region, which, when viewed from above perpendicular to the first main surface, has a portion overlapping the contact region, is located between the body region and the second main surface, and has the second conductivity type. The first electric field relief region and the second electric field relief region are arranged side by side along the first axis.

3. The silicon carbide semiconductor device according to claim 1 or 2, wherein the first electric field relief region and the second electric field relief region are alternately and repeatedly arranged along the first axis.

4. The silicon carbide semiconductor device according to any one of claims 1 to 3, wherein the first electric field relief region is connected to the second electric field relief region adjacent along the first axis.

5. The silicon carbide semiconductor device of claim 4, wherein the first electric field relief region has a first length along a second axis parallel to the first main surface and perpendicular to the first axis. The second electric field relief region has a second length along the second axis. The first length is shorter than the second length.

6. The silicon carbide semiconductor device according to claim 5, wherein the first length is shorter than the third length along the first axis of the portion where the first electric field relief region and the second electric field relief region are connected.

7. The silicon carbide semiconductor device according to any one of claims 1 to 6, wherein the concentration of impurities of the first conductivity type in the drift region decreases from the first main surface toward the second main surface.

8. The silicon carbide semiconductor device according to any one of claims 1 to 7, having a connection region electrically connecting the body region and the first electric field relief region.

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