Semiconductor module and power conversion device

Abstract

Provided is a technique capable of reducing thermal stress due to temperature changes in a semiconductor module. The semiconductor module includes: a first semiconductor device having a package that seals a semiconductor element and P and N electrodes that protrude from the package; a second semiconductor device having a package that seals a semiconductor element and P and N electrodes that protrude from the package, and arranged adjacent to the first semiconductor device in a manner that the P and N electrodes are mirror-symmetric to the P and N electrodes of the first semiconductor device; a P bus bar that connects the P electrodes of the first and second semiconductor devices to each other; and an N bus bar that connects the N electrodes of the first and second semiconductor devices to each other. The P bus bar and the N bus bar partially overlap when viewed from above.

Description

Technical Field

[0001] This disclosure relates to semiconductor modules and power conversion devices. Background Technology

[0002] When power semiconductor devices used in inverters and the like are used for high-current applications, they are sometimes connected in parallel. For example, Patent Document 1 discloses a structure in which the positive and negative terminals corresponding to one circuit block and the positive and negative terminals corresponding to another circuit block are arranged in a mirror-symmetrical manner in order to reduce the inductance deviation between the parallel-connected circuit blocks. Existing technical documents Patent documents

[0003] Patent Document 1: Japanese Patent Application Publication No. 2014-225706 Summary of the Invention The technical problem that the invention aims to solve

[0004] However, in the technology described in Patent Document 1, since multiple circuit blocks are arranged in a mirror-symmetric manner within a package of a semiconductor module, there is a problem that the package becomes larger and the thermal stress caused by temperature changes increases.

[0005] Therefore, the purpose of this disclosure is to provide a technique for reducing thermal stress in semiconductor modules in response to temperature changes. Technical means to solve technical problems

[0006] The semiconductor module disclosed herein comprises: a first semiconductor device having a hermetically sealed semiconductor element package and P-electrodes and N-electrodes protruding from the package; a second semiconductor device having a hermetically sealed semiconductor element package and P-electrodes and N-electrodes protruding from the package, and the P-electrodes and N-electrodes being arranged adjacent to the first semiconductor device in a mirror-symmetric manner with respect to the P-electrodes and N-electrodes of the first semiconductor device; a P-busbar connecting the P-electrodes of the first semiconductor device and the second semiconductor device to each other; and an N-busbar connecting the N-electrodes of the first semiconductor device and the second semiconductor device to each other, wherein the P-busbar and the N-busbar partially overlap when viewed from above. Invention Effects

[0007] According to this disclosure, since the first semiconductor device and the second semiconductor device, which contain semiconductor elements, are arranged adjacent to each other, the package size of each semiconductor device can be reduced compared to the case where all semiconductor elements are housed in a single package. This reduces thermal stress from temperature changes.

[0008] The purpose, features, aspects, and advantages of this disclosure will become clearer from the following detailed description and accompanying drawings. Attached Figure Description

[0009] Figure 1 This is a top view of the semiconductor module involved in Embodiment 1. Figure 2 This is a top view showing the internal layout of the semiconductor module involved in Embodiment 1. Figure 3 It is a graph used to compare the voltage waveforms when the switch is turned on. Figure 4 This is a top view of the semiconductor module involved in Embodiment 2. Figure 5 This is a top view of the semiconductor module involved in Embodiment 3. Figure 6 This is a top view of the semiconductor module involved in Embodiment 4. Figure 7 This is a top view of the semiconductor module involved in Embodiment 5. Figure 8 This is a cross-sectional view showing the state in which a heat sink is fixed on the semiconductor module according to Embodiment 5. Figure 9 This is a top view of the semiconductor module involved in Implementation Method 6. Figure 10 This is a block diagram showing the structure of a power conversion system that uses the power conversion device described in Embodiment 7. Detailed Implementation

[0010] <Implementation Method 1> Embodiment 1 will be described below with reference to the accompanying drawings. Figure 1 This is a top view of the semiconductor module 202 according to Embodiment 1.

[0011] like Figure 1 As shown, the semiconductor module 202 includes a first semiconductor device 10, a second semiconductor device 11, a P bus 20, an N bus 21, and an AC bus 22. The second semiconductor device 11 is arranged adjacent to the first semiconductor device 10. Figure 1 In the middle, the first semiconductor device 10 is arranged on the left and the second semiconductor device 11 is arranged on the right.

[0012] The first semiconductor device 10 includes a P-electrode 4, an N-electrode 5, an AC terminal 6, a P-side control terminal 7, an N-side control terminal 8, and a package 9. The package 9, when viewed from above, is formed in a quadrilateral shape (more specifically, a rectangular shape), and is made of, for example, epoxy resin or silicone gel. The P-electrode 4, N-electrode 5, and N-side control terminal 8 protrude from a first side of the package 9. The AC terminal 6 and the P-side control terminal 7 protrude from a second side of the package 9 opposite to the first side. Here, the first side is... Figure 1The upper short side, the second side is Figure 1 The lower short side in the middle.

[0013] The second semiconductor device 11, like the first semiconductor device 10, includes a P-electrode 4, an N-electrode 5, an AC terminal 6, a P-side control terminal 7, an N-side control terminal 8, and a package 9. However, the configuration of the P-electrode 4, N-electrode 5, N-side control terminal 8, AC terminal 6, and P-side control terminal 7 differs from that of the first semiconductor device 10. Only the differences will be described here.

[0014] The P-electrode 4, N-electrode 5, and N-side control terminal 8 of the second semiconductor device 11 are arranged in a mirror-symmetrical manner with respect to the boundary line A, as are the P-electrode 4, N-electrode 5, and N-side control terminal 8 of the first semiconductor device 10. The P-electrode 4, N-electrode 5, and N-side control terminal 8 are arranged on the first side of the package 9 in both the first semiconductor device 10 and the second semiconductor device 11, along the direction close to the adjacent semiconductor device, in the order of N-side control terminal 8, N-electrode 5, and P-electrode 4. Therefore, the P-electrode 4 of the first semiconductor device 10 and the second semiconductor device 11 are close to each other.

[0015] Furthermore, the AC terminal 6 and P-side control terminal 7 of the second semiconductor device 11 are arranged in a mirror-symmetrical manner with respect to the boundary line A, as are the AC terminal 6 and P-side control terminal 7 of the first semiconductor device 10. The AC terminal 6 and P-side control terminal 7 are arranged in the order of AC terminal 6 and P-side control terminal 7 on the second side of the package 9 in the first semiconductor device 10 and the second semiconductor device 11, along the direction close to the adjacent semiconductor device. Therefore, the P-side control terminals 7 of the first semiconductor device 10 and the second semiconductor device 11 are close to each other.

[0016] This configuration allows the N-side control terminal 8 and the N-electrode 5, as well as the AC terminal 6 and the P-side control terminal 7, to be placed close together. As a result, the short side of the package 9 in the first semiconductor device 10 and the second semiconductor device 11 can be shortened, thus enabling miniaturization of the semiconductor module 202.

[0017] P-bus 20 connects the P-electrodes 4 of the first semiconductor device 10 and the second semiconductor device 11 to each other. P-bus 20 has a straight section 20a and a first connecting section 20b. The straight section 20a is a main wiring extending parallel to the direction in which the first semiconductor device 10 and the second semiconductor device 11 are arranged adjacently. The first connecting section 20b connects the P-electrodes 4 to the straight section 20a. N-bus 21 is disposed below P-bus 20 and connects the N-electrodes 5 of the first semiconductor device 10 and the second semiconductor device 11 to each other. N-bus 21 has a straight section (not shown) and a second connecting section 21b. The straight section is a main wiring extending parallel to the direction in which the first semiconductor device 10 and the second semiconductor device 11 are arranged adjacently. The second connecting section 21b connects the N-electrodes 5 to the straight section.

[0018] P-bus 20 and N-bus 21 partially overlap when viewed from above. Specifically, in order to minimize the inductance of the paths to the smoothing capacitor (not shown) in the first semiconductor device 10 and the smoothing capacitor (not shown) in the second semiconductor device 11, the straight portions 20a of P-bus 20 and N-bus 21 are arranged to overlap when viewed from above, and an insulating layer (not shown) is disposed between them. Furthermore, the first semiconductor device 10 and the second semiconductor device 11 are connected in parallel such that the overlapping portions of P-bus 20 and N-bus 21 when viewed from above, i.e., the straight portions 20a of P-bus 20 and N-bus 21, extend in a straight line.

[0019] On the other hand, the first connecting portion 20b of P busbar 20 and the second connecting portion 21b of N busbar 21 do not overlap when viewed from above.

[0020] Next, the internal layout of the first semiconductor device 10 and the second semiconductor device 11 will be described. Figure 2 This is a top view showing the internal layout of the semiconductor module 202 according to Embodiment 1.

[0021] like Figure 2 As shown, the first semiconductor device 10 and the second semiconductor device 11 have a 2-in-1 structure. The first semiconductor device 10 and the second semiconductor device 11 are identical in structure except that each electrode and each terminal is mirror-symmetrical with respect to the boundary line A. Therefore, the internal layout of the first semiconductor device 10 will be described here.

[0022] In addition to the P electrode 4, N electrode 5, AC terminal 6, P-side control terminal 7, N-side control terminal 8, and package 9, the first semiconductor device 10 also includes an insulating substrate 1, a circuit pattern 2, and a plurality of (e.g., 2) semiconductor elements 3.

[0023] The insulating substrate 1, when viewed from above, is quadrilateral (specifically rectangular). A circuit pattern 2 is formed on the upper surface of the insulating substrate 1. The circuit pattern 2 is divided into multiple parts, and multiple semiconductor elements 3 are mounted on the upper surface of the circuit pattern 2. The semiconductor elements 3 are power semiconductor elements, such as IGBTs (Insulated Gate Bipolar Transistors), MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), RC-IGBTs (Reverse Conductive IGBTs), or diodes. The semiconductor material of the semiconductor elements 3 can be Si or SiC, but SiC is preferred.

[0024] One end of the P electrode 4 is connected to the circuit pattern 2, and the other end of the P electrode 4 protrudes from the package 9 and is connected to the first connection portion 20b of the P bus 20. One end of the N electrode 5 is connected to the upper surface electrode (not shown) of a semiconductor element 3, and the other end of the N electrode 5 protrudes from the package 9 and is connected to the second connection portion 21b of the N bus 21. One end of the AC terminal 6 is connected to the upper surface electrode (not shown) of another semiconductor element 3 and the circuit pattern 2, and the other end of the AC terminal 6 is connected to the AC bus 22. Thus, within the package 9, each electrode and each terminal is also arranged in a mirror-symmetrical manner with respect to the boundary line A. Since the first semiconductor device 10 and the second semiconductor device 11 have a 2-in-1 structure, miniaturization of the semiconductor module 202 can be achieved.

[0025] Figure 3 It is a graph used to compare the voltage waveforms when the switch is turned on. Figure 3 (a) shows the voltage waveform when the switch is turned on, provided that the electrodes and terminals are not arranged in a mirror-symmetric configuration relative to boundary line A. Figure 3 (b) shows the voltage waveform when the switch is turned on in the case where each electrode and each terminal is arranged in a mirror symmetrical configuration with respect to the boundary line A, i.e., in the case of embodiment 1.

[0026] like Figure 3 As shown in (a) and (b), it can be seen that compared with the case where each electrode and each terminal is not arranged in a mirror symmetric manner with respect to the boundary line A, the noise waveform when the switch is turned on is significantly reduced in Embodiment 1. Thus, by adopting the structure of Embodiment 1, resonance between semiconductor elements 3 can be suppressed, and noise can be significantly reduced.

[0027] As described above, the semiconductor module 202 according to Embodiment 1 includes: a first semiconductor device 10 having a package 9 that hermetically seals a semiconductor element 3 and P-electrode 4 and N-electrode 5 protruding from the package 9; a second semiconductor device 11 having a package 9 that hermetically seals a semiconductor element 3 and P-electrode 4 and N-electrode 5 protruding from the package 9, and the P-electrode 4 and N-electrode 5 being arranged adjacent to the first semiconductor device 10 in a mirror-symmetric manner with respect to the P-electrode 4 and N-electrode 5 of the first semiconductor device 10; a P-bus 20 connecting the P-electrode 4 of the first semiconductor device 10 and the second semiconductor device 11 to each other; and an N-bus 21 connecting the N-electrode 5 of the first semiconductor device 10 and the second semiconductor device 11 to each other. The P-bus 20 and the N-bus 21 partially overlap when viewed from above.

[0028] Therefore, since the first semiconductor device 10 and the second semiconductor device 11, which house the semiconductor elements 3, are arranged adjacent to each other, the size of the package 9 for each semiconductor element 3 can be reduced compared to the case where all semiconductor elements 3 are housed in a single package 9. This reduces thermal stress from temperature changes. As described above, the durability of the semiconductor module 202 is improved.

[0029] Furthermore, the P busbar 20 and the N busbar 21 partially overlap when viewed from above. Specifically, the straight portion 20a of the P busbar 20 and the straight portion of the N busbar 21 overlap when viewed from above. Therefore, while suppressing the overall inductance of the semiconductor module 202, the inductance difference between the first semiconductor device 10 and the second semiconductor device 11 is reduced, so that the path from the semiconductor element 3 of the first semiconductor device 10 and the second semiconductor device 11 to the smoothing capacitor (not shown) is the same between the first semiconductor device 10 and the second semiconductor device 11, thus suppressing resonance and oscillation.

[0030] Furthermore, the first semiconductor device 10 and the second semiconductor device 11 have a 2-in-1 structure, and the packages 9 of both the first semiconductor device 10 and the second semiconductor device 11 are formed into a quadrilateral shape when viewed from above. Both the first semiconductor device 10 and the second semiconductor device 11 also have AC terminals 6 protruding from the packages 9. The AC terminal 6 of the first semiconductor device 10 is disposed on the second side opposite to the first side of the package 9 where the P electrode 4 and N electrode 5 of the first semiconductor device 10 are disposed, and the AC terminal 6 of the second semiconductor device 11 is disposed on the second side opposite to the first side of the package 9 where the P electrode 4 and N electrode 5 of the second semiconductor device 11 are disposed. Therefore, miniaturization of the semiconductor module 202 is possible.

[0031] Furthermore, since the semiconductor material of semiconductor element 3 is SiC, the output of semiconductor module 202 can be increased.

[0032] <Implementation Method 2> Next, the semiconductor module 202 involved in Embodiment 2 will be described. Figure 4 This is a top view of the semiconductor module 202 according to Embodiment 2. Furthermore, in Embodiment 2, the same reference numerals are used for components that are the same as those described in Embodiment 1, and their descriptions are omitted.

[0033] like Figure 4 As shown, in Embodiment 2, the semiconductor module 202 includes three sets of first semiconductor devices 10 and second semiconductor devices 11, with the first semiconductor devices 10 and second semiconductor devices 11 arranged adjacent to each other.

[0034] The three sets of first semiconductor devices 10 and second semiconductor devices 11 from Figure 4 The components are arranged in the order of phase A, phase B, and phase C, starting from the left. The P busbar 20 connects the P electrodes 4 of the three sets of first semiconductor devices 10 and second semiconductor devices 11 to each other. The N busbar 21 connects the N electrodes 5 of the three sets of first semiconductor devices 10 and second semiconductor devices 11 to each other.

[0035] The straight portions 20a of the P busbar 20 and the N busbar 21 are arranged to overlap in a top view to minimize the inductance of the paths to the smooth capacitor (not shown) in the first semiconductor device 10 and the smooth capacitor (not shown) in the second semiconductor device 11, and an insulating layer (not shown) is disposed between them. Furthermore, the three sets of first semiconductor devices 10 and second semiconductor devices 11 are connected in parallel such that the overlapping portions of the P busbar 20 and N busbar 21 in a top view, i.e., the straight portions 20a of the P busbar 20 and the N busbar 21, extend in a straight line.

[0036] On the other hand, the first connecting portion 20b of the P busbar 20 and the second connecting portion 21b of the N busbar 21 do not overlap when viewed from above. Furthermore, the structure of Embodiment 2 can also be adopted in Embodiments 3 to 6 described later.

[0037] As described above, in Embodiment 2, the semiconductor module 202 includes three sets of first semiconductor devices 10 and second semiconductor devices 11, with the first semiconductor devices 10 and second semiconductor devices 11 arranged adjacent to each other.

[0038] Therefore, it can reduce thermal stress caused by temperature changes and obtain the three-phase AC output required for AC motor drive.

[0039] Furthermore, both the first semiconductor device 10 and the second semiconductor device 11 have an N-side control terminal 8 and a P-side control terminal 7 protruding from the package 9. On the first side of the package 9 in the first semiconductor device 10 and the second semiconductor device 11, along the direction close to another adjacent semiconductor device, the N-side control terminal 8, the N electrode 5, and the P electrode 4 are arranged in that order. On the second side of the package 9 in the first semiconductor device 10 and the second semiconductor device 11, along the direction close to another adjacent semiconductor device, the AC terminal 6 and the P-side control terminal 7 are arranged in that order. The first semiconductor device 10 and the second semiconductor device 11 are connected in parallel such that, when viewed from above, the overlapping portions of the P busbar 20 and the N busbar 21 extend in a straight line.

[0040] Therefore, by placing the N-side control terminal 8 and the N-electrode 5, and the AC terminal 6 and the P-side control terminal 7 close together, the short sides of the first semiconductor device 10 and the second semiconductor device 11 can be shortened. As a result, the semiconductor module 202 can be miniaturized.

[0041] Furthermore, since the P-side control terminal 7 is centrally located within each phase, the insulation distance between phases can be ensured. As a result, the insulation design of the driver board connected to each phase becomes easier.

[0042] <Implementation Method 3> Next, the semiconductor module 202 involved in Embodiment 3 will be described. Figure 5 This is a top view of the semiconductor module 202 according to Embodiment 3. Furthermore, in Embodiment 3, the same reference numerals are used for components that are the same as those described in Embodiments 1 and 2, and their descriptions are omitted.

[0043] like Figure 5 As shown, in Embodiment 3, the semiconductor devices 10 and 11 are configured to be connected to each other at the source potential of the semiconductor element 3 of the first semiconductor device 10 and the second semiconductor device 11.

[0044] Specifically, the middle portion of the N electrode 5 of the first semiconductor device 10 and the second semiconductor device 11 is connected to the upper surface electrode (not shown) of a semiconductor element 3, and one end of the N electrode 5 is connected to the package 9 located on the side of the other semiconductor device located adjacent to it (see reference 3). Figure 1 The third side of the first semiconductor device 10 and the second semiconductor device 11 protrudes. One end of the AC terminal 6 of the first semiconductor device 10 and the second semiconductor device 11 branches into two branches. One end of the AC terminal 6 is connected to the upper surface electrode (not shown) of another semiconductor element 3 and the circuit pattern 2. The other end of the AC terminal 6 is connected to the package 9 (see reference 2) located on the side of another semiconductor device located in an adjacent configuration. Figure 1The third side of the ) is prominent. Additionally, the third side is... Figure 1 The right long side in the middle.

[0045] As described above, in Embodiment 3, a portion of the N electrode 5 and AC terminal 6 of the first semiconductor device 10 and the second semiconductor device 11 protrudes from the third side of the package 9 located on the side of the other semiconductor device in an adjacent configuration.

[0046] Therefore, by connecting each semiconductor device 10 and 11 to each other at the source potential of the semiconductor element 3 of the first semiconductor device 10 and the second semiconductor device 11, the inductance difference between the first semiconductor device 10 and the second semiconductor device 11 can be further reduced.

[0047] <Implementation Method 4> Next, the semiconductor module 202 involved in Embodiment 4 will be described. Figure 6 This is a top view of the semiconductor module 202 according to Embodiment 4. Furthermore, in Embodiment 4, the same reference numerals are used for components that are the same as those described in Embodiments 1 to 3, and their descriptions are omitted.

[0048] like Figure 6 As shown, in embodiment 4, the P bus 20 and N bus 21 are led out in a parallel plate state to the vicinity of the first semiconductor device 10 and the second semiconductor device 11 at the center B between the P electrode 4 and the N electrode 5 of the first semiconductor device 10 and the second semiconductor device 11, that is, at the center B between the first connecting portion 20b and the second connecting portion 21b, and are connected to the P electrode 4 and the N electrode 5 respectively.

[0049] As described above, in the semiconductor module 202 according to Embodiment 4, both the P bus 20 and the N bus 21 have: a straight portion 20a that extends parallel to the direction in which the first semiconductor device 10 and the second semiconductor device 11 are arranged adjacent to each other; a first connecting portion 20b that connects the P electrode 4 to the straight portion 20a; and a second connecting portion 21b that connects the N electrode 5 to the straight portion. The first connecting portion 20b and the second connecting portion 21b are connected to the straight portion 20a at the center B between the first connecting portion 20b and the second connecting portion 21b.

[0050] Therefore, since the P bus 20 and N bus 21 are led out to the vicinity of the first semiconductor device 10 and the second semiconductor device 11 in a parallel plate state, the inductance difference between the first semiconductor device 10 and the second semiconductor device 11 can be further reduced compared to Embodiment 1.

[0051] <Implementation Method 5> Next, the semiconductor module 202 according to Embodiment 5 will be described. Figure 7This is a top view of the semiconductor module 202 according to Embodiment 5. Figure 8 This is a cross-sectional view showing the state in which the heat sink 23 is fixed on the semiconductor module 202 according to Embodiment 5. Furthermore, in Embodiment 5, the same reference numerals are used for components that are the same as those described in Embodiments 1 to 4, and their descriptions are omitted.

[0052] In implementation method 5, such as Figure 7 As shown, the first semiconductor device 10 and the second semiconductor device 11 are provided with a connection structure capable of connecting the two. Furthermore, as... Figure 8 As shown, a heat sink 23 for cooling the first semiconductor device 10 and the second semiconductor device 11 is fixed on the semiconductor module 202.

[0053] First, the connection structure between the first semiconductor device 10 and the second semiconductor device 11 will be explained. For example... Figure 7 As shown, the connection structure between the first semiconductor device 10 and the second semiconductor device 11 is provided on the third side of the package 9 located on the side of the other semiconductor device in the first semiconductor device 10 and the second semiconductor device 11, which is arranged adjacent to each other. Specifically, on the fourth side of the package 9 in the first semiconductor device 10 and the second semiconductor device 11 opposite to the third side, two protrusions 9a spaced apart laterally are provided. On the third side of the package 9, two recesses 9b spaced apart laterally are provided, which can connect with the two protrusions 9a in the other semiconductor device. With this structure, when the first semiconductor device 10 and the second semiconductor device 11 are arranged adjacently, the two recesses 9b of the first semiconductor device 10 are adjacent to and can connect with the two protrusions 9a of the second semiconductor device 11. In addition, the fourth side is Figure 7 The left long side. In addition, the horizontal direction is... Figure 7 The left and right directions.

[0054] The protrusion 9a and the recess 9b do not need to have a dimensional relationship that generates an engaging force. Even if the protrusion 9a and the recess 9b are tightly fitted or have a minimal gap, the same effect can be achieved for the connection of the first semiconductor device 10 and the second semiconductor device 11.

[0055] Next, as Figure 8 As shown, on the lower surface of the package 9 in the first semiconductor device 10 and the second semiconductor device 11, there are protrusions 9c that protrude downwards from positions that are not mirror images of each other. Here, the positions that are not mirror images of each other only need to be the same positions in the first semiconductor device 10 and the second semiconductor device 11, for example, […]. Figure 8 The left end of the package. The protrusion 9c is on the lower surface of the package 9. Figure 8The heat sink 23 is continuously provided on the left end. In addition, a recess 23a is provided on the upper surface of the heat sink 23 for the protrusions 9c of the first semiconductor device 10 and the second semiconductor device 11 to fit into.

[0056] As described above, in the semiconductor module 202 according to Embodiment 5, a heat sink 23 is provided to fix and cool the first semiconductor device 10 and the second semiconductor device 11. On the lower surface of the package 9 in the first semiconductor device 10 and the second semiconductor device 11, a protrusion 9c protruding downward from a position that is not mirror-symmetrical to each other is provided. On the upper surface of the heat sink 23, a recess 23a is provided for the protrusion 9c of the first semiconductor device 10 and the second semiconductor device 11 to fit into.

[0057] Therefore, the semiconductor module 202 and the heat sink 23 can be securely fixed.

[0058] Furthermore, a connection structure capable of connecting to another semiconductor device is provided on the third side of the package 9 located on the side of the adjacent semiconductor device in the first semiconductor device 10 and the second semiconductor device 11. While there is a concern that the semiconductor module 202 might become larger if a protrusion 9c that engages with the recess 23a of the heat sink 23 is provided on the lower surface of the package 9, the large size of the semiconductor module 202 can be suppressed because the first semiconductor device 10 and the second semiconductor device 11 can be connected in a tightly closed state or with minimal gaps.

[0059] <Implementation Method 6> Next, the semiconductor module 202 according to Embodiment 6 will be described. Figure 9 This is a top view of the semiconductor module 202 according to Embodiment 6. Furthermore, in Embodiment 6, the same reference numerals are used for components that are the same as those described in Embodiments 1 to 5, and their descriptions are omitted.

[0060] like Figure 9 As shown, in embodiment 6, the semiconductor element 3 in the first semiconductor device 10 and the second semiconductor device 11 includes a plurality of switching elements. Therefore, the output of the semiconductor module 202 can be increased.

[0061] <Implementation Method 7> This embodiment applies the semiconductor module 202 described in embodiments 1 to 6 to a power conversion device 200. The application of the semiconductor module 202 described in embodiments 1 to 6 is not limited to a specific power conversion device, but the following description, as embodiment 7, illustrates the application of the semiconductor module 202 described in embodiments 1 to 6 to a three-phase inverter.

[0062] Figure 10This is a block diagram showing the structure of a power conversion system that uses the power conversion device 200 described in Embodiment 7.

[0063] Figure 10 The power conversion system shown consists of a power supply 100, a power conversion device 200, and a load 300. The power supply 100 is a DC power supply, providing DC power to the power conversion device 200. The power supply 100 can be constructed from various devices, such as a DC system, solar cells, or batteries, or from a rectifier circuit or AC / DC converter connected to an AC system. Alternatively, the power supply 100 can also be constructed from a DC / DC converter that converts DC power output from a DC system to a specified power.

[0064] The power conversion device 200 is a three-phase inverter connected between the power supply 100 and the load 300, which converts the DC power supplied from the power supply 100 into AC power and supplies AC power to the load 300. Figure 10 As shown, the power conversion device 200 includes: a main conversion circuit 201 that converts DC power into AC power and outputs it; and a control circuit 203 that outputs a control signal to the main conversion circuit 201 to control the main conversion circuit 201.

[0065] Load 300 is a three-phase motor driven by AC power supplied from power conversion device 200. Furthermore, load 300 is not limited to a specific application; it is a motor mounted on various electrical equipment, such as motors used in hybrid vehicles, electric vehicles, railway vehicles, elevators, or air conditioning equipment.

[0066] The following describes the power conversion device 200 in detail. The main conversion circuit 201 includes switching elements (not shown) and freewheeling diodes (not shown). By switching the switching elements, it converts the DC power supplied from the power supply 100 into AC power and provides it to the load 300. There are various specific circuit structures for the main conversion circuit 201, but the main conversion circuit 201 involved in this embodiment is a dual-level three-phase full-bridge circuit, which can be composed of 6 switching elements and 6 freewheeling diodes connected in reverse parallel with each switching element.

[0067] At least one of the switching elements and freewheeling diodes in the main conversion circuit 201 is constituted by a semiconductor module 202 equivalent to any of the embodiments 1 to 6 described above. In embodiment 7, as an example, the main conversion circuit 201 includes the semiconductor module 202 described in embodiment 1. The six switching elements are connected in series in pairs to form upper and lower arms, and each upper and lower arm constitutes each phase (U phase, V phase, W phase) of the full-bridge circuit. Furthermore, the output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0068] Furthermore, the main conversion circuit 201 includes a drive circuit (not shown) for driving each switching element. However, the drive circuit can be integrated into the semiconductor module 202, or it can be structured separately from the semiconductor module 202. The drive circuit generates drive signals for driving the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements in the main conversion circuit 201. Specifically, based on the control signal from the control circuit 203 (described later), a drive signal that turns the switching element on and a drive signal that turns the switching element off are output to the control electrodes of each switching element. When maintaining the on state of the switching element, the drive signal is a voltage signal above the threshold voltage of the switching element (on signal); when maintaining the off state of the switching element, the drive signal is a voltage signal below the threshold voltage of the switching element (off signal).

[0069] Control circuit 203 controls the switching elements of main conversion circuit 201 to supply the desired power to load 300. Specifically, based on the power to be supplied to load 300, the time (on-time) during which each switching element of main conversion circuit 201 should be in the on state is calculated. For example, main conversion circuit 201 can be controlled by PWM control that modulates the on-time of the switching elements according to the output voltage. Then, control commands (control signals) are output to the drive circuit of main conversion circuit 201, causing on signals to be output to the switching elements that should be in the on state at each time point, and off signals to be output to the switching elements that should be in the off state. The drive circuit outputs on or off signals as drive signals to the control electrodes of each switching element according to the control signal.

[0070] In the power conversion device 200 according to this embodiment, since the semiconductor module 202 is used as a switching element and freewheeling diode of the main conversion circuit 201, the durability can be improved.

[0071] In this embodiment, an example of applying the semiconductor module 202 described in Embodiments 1 to 6 to a dual-level three-phase inverter is given. However, the application of the semiconductor module 202 described in Embodiments 1 to 6 is not limited to this, and it can be applied to various power conversion devices. In this embodiment, a dual-level power conversion device is described, but it can also be a three-level or multi-level power conversion device. When supplying power to a single-phase load, the semiconductor module 202 described in Embodiments 1 to 6 can also be applied to a single-phase inverter. Furthermore, when supplying power to DC loads, the semiconductor module 202 described in Embodiments 1 to 6 can also be applied to a DC / DC converter or an AC / DC converter.

[0072] Furthermore, the power conversion device 200 that applies the semiconductor module 202 according to embodiments 1 to 6 is not limited to the case where the load is an electric motor. For example, it can also be used as a power supply device for electrical discharge machining, laser processing machine, induction heating cooker, or contactless power supply system, and can also be used as a power regulator for photovoltaic power generation system, energy storage system, etc.

[0073] While this disclosure has been described in detail, the foregoing description is exemplary in all respects and is not limiting. It should be understood that numerous variations not illustrated can be contemplated.

[0074] Furthermore, it is possible to freely combine various implementation methods, or to appropriately modify or omit certain implementation methods. Figure Labels

[0075] 3 Semiconductor element, 4 P electrode, 5 N electrode, 6 AC terminal, 7 P-side control terminal, 8 N-side control terminal, 9 Package, 9c Protrusion, 10 First semiconductor device, 11 Second semiconductor device, 20 P busbar, 20a Straight section, 20b First connection section, 21 N busbar, 21b Second connection section, 23 Heat sink, 23a Recess, 200 Power conversion device, 201 Main conversion circuit, 202 Semiconductor module, 203 Control circuit.

Claims

1. A semiconductor module, characterized in that, include: A first semiconductor device having a package containing hermetically sealed semiconductor elements and P and N electrodes protruding from the package; The second semiconductor device has a hermetically sealed semiconductor element package and P and N electrodes protruding from the package, and is arranged adjacent to the first semiconductor device in a mirror-symmetric manner with respect to the P and N electrodes of the first semiconductor device. A P-busbar connects the P-electrodes of the first semiconductor device and the second semiconductor device to each other; as well as The N-bus connects the N-electrodes of the first semiconductor device and the second semiconductor device to each other. The P busbar and the N busbar partially overlap when viewed from above.

2. The semiconductor module according to claim 1, characterized in that, The first semiconductor device and the second semiconductor device have a 2-in-1 structure. The packages of both the first semiconductor device and the second semiconductor device are formed into a quadrilateral shape when viewed from above. Both the first semiconductor device and the second semiconductor device also have an AC terminal protruding from the package. The AC terminal of the first semiconductor device is disposed on a second side opposite to the first side of the package on which the P electrode and the N electrode of the first semiconductor device are disposed. The AC terminal of the second semiconductor device is disposed on a second side opposite to the first side of the package on which the P electrode and the N electrode of the second semiconductor device are disposed.

3. The semiconductor module according to claim 2, characterized in that, It has three sets of the first semiconductor device and the second semiconductor device. The first semiconductor device and the second semiconductor device are arranged in adjacent groups.

4. The semiconductor module according to claim 3, characterized in that, Both the first semiconductor device and the second semiconductor device further include an N-side control terminal and a P-side control terminal protruding from the package. On the first side of the package in the first semiconductor device and the second semiconductor device, along the direction close to another adjacent semiconductor device, the N-side control terminal, the N-electrode, and the P-electrode are arranged in that order. On the second side of the package in the first semiconductor device and the second semiconductor device, along the direction close to the other semiconductor device, the AC terminal and the P-side control terminal are arranged in that order. The first semiconductor device and the second semiconductor device are connected in parallel such that, when viewed from above, the overlapping portions of the P busbar and the N busbar extend in a straight line.

5. The semiconductor module according to claim 2, characterized in that, A portion of the N-electrode and AC terminal of the first and second semiconductor devices protrudes from a third side of the package located on the side of another semiconductor device in an adjacent configuration.

6. The semiconductor module according to any one of claims 1 to 5, characterized in that, Both the P-bus and the N-bus have: a straight portion extending parallel to the direction in which the first semiconductor device and the second semiconductor device are arranged adjacent to each other; a first connecting portion connecting the P-electrode to the straight portion; and a second connecting portion connecting the N-electrode to the straight portion. The first connecting portion and the second connecting portion are connected to the straight portion at the center between the first connecting portion and the second connecting portion.

7. The semiconductor module according to any one of claims 1 to 6, characterized in that, A heat sink capable of fixing and cooling the first semiconductor device and the second semiconductor device On the lower surface of the package in the first semiconductor device and the second semiconductor device, there is a protrusion that protrudes downward from a position that is not a mirror image of each other. On the upper surface of the heat sink, there is a recess for the protrusions of the first semiconductor device and the second semiconductor device to engage.

8. The semiconductor module according to claim 7, characterized in that, A connection structure capable of connecting to the other semiconductor device is provided on the third side of the package located on the side of the other semiconductor device in an adjacent configuration, in the first semiconductor device and the second semiconductor device.

9. The semiconductor module according to any one of claims 1 to 8, characterized in that, The semiconductor elements in the first semiconductor device and the second semiconductor device include a plurality of switching elements.

10. The semiconductor module according to any one of claims 1 to 9, characterized in that, The semiconductor material of the semiconductor element is SiC.

11. A power conversion device, characterized in that, include: The main conversion circuit has a semiconductor module according to any one of claims 1 to 10, and converts the input power and outputs it. as well as A control circuit that outputs control signals to the main conversion circuit to control the main conversion circuit.

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