Display device and method for manufacturing the same

Abstract

The display device includes light emitting elements disposed on a pixel circuit layer, light extraction structures spaced apart from one another on the pixel circuit layer to overlie the light emitting elements, first bank layers disposed between the light extraction structures, and a reflective layer disposed between the light extraction structures and the first bank layers to at least surround side surfaces of the individual light extraction structures. Each of the light emitting elements is covered by a corresponding one of the light extraction structures. The side surfaces of the individual light extraction structures include substantially inverted conical sloped surfaces.

Description

Technical Field

[0001] The disclosure relates to a display device and a method for manufacturing the display device. Background Technology

[0002] A display device may include pixels, and each pixel may emit light. The display device can display an image by combining the light emitted from the pixels.

[0003] Research is underway to improve the light output efficiency of pixels included in display devices.

[0004] It will be understood that this background section is intended in part to provide useful background for understanding the art. However, this background section may also include ideas, concepts, or knowledge that were known or understood prior to the corresponding valid submission date of the subject matter not disclosed herein by a person skilled in the art. Summary of the Invention

[0005] Technical issues The purpose of this disclosure is to provide a display device with improved light output efficiency.

[0006] Another objective of this disclosure is to provide a method for manufacturing the display device.

[0007] Technical solution According to the disclosed embodiments, the display device may include: a plurality of light-emitting elements disposed on a pixel circuit layer; a plurality of light-extracting structures spaced apart from each other and stacked with the plurality of light-emitting elements on the pixel circuit layer; a first dam layer disposed between the plurality of light-extracting structures; and a reflective layer disposed between the plurality of light-extracting structures and the first dam layer, the reflective layer at least surrounding a side surface of each of the plurality of light-extracting structures, wherein each of the plurality of light-emitting elements is covered by a corresponding light-extracting structure among the plurality of light-extracting structures, and the side surface of each of the plurality of light-extracting structures may include a substantially inverted conical inclined surface.

[0008] In an embodiment, each of the plurality of light extraction structures may include a negative photoresist material.

[0009] In this embodiment, the reflective layer may not be disposed between the lower surface of each of the plurality of light extraction structures and the pixel circuit layer.

[0010] In an embodiment, each of the plurality of light extraction structures may surround at least a portion of a side surface adjacent to the upper surface of a corresponding light-emitting element among the plurality of light-emitting elements.

[0011] In one embodiment, each of the plurality of light extraction structures may include scattering particles.

[0012] In an embodiment, the upper edge of each of the plurality of light extraction structures may have a substantially circular (rounded) shape in cross-section.

[0013] In an embodiment, the side surface between the lower surface and the upper edge of each of the plurality of light extraction structures can be a substantially inverted conical inclined surface in cross-section.

[0014] In one embodiment, the reflective layer may extend from the side surface of each of the plurality of light extraction structures to further cover the upper edge of each of the plurality of light extraction structures and the portion of the upper surface adjacent to the upper edge.

[0015] In one embodiment, the reflective layer may cover the lowest surface of the first embankment layer.

[0016] In one embodiment, the side surfaces of the reflective layer and the first dam layer can be aligned with each other on the upper surface of each of the plurality of light extraction structures.

[0017] In one embodiment, the reflective layer may cover the portion of the upper edge adjacent to the side surface of each of the plurality of light extraction structures, but may not cover the upper surface of each of the plurality of light extraction structures.

[0018] In one embodiment, the lowest surface of the first embankment may not be covered by the reflective layer.

[0019] In an embodiment, the display device may further include: a plurality of light conversion patterns spaced apart from each other, and superimposed on a plurality of light extraction structures.

[0020] In an embodiment, the display device may further include: a second dam layer stacked with the first dam layer to surround each of the plurality of light conversion patterns; and a light reflective layer disposed between the plurality of light conversion patterns and the second dam layer.

[0021] According to the disclosed embodiments, a method for manufacturing a display device may include the following steps: forming a plurality of light-emitting elements on a pixel circuit layer; forming a plurality of light extraction structures spaced apart from each other on the pixel circuit layer, the plurality of light extraction structures being stacked with the plurality of light-emitting elements; forming a reflective layer entirely on the pixel circuit layer, the reflective layer covering the plurality of light extraction structures; forming a first dam layer entirely on the reflective layer, the first dam layer covering the reflective layer; etching the first dam layer in a region that overlaps with at least a portion of the upper surface of each of the plurality of light extraction structures; and using the first dam layer as a mask to etch the reflective layer, wherein each of the plurality of light-emitting elements may be surrounded by a corresponding light extraction structure among the plurality of light extraction structures, and the side surface of each of the plurality of light extraction structures may include a substantially inverted conical inclined surface.

[0022] In an embodiment, the step of forming multiple light extraction structures may include: forming an outer coating layer entirely on the pixel circuit layer, the outer coating layer covering multiple light-emitting elements; and forming multiple light extraction structures by exposing and developing the outer coating layer.

[0023] In an embodiment, the outer coating may include a negative photoresist material.

[0024] According to the disclosed embodiments, a method of manufacturing a display device may include the following steps: forming a plurality of light-emitting elements on a pixel circuit layer; forming a plurality of light-extracting structures spaced apart from each other and stacked with the plurality of light-emitting elements on the pixel circuit layer; forming a reflective layer entirely on the pixel circuit layer, the reflective layer covering the plurality of light-extracting structures; etching the reflective layer in a region that overlaps with at least a portion of the upper surface of each of the plurality of light-extracting structures; forming a first dam layer entirely on the pixel circuit layer, the first dam layer covering the plurality of light-extracting structures and the reflective layer; and etching the first dam layer in a region that overlaps with at least a portion of the upper surface of each of the plurality of light-extracting structures, wherein each of the plurality of light-emitting elements may be surrounded by a corresponding light-extracting structure among the plurality of light-extracting structures, and the side surface of each of the plurality of light-extracting structures may include a substantially inverted conical inclined surface.

[0025] In an embodiment, the step of etching the reflective layer may include anisotropic dry etching of the reflective layer.

[0026] In one embodiment, during the step of etching the reflective layer, a portion of the reflective layer disposed between multiple light extraction structures may be etched.

[0027] Beneficial effects The display device according to the disclosed embodiments may include: a plurality of light extraction structures spaced apart from each other to be stacked with a plurality of light-emitting elements; and a reflective layer surrounding at least a side surface of each of the plurality of light extraction structures. Each of the plurality of light-emitting elements is covered by a corresponding light extraction structure among the plurality of light extraction structures, and the side surface of each of the plurality of light extraction structures may include a substantially inverted conical inclined surface. Therefore, the light output efficiency of light emitted from the plurality of light-emitting elements can be improved by using the plurality of light extraction structures and the reflective layer.

[0028] The method for manufacturing a display device according to the disclosed embodiments can provide an efficient method for manufacturing the above-described display device. Attached Figure Description

[0029] Figure 1 This is a block diagram illustrating a display device according to a disclosed embodiment; Figure 2 It is shown that it includes Figure 1 A block diagram of one of the subpixels in a display device; Figure 3 It shows the composition Figure 1 A schematic plan view of the display panel of the display device; Figure 4 It is shown Figure 3 A schematic cross-sectional view of an embodiment of the display panel; Figure 5 It is shown Figure 3 A schematic cross-sectional view of an embodiment of the display panel; Figure 6 It is shown that it includes Figure 3 A schematic plan view of an embodiment of one pixel in a display panel; Figure 7 and Figure 8 It shows the basis Figure 6 A schematic cross-sectional view of the pixels in an embodiment; Figure 9 and Figure 10 It shows the basis Figure 6 A schematic cross-sectional view of an example of pixel modification in an embodiment; Figure 11 and Figure 12 It shows the basis Figure 6 A schematic cross-sectional view of an example of pixel modification in an embodiment; Figure 13 It is shown that it includes Figure 3 A schematic plan view of a second embodiment of one pixel in a display panel; Figure 14 It is along Figure 13 A schematic cross-sectional view taken by line X2-X2'; Figure 15 It is along Figure 13 A schematic cross-sectional view taken by line Y2-Y2'; Figure 16 It is shown that it includes Figure 3 A schematic plan view of a third embodiment of a pixel in a display panel; Figure 17 It is along Figure 16 A schematic cross-sectional view taken by line X3-X3'; Figures 18 to 24 This is a diagram illustrating a method of manufacturing a display device according to a disclosed embodiment; Figures 25 to 28 This is a diagram illustrating a method of manufacturing a display device according to an embodiment; Figure 29 This is a block diagram illustrating a display system according to an embodiment; and Figures 30 to 33 It is shown Figure 29 A schematic perspective view illustrating an application example of the display system. Detailed Implementation

[0030] In the following, embodiments according to the disclosure are described in detail with reference to the accompanying drawings. It should be noted that in the following description, only the parts necessary for understanding the operation according to the disclosure are described, and descriptions of other parts may be omitted so as not to obscure the subject matter of the disclosure. The disclosure may be implemented in other forms and is not limited to the embodiments described herein. However, the embodiments described herein are provided for detailed description to enable those skilled in the art to readily implement the technical spirit of the disclosure.

[0031] Throughout this specification, the phrase "connected" to another part includes not only cases where the part is "directly connected," but also cases where the part is "indirectly connected" and another element is disposed between the two parts. The terminology used herein is for describing a given embodiment and is not intended to limit the disclosure.

[0032] When the terms “comprising,” “including,” “having,” and variations thereof are used in this specification, they indicate the presence of the stated features, integrals, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0033] "At least one of X, Y, and Z (species / beings)" and "at least one of the groups consisting of X, Y, and Z (species / beings)" can be interpreted as one X, one Y, one Z, or any combination of two or more of X, Y, and Z (e.g., XYZ, XYY, YZ, and ZZ). Here, "and / or" includes all combinations of one or more corresponding constructs.

[0034] As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “one,” and “the” are also intended to include the plural forms.

[0035] In the specification and claims, for purposes of meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" can be understood to mean "A, B, or A and B". The terms "and" and "or" can be used in a conjunctional or disjunctive sense and can be understood as equivalent to "and / or".

[0036] In the specification and claims, for the purposes of their meaning and interpretation, the phrase “at least one of…” is intended to include the meaning of “at least one of the group consisting of…”. For example, “at least one of A and B” can be understood to mean “A, B, or A and B”.

[0037] Various components may be described here using terms such as "first" and "second," but these components are not limited to these terms. These terms are used to distinguish one component from another. Therefore, without departing from the scope of this disclosure, "first component" may refer to "second component."

[0038] Spatial relative terms such as “below” and “above” can be used for descriptive purposes to describe the relationship between one element or feature and another (additional) element or feature, as shown in the accompanying drawings. In addition to the directions depicted in the drawings, spatial relative terms are intended to include other directions of use, operation, and / or manufacture. For example, when the device shown in the drawings is inverted, the element depicted as positioned “below” another element or feature is positioned in a direction “above” said other element or feature. Therefore, in embodiments, the term “below” can include both above and below directions. The device may face other directions (e.g., rotated 90 degrees or in other directions), and thus the spatial relative terms used herein should be interpreted accordingly.

[0039] The terms “overlay with” or “overlaying” mean that the first object may be on top of, below, or to the side of the second object, or vice versa. Additionally, the term “overlay with” may include cascading, stacking, facing or oriented towards, extending over, covering or partially covering, or any other suitable term that will be understood and appreciated by one of ordinary skill in the art.

[0040] The terms "facing" and "oriented" mean that the first element can be directly or indirectly opposite the second element. When a third element is placed between the first and second elements, the first and second elements, although still facing each other, can be understood as being indirectly opposite each other.

[0041] When an element is described as “not stacked” with another element or a variation thereof, this may include elements spaced apart from each other, offset from each other, or deviated from each other, or any other suitable terminology as will be understood and appreciated by one of ordinary skill in the art.

[0042] Various embodiments are described with reference to the accompanying drawings, which schematically illustrate preferred embodiments. Therefore, the intended shapes may vary, for example, depending on tolerances and / or manufacturing techniques. Consequently, the embodiments disclosed herein should not be construed as limited to the shapes shown and should be interpreted as including variations in shape, for example, that occur due to manufacturing processes. As noted above, the shapes shown in the drawings may not represent the actual shape of areas of the device, and the embodiments are not limited thereto.

[0043] As used herein, “about” or “approximately” includes the stated value and means: within an acceptable deviation of the stated value as determined by one of ordinary skill in the art, taking into account the measurement in question and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0044] Unless otherwise defined or implied herein, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which they pertain. It will also be understood that terms (such as those defined in common dictionaries) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formalized sense unless expressly defined herein.

[0045] With regard to functional blocks, units, and / or modules, embodiments can be described and illustrated in the accompanying drawings.

[0046] Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, etc.) that can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques.

[0047] Where blocks, units, and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled by software (e.g., microcode) to perform the various functions discussed herein, and can optionally be driven by firmware and / or software.

[0048] It is also anticipated that each block, unit, and / or module can be implemented by dedicated hardware, or can be implemented as a combination of dedicated hardware for performing some functions and processors (e.g., one or more programmed microprocessors and associated circuitry) for performing other functions.

[0049] Without departing from the scope of disclosure, each block, unit, and / or module of the embodiments may be physically divided into two or more interacting and separate blocks, units, and / or modules.

[0050] Furthermore, without departing from the scope of disclosure, the blocks, units, and / or modules of the embodiments may be physically combined into more complex blocks, units, and / or modules.

[0051] Figure 1 This is a block diagram illustrating a display device according to a disclosed embodiment.

[0052] Reference Figure 1The display device DD may include a display panel DP, a gate driver 120, a data driver 130, a voltage generator 140, and a controller 150.

[0053] The display panel DP may include sub-pixels SP. Sub-pixels SP can be connected to gate driver 120 via first gate line GL1 to m-th gate line GLm. Sub-pixels SP can be connected to data driver 130 via first data line DL1 to n-th data line DLn.

[0054] Subpixels (SPs) can produce two or more colors of light. For example, each subpixel SP can produce light such as red, green, blue, cyan, magenta, or yellow.

[0055] Two or more subpixels in subpixel SP can form a pixel PXL. For example, as shown in the image. Figure 1 As shown, pixel PXL can include three sub-pixels. Pixel PXL can emit light of various colors and brightnesses based on the combination of light emitted from the sub-pixels included in pixel PXL.

[0056] Gate driver 120 is connected to sub-pixels SP arranged (or configured) in the row direction via first gate lines GL1 to m-th gate lines GLm. Gate driver 120 may output gate signals to first gate lines GL1 to m-th gate lines GLm in response to gate control signal GCS. In embodiments, within the spirit and scope of the disclosure, gate control signal GCS may include a start signal indicating the start of each frame, a horizontal synchronization signal, etc.

[0057] The gate driver 120 may be disposed on one side of the display panel DP. However, the embodiments are not limited thereto. For example, the gate driver 120 may be divided into two or more physically and / or logically separated drivers, and such drivers may be disposed on one side of the display panel DP and on the opposite side of the display panel DP. As described above, according to the embodiments, the gate driver 120 may be disposed around the display panel DP in various shapes.

[0058] Data driver 130 is connected to sub-pixels SP arranged in the column direction via first data lines DL1 to nth data lines DLn. Data driver 130 receives image data DATA and data control signal DCS from controller 150. Data driver 130 operates in response to data control signal DCS. In embodiments, within the spirit and scope of the disclosure, data control signal DCS may include a source start signal, a source shift clock, a source output enable signal, etc.

[0059] The data driver 130 can receive voltage from the voltage generator 140. The data driver 130 can use the received voltage to apply a data signal having a grayscale voltage corresponding to the image data DATA to the first data lines DL1 to the nth data line DLn. When a gate signal is applied to each of the first gate lines GL1 to the mth gate line GLm, the data signal corresponding to the image data DATA can be applied to the data lines DL1 to DLn. Therefore, the sub-pixel SP can generate light corresponding to the data signal, and the display panel DP can display an image.

[0060] In one embodiment, gate driver 120 and data driver 130 may include complementary metal-oxide-semiconductor (CMOS) circuit elements.

[0061] Voltage generator 140 can operate in response to a voltage control signal VCS from controller 150. Voltage generator 140 is configured to generate a voltage and provide the generated voltage to components of display device DD (such as gate driver 120, data driver 130, and controller 150). Voltage generator 140 can generate a voltage by receiving an input voltage from outside display device DD and modulating the received voltage.

[0062] Voltage generator 140 can generate a first electrical voltage and a second electrical voltage. The generated first and second electrical voltages can be provided to the sub-pixel SP via power line PL. In an embodiment, at least one of the first and second electrical voltages can be provided from outside the display device DD.

[0063] Voltage generator 140 can provide various voltages and / or signals. For example, voltage generator 140 can provide one or more initialization voltages applied to sub-pixel SP. For example, during sensing operations for sensing the electrical characteristics of the transistors and / or light-emitting elements of sub-pixel SP, selectable reference voltages can be applied to first data lines DL1 to nth data lines DLn, and voltage generator 140 can generate and transmit the reference voltages to data driver 130. For example, during display operations for displaying an image on display panel DP, a common pixel control signal can be applied to sub-pixel SP, and voltage generator 140 can generate the pixel control signal. In an embodiment, voltage generator 140 can provide pixel control signals to sub-pixel SP via pixel control line PXCL. Figure 1 In this embodiment, the pixel control line PXCL is connected between the voltage generator 140 and the display panel DP, but the embodiment is not limited to this. For example, the pixel control line PXCL can be connected between the gate driver 120 and the display panel DP. In this case, the pixel control signal can be transmitted from the voltage generator 140 to the pixel control line PXCL through the gate driver 120.

[0064] The controller 150 controls the overall operation of the display device DD. The controller 150 receives input image data IMG and its corresponding control signal CTRL from an external source. The controller 150 can provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS in response to the control signal CTRL.

[0065] The controller 150 can convert the input image data IMG to fit the display device DD or display panel DP, and output image data DATA. In an embodiment, the controller 150 can output image data DATA by aligning the input image data IMG to fit the sub-pixels SP of the row unit.

[0066] Two or more of the components—data driver 130, voltage generator 140, and controller 150—can be mounted on a single integrated circuit. For example... Figure 1 As shown, the data driver 130, voltage generator 140, and controller 150 may be included in a driver integrated circuit (DIC). In this case, the data driver 130, voltage generator 140, and controller 150 may be functionally separated components within a single driver integrated circuit (DIC). In other embodiments, at least one of the data driver 130, voltage generator 140, and controller 150 may be configured as a component distinct from the driver integrated circuit (DIC).

[0067] Figure 2 It is shown that it includes Figure 1 A block diagram of one of the subpixels in a display device. Figure 2 In Figure 1 Among the sub-pixels SP, sub-pixels SPij arranged in the i-th row (i is an integer greater than or equal to 1 and less than or equal to m) and j-th column (j is an integer greater than or equal to 1 and less than or equal to n) are shown as an example.

[0068] Reference Figure 2 Subpixel SPij may include subpixel circuit SPC and light-emitting element LD.

[0069] The light-emitting element (LD) is connected between the first power voltage node VDDN and the second power voltage node VSSN. The first power voltage node VDDN is connected to... Figure 1 One of the power lines PL receives the first power voltage. The second power voltage node VSSN is connected to... Figure 1 The first power line is another power line PL and receives a second power voltage. The first power voltage may have a higher voltage level than the second power voltage.

[0070] The light-emitting element LD is connected between the anode electrode AE ​​and the cathode electrode CE. The anode electrode AE ​​can be connected to the first power voltage node VDDN via a sub-pixel circuit SPC. For example, the anode electrode AE ​​can be connected to the first power voltage node VDDN via one or more transistors included in the sub-pixel circuit SPC. The cathode electrode CE can be connected to a second power voltage node VSSN. The light-emitting element LD is configured to emit light according to the current flowing from the anode electrode AE ​​to the cathode electrode CE.

[0071] Sub-pixel circuits (SPCs) can be connected to Figure 1 The i-th gate line GLi among the first gate line GL1 to the m-th gate line GLm and Figure 1 The first data line DL1 to the nth data line DLn, specifically the j-th data line DLj. In response to the gate signal received via the i-th gate line GL1, the sub-pixel circuit SPC can control the light-emitting element LD to emit light based on the data signal received via the j-th data line DLj. In an embodiment, the sub-pixel circuit SPC can also be connected to... Figure 1 The pixel control line PXCL. In this case, the sub-pixel circuit SPC can further control the light-emitting element LD in response to the pixel control signal received through the pixel control line PXCL.

[0072] For such an operation, the subpixel circuit (SPC) may include circuit elements (e.g., transistors and one or more capacitors).

[0073] The transistors of the sub-pixel circuit SPC may include P-type transistors and / or N-type transistors. In an embodiment, the transistors of the sub-pixel circuit SPC may include metal-oxide-semiconductor field-effect transistors (MOSFETs). In an embodiment, within the spirit and scope of the disclosure, the transistors of the sub-pixel circuit SPC may include amorphous silicon semiconductors, monocrystalline silicon semiconductors, polycrystalline silicon semiconductors, oxide semiconductors, etc.

[0074] Figure 3 It shows the composition Figure 1 A schematic plan view of the display panel of the display device.

[0075] Reference Figure 3 The display panel DP can include a display area DA and a non-display area NDA. The display panel DP displays the image through the display area DA. The non-display area NDA is positioned around the display area DA.

[0076] The display panel DP may include subpixels SP disposed in the display area DA. The subpixels SP may be arranged along a first direction DR1 and a second direction DR2 that intersects (or crosses) the first direction DR1. For example, the subpixels SP may be arranged in a matrix along the first direction DR1 and the second direction DR2. As another example, the subpixels SP may be arranged in a zigzag pattern along the first direction DR1 and the second direction DR2. The arrangement of the subpixels SP may vary depending on the embodiment. The first direction DR1 may be a row direction, and the second direction DR2 may be a column direction.

[0077] Two or more subpixels within a subpixel SP can form a pixel PXL. Figure 3 In this embodiment, pixel PXL may include three sub-pixels SP1, SP2, and SP3, but the embodiment is not limited thereto. For example, pixel PXL may include two sub-pixels. In the following description, it is assumed that pixel PXL may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3.

[0078] Each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can produce light of one of various colors, such as red, green, blue, cyan, magenta, and yellow. In the following description, for clarity and brevity, it is assumed that the first sub-pixel SP1 is configured to produce red light, the second sub-pixel SP2 is configured to produce green light, and the third sub-pixel SP3 is configured to produce blue light.

[0079] Each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may include at least one light-emitting element configured to generate light. In one embodiment, the light-emitting elements of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may generate light of the same color. For example, the light-emitting elements of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may generate blue light. In other embodiments, the light-emitting elements of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may generate light of different colors. For example, the light-emitting elements of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may generate red, green, and blue light, respectively.

[0080] As a display panel DP, LED display panels that utilize micron- or nano-sized light-emitting diodes as light-emitting elements can be used, as well as self-emitting display panels such as OLED display panels that use organic light-emitting diodes as light-emitting elements.

[0081] The components used to control the subpixel SP can be located in the non-display area NDA. Lines connected to the subpixel SP (e.g., Figure 1 The first gate line GL1 to the m-th gate line GLm, the first data line DL1 to the n-th data line DLn, the power line PL, and the pixel control line PXCL can be set in the non-display area NDA.

[0082] Figure 1 At least one of the gate driver 120, data driver 130, voltage generator 140, and controller 150 can be disposed in the non-display area NDA of the display panel DP. In an embodiment, the gate driver 120 can be disposed in the non-display area NDA. In this case, the data driver 130, voltage generator 140, and controller 150 can be implemented as follows: Figure 1 The driver integrated circuit (DIC) is separate from the display panel (DP), and the driver integrated circuit (DIC) can be connected to a line disposed in the non-display area (NDA). In other embodiments, the gate driver 120 can be implemented together with the data driver 130, voltage generator 140, and controller 150 as a single integrated circuit separate from the display panel (DP).

[0083] In embodiments, the display area DA can have various shapes. The display area DA can have a closed-loop shape with sides including straight lines and / or curves. For example, within the spirit and scope of the disclosure, the display area DA can have shapes such as polygons, circles, semicircles, ellipses, etc.

[0084] In one embodiment, the display panel DP may have a flat display surface. In other embodiments, the display panel DP may have a display surface that is at least partially rounded. In another embodiment, the display panel DP may be flexible, foldable, or rollable. In this case, the display panel DP and / or the substrate of the display panel DP may include a material with flexible properties.

[0085] Figure 4 It is shown Figure 3 A schematic cross-sectional view of an embodiment of the display panel.

[0086] Reference Figure 4 The display panel DP may include a substrate SUB and a pixel circuit layer PCL, a display element layer DPL, and an optical function layer LFL that are sequentially stacked on the substrate SUB on a third direction DR3 that intersects (or crosses) the first direction DR1 and the second direction DR2.

[0087] The substrate SUB can be formed of an insulating material, such as glass or resin. For example, the substrate SUB may include a glass substrate. As another example, the substrate SUB may include a polyimide (PI) substrate. As yet another example, the substrate SUB may include a silicon wafer substrate formed using semiconductor processes.

[0088] In the embodiments, the substrate SUB can be formed of a flexible material that can be bent or folded, and can have a single-layer or multi-layer structure. For example, the flexible material may include at least one selected from polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate. However, the embodiments are not limited thereto.

[0089] A pixel circuit layer (PCL) is disposed on a substrate (SUB). The pixel circuit layer (PCL) may include an insulating layer and semiconductor and conductive patterns disposed between the insulating layers. Within the spirit and scope of the disclosure, the conductive patterns of the pixel circuit layer (PCL) can be used as circuit elements, lines, etc.

[0090] The circuit elements of the pixel circuit layer PCL may include Figure 3 Each of the sub-pixels in SP Figure 2 The sub-pixel circuit (SPC). In other words, the circuit elements of the pixel circuit layer (PCL) can be configured as transistors of the sub-pixel circuit (SPC) and one or more capacitors.

[0091] The lines in the pixel circuit layer (PCL) may include lines connected to the sub-pixels (SP). The lines in the PCL may also include various signal lines and / or voltage lines to drive the display element layer (DPL).

[0092] The display element layer (DPL) is disposed on the pixel circuit layer (PCL). The display element layer (DPL) may include the light-emitting elements of the sub-pixels (SP).

[0093] An optical functional layer (LFL) may be disposed on the display element layer (DPL). The LFL may include a light conversion pattern with color conversion particles and / or scattering particles. For example, the color conversion particles may include quantum dots. Quantum dots can change the wavelength (or color) of light emitted from the display element layer (DPL). The LFL may also include a light scattering pattern with scattering particles. In embodiments, the light conversion pattern and light scattering pattern may be omitted.

[0094] The optical functional layer (LFL) may also include a color filter layer containing a color filter. The color filter can selectively transmit light of a specific wavelength (or a specific color). In some embodiments, the color filter layer may be omitted.

[0095] A window for protecting the exposed surface (or top surface) of the display panel (DP) can be disposed on the light functional layer (LFL). The window protects the display panel (DP) from external impacts. The window can be bonded or attached to the light functional layer (LFL) using optically transparent adhesive (or bonding) components. The window can have a multi-layered structure selected from glass substrates, plastic films, and plastic substrates. The multi-layered structure can be formed through a continuous process or an adhesive process using adhesive layers. All or part of the window can be flexible.

[0096] Figure 5 It is shown Figure 3 A schematic cross-sectional view of an embodiment of the display panel.

[0097] Reference Figure 5 The display panel DP' may include a substrate SUB, a pixel circuit layer PCL, a display element layer DPL, an input sensing layer ISL, and a light function layer LFL. The substrate SUB, pixel circuit layer PCL, display element layer DPL, and light function layer LFL can be connected to a reference... Figure 4 The substrate (SUB), pixel circuit layer (PCL), display element layer (DPL), and optical function layer (LFL) described are constructed in the same (or similar) manner. Therefore, descriptions of repeated content can be omitted.

[0098] The input sensing layer (ISL) can sense user input on the upper surface (or display surface) of the display panel (DP'). The input sensing layer (ISL) may include components suitable for sensing external objects, such as the user's hand or pen. For example, the input sensing layer (ISL) may include touch electrodes.

[0099] Figure 6 It is shown that it includes Figure 3 A schematic plan view of an embodiment of one pixel in a display panel.

[0100] Reference Figure 6 Pixel PXL may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be arranged in a first direction DR1. However, the arrangement of pixel PXL is not limited to this and can be varied according to embodiments. For example, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be arranged in a zigzag pattern.

[0101] The first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 can be respectively disposed in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The first anode electrode AE1 can be configured to be connected to the first sub-pixel SP1. Figure 2 Sub-pixel circuit SPC Figure 2The first anode electrode is AE. The second anode electrode AE2 can be configured as the anode electrode AE ​​connected to the sub-pixel circuit SPC of the second sub-pixel SP2. The third anode electrode AE3 can be configured as the anode electrode AE ​​connected to the sub-pixel circuit SPC of the third sub-pixel SP3.

[0102] The cathode electrode CE can be spaced apart from the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3. The cathode electrode CE can be positioned at the same height as the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3. The cathode electrode CE can be spaced apart from the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 in the second direction DR2.

[0103] In an embodiment, the cathode electrode CE can extend in the first direction DR1 and can be used as a common electrode for pixel PXL and other pixels adjacent to pixel PXL. Although not shown, the cathode electrode CE can extend not only in the first direction DR1 but also in the second direction DR2 and can be used as a common electrode for... Figure 3 All common electrodes in the sub-pixel SP. As mentioned above, the cathode electrode CE can have various shapes.

[0104] The first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 can be disposed on the first anode electrode AE1, the second anode electrode AE2, the third anode electrode AE3, and the cathode electrode CE. The first light-emitting element LD1 can be electrically connected to the first anode electrode AE1 and the cathode electrode CE. The first light-emitting element LD1 can be configured to be connected to the sub-pixel circuit SPC of the first sub-pixel SP1. Figure 2 The first light-emitting element is LD. The second light-emitting element LD2 can be electrically connected to the second anode electrode AE2 and the cathode electrode CE. The second light-emitting element LD2 can be configured as a light-emitting element LD connected to the sub-pixel circuit SPC of the second sub-pixel SP2. The third light-emitting element LD3 can be electrically connected to the third anode electrode AE3 and the cathode electrode CE. The third light-emitting element LD3 can be configured as a light-emitting element LD connected to the sub-pixel circuit SPC of the third sub-pixel SP3.

[0105] The first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 can be inorganic light-emitting diodes that include inorganic light-emitting materials. However, the embodiments are not limited to this; for example, organic light-emitting diodes can be used.

[0106] Figure 7 and Figure 8 It shows the basis Figure 6 A schematic cross-sectional view of the pixels in an embodiment. Figure 7 It is along Figure 6A schematic cross-sectional view taken by line X1-X1', and Figure 8 It is along Figure 6 A schematic cross-sectional view taken from line Y1-Y1'.

[0107] Reference Figure 6 and Figure 7 The pixel circuit layer PCL, the display element layer DPL, and the light function layer LFL can be sequentially arranged on the substrate SUB.

[0108] The pixel circuit layer (PCL) may include insulating layers, semiconductor patterns, and conductive patterns stacked on top of each other on a substrate (SUB). The insulating layers may include a buffer layer (BFL), one or more interlayer insulating layers (ILDs), and one or more passivation layers (PSV1 and PSV2). The semiconductor patterns and conductive patterns may be located between the insulating layers. The conductive patterns may include at least one of copper (Cu), molybdenum (Mo), tungsten (W), neodymium aluminum (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0109] For reference Figure 2 As described, each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 Figure 2 The sub-pixel circuit SPC may include transistors and one or more capacitors. The semiconductor and conductive patterns of the pixel circuit layer PCL can be used as the transistors and capacitors of the sub-pixel circuit SPC. The conductive patterns of the pixel circuit layer PCL can also be used as lines (e.g., Figure 1 The first gate line GL1 to the m-th gate line GLm, the first data line DL1 to the n-th data line DLn, the power line PL, and the pixel control line PXCL.

[0110] A buffer layer (BFL) can be disposed on one or more surfaces of the substrate (SUB). The buffer layer (BFL) can be used to prevent impurities from diffusing into circuit elements and lines included in the pixel circuit layer (PCL). The buffer layer (BFL) may include an inorganic insulating layer comprising inorganic materials. In embodiments, the buffer layer (BFL) may include at least one metal oxide such as silicon nitride, silicon oxide, silicon oxynitride, and aluminum oxide. The buffer layer (BFL) can be a single layer or multiple layers. When the buffer layer (BFL) is configured as multiple layers, each layer may be formed of the same material or may be formed of different materials.

[0111] In one embodiment, one or more barrier layers may be disposed between the substrate SUB and the buffer layer BFL. Each of the barrier layers may comprise polyimide.

[0112] Transistor T_SP1 can be disposed on the buffer layer BFL. Transistor T_SP1 can be one of the transistors in the sub-pixel circuit SPC included in the first sub-pixel SP1. For example, transistor T_SP1 can be a transistor in the sub-pixel circuit SPC that is connected to the first anode electrode AE1.

[0113] Transistor T_SP1 may include a semiconductor pattern SCP, a gate electrode GE, a first terminal ET1, and a second terminal ET2. The first terminal ET1 may be one of the source electrode and the drain electrode, and the second terminal ET2 may be the other of the source electrode and the drain electrode. For example, the first terminal ET1 may be the source electrode, and the second terminal ET2 may be the drain electrode.

[0114] A semiconductor pattern SCP can be disposed on a buffer layer BFL. The semiconductor pattern SCP may include a first contact region contacting a first terminal ET1 and a second contact region contacting a second terminal ET2. The region between the first and second contact regions may be a channel region. The channel region may be superimposed on the gate electrode GE of transistor T_SP1. The channel region may be an undoped semiconductor pattern and may be an intrinsic semiconductor. The first and second contact regions may be doped semiconductor patterns. For example, a p-type impurity may be used as the impurity, but the embodiment is not limited thereto.

[0115] Semiconductor pattern SCP can include one of various types of semiconductors (e.g., amorphous silicon semiconductors, monocrystalline silicon semiconductors, polycrystalline silicon semiconductors, low-temperature polycrystalline silicon semiconductors, and oxide semiconductors).

[0116] Interlayer insulating layers (ILDs) stacked sequentially on top of each other can be disposed on a semiconductor pattern (SCP). The ILDs can be inorganic insulating layers comprising inorganic materials. For example, each of the ILDs may include at least one metal oxide such as silicon nitride, silicon oxide, silicon oxynitride, and aluminum oxide. However, the ILDs are not limited to this. For example, one of the ILDs may include an organic insulating layer comprising organic materials.

[0117] Interlayer insulating layers (ILDs) electrically isolate conductive patterns and / or semiconductor patterns disposed between interlayer insulating layers (ILDs). For example, an interlayer insulating layer (ILD) may include a gate insulating layer (GI) disposed on a semiconductor pattern (SCP). The gate insulating layer (GI) may be disposed between the semiconductor pattern (SCP) and the gate electrode (GE), such that the gate electrode (GE) is spaced apart from the semiconductor pattern (SCP). In an embodiment, the gate insulating layer (GI) may be disposed entirely on the semiconductor pattern (SCP) and the buffer layer (BFL) to cover both the semiconductor pattern (SCP) and the buffer layer (BFL). The number of interlayer insulating layers (ILDs) can be increased as the number of layers required to form the conductive patterns and / or semiconductor patterns increases.

[0118] The gate electrode GE is disposed on the gate insulating layer GI. The gate electrode GE may be stacked with the channel region of the semiconductor pattern SCP. In an embodiment, the gate electrode GE may be a single layer comprising at least one material selected from copper (Cu), molybdenum (Mo), tungsten (W), neodymium aluminum (AlNd), titanium (Ti), aluminum (Al), and silver (Ag). In an embodiment, the gate electrode GE may be multiple layers comprising at least one material selected from molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), and silver (Ag) as low-resistance materials.

[0119] First terminal ET1 and second terminal ET2 are disposed on the interlayer insulating layer (ILD). First terminal ET1 and second terminal ET2 can contact the semiconductor pattern SCP through contact holes penetrating the ILD. First terminal ET1 and second terminal ET2 can respectively contact a first contact area and a second contact area of ​​the semiconductor pattern SCP. Each of first terminal ET1 and second terminal ET2 may comprise at least one material selected from copper (Cu), molybdenum (Mo), tungsten (W), neodymium aluminum (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0120] Although the first terminal ET1 and the second terminal ET2 are shown as separate electrodes electrically connected to the semiconductor pattern SCP, the embodiment is not limited thereto. In an embodiment, the first terminal ET1 may be a first contact region adjacent to one side of the channel region of the semiconductor pattern SCP, and the second terminal ET2 may be a second contact region adjacent to the other side of the channel region. In this case, the first terminal ET1 may be electrically connected to the light-emitting element LD via a connection device such as a bridging electrode disposed on at least one of a plurality of interlayer insulating layers (ILDs).

[0121] In this embodiment, transistor T_SP1 may be constructed from a low-temperature polysilicon transistor. However, the embodiment is not limited to this. For example, transistor T_SP1 may be constructed from an oxide semiconductor transistor. In this embodiment, the sub-pixel circuit of the first sub-pixel SP1 may include different types of transistors. For example, transistor T_SP1 may be constructed from a low-temperature polysilicon transistor, and another transistor of the first sub-pixel SP1 may be constructed from an oxide semiconductor transistor. In this case, the oxide semiconductor of the corresponding oxide semiconductor transistor may be disposed on one of a plurality of interlayer insulating layers (ILDs), rather than on the insulating layer on which the semiconductor pattern SCP of transistor T_SP1 is disposed.

[0122] In this embodiment, the case where transistor T_SP1 is a top-gate transistor is described as an example, but the embodiment is not limited to this. For example, transistor T_SP1 can be a bottom-gate transistor. The structure of transistor T_SP1 can be varied.

[0123] At least some of the various lines of the display panel DP and / or display device DD can also be provided on the interlayer insulation layer ILD.

[0124] The first passivation layer PSV1 can be disposed on the interlayer insulating layer ILD and the first terminal ET1 and the second terminal ET2. The passivation layer can be referred to as a protective layer or a via layer. The first passivation layer PSV1 can protect the components disposed below (or beneath) the first passivation layer PSV1 and can provide a flat upper surface.

[0125] The connection electrode CP can be disposed on the first passivation layer PSV1. The connection electrode CP can be connected to the first terminal ET1 of the transistor T_SP1 through the first passivation layer PSV1. The connection electrode CP can include at least one material selected from copper (Cu), molybdenum (Mo), tungsten (W), neodymium aluminum (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0126] At least some of the various lines of the display panel DP and / or display device DD can also be provided on the first passivation layer PSV1.

[0127] A second passivation layer PSV2 is disposed on the connecting electrode CP and the first passivation layer PSV1. The second passivation layer PSV2 can protect the components disposed beneath it and can provide a flat upper surface.

[0128] Each of the first passivation layer PSV1 and the second passivation layer PSV2 may include an inorganic insulating layer comprising inorganic materials and / or an organic insulating layer comprising organic materials. The inorganic insulating layer may include at least one metal oxide, such as silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. The organic insulating layer may include at least one of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene resin.

[0129] The display element layer DPL can be disposed on the second passivation layer PSV2. The display element layer DPL may include a first anode electrode AE1, a cathode electrode CE, an adhesive layer ADL, a first bridging electrode BRE1 and a second bridging electrode BRE2, a first light-emitting element LD1, a third passivation layer PSV3, a first light extraction structure OC1, a cover layer CPL, a reflective layer RFL, and a first dam layer BNK.

[0130] The electrode layer, including the first anode electrode AE1 and the cathode electrode CE, can be disposed on the pixel circuit layer PCL.

[0131] The first anode electrode AE1 can be electrically connected to the connection electrode CP through a contact hole passing through the second passivation layer PSV2. As described above, the first anode electrode AE1 can be electrically connected to the transistor T_SP1.

[0132] The cathode electrode CE can be spaced apart from the first anode electrode AE1 in the second direction DR2. The cathode electrode CE can be electrically connected to Figure 2 The second power voltage node VSSN. Therefore, the second power voltage applied to the second power voltage node VSSN can be transmitted to the cathode electrode CE.

[0133] The adhesive layer ADL can be disposed on the first anode electrode AE1, the cathode electrode CE, and the second passivation layer PSV2 between the first anode electrode AE1 and the cathode electrode CE. The adhesive layer ADL may include an insulating material with adhesive properties. The adhesive layer ADL can be used to fix the first light-emitting element LD1 attached to the adhesive layer ADL.

[0134] The first light-emitting element LD1 may include a light-emitting stack comprising a first semiconductor layer 11, a second semiconductor layer 12 disposed on the first semiconductor layer 11, and an active layer 13 disposed between the first semiconductor layer 11 and the second semiconductor layer 12. In an embodiment, the light-emitting stack may further include an auxiliary layer 14 disposed on the second semiconductor layer 12.

[0135] The first semiconductor layer 11 provides holes to the active layer 13. The first semiconductor layer 11 may include at least one p-type semiconductor layer. For example, the first semiconductor layer 11 may include at least one semiconductor material selected from gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and may be a p-type semiconductor layer doped with p-type dopants (such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), and barium (Ba)). However, the materials constituting the first semiconductor layer 11 are not limited to these, and various other materials may constitute the first semiconductor layer 11. In an embodiment, the first semiconductor layer 11 may include a gallium nitride (GaN) semiconductor material doped with a p-type dopant.

[0136] The second semiconductor layer 12 provides electrons to the active layer 13. The second semiconductor layer 12 may include at least one n-type semiconductor material. For example, the second semiconductor layer 12 may include at least one semiconductor material selected from gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and may be an n-type semiconductor layer doped with n-type dopants such as silicon (Si), germanium (Ge), and tin (Sn). However, the materials constituting the second semiconductor layer 12 are not limited to these, and various other materials may constitute the second semiconductor layer 12. In an embodiment, the second semiconductor layer 12 may include gallium nitride (GaN) semiconductor material doped with an n-type dopant. According to an embodiment, the second semiconductor layer 12 may form an n-type semiconductor layer together with an auxiliary layer 14.

[0137] The active layer 13 can be disposed between the first semiconductor layer 11 and the second semiconductor layer 12, and can be a region where electrons and holes recombine. When electrons and holes recombine in the active layer 13, they can transition to lower energy levels, thus generating light with a corresponding wavelength. The active layer 13 can be formed as a single quantum well structure or a multi-quantum well structure. In the case where the active layer 13 is formed as a multi-quantum well structure, units including a barrier layer, a strain enhancement layer, and a well layer can be repeatedly stacked on top of each other to form the active layer 13. However, embodiments of the active layer 13 are not limited to this.

[0138] The auxiliary layer 14 may include gallium nitride (GaN) semiconductor material that is substantially undoped or doped with impurities at a relatively low concentration, and may form an n-type semiconductor layer together with the second semiconductor layer 12.

[0139] The first light-emitting element LD1 may include a first bonding electrode BDE1 and a second bonding electrode BDE2. The first bonding electrode BDE1 may be connected to the lower surface of the first semiconductor layer 11. The first bonding electrode BDE1 may not physically contact the second semiconductor layer 12 and the active layer 13. The second bonding electrode BDE2 may be connected to the second semiconductor layer 12 that is not stacked with the first semiconductor layer 11 and the active layer 13. For example, the second bonding electrode BDE2 may be connected to the second semiconductor layer 12 exposed by etching away the first semiconductor layer 11 and the active layer 13. The second bonding electrode BDE2 may not physically contact the first semiconductor layer 11, the active layer 13, and the first bonding electrode BDE1. The first light-emitting element LD1 may be a flip-chip type light-emitting element. In an embodiment, the first bonding electrode BDE1 and the second bonding electrode BDE2 may include a eutectic metal.

[0140] In embodiments, the first bonding electrode BDE1 and the second bonding electrode BDE2 may comprise materials suitable for reflecting incident light. For example, the first bonding electrode BDE1 and the second bonding electrode BDE2 may comprise at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and alloys selected from two or more of these materials. However, embodiments are not limited thereto. Because the first bonding electrode BDE1 and the second bonding electrode BDE2 comprise materials suitable for reflecting light, the light output efficiency of the light generated in the active layer 13 can be further improved.

[0141] The first light-emitting element LD1 may include an insulating layer 15 covering at least a portion of the outer peripheral surface of the light-emitting stack. For example, the insulating layer 15 may completely cover the outer peripheral surfaces of the light-emitting stack except for the top surface. The insulating layer 15 may be used to prevent electrical short circuits that may occur when the active layer 13 contacts conductive materials other than the first semiconductor layer 11 and the second semiconductor layer 12. The insulating layer 15 may also be used to prevent electrical short circuits that may occur when the second bonding electrode BDE2 contacts the first semiconductor layer 11 and the active layer 13. The insulating layer 15 may include a transparent insulating material. Figure 7 As shown, a portion of the first bonding electrode BDE1 and a portion of the second bonding electrode BDE2 can be exposed without being covered by the insulating layer 15.

[0142] The first bonding electrode BDE1 may extend along the insulating layer 15 covering the side surface of the light-emitting stack. The extended portion of the first bonding electrode BDE1 and the exposed portion of the first anode electrode AE1 without the adhesive layer ADL can be electrically connected to each other via the first bridging electrode BRE1. The second bonding electrode BDE2 may extend along the insulating layer 15 covering the side surface of the light-emitting stack. The extended portion of the second bonding electrode BDE2 and the exposed portion of the cathode electrode CE without the adhesive layer ADL can be electrically connected to each other via the second bridging electrode BRE2. The first bridging electrode BRE1 and the second bridging electrode BRE2 may comprise the same material as one of the first anode electrode AE1, the cathode electrode CE, the first bonding electrode BDE1, and the second bonding electrode BDE2, but the embodiments are not limited thereto.

[0143] A third passivation layer PSV3, completely covering components such as the first bridging electrode BRE1, the second bridging electrode BRE2, and the first light-emitting element LD1, is disposed on the pixel circuit layer PCL. The third passivation layer PSV3 protects the components disposed beneath it. The third passivation layer PSV3 may include the same material as one of the first passivation layer PSV1, the second passivation layer PSV2, and the interlayer insulating layer ILD, but embodiments are not limited thereto. In embodiments, the third passivation layer PSV3 may not be disposed on the upper surface of the first light-emitting element LD1. The third passivation layer PSV3 may be omitted.

[0144] The first light extraction structure OC1 is configured to be stacked with the first light-emitting element LD1. The first light extraction structure OC1 may cover the first light-emitting element LD1. In an embodiment, the first light extraction structure OC1 may surround at least a portion of a side surface adjacent to the upper surface of the first light-emitting element LD1. The first light extraction structure OC1 may include a material with relatively high light transmittance to transmit light generated in the first light-emitting element LD1.

[0145] The capping layer CPL can completely cover the first light extraction structure OC1 and the third passivation layer PSV3. Within the spirit and scope of the disclosure, the capping layer CPL can protect the components beneath it (such as the first light-emitting element LD1) from external water, moisture, etc. The capping layer CPL can include at least one of metal oxides such as silicon nitride, silicon oxide, silicon oxynitride, and aluminum oxide. However, the material of the capping layer CPL is not limited to these. The capping layer CPL can be omitted.

[0146] The first embankment layer BNK can be set in the first light extraction structure OC1 and as will be described later. Figure 8The first dam layer BNK is located between the second light extraction structure OC2 and the third light extraction structure OC3. Therefore, the first dam layer BNK can surround the first light extraction structure OC1 and the second and third light extraction structures OC2, which will be described later. The first dam layer BNK can be configured to include a light-blocking material to prevent light mixing between adjacent sub-pixels. In embodiments, the first dam layer BNK may include organic materials. For example, the first dam layer BNK may include organic insulating materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0147] A reflective layer RFL is disposed between the first embankment layer BNK and the first light extraction structure OC1. The reflective layer RFL may at least surround the side surface of the first light extraction structure OC1. The reflective layer RFL may include a material suitable for reflecting light. The reflective layer RFL may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and alloys selected from two or more of these materials. However, the embodiments are not limited thereto.

[0148] The first light extraction structure OC1 and the reflective layer RFL can be used to improve the light output efficiency of the light generated in the first light-emitting element LD1. More specifically, the side surface of the first light extraction structure OC1 may include an inverted conical inclined surface. For example, as... Figure 7 As shown, the first light extraction structure OC1 can have a shape substantially the same as (or similar to) a trapezoidal shape in cross-section where the upper side is longer than the lower side. Here, the reflective layer RFL surrounding the side surface of the first light extraction structure OC1 can also have an inverted conical shape corresponding to the shape of the side surface of the first light extraction structure OC1. Therefore, the light generated in the first light-emitting element LD1 can be reflected to travel in the front surface direction (e.g., the third direction DR3 and the direction intersecting with it), thereby improving light output efficiency.

[0149] In an embodiment, the first light extraction structure OC1 may include a negative photoresist material. Therefore, the first light extraction structure OC1 may be formed with side surfaces including an inverted conical, inclined surface. See below for further details. Figure 18 and Figure 19 This will be described in detail.

[0150] In one embodiment, the first light extraction structure OC1 may include scattering particles SCT. The scattering particles SCT can scatter the light generated in the first light-emitting element LD1. Therefore, the light output efficiency can be further improved.

[0151] In this embodiment, the upper edge of the first light extraction structure OC1 may have a circular (rounded) shape. In this case, the side surface between the lower surface and the upper edge of the first light extraction structure OC1 may be an inverted conical inclined surface.

[0152] In this embodiment, the reflective layer RFL can extend from the side surface of the first light extraction structure OC1 to further cover the upper edge of the first light extraction structure OC1 and the portion of the upper surface adjacent to the upper edge. In this case, the side surfaces of the reflective layer RFL and the first dam layer BNK can be aligned with each other on the upper surface of the first light extraction structure OC1. As described above, since the upper edge of the first light extraction structure OC1 and the portion of the upper surface adjacent to the upper edge are covered by the reflective layer RFL and the first dam layer BNK, light mixing between adjacent sub-pixels can be further effectively prevented.

[0153] In the above embodiment, another portion of the upper surface of the first light extraction structure OC1 may not be covered by the reflective layer RFL and the first dam layer BNK. Therefore, the light generated in the first light-emitting element LD1 can be normally emitted through the other portion of the upper surface of the first light extraction structure OC1 that is not covered by the reflective layer RFL and the first dam layer BNK.

[0154] In one embodiment, the reflective layer RFL may cover the lowest surface of the first dam layer BNK. This can be a structure produced by a disclosed manufacturing method in which the reflective layer RFL is formed by an etching process using the first dam layer BNK as a mask. See below. Figures 21 to 24 This will be described in detail.

[0155] In an embodiment, the reflective layer RFL may not be disposed between the lower surface of the first light extraction structure OC1 and the pixel circuit layer PCL. For example, the reflective layer RFL may not be disposed between the first light extraction structure OC1 and the components immediately disposed below the first light extraction structure OC1 (e.g., it may not be disposed between the first light extraction structure OC1 and the third passivation layer PSV3, or, if the third passivation layer PSV3 can be omitted, it may not be disposed between the first light extraction structure OC1 and the first light-emitting element LD1, the first bridging electrode BRE1, and the second bridging electrode BRE2). This can be a structure that occurs through a disclosed manufacturing method in which the reflective layer RFL is formed after the first light extraction structure OC1 is formed. Refer to later. Figures 19 to 21 This will be described in detail.

[0156] The above describes the pixel circuit layer PCL and display element layer DPL of the first sub-pixel SP1. Unless otherwise described herein, Figure 6 Each of the second sub-pixel SP2 and the third sub-pixel SP3 can be constructed similarly to the first sub-pixel SP1.

[0157] The light functional layer (LFL) is disposed on the first dam layer (BNK) and the cover layer (CPL). The light functional layer (LFL) may include a fill layer (LRL) and a color filter layer (CFL).

[0158] A filler layer (LRL) is disposed on the first embankment layer (BNK) and the cover layer (CPL). The filler layer (LRL) may comprise a material with relatively high light transmittance. The filler layer (LRL) may provide a flat upper surface. The filler layer (LRL) may be omitted.

[0159] A color filter layer CFL is disposed on a filler layer LRL. The color filter layer CFL may include a first color filter CF1 and a light-blocking pattern LBP. The first color filter CF1 is superimposed on a first light extraction structure OC1. The first color filter CF1 can selectively transmit light within a desired wavelength range. If the first sub-pixel SP1 is a red sub-pixel, the first color filter CF1 may include a red color filter. The light-blocking pattern LBP may include at least one of various types of light-blocking materials.

[0160] Reference Figure 6 and Figure 8 The pixel circuit layer PCL, the display element layer DPL, and the light function layer LFL can be sequentially arranged on the substrate SUB.

[0161] With reference Figure 7 The pixel circuit layer PCL is described similarly. In the pixel circuit layer PCL, sub-pixel circuits are provided, corresponding to the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, respectively.

[0162] With reference Figure 7 The description of the display element layer DPL is similar. In the display element layer DPL, a first light-emitting element LD1, a second light-emitting element LD2, and a third light-emitting element LD3 are respectively provided, corresponding to the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The first light-emitting element LD1 is connected to... Figure 7 The cathode electrode CE and the sub-pixel circuit included in the first sub-pixel SP1 Figure 7 The first light-emitting element (LD2) is connected between the cathode electrode CE and the transistor included in the sub-pixel circuit of the second sub-pixel SP2. The second light-emitting element (LD3) is connected between the cathode electrode CE and the transistor included in the sub-pixel circuit of the third sub-pixel SP3.

[0163] In an embodiment, when the first sub-pixel SP1 is a red sub-pixel, the first light-emitting element LD1 can be configured to emit red light. When the second sub-pixel SP2 is a green sub-pixel, the second light-emitting element LD2 can be configured to emit green light. When the third sub-pixel SP3 is a blue sub-pixel, the third light-emitting element LD3 can be configured to emit blue light. As described above, each of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 can be configured to emit light of a color corresponding to the type of the corresponding sub-pixel.

[0164] A first light extraction structure OC1, a second light extraction structure OC2, and a third light extraction structure OC3 are respectively provided, corresponding to the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3. The first light extraction structure OC1, the second light extraction structure OC2, and the third light extraction structure OC3 can be spaced apart from each other. The first light extraction structure OC1 can cover the first light-emitting element LD1. The second light extraction structure OC2 can cover the second light-emitting element LD2. The third light extraction structure OC3 can cover the third light-emitting element LD3. The side surface of each of the first light extraction structure OC1, the second light extraction structure OC2, and the third light extraction structure OC3 may include an inverted conical inclined surface.

[0165] The first dam layer BNK is positioned between the first light extraction structure OC1, the second light extraction structure OC2, and the third light extraction structure OC3. Therefore, the first dam layer BNK can surround the first light extraction structure OC1, the second light extraction structure OC2, and the third light extraction structure OC3.

[0166] A reflective layer RFL is disposed between the first light extraction structure OC1, the second light extraction structure OC2, and the third light extraction structure OC3 and the first embankment layer BNK. The reflective layer RFL may surround at least the side surface of each of the first light extraction structure OC1, the second light extraction structure OC2, and the third light extraction structure OC3.

[0167] In this embodiment, the reflective layer RFL can cover the lowest surface of the first dam layer BNK. That is, the reflective layer RFL can extend from the side surfaces of the first light extraction structure OC1, the second light extraction structure OC2, and the third light extraction structure OC3, and can be disposed between the lowest surface of the first dam layer BNK and the cover layer CPL (if the cover layer CPL can be omitted, it can be disposed between the lowest surface of the first dam layer BNK and the third passivation layer PSV3).

[0168] The light functional layer (LFL) is disposed on the display element layer (DPL). (Referencing) Figure 7 The optical functional layer LFL is described similarly.

[0169] The fill layer LRL is disposed on the first embankment layer BNK and the cover layer CPL. In an embodiment, the fill layer LRL may be omitted in the region corresponding to the third sub-pixel SP3.

[0170] The color filter layer CFL is disposed on the fill layer LRL. The color filter layer CFL may include a first color filter CF1, a second color filter CF2, and a third color filter CF3, as well as a light blocking pattern LBP.

[0171] Each of the first color filter CF1, the second color filter CF2, and the third color filter CF3 can selectively transmit light within a desired wavelength range. If the first sub-pixel SP1 is a red sub-pixel, the first color filter CF1 may include a red color filter. If the second sub-pixel SP2 is a green sub-pixel, the second color filter CF2 may include a green color filter. If the third sub-pixel SP3 is a blue sub-pixel, the third color filter CF3 may include a blue color filter.

[0172] A light-blocking pattern (LBP) is positioned between the first color filter (CF1), the second color filter (CF2), and the third color filter (CF3). It is understood that the emission region (or light output region) EMA and the non-emission region (NEMA) of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 are defined by the light-blocking pattern (LBP). Areas overlapping with the light-blocking pattern (LBP) may correspond to the non-emission region (NEMA). Areas not overlapping with the light-blocking pattern (LBP) may correspond to the emission region (EMA).

[0173] The light-blocking pattern LBP can be superimposed on the first dam layer BNK. The first color filter CF1, the second color filter CF2, and the third color filter CF3 can be superimposed on the first light extraction structure OC1, the second light extraction structure OC2, and the third light extraction structure OC3. For example, the first color filter CF1 can be superimposed on the first light extraction structure OC1, the second color filter CF2 can be superimposed on the second light extraction structure OC2, and the third color filter CF3 can be superimposed on the third light extraction structure OC3.

[0174] In embodiments, the light-blocking pattern LBP may include at least one of various types of light-blocking materials. In embodiments, each of the light-blocking patterns LBP may be configured as multiple layers in which at least two of the first color filter CF1, second color filter CF2, and third color filter CF3 are stacked. For example, each of the light-blocking patterns LBP may be formed by stacking the first color filter CF1, second color filter CF2, and third color filter CF3. As another example, the light-blocking pattern between the first color filter CF1 and the second color filter CF2 in the light-blocking pattern LBP may be formed as multiple layers in which the first color filter CF1 and the second color filter CF2 are stacked, and the light-blocking pattern between the second color filter CF2 and the third color filter CF3 in the light-blocking pattern LBP may be formed as multiple layers in which the second color filter CF2 and the third color filter CF3 are stacked. The light-blocking pattern between the first color filter CF1 and the third color filter CF3 of adjacent pixels may be formed as multiple layers in which the first color filter CF1 and the third color filter CF3 are stacked. As described above, each of the first color filter CF1, the second color filter CF2, and the third color filter CF3 can extend into the non-emissive region NEMA to form a light-blocking pattern LBP.

[0175] Figure 9 and Figure 10 It shows the basis Figure 6 A schematic cross-sectional view of an example of a modified pixel in an embodiment. Figure 9 It is along Figure 6 A schematic cross-sectional view taken by line X1-X1', and Figure 10 It is along Figure 6 A schematic cross-sectional view taken from line Y1-Y1'.

[0176] As shown above (refer to the reference) Figure 7 and Figure 8 As described, it can be set Figure 7 and Figure 8 The reflective layer RFL. Here, besides the shape of the reflective layer RFL', Figure 9 and Figure 10 The pixels shown can be compared with the reference. Figure 7 and Figure 8 The described pixels are essentially the same. Therefore, descriptions of repeated content can be omitted.

[0177] Reference Figure 6 , Figure 9 and Figure 10The reflective layer RFL' can cover the portion of the upper edge of each of the first light extraction structure OC1, the second light extraction structure OC2, and the third light extraction structure OC3 adjacent to the side surface. In this case, the other portion of the upper edge of each of the first light extraction structure OC1, the second light extraction structure OC2, and the third light extraction structure OC3, as well as the upper surface of each of the first light extraction structure OC1, the second light extraction structure OC2, and the third light extraction structure OC3, may not be covered by the reflective layer RFL'.

[0178] In this case, the lowest surface of the first dam layer BNK may not be covered by the reflective layer RFL'. This can be a structure that occurs through a disclosed manufacturing method in which the reflective layer RFL' is formed prior to the formation of the first dam layer BNK. See later. Figures 25 to 28 This will be described in detail.

[0179] Figure 11 and Figure 12 It shows the basis Figure 6 A schematic cross-sectional view of an example of a modified pixel in an embodiment. Figure 11 It is along Figure 6 A schematic cross-sectional view taken by line X1-X1', and Figure 12 It is along Figure 6 A schematic cross-sectional view taken from line Y1-Y1'.

[0180] Reference Figure 6 and Figure 11 The pixel circuit layer PCL, the display element layer DPL, and the optical function layer LFL can be sequentially arranged on the substrate SUB.

[0181] With reference Figure 7 The pixel circuit layer PCL is described similarly. Therefore, descriptions of repeated content can be omitted.

[0182] With reference Figure 7 The description of the Display Element Layer (DPL) is similar to that of the Display Element Layer (DPL). Therefore, descriptions of repeated content can be omitted.

[0183] The optical functional layer LFL is disposed on the first dam layer BNK and the cover layer CPL. The optical functional layer LFL may include a second dam layer BNK', a light reflection layer RFL'', a first light conversion pattern CCP1, a fill layer LRL, and a color filter layer CFL.

[0184] A second dam layer BNK' is disposed on top of the first dam layer BNK to overlap with it. The second dam layer BNK' may have an opening OP overlapping the first light extraction structure OC1. The second dam layer BNK' is configured to include a light-blocking material to prevent light mixing between adjacent sub-pixels. In embodiments, the second dam layer BNK' may include organic materials. For example, the second dam layer BNK' may include organic insulating materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0185] A light-reflecting layer RFL'' is disposed on the side surface of the second embankment layer BNK' adjacent to the opening OP. The light-reflecting layer RFL'' is configured to reflect incident light, thus improving light output efficiency. The light-reflecting layer RFL'' may include a material suitable for reflecting light. The light-reflecting layer RFL'' may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and alloys selected from two or more of these materials. However, the embodiments are not limited thereto.

[0186] A first light conversion pattern CCP1 is disposed on and superimposed on a first light extraction structure OC1. The first light conversion pattern CCP1 is disposed within an opening OP. The first light conversion pattern CCP1 may include color conversion particles and / or scattering particles. The color conversion particles can change the wavelength of the incident light and convert the incident light into different colors. The color conversion particles can scatter the incident light. In an embodiment, the color conversion particles may be quantum dots.

[0187] When the first sub-pixel SP1 is a red sub-pixel, the first light-emitting element LD1 can emit light of a different color than red. For example, the first light-emitting element LD1 can emit blue light. In this case, the first light conversion pattern CCP1 can include a first color conversion particle QD1 configured to convert blue light into red light.

[0188] A filler layer LRL is disposed on the second embankment layer BNK' and the first light conversion pattern CCP1. The filler layer LRL may comprise a material with relatively high light transmittance. The filler layer LRL may provide a flat upper surface. In an embodiment, the filler layer LRL may have a lower refractive index than the first light conversion pattern CCP1. The filler layer LRL is configured to refract or totally reflect light according to the angle of incidence. For example, the filler layer LRL may direct light passing through the first light conversion pattern CCP1 back to the first light conversion pattern CCP1. Therefore, the light conversion efficiency of the first light conversion pattern CCP1 can be improved. The filler layer LRL may be omitted.

[0189] A color filter layer (CFL) is disposed on a filler layer (LRL). The color filter layer (CFL) may include a first color filter (CF1) and a light-blocking pattern (LBP). The first color filter (CF1) is superimposed on a first light conversion pattern (CCP1). The first color filter (CF1) can selectively transmit light within a desired wavelength range. If the first sub-pixel (SP1) is a red sub-pixel, the first color filter (CF1) may include a red color filter. The light-blocking pattern (LBP) may include at least one of various types of light-blocking materials.

[0190] Reference Figure 6 and Figure 12 The pixel circuit layer PCL, the display element layer DPL, and the optical function layer LFL can be sequentially arranged on the substrate SUB.

[0191] With reference Figure 7 The pixel circuit layer PCL is described similarly. In the pixel circuit layer PCL, sub-pixel circuits corresponding to the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 are provided.

[0192] In addition to the color of the light emitted from each of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3, it is also comparable to the reference light. Figure 7 The description of the display element layer DPL is similar to the description of the display element layer DPL. Figure 12 The first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 shown can emit light of the same color. For example, the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 can produce blue light.

[0193] The light functional layer (LFL) is disposed on the display element layer (DPL). (Referencing) Figure 11 The optical functional layer LFL is described similarly.

[0194] A second dam layer BNK' is disposed on top of the first dam layer BNK to be superimposed on the first dam layer BNK. The second dam layer BNK' may have an opening OP superimposed on the first light extraction structure OC1, the second light extraction structure OC2, and the third light extraction structure OC3. A first light conversion pattern CCP1, a second light conversion pattern CCP2, and a light scattering pattern LSP are disposed in the opening OP to be superimposed on the first light extraction structure OC1, the second light extraction structure OC2, and the third light extraction structure OC3. The first light conversion pattern CCP1 is disposed on the first light extraction structure OC1. The second light conversion pattern CCP2 is disposed on the second light extraction structure OC2. The light scattering pattern LSP is disposed on the third light extraction structure OC3. The first light conversion pattern CCP1, the second light conversion pattern CCP2, and the light scattering pattern LSP may be spaced apart from each other.

[0195] A light-reflecting layer RFL'' is disposed on the side surface of the second dam layer BNK' adjacent to the opening OP. Here, the light-reflecting layer RFL'' can be disposed between the first light conversion pattern CCP1 and the second light conversion pattern CCP2 and the second dam layer BNK' surrounding the first light conversion pattern CCP1 and the second light conversion pattern CCP2, and between the light scattering pattern LSP and the second dam layer BNK' surrounding the light scattering pattern LSP.

[0196] In an embodiment, the first sub-pixel SP1 can be a red sub-pixel, the second sub-pixel SP2 can be a green sub-pixel, and the third sub-pixel SP3 can be a blue sub-pixel. The first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 can be configured to emit blue light. In this case, the first light conversion pattern CCP1 can include a first color conversion particle QD1 configured to convert blue light to red light. The second light conversion pattern CCP2 can include a second color conversion particle QD2 configured to convert blue light to green light. The light scattering pattern LSP can include scattering particles SCT that scatter blue light to improve light output efficiency. Therefore, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be respectively set as a red sub-pixel, a green sub-pixel, and a blue sub-pixel. In an embodiment, at least one of the first light conversion pattern CCP1, the second light conversion pattern CCP2, and the light scattering pattern LSP can also include a color conversion particle that converts blue light to white light.

[0197] The fill layer LRL can be disposed on the second embankment layer BNK', the first light conversion pattern CCP1, the second light conversion pattern CCP2, and the light scattering pattern LSP. In an embodiment, the fill layer LRL can be omitted in the region corresponding to the third sub-pixel SP3.

[0198] The color filter layer CFL can be disposed on the fill layer LRL. The color filter layer CFL may include a first color filter CF1, a second color filter CF2, and a third color filter CF3, as well as a light blocking pattern LBP.

[0199] Each of the first color filter CF1, the second color filter CF2, and the third color filter CF3 can selectively transmit light within a desired wavelength range. If the first sub-pixel SP1 is a red sub-pixel, the first color filter CF1 may include a red color filter. If the second sub-pixel SP2 is a green sub-pixel, the second color filter CF2 may include a green color filter. If the third sub-pixel SP3 is a blue sub-pixel, the third color filter CF3 may include a blue color filter.

[0200] A light-blocking pattern (LBP) can be positioned between the first color filter (CF1), the second color filter (CF2), and the third color filter (CF3). It is understood that the emission region (or light output region) EMA and the non-emission region (NEMA) of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 are defined by the light-blocking pattern (LBP). The area overlapping with the light-blocking pattern (LBP) can correspond to the non-emission region (NEMA). The area not overlapping with the light-blocking pattern (LBP) can correspond to the emission region (EMA).

[0201] The light-blocking pattern LBP can be superimposed on the second dam layer BNK'. The first color filter CF1, the second color filter CF2, and the third color filter CF3 can be superimposed on the first light conversion pattern CCP1, the second light conversion pattern CCP2, and the light scattering pattern LSP. For example, the first color filter CF1 can be superimposed on the first light conversion pattern CCP1, the second color filter CF2 can be superimposed on the second light conversion pattern CCP2, and the third color filter CF3 can be superimposed on the light scattering pattern LSP.

[0202] In embodiments, the light-blocking pattern LBP may include at least one of various types of light-blocking materials. In embodiments, each of the light-blocking patterns LBP may be configured as multiple layers in which at least two of the first color filter CF1, second color filter CF2, and third color filter CF3 are stacked. For example, each of the light-blocking patterns LBP may be formed by stacking the first color filter CF1, second color filter CF2, and third color filter CF3. As another example, the light-blocking pattern between the first color filter CF1 and the second color filter CF2 in the light-blocking pattern LBP may be formed as multiple layers in which the first color filter CF1 and the second color filter CF2 are stacked, and the light-blocking pattern between the second color filter CF2 and the third color filter CF3 in the light-blocking pattern LBP may be formed as multiple layers in which the second color filter CF2 and the third color filter CF3 are stacked. The light-blocking pattern between the first color filter CF1 and the third color filter CF3 of adjacent pixels may be formed as multiple layers in which the first color filter CF1 and the third color filter CF3 are stacked. As described above, each of the first color filter CF1, the second color filter CF2, and the third color filter CF3 can extend into the non-emissive region NEMA to form a light-blocking pattern LBP.

[0203] exist Figure 11 and Figure 12 In the diagram, pixels are shown as including references. Figure 7 and Figure 8 The described reflective layer RFL, but Figure 11 and Figure 12 The pixels can also include references Figure 9 and Figure 10 The described reflective layer RFL'.

[0204] Figure 13 It is shown that it includes Figure 3 A schematic plan view of a second embodiment of one pixel in a display panel.

[0205] Reference Figure 13 Pixel PXL may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. (Refer to reference...) Figure 6 The descriptions of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 are similar to those of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. Therefore, the descriptions of repeated content can be omitted.

[0206] With reference Figure 6 The first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3, as well as the cathode electrode CE, are described similarly. The first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 can be respectively disposed in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The cathode electrode CE can be spaced apart from the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3. In the following description, repeated content may be omitted.

[0207] The first light-emitting element LD1', the second light-emitting element LD2', and the third light-emitting element LD3' can be disposed on the first anode electrode AE1, the second anode electrode AE2, the third anode electrode AE3, and the cathode electrode CE. The first light-emitting element LD1' can be electrically connected to the first anode electrode AE1 and the cathode electrode CE. The first light-emitting element LD1' can be configured to be connected to the first sub-pixel SP1. Figure 2 Sub-pixel circuit SPC Figure 2 The first light-emitting element is LD. The second light-emitting element LD2' can be electrically connected to the second anode electrode AE2 and the cathode electrode CE. The second light-emitting element LD2' can be configured to be connected to the second sub-pixel SP2. Figure 2 Sub-pixel circuit SPC Figure 2 The third light-emitting element LD3' can be electrically connected to the third anode electrode AE3 and the cathode electrode CE. The third light-emitting element LD3' can be configured to be connected to the third sub-pixel SP3. Figure 2 Sub-pixel circuit SPC Figure 2 The light-emitting element LD.

[0208] The first light-emitting element LD1', the second light-emitting element LD2', and the third light-emitting element LD3' can be inorganic light-emitting diodes that include inorganic light-emitting materials. However, the embodiments are not limited to this; for example, the first light-emitting element LD1', the second light-emitting element LD2', and the third light-emitting element LD3' can be organic light-emitting diodes that include organic light-emitting materials.

[0209] Figure 14 It is along Figure 13 A schematic cross-sectional view taken by line X2-X2'. Figure 15 It is along Figure 13 A schematic cross-sectional view taken by line Y2-Y2'.

[0210] Reference Figure 13 and Figure 14 The pixel circuit layer PCL, the display element layer DPL, and the optical function layer LFL can be sequentially arranged on the substrate SUB.

[0211] With reference Figure 7 The pixel circuit layer PCL is described similarly. Therefore, descriptions of repeated content can be omitted.

[0212] The display element layer DPL can be disposed on the second passivation layer PSV2. The display element layer DPL may include a first anode electrode AE1, a cathode electrode CE, a first reflective electrode RFE1, a second reflective electrode RFE2, an adhesive layer ADL, a first bridging electrode BRE1 and a second bridging electrode BRE2, a first light-emitting element LD1', a third passivation layer PSV3, a first light extraction structure OC1, a cover layer CPL, a reflective layer RFL, and a first dam layer BNK.

[0213] An electrode layer, including a first anode electrode AE1 and a cathode electrode CE, can be disposed on the pixel circuit layer PCL. (Refer to reference...) Figure 7 The first anode electrode AE1 and the cathode electrode CE are described similarly. Therefore, descriptions of repeated content can be omitted.

[0214] The first reflective electrode RFE1 may cover the first anode electrode AE1. The second reflective electrode RFE2 may cover the cathode electrode CE. The first reflective electrode RFE1 and the second reflective electrode RFE2 may include materials suitable for reflecting light. For example, the first reflective electrode RFE1 and the second reflective electrode RFE2 may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and alloys selected from two or more of these materials. However, the embodiments are not limited to this. Therefore, light emitted from the light-emitting element LD1' can be reflected by the first reflective electrode RFE1 and the second reflective electrode RFE2, thereby improving light output efficiency.

[0215] In this embodiment, the first reflecting electrode RFE1 and the second reflecting electrode RFE2 can be omitted. In this case, the first anode electrode AE1 and the cathode electrode CE can comprise materials suitable for reflecting light. That is, the first anode electrode AE1 and the cathode electrode CE can perform the functions of the first reflecting electrode RFE1 and the second reflecting electrode RFE2 described above.

[0216] The adhesive layer ADL can be disposed on the first reflective electrode RFE1, the second reflective electrode RFE2, and the second passivation layer PSV2 located between the first reflective electrode RFE1 and the second reflective electrode RFE2. The adhesive layer ADL may include an insulating material with adhesive properties. The adhesive layer ADL can be used to fix the first light-emitting element LD1' attached to the adhesive layer ADL.

[0217] The first light-emitting element LD1' may include a light-emitting stack comprising a first semiconductor layer 11', a second semiconductor layer 12' disposed below the first semiconductor layer 11', and an active layer 13' disposed between the first semiconductor layer 11' and the second semiconductor layer 12'. In an embodiment, the light-emitting stack may further include an auxiliary layer 14' disposed below the second semiconductor layer 12'.

[0218] Can be compared with reference Figure 7 The first semiconductor layer 11 is described similarly to the first semiconductor layer 11'. The first semiconductor layer 11' provides holes to the active layer 13'. The first semiconductor layer 11' may include at least one p-type semiconductor material. In the following description, repeated content may be omitted.

[0219] Can be compared with reference Figure 7 The second semiconductor layer 12 is similarly described as the second semiconductor layer 12'. The second semiconductor layer 12' provides electrons to the active layer 13'. The second semiconductor layer 12' may include at least one n-type semiconductor material. In the following description, repeated content may be omitted.

[0220] Can be compared with reference Figure 7 The active layer 13 is similarly described to the active layer 13'. The active layer 13' may be disposed between the first semiconductor layer 11' and the second semiconductor layer 12', and may be a region where electrons and holes recombine. When electrons and holes recombine in the active layer 13', they can transition to lower energy levels, thus generating light with a corresponding wavelength. In the following description, repeated content may be omitted.

[0221] The auxiliary layer 14' may include gallium nitride (GaN) semiconductor material in which it is substantially undoped or doped with impurities at a relatively low concentration, and may together with the second semiconductor layer 12' form an n-type semiconductor layer.

[0222] The first light-emitting element LD1' may include a first bonding electrode BDE1' and a second bonding electrode BDE2'. The first bonding electrode BDE1' may be connected to the upper surface of the first semiconductor layer 11'. The first bonding electrode BDE1' may not physically contact the second semiconductor layer 12' and the active layer 13'. The second bonding electrode BDE2' may be connected to the second semiconductor layer 12' which is not stacked with the first semiconductor layer 11' and the active layer 13'. For example, the second bonding electrode BDE2' may be connected to the second semiconductor layer 12' exposed by etching away the first semiconductor layer 11' and the active layer 13'. The second bonding electrode BDE2' may not physically contact the first semiconductor layer 11', the active layer 13', and the first bonding electrode BDE1'. The first light-emitting element LD1' may be a lateral chip-type light-emitting element.

[0223] The first bonding electrode BDE1' and the second bonding electrode BDE2' can be configured to be substantially transparent or translucent to meet a selectable transmittance. In embodiments, the first bonding electrode BDE1' and the second bonding electrode BDE2' may comprise at least one of a variety of transparent conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO). However, the materials of the first bonding electrode BDE1' and the second bonding electrode BDE2' are not limited thereto.

[0224] The first light-emitting element LD1' may include an insulating layer 15' covering at least a portion of the outer peripheral surface of the light-emitting stack. For example, the insulating layer 15' may completely cover the outer peripheral surface of the light-emitting stack. The insulating layer 15' may be used to prevent electrical short circuits that may occur when the active layer 13' contacts a conductive material other than the first semiconductor layer 11' and the second semiconductor layer 12'. The insulating layer 15' may also be used to prevent electrical short circuits that may occur when the second bonding electrode BDE2' contacts the first semiconductor layer 11' and the active layer 13'. The insulating layer 15' may include a transparent insulating material. Figure 14 As shown, a portion of the first bonding electrode BDE1' and a portion of the second bonding electrode BDE2' can be exposed without being covered by the insulating layer 15'.

[0225] The first bonding electrode BDE1' may extend along the insulating layer 15' covering the side surface of the light-emitting stack. The extended portion of the first bonding electrode BDE1' and the exposed portion of the first reflective electrode RFE1 without the adhesive layer ADL (or the exposed portion of the first anode electrode AE1 if the first reflective electrode RFE1 can be omitted) may be electrically connected to each other via the first bridging electrode BRE1. The second bonding electrode BDE2' may extend along the insulating layer 15' covering the side surface of the light-emitting stack. The extended portion of the second bonding electrode BDE2' and the exposed portion of the second reflective electrode RFE2 without the adhesive layer ADL (or the exposed portion of the cathode electrode CE if the second reflective electrode RFE2 can be omitted) may be electrically connected to each other via the second bridging electrode BRE2. The first bridging electrode BRE1 and the second bridging electrode BRE2 may include the same material as one of the first anode electrode AE1, the cathode electrode CE, the first bonding electrode BDE1', and the second bonding electrode BDE2', but the embodiments are not limited thereto.

[0226] A third passivation layer PSV3, completely covering components such as the first bridging electrode BRE1, the second bridging electrode BRE2, and the first light-emitting element LD1', is disposed on the pixel circuit layer PCL. The third passivation layer PSV3 protects the components disposed beneath it. The third passivation layer PSV3 may include the same material as one of the first passivation layer PSV1, the second passivation layer PSV2, and the interlayer insulating layer ILD, but embodiments are not limited thereto. In embodiments, the third passivation layer PSV3 may not be disposed on the upper surface of the first light-emitting element LD1'. The third passivation layer PSV3 may be omitted.

[0227] With reference Figure 7The first light extraction structure OC1 is described similarly. The first light extraction structure OC1 is configured to be stacked with the first light-emitting element LD1'. In an embodiment, the first light extraction structure OC1 may surround at least a portion of the side surface adjacent to the upper surface of the first light-emitting element LD1'. Descriptions of repeated content may be omitted below.

[0228] With reference Figure 7 The overlay layer CPL is described similarly. The overlay layer CPL can completely cover the first light extraction structure OC1 and the third passivation layer PSV3. Descriptions of repeated content may be omitted below.

[0229] With reference Figure 7 The first dam layer BNK and the reflective layer RFL are described similarly. The first dam layer BNK1 can be set in the first light extraction structure OC1 and will be described later. Figure 15 The second light extraction structure OC2 and the third light extraction structure OC3 are located between them. The reflective layer RFL is disposed between the first embankment layer BNK and the first light extraction structure OC1. In the following text, descriptions of repeated content may be omitted.

[0230] The first light extraction structure OC1 and the reflective layer RFL can be used to improve the light output efficiency of the light generated in the first light-emitting element LD1'. As described above, even if the first light-emitting element LD1' is a lateral chip type, it can be applied in essentially the same (or similarly) to improve the reference... Figure 7 The structure of the first light extraction structure OC1 and the reflective layer RFL describes the light output efficiency of the flip-chip type first light-emitting element LD1.

[0231] The above describes the pixel circuit layer PCL and display element layer DPL of the first sub-pixel SP1. Unless otherwise described herein, Figure 13 Each of the second sub-pixel SP2 and the third sub-pixel SP3 can be constructed similarly to the first sub-pixel SP1.

[0232] The optical functional layer (LFL) is disposed on the first embankment layer (BNK) and the cover layer (CPL). (Refer to reference) Figure 7 The description of the optical functional layer (LFL) is similar. An LFL may include a fill layer (LRL) and a color filter layer (CFL). Repeated descriptions may be omitted below.

[0233] Reference Figure 13 and Figure 15 The pixel circuit layer PCL, the display element layer DPL, and the optical function layer LFL can be sequentially arranged on the substrate SUB.

[0234] With reference Figure 14 The pixel circuit layer PCL is described similarly. In the pixel circuit layer PCL, sub-pixel circuits corresponding to the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 are provided.

[0235] With reference Figure 14 The description of the display element layer DPL is similar. In the display element layer DPL, a first light-emitting element LD1', a second light-emitting element LD2', and a third light-emitting element LD3' are respectively provided, corresponding to the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The first light-emitting element LD1' is connected to... Figure 14 The cathode electrode CE and the sub-pixel circuit included in the first sub-pixel SP1 Figure 14 The second light-emitting element LD2' is connected between the cathode electrode CE and the transistor included in the sub-pixel circuit of the second sub-pixel SP2. The third light-emitting element LD3' is connected between the cathode electrode CE and the transistor included in the sub-pixel circuit of the third sub-pixel SP3.

[0236] In an embodiment, when the first sub-pixel SP1 is a red sub-pixel, the first light-emitting element LD1' can be configured to emit red light. When the second sub-pixel SP2 is a green sub-pixel, the second light-emitting element LD2' can be configured to emit green light. When the third sub-pixel SP3 is a blue sub-pixel, the third light-emitting element LD3' can be configured to emit blue light. As described above, each of the first light-emitting element LD1', the second light-emitting element LD2', and the third light-emitting element LD3' can be configured to emit light of a color corresponding to the type of the corresponding sub-pixel.

[0237] A first light extraction structure OC1, a second light extraction structure OC2, and a third light extraction structure OC3 are respectively provided, corresponding to the first light-emitting element LD1', the second light-emitting element LD2', and the third light-emitting element LD3'. The first light extraction structure OC1, the second light extraction structure OC2, and the third light extraction structure OC3 can be spaced apart from each other. The first light extraction structure OC1 can cover the first light-emitting element LD1'. The second light extraction structure OC2 can cover the second light-emitting element LD2'. The third light extraction structure OC3 can cover the third light-emitting element LD3'. The side surface of each of the first light extraction structure OC1, the second light extraction structure OC2, and the third light extraction structure OC3 may include an inverted conical inclined surface.

[0238] With reference Figure 8The first dam layer BNK and the reflective layer RFL are described similarly. The first dam layer BNK is disposed between the first light extraction structure OC1, the second light extraction structure OC2, and the third light extraction structure OC3. Therefore, the first dam layer BNK may surround the first light extraction structure OC1, the second light extraction structure OC2, and the third light extraction structure OC3. The reflective layer RFL is disposed between the first light extraction structure OC1, the second light extraction structure OC2, and the third light extraction structure OC3 and the first dam layer BNK. The reflective layer RFL may surround at least the side surface of each of the first light extraction structure OC1, the second light extraction structure OC2, and the third light extraction structure OC3.

[0239] The light functional layer (LFL) is disposed on the display element layer (DPL). (Referencing) Figure 8 The description of the optical functional layer LFL is similar. Therefore, descriptions of repeated content can be omitted.

[0240] Refer again Figures 13 to 15 References can be applied Figure 9 and Figure 10 The described reflective layer RFL' is used instead Figure 14 and Figure 15 The reflective layer RFL is shown in the figure.

[0241] According to an embodiment, the first light-emitting element LD1', the second light-emitting element LD2', and the third light-emitting element LD3' can emit light of the same color. In this case, a reference can be applied. Figure 11 and Figure 12 The optical functional layer LFL described is used to replace Figure 14 and Figure 15 The light functional layer LFL shown in the figure.

[0242] Figure 16 It is shown that it includes Figure 3 A schematic plan view of a third embodiment of a pixel in a display panel.

[0243] Reference Figure 16 Pixel PXL may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be arranged in a first direction DR1. However, the arrangement of pixel PXL is not limited to this and can be varied according to embodiments. For example, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be arranged in a zigzag pattern.

[0244] The first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 can be respectively disposed in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The first anode electrode AE1 can be disposed within the first sub-pixel SP1. Figure 2 In the sub-pixel circuit SPC Figure 2 The first anode electrode is AE. The second anode electrode AE2 can be configured as the anode electrode AE ​​included in the sub-pixel circuit SPC of the second sub-pixel SP2. The third anode electrode AE3 can be configured as the anode electrode AE ​​included in the sub-pixel circuit SPC of the third sub-pixel SP3.

[0245] One or more first light-emitting elements LD1'', one or more second light-emitting elements LD2'', and one or more third light-emitting elements LD3'' can be disposed on the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3. The first light-emitting element LD1'' is connected to the first anode electrode AE1. The second light-emitting element LD2'' is connected to the second anode electrode AE2. The third light-emitting element LD3'' is connected to the third anode electrode AE3. With light-emitting elements disposed in each sub-pixel, each anode electrode can have a shape extending in a specific direction such as the second direction DR2, and the light-emitting elements connected to it can be arranged in the same direction.

[0246] The first light-emitting element LD1'' can be configured to be included in the first sub-pixel SP1 Figure 2 The second light-emitting element LD. The second light-emitting element LD2'' can be configured to be included in the second sub-pixel SP2. Figure 2 The light-emitting element LD. The third light-emitting element LD3'' can be configured as a light-emitting element LD included in the third sub-pixel SP3. When multiple light-emitting elements are set in one sub-pixel, the multiple light-emitting elements can be connected in parallel between the anode electrode and the cathode electrode, and can be configured as follows: Figure 2 The light-emitting element LD.

[0247] The first light-emitting element LD1'', the second light-emitting element LD2'', and the third light-emitting element LD3'' can be inorganic light-emitting diodes comprising inorganic light-emitting materials. However, the embodiments are not limited thereto; for example, organic light-emitting diodes can be used.

[0248] Figure 17 It is along Figure 16 A schematic cross-sectional view taken by line X3-X3'.

[0249] Reference Figure 16 and Figure 17 The pixel circuit layer PCL, the display element layer DPL, and the optical function layer LFL can be sequentially arranged on the substrate SUB.

[0250] With reference Figure 7 The pixel circuit layer PCL is described similarly. Therefore, descriptions of repeated content can be omitted.

[0251] On the pixel circuit layer PCL, the first anode electrode AE1, the second anode electrode AE2 and the third anode electrode AE3 are respectively disposed in the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3.

[0252] The first anode electrode AE1 can be electrically connected to a transistor included in the first sub-pixel circuit through a contact hole passing through at least a portion of the pixel circuit layer PCL. The second anode electrode AE2 can be electrically connected to a transistor included in the second sub-pixel circuit through a contact hole passing through at least a portion of the pixel circuit layer PCL. The third anode electrode AE3 can be electrically connected to a transistor included in the third sub-pixel circuit through a contact hole passing through at least a portion of the pixel circuit layer PCL.

[0253] The first light-emitting element LD1'', the second light-emitting element LD2'', and the third light-emitting element LD3'' are respectively disposed on the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3. The first light-emitting element LD1'', the second light-emitting element LD2'', and the third light-emitting element LD3'' can be respectively coupled to or connected to the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3.

[0254] The first light-emitting element LD1'' may include a bonding electrode BDE'', a first semiconductor layer 11'', a second semiconductor layer 12'', an active layer 13'', and an auxiliary layer 14''. The first light-emitting element LD1'' may be implemented as a vertical light-emitting stack in which the bonding electrode BDE'', the first semiconductor layer 11'', the active layer 13'', the second semiconductor layer 12'', and the auxiliary layer 14'' may be sequentially stacked on top of each other along a third direction DR3.

[0255] With reference Figure 7 The first semiconductor layer 11 described is similarly described as the first semiconductor layer 11''. (Refer to reference...) Figure 7 The second semiconductor layer 12 is described similarly to the second semiconductor layer 12''. (Refer to reference...) Figure 7 The active layer 13 is described similarly to the active layer 13''. (Referencing a reference layer...) Figure 7 The description of auxiliary layer 14 is similar to that of auxiliary layer 14''. Therefore, the description of repeated content can be omitted.

[0256] The bonding electrode BDE can be electrically connected to the first semiconductor layer 11''. The bonding electrode BDE may include a eutectic metal.

[0257] The first light-emitting element LD1'' may further include an insulating layer 15'' covering at least a portion of the outer peripheral surface of the vertically stacked light-emitting elements. The insulating layer 15'' prevents electrical short circuits that may occur when the active layer 13'' contacts conductive materials other than the first semiconductor layer 11'' and the second semiconductor layer 12''. The insulating layer 15'' may include a transparent insulating material. Figure 17 As shown, the insulating layer 15'' is configured to expose at least a portion of the bonding electrode BDE''. The insulating layer 15'' is configured to expose the upper surface of the auxiliary layer 14'' for contact with the cathode electrode CE.

[0258] The lower surface of the bonding electrode BDE can be connected to the first anode electrode AE1. The upper surface of the auxiliary layer 14'' can be connected to the cathode electrode CE. Therefore, the first light-emitting element LD1'' can be electrically connected between the first anode electrode AE1 and the cathode electrode CE.

[0259] According to an embodiment, a reflective electrode may also be disposed between the bonding electrode BDE and the first semiconductor layer 11''. In this case, light emitted from the first light-emitting element LD1'' can be effectively output toward the light functional layer LFL. The reflective electrode may be formed of a conductive material having a selectable reflectivity. The conductive material may include an opaque metal. The opaque metal may include, for example, metals such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and alloys thereof. However, the material of the reflective electrode is not limited to this.

[0260] Each of the second light-emitting element LD2'' and the third light-emitting element LD3'' is constructed similarly to the first light-emitting element LD1''. Descriptions of repeated content may be omitted below.

[0261] The third passivation layer PSV3 is disposed entirely on the pixel circuit layer PCL. The third passivation layer PSV3 can be used to fix the first light-emitting element LD1'', the second light-emitting element LD2'', and the third light-emitting element LD3'' to the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3, such that the first light-emitting element LD1'', the second light-emitting element LD2'', and the third light-emitting element LD3'' do not move. The third passivation layer PSV3 can be used to protect the components disposed beneath the third passivation layer PSV3 from foreign matter such as dust or moisture. For example, the third passivation layer PSV3 may include at least one of an inorganic insulating layer and an organic insulating layer. For example, the third passivation layer PSV3 may include epoxy resin, but the embodiments are not limited thereto.

[0262] In an embodiment, the third passivation layer PSV3 may not be disposed on the upper surface of each of the first light-emitting element LD1'', the second light-emitting element LD2'', and the third light-emitting element LD3''. Each of the first light-emitting element LD1'', the second light-emitting element LD2'', and the third light-emitting element LD3'' may protrude from the third passivation layer PSV3 on the third-direction DR3.

[0263] The cathode electrode CE can be disposed on the first light-emitting element LD1'', the second light-emitting element LD2'', and the third light-emitting element LD3''. The cathode electrode CE can be entirely disposed on the first light-emitting element LD1'', the second light-emitting element LD2'', the third light-emitting element LD3'', and the third passivation layer PSV3. The cathode electrode CE can contact the auxiliary layer 14'' of each of the first light-emitting element LD1'', the second light-emitting element LD2'', and the third light-emitting element LD3''. The cathode electrode CE can be electrically connected to... Figure 2 The second power voltage node VSSN. Therefore, the second power voltage applied to the second power voltage node VSSN can be transmitted to the first light-emitting element LD1'', the second light-emitting element LD2'', and the third light-emitting element LD3'' through the cathode electrode CE.

[0264] The cathode electrode CE can be configured to be substantially transparent or translucent to meet a selectable transmittance. In embodiments, the cathode electrode CE may comprise at least one of a variety of transparent conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO). However, the material of the cathode electrode CE is not limited to these.

[0265] According to an embodiment, an encapsulation layer may also be provided on the cathode electrode CE. The encapsulation layer may be configured to completely cover the cathode electrode CE. Within the spirit and scope of the disclosure, the encapsulation layer may protect the components beneath the encapsulation layer (such as the cathode electrode CE and the first light-emitting element LD1'', the second light-emitting element LD2'', and the third light-emitting element LD3'') from external water, moisture, etc. The encapsulation layer may include at least one of a metal oxide such as silicon nitride, silicon oxide, silicon oxynitride, and aluminum oxide. However, the material of the encapsulation layer is not limited to this.

[0266] A first light extraction structure OC1, a second light extraction structure OC2, and a third light extraction structure OC3 are respectively disposed on a first light-emitting element LD1'', a second light-emitting element LD2'', and a third light-emitting element LD3''. The first light extraction structure OC1 may be stacked on top of the first light-emitting element LD1''. The first light extraction structure OC1 may surround at least a portion of the side surface adjacent to the upper surface of the first light-emitting element LD1''. The second light extraction structure OC2 may be stacked on top of the second light-emitting element LD2''. The second light extraction structure OC2 may surround at least a portion of the side surface adjacent to the upper surface of the second light-emitting element LD2''. The third light extraction structure OC3 may be stacked on top of the third light-emitting element LD3''. The third light extraction structure OC3 may surround at least a portion of the side surface adjacent to the upper surface of the third light-emitting element LD3''. The first light extraction structure OC1, the second light extraction structure OC2, and the third light extraction structure OC3 may be spaced apart from each other.

[0267] With reference Figure 7 and Figure 8 The capping layer CPL is described similarly. The capping layer CPL can completely cover the first light extraction structure OC1, the second light extraction structure OC2, the third light extraction structure OC3, and the cathode electrode CE.

[0268] With reference Figure 7 and Figure 8 The first dam layer BNK and the reflective layer RFL are described similarly. The first dam layer BNK is disposed between the first light extraction structure OC1, the second light extraction structure OC2, and the third light extraction structure OC3. The reflective layer RFL is disposed between the first dam layer BNK and the first light extraction structure OC1, the second light extraction structure OC2, and the third light extraction structure OC3. The reflective layer RFL may surround at least the side surface of each of the first light extraction structure OC1, the second light extraction structure OC2, and the third light extraction structure OC3.

[0269] The first light extraction structure OC1, the second light extraction structure OC2, and the third light extraction structure OC3, along with the reflective layer RFL, can be used to improve the light output efficiency of the light generated in the first light-emitting element LD1'', the second light-emitting element LD2'', and the third light-emitting element LD3''. As described above, even if the first light-emitting element LD1'', the second light-emitting element LD2'', and the third light-emitting element LD3'' are vertical light-emitting elements, the reference can be applied substantially the same (or similarly). Figure 7 and Figure 8 The structure of the first light extraction structure OC1 and the reflective layer RFL is described to improve the light output efficiency of the flip-chip type first light-emitting element LD1.

[0270] The optical functional layer (LFL) is disposed on the first embankment layer (BNK) and the cover layer (CPL). (Refer to reference) Figure 7 The optical functional layer (LFL) described is similarly described. An optical functional layer (LFL) may include a fill layer (LRL) and a color filter layer (CFL).

[0271] In an embodiment, when the first sub-pixel SP1 is a red sub-pixel, the first light-emitting element LD1'' can be configured to emit red light. When the second sub-pixel SP2 is a green sub-pixel, the second light-emitting element LD2'' can be configured to emit green light. When the third sub-pixel SP3 is a blue sub-pixel, the third light-emitting element LD3'' can be configured to emit blue light. As described above, each of the first light-emitting element LD1'', the second light-emitting element LD2'', and the third light-emitting element LD3'' can be configured to emit light of a color corresponding to the type of the corresponding sub-pixel. In this case, reference can be applied. Figure 9 and Figure 10 The described reflective layer RFL' is used instead Figure 17 The reflective layer RFL is shown in the figure.

[0272] According to an embodiment, the first light-emitting element LD1'', the second light-emitting element LD2'', and the third light-emitting element LD3'' can emit light of the same color. In this case, a reference can be applied. Figure 11 and Figure 12 The optical functional layer LFL described is used to replace Figure 17 The light functional layer LFL shown in the figure.

[0273] Figures 18 to 24 This is a diagram illustrating a method of manufacturing a display device according to an embodiment of the present disclosure.

[0274] In the following text, refer to Figures 18 to 24 It describes the manufacturing reference. Figures 6 to 8 The method described is for display element layer DPL. In the description Figures 18 to 24 When, references can be omitted. Figures 6 to 8 The description repeats the same content.

[0275] Reference Figure 18 It can form a substrate SUB, a pixel circuit layer PCL, an adhesive layer ADL, a first light-emitting element LD1, a second light-emitting element LD2, a third light-emitting element LD3, and a third passivation layer PSV3.

[0276] Subsequently, an outer coating OC can be formed entirely on the third passivation layer PSV3. The outer coating OC can have sufficient thickness on the third-direction DR3 to completely cover the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3.

[0277] Reference Figure 19 , can be Figure 18 The outer coating OC is exposed and developed to form the first light extraction structure OC1, the second light extraction structure OC2 and the third light extraction structure OC3.

[0278] In an embodiment, the outer coating OC may include a negative photoresist material. Here, the negative photoresist material may be a material that is cured by exposure, and during development after exposure, the exposed portion of the negative photoresist material may be retained while the unexposed portion may be removed. For example, the first light extraction structure OC1, the second light extraction structure OC2, and the third light extraction structure OC3 may be the exposed portions of the outer coating OC.

[0279] As described above, since the first light extraction structure OC1, the second light extraction structure OC2, and the third light extraction structure OC3 are formed by exposing and developing an outer coating OC including a negative photoresist material, the side surfaces of the first light extraction structure OC1, the second light extraction structure OC2, and the third light extraction structure OC3 may include inverted conical inclined surfaces. Conversely, when the first light extraction structure OC1, the second light extraction structure OC2, and the third light extraction structure OC3 are formed by exposing and developing an outer coating OC including a positive photoresist material, the side surfaces of the first light extraction structure OC1, the second light extraction structure OC2, and the third light extraction structure OC3 will include positive conical inclined surfaces.

[0280] In this embodiment, the outer coating OC may include scattering particles SCT. Therefore, the first light extraction structure OC1, the second light extraction structure OC2, and the third light extraction structure OC3 formed by exposing and developing the outer coating OC may also include scattering particles SCT.

[0281] Reference Figure 20 A capping layer CPL can be formed that completely covers the first light extraction structure OC1, the second light extraction structure OC2, the third light extraction structure OC3, and the third passivation layer PSV3. There are no restrictions on the method for forming the capping layer CPL, and various methods can be used.

[0282] Reference Figure 21 A reflective layer RFL can be formed that completely covers the cover layer CPL. There are no restrictions on the method for forming the reflective layer RFL, and various methods can be used.

[0283] Reference Figure 22This allows for the formation of a first dam layer (BNK) that completely covers the reflective layer RFL. In this case, the upper surface of the first dam layer (BNK) can be substantially flat. Between the first light extraction structure OC1, the second light extraction structure OC2, and the third light extraction structure OC3, the lowermost surface of the first dam layer (BNK) can be completely covered by the reflective layer RFL.

[0284] Reference Figure 23 The first embankment layer BNK can be removed by etching in a region that overlaps with at least a portion of the upper surface of each of the first light extraction structure OC1, the second light extraction structure OC2, and the third light extraction structure OC3. Therefore, the reflective layer RFL in the region that overlaps with at least a portion of the upper surface of each of the first light extraction structure OC1, the second light extraction structure OC2, and the third light extraction structure OC3 can be exposed.

[0285] Reference Figure 24 The first dam layer (BNK) can be used as a mask to etch the reflective layer (RFL). Therefore, the reference layer can be removed. Figure 23 The exposed portion of the reflective layer RFL is described. The side surfaces of the first embankment layer BNK and the side surfaces of the reflective layer RFL can be aligned with each other.

[0286] Figures 25 to 28 This is a diagram illustrating a method for manufacturing a display device according to an embodiment.

[0287] In the following text, refer to Figures 25 to 28 It describes the manufacturing reference. Figure 6 , Figure 9 and Figure 10 The method described is for display element layer DPL. In the description Figures 25 to 28 When, the reference can be omitted. Figure 6 , Figure 9 and Figure 10 The description repeats the same content.

[0288] Reference Figure 25 , can execute reference Figures 18 to 21 The steps described. Therefore, descriptions of repeated content can be omitted.

[0289] Reference Figure 26 The reflective layer RFL can be etched in a region that overlaps with at least a portion of the upper surface of each of the first light extraction structure OC1, the second light extraction structure OC2, and the third light extraction structure OC3.

[0290] In an embodiment, the etching of the reflective layer RFL can be anisotropic dry etching of the reflective layer RFL. In this case, a portion of the side surface of the reflective layer RFL surrounding the first light extraction structure OC1, the second light extraction structure OC2, and the third light extraction structure OC3, including the inverted conical inclined surface, can be retained without being removed by anisotropic dry etching. Another portion of the reflective layer RFL disposed on the capping layer CPL between the first light extraction structure OC1, the second light extraction structure OC2, and the third light extraction structure OC3, adjacent to the aforementioned portion of the reflective layer RFL, can be retained without being removed by anisotropic dry etching. Therefore, a reference can be formed. Figure 9 and Figure 10 The reflective layer RFL' is described. In this case, between the first light extraction structure OC1, the second light extraction structure OC2, and the third light extraction structure OC3, a portion of the overlay layer CPL can be exposed and not covered by the reflective layer RFL'.

[0291] Reference Figure 27 A first dam layer BNK can be formed that completely covers the overlay layer CPL and the reflective layer RFL'. In this case, the upper surface of the first dam layer BNK can be substantially flat. The lowermost surface of the first dam layer BNK can be uncovered by the reflective layer RFL' between the first light extraction structure OC1, the second light extraction structure OC2, and the third light extraction structure OC3, and can contact the exposed overlay layer CPL.

[0292] Reference Figure 28 The first embankment layer BNK can be removed by etching in a region that overlaps with at least a portion of the upper surface of each of the first light extraction structure OC1, the second light extraction structure OC2, and the third light extraction structure OC3. Therefore, the cover layer CPL in the region overlapping with at least a portion of the upper surface of each of the first light extraction structure OC1, the second light extraction structure OC2, and the third light extraction structure OC3 can be exposed.

[0293] Figure 29 This is a block diagram illustrating a display system according to an embodiment.

[0294] Reference Figure 29 The display system 1000 may include a processor 1100 and a display device 1200.

[0295] Processor 1100 can perform various tasks and calculations. In embodiments, within the spirit and scope of the disclosure, processor 1100 may include an application processor, graphics processor, microprocessor, central processing unit (CPU), etc. Processor 1100 can be connected to other components of display system 1000 via a bus system to control those other components.

[0296] The processor 1100 can transmit image data IMG and control signal CTRL to the display device 1200. The display device 1200 can display an image based on the image data IMG and control signal CTRL. The display device 1200 can be compared with a reference... Figure 1 The described display device DD is similarly constructed. In this case, the image data IMG and the control signal CTRL can be respectively used as... Figure 1 The input image data IMG and control signal CTRL are provided.

[0297] Display system 1000 may include computing systems that provide image display capabilities, such as smartwatches, mobile phones, smartphones, portable computers, tablet PCs, watch phones, car displays, smart glasses, portable multimedia players (PMPs), navigation devices, and ultra-mobile personal computers (UMPCs). Display system 1000 may include at least one of head-mounted display (HMD) devices, virtual reality (VR) devices, mixed reality (MR) devices, and augmented reality (AR) devices.

[0298] Figures 30 to 33 It is shown Figure 29 A schematic perspective view illustrating an application example of the display system.

[0299] Reference Figure 30 , Figure 29 The display system 1000 can be applied to a smartwatch 2000, which includes a display unit 2100 and a belt unit 2200.

[0300] The smartwatch 2000 can be a wearable electronic device. For example, the smartwatch 2000 can have a structure in which the strap unit 2200 is mounted on the user's wrist. Here, the display system 1000 and / or display device 1200 can be applied to the display unit 2100 and can provide the user with image data including time information.

[0301] Reference Figure 31 , Figure 29 The display system 1000 can be applied to the automotive display system 3000. Here, the automotive display system 3000 may include a computing system disposed inside and / or outside the vehicle to provide image data.

[0302] For example, the display system 1000 and / or display device 1200 can be applied to at least one of the infotainment panel 3100, instrument cluster 3200, passenger display 3300, head-up display 3400, side mirror display 3500 and rear seat display 3600 installed in the vehicle.

[0303] Reference Figure 32 , Figure 29 The display system 1000 can be applied to the smart glasses 4000. The smart glasses 4000 can be a wearable electronic device that can be worn on a user's head. For example, the smart glasses 4000 can be a wearable device for augmented reality.

[0304] The smart glasses 4000 may include a frame 4100 and a lens unit 4200. The frame 4100 may include a housing 4110 supporting the lens unit 4200 and a leg unit 4120 for the user to wear. The leg unit 4120 may be hinged to the housing 4110 and may be folded or unfolded relative to the housing 4110.

[0305] The battery, touch pad, microphone, camera, etc. can be built into the frame 4100. The projector that outputs light, the processor that controls the light signal, etc. can be built into the frame 4100.

[0306] Lens unit 4200 may include optical components that transmit or reflect light. For example, within the spirit and scope of the disclosure, lens unit 4200 may include glass, transparent synthetic resin, etc.

[0307] To enable the user's eyes to recognize visual information, the lens unit 4200 can reflect the image generated by the light signal transmitted from the projector of the frame 4100 onto the rear surface of the lens unit 4200 (e.g., the surface facing the user's eyes). For example, the user can recognize visual information (such as time and date) displayed on the lens unit 4200. In this case, the projector and / or lens unit 4200 can be a type of display device. The display device 1200 can be applied to the projector and / or lens unit 4200.

[0308] Reference Figure 33 , Figure 29 The display system 1000 can be applied to head-mounted display devices 5000.

[0309] The head-mounted display device 5000 can be a wearable electronic device that can be worn on a user's head. For example, the head-mounted display device 5000 can be a wearable device for virtual reality or mixed reality.

[0310] The head-mounted display device 5000 may include a headband 5100 and a display device housing 5200. The headband 5100 may be connected to the display device housing 5200. The headband 5100 may include a horizontal strap and / or a vertical strap for securing the head-mounted display device 5000 to a user's head. The horizontal strap may be configured to surround the sides of the user's head, and the vertical strap may be configured to surround the upper part of the user's head. However, the embodiments are not limited thereto. For example, within the spirit and scope of the disclosure, the headband 5100 may be implemented in the form of eyeglass frames, helmets, etc.

[0311] The display device housing 5200 can accommodate the display system 1000 and / or the display device 1200.

[0312] Although the above embodiments have been described, it will be understood that those skilled in the art can make various modifications and changes to the disclosure without departing from the spirit and scope of the disclosure and the appended claims.

Claims

1. A display device, the display device comprising: Multiple light-emitting elements are disposed on the pixel circuit layer; Multiple light extraction structures are spaced apart from each other on the pixel circuit layer and stacked with the multiple light-emitting elements; The first embankment layer is disposed between the plurality of light extraction structures; as well as A reflective layer is disposed between the plurality of light extraction structures and the first dam layer, the reflective layer at least surrounding a side surface of each of the plurality of light extraction structures, wherein, Each of the plurality of light-emitting elements is covered by a corresponding light-extraction structure among the plurality of light-extraction structures, and The side surface of each of the plurality of light extraction structures includes a substantially inverted conical inclined surface.

2. The display device according to claim 1, wherein, Each of the plurality of light extraction structures includes a negative photoresist material.

3. The display device according to claim 1, wherein, The reflective layer is not disposed between the lower surface of each of the plurality of light extraction structures and the pixel circuit layer.

4. The display device according to claim 1, wherein, Each of the plurality of light extraction structures surrounds at least a portion of a side surface adjacent to the upper surface of a corresponding light-emitting element among the plurality of light-emitting elements.

5. The display device according to claim 1, wherein, Each of the plurality of light extraction structures includes scattering particles.

6. The display device according to claim 1, wherein, The upper edge of each of the plurality of light extraction structures has a substantially circular shape in cross-section.

7. The display device according to claim 1, wherein, The side surface between the lower surface and the upper edge of each of the plurality of light extraction structures is a substantially inverted conical inclined surface in cross-section.

8. The display device according to claim 7, wherein, The reflective layer extends from the side surface of each of the plurality of light extraction structures to further cover the upper edge of each of the plurality of light extraction structures and the portion of the upper surface adjacent to the upper edge.

9. The display device according to claim 8, wherein, The reflective layer covers the lowest surface of the first embankment layer.

10. The display device according to claim 8, wherein, The side surfaces of the reflective layer and the side surfaces of the first dam layer are aligned with each other on the upper surface of each of the plurality of light extraction structures.

11. The display device according to claim 7, wherein, The reflective layer covers the portion of the upper edge adjacent to the side surface of each of the plurality of light extraction structures, but does not cover the upper surface of each of the plurality of light extraction structures.

12. The display device according to claim 11, wherein, The lowest surface of the first embankment is not covered by the reflective layer.

13. The display device according to claim 1, further comprising: Multiple light conversion patterns are spaced apart from each other and are superimposed on the multiple light extraction structures.

14. The display device according to claim 13, further comprising: A second dike layer, superimposed on the first dike layer and surrounding each of the plurality of light conversion patterns; as well as A light-reflecting layer is disposed between the plurality of light conversion patterns and the second dam layer.

15. A method for manufacturing a display device, the method comprising the following steps: Multiple light-emitting elements are formed on the pixel circuit layer; Multiple light extraction structures spaced apart from each other are formed on the pixel circuit layer, and the multiple light extraction structures are stacked with the multiple light-emitting elements; A reflective layer is formed entirely on the pixel circuit layer, and the reflective layer covers the plurality of light extraction structures; A first dam layer is formed entirely on the reflective layer, the first dam layer covering the reflective layer; The first embankment is etched in a region that overlaps with at least a portion of the upper surface of each of the plurality of light extraction structures; as well as The reflective layer is etched using the first dike layer as a mask. Each of the plurality of light-emitting elements is surrounded by a corresponding light-extraction structure among the plurality of light-extraction structures, and Each of the plurality of light extraction structures has a side surface comprising a substantially inverted conical inclined surface.

16. The method according to claim 15, wherein, The steps for forming the plurality of light extraction structures include: An outer coating is formed entirely on the pixel circuit layer, the outer coating covering the plurality of light-emitting elements; and The plurality of light extraction structures are formed by exposing and developing the outer coating.

17. The method according to claim 16, wherein, The outer coating comprises a negative photoresist material.

18. A method of manufacturing a display device, the method comprising the following steps: Multiple light-emitting elements are formed on the pixel circuit layer; Multiple light extraction structures are formed on the pixel circuit layer, spaced apart from each other and superimposed on the multiple light-emitting elements; A reflective layer is formed entirely on the pixel circuit layer, and the reflective layer covers the plurality of light extraction structures; The reflective layer is etched in a region that overlaps with at least a portion of the upper surface of each of the plurality of light extraction structures; A first dam layer is formed entirely on the pixel circuit layer, the first dam layer covering the plurality of light extraction structures and the reflective layer; as well as The first embankment is etched in a region overlapping at least a portion of the upper surface of each of the plurality of light extraction structures. Each of the plurality of light-emitting elements is surrounded by a corresponding light-extraction structure among the plurality of light-extraction structures, and Each of the plurality of light extraction structures has a side surface comprising a substantially inverted conical inclined surface.

19. The method according to claim 18, wherein, The step of etching the reflective layer includes anisotropic dry etching of the reflective layer.

20. The method according to claim 19, wherein, In the step of etching the reflective layer, a portion of the reflective layer disposed between the plurality of light extraction structures is etched.

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