Improvement of joint performance for large area gap filling

Abstract

Methods of filling features on a semiconductor substrate can include performing a process of filling the features on the semiconductor substrate by repeatedly performing first operations. The first operations can include providing a silicon-containing precursor. The first operations can include contacting the substrate with the silicon-containing precursor to form a silicon-containing material within the features defined on the substrate. The first operations can include purging a semiconductor processing chamber. The first operations can include providing an oxygen-containing precursor. The first operations can include contacting the substrate with the oxygen-containing precursor to form a silicon-and-oxygen-containing material within the features defined on the substrate. At least some portions of the first operations can be performed with frequency characteristics, power characteristics, and pressure characteristics.

Description

[0001] Interactive reference for related applications

[0002] This application claims the benefit and priority of U.S. non-provisional application No. 18 / 410,634, filed January 11, 2024, entitled “SEAM PERFORMANCE IMPROVEMENT FOR LARGE AREA GAPFILL”, the contents of which are incorporated herein by reference in their entirety for all purposes. Technical Field

[0003] This technology relates to methods for processing semiconductors. More specifically, this technology relates to methods for forming materials on semiconductor structures. Background Technology

[0004] Integrated circuits are made possible by processes that create complex patterned material layers on substrate surfaces. Creating patterned materials on a substrate requires controlled methods for forming and removing the material. As device size continues to shrink and device complexity continues to increase, the resulting structures have become increasingly complex. Developing structures may involve more operations to create complex patterning and material integration. Furthermore, complex patterning and material integration at the junctions of materials (including similar materials) may require more operations to prevent potential deformation or undesirable formation.

[0005] Therefore, there is a need for improved systems and methods that can be used to produce high-quality devices and structures. These and other needs are addressed by this technology. Summary of the Invention

[0006] In some embodiments, a method of filling a feature on a semiconductor substrate may include performing a process in a semiconductor processing chamber for filling the feature on the semiconductor substrate, wherein the process includes repeatedly performing first operations, the first operations including: providing a silicon-containing precursor; contacting the substrate with the silicon-containing precursor to form a silicon-containing material within the feature defined on the substrate; purifying the semiconductor processing chamber; providing an oxygen-containing precursor plasma with a power characteristic and a pressure characteristic based at least in part on the frequency characteristics of a plasma power source of the semiconductor processing chamber, wherein the power characteristic, the pressure characteristic, and the frequency characteristic are configured to increase the radical density of the oxygen-containing precursor plasma and provide a range of kinetic energy to the ions of the oxygen-containing precursor plasma; and contacting the substrate with the oxygen-containing precursor to form a silicon- and oxygen-containing material within the feature defined on the substrate.

[0007] In some embodiments, a method of filling a feature on a semiconductor substrate includes performing a process in a semiconductor processing chamber for filling the feature on the semiconductor substrate, wherein the process includes repeatedly performing first operations, the first operations including: providing a silicon-containing precursor; contacting the substrate with the silicon-containing precursor to form a silicon-containing material within the feature defined on the substrate; purifying the semiconductor processing chamber; providing an oxygen-containing precursor; and contacting the substrate with the oxygen-containing precursor by forming a plasma with a frequency characteristic, a power characteristic, and a pressure characteristic, wherein the power characteristic, the pressure characteristic, and the frequency characteristic are configured to provide sufficient radical density and kinetic energy, wherein contacting the substrate with the oxygen-containing precursor forms a silicon- and oxygen-containing material within the feature defined on the substrate.

[0008] In some embodiments, a method of filling a feature on a semiconductor substrate includes performing a process in a semiconductor processing chamber to fill the feature on the semiconductor substrate, wherein the process includes repeatedly performing first operations at a first pressure level, the first operations including: providing a silicon-containing precursor; contacting the substrate with the silicon-containing precursor to form a silicon-containing material within the feature defined on the substrate; purging the semiconductor processing chamber; providing an oxygen-containing precursor; and providing an oxygen-containing precursor. The process for further filling the feature may further include a second operation, the second operation including applying a silicon-containing, non-oxide-containing material by a conformal coating process.

[0009] In any implementation, any and all of the following features may be implemented in any combination and without limitation. In some implementations, providing the oxygen-containing precursor with the power characteristics, pressure characteristics, and frequency characteristics may close the gaps in the feature by bonding a first side of the silicon- and oxygen-containing material within the feature to a second side of the silicon- and oxygen-containing material within the feature. In some implementations, forming the silicon-containing material within the feature may include forming a silicon atom layer on the exposed surface of the feature. In some implementations, forming the silicon- and oxygen-containing material within the feature may include providing oxygen to the silicon atom layer. In some implementations, contacting the silicon- and oxygen-containing material with the oxygen-containing precursor under the frequency characteristics, power characteristics, and pressure characteristics may close the gaps in the feature by bonding a first side of the silicon- and oxygen-containing material within the feature to a second side of the silicon- and oxygen-containing material within the feature. In some implementations, the frequency characteristics may be in the range of about 25 MHz to 30 MHz. In some implementations, the pressure characteristics may be in a second range of about 4 Torr to about 15 Torr. In some embodiments, the power characteristic is in a third range of about 1500 watts to about 3000 watts. In some embodiments, providing the oxygen-containing precursor plasma may include providing the oxygen-containing precursor plasma at a second frequency characteristic of a second plasma power supply in the semiconductor processing chamber, the second frequency characteristic being in a fourth range of about 1 kHz to 1 MHz. In some embodiments, the characteristic may be characterized as an aspect ratio greater than or about 10:1. In some embodiments, the oxygen-containing precursor may include O2. In some embodiments, the power characteristic is in the range of about 1000 watts to about 2000 watts. In some embodiments, the pressure characteristic is in a second range of about 8 Torr to about 15 Torr. In some embodiments, the frequency characteristic is in a third range of about 10 MHz to 15 MHz. In some embodiments, the process may be performed at a temperature above or about 400°C. In some embodiments, the conformal coating process may be a chemical vapor deposition process. In some embodiments, the conformal coating process may be an atomic layer deposition process. In some embodiments, the silicon-containing and non-oxide-containing material may include at least one of the following: SiC, SiN, and high-purity silicon. In some embodiments, these second operations may be performed in a semiconductor processing chamber. Attached Figure Description

[0010] The nature and advantages of the disclosed technology can be further understood by referring to the rest of the specification and the accompanying drawings.

[0011] Figure 1 A schematic cross-sectional view of an exemplary plasma system according to some embodiments of the present technology is shown.

[0012] Figures 2A to 2D An exemplary cross-sectional schematic structure in which a material layer is generated according to some embodiments of the present technology is shown.

[0013] Figures 3A to 3B An exemplary cross-sectional schematic structure in which a material layer is generated according to some embodiments of the present technology is shown.

[0014] Figure 4 Operations in a semiconductor processing method according to some embodiments of the present technology are illustrated.

[0015] Figures 5A to 5B An exemplary cross-sectional schematic structure in which a material layer is generated according to some embodiments of the present technology is shown.

[0016] Figure 6 Operations in a semiconductor processing method according to some embodiments of the present technology are illustrated.

[0017] Several figures in the accompanying drawings are included as schematic diagrams. It should be understood that the drawings are for illustrative purposes and should not be considered to scale unless specifically stated otherwise. Furthermore, as schematic diagrams, the drawings are provided to aid understanding and may not include all aspects or information compared to actual representations, and may include exaggerated material for illustrative purposes.

[0018] In the accompanying drawings, similar parts and / or features may have the same reference numerals. Furthermore, various parts of the same type may be distinguished by a letter following the reference numeral to differentiate them among similar parts. If only the first reference numeral is used in the specification, the description applies to any similar parts having the same first reference numeral, regardless of the letter. Detailed Implementation

[0019] In semiconductor device manufacturing, silicon is used in a wide range of structures and processes. In gap-filling operations, some processes utilize plasma-enhanced deposition under process conditions to attempt to improve deposition directionality, allowing the deposited material to better fill features on the substrate. However, in some deposition processes, when deposited materials meet with other deposited materials, the deposited material in certain types of features may characterize as seams. For example, if a feature has a significantly large aspect ratio (meaning the feature is deep, but the opening size of the feature is relatively small in width), the deposited material from the sides of the feature may meet and form seams. These seams can indicate that the gap-filling process has failed to properly fill the gaps and may lead to structural problems as other semiconductor manufacturing processes are performed on the substrate.

[0020] As feature sizes continue to shrink, deposition can present challenges for narrow features that may further characterize even higher aspect ratios. For example, when the material is deposited onto a feature with a high aspect ratio, seams may form between the deposited material on the first side and the deposited material on the second side of the feature. Seams can also be referred to as gaps or voids. A seam indicates that the deposited material on the sides of the feature is not bonded when they meet. These seams may be undetectable by tools because they are at the atomic level. However, etchants used on the deposited material (such as buffered oxide etchants on silicon oxide deposits) may expose and / or reveal the seams between the deposited material on the sides of the feature.

[0021] This technique overcomes these limitations by performing atomic layer deposition of materials with sufficiently high radical density and optimized kinetic energy, which improves large gap-filling operations by eliminating and / or reducing seams in the gap-filling material. Sufficiently high radical density and optimized kinetic energy can be achieved by carefully tuning the power supplied to the plasma and the pressure within the semiconductor fabrication chamber based on the frequency of the plasma power source. Increasing the radical density in the gap-filling material provides more bonding sites on both sides of the deposited material, aiding in side-bonding. Sufficient kinetic energy, when sufficient radicals are present, provides enough energy to bond the two sides. Excessive kinetic energy may cause damage within the gap-filling material. Furthermore, the gap-filling operation can include partially filling the gap by forming a compressible film layer, and then filling the remaining portion of the gap by applying a non-oxide silicon material using a conformal process. In this way, the gap filling can be both compressive and does not form seams between the two sides of the non-oxide silicon material at the center of the gap filler.

[0022] While the remainder of the disclosure will routinely identify specific deposition processes utilizing the disclosed technology and will describe one type of semiconductor processing chamber, it should be readily understood that the described processes can be performed in any number of semiconductor processing chambers. Furthermore, this technology is applicable to any number of semiconductor processes, not limited to the exemplary processes described below. Therefore, this technology should not be considered as limited to use with these specific deposition processes or chambers. Before describing the method of semiconductor processing according to this technology, this disclosure will discuss a possible chamber that can be used to perform the processes according to embodiments of this technology.

[0023] Figure 1A cross-sectional view of an exemplary processing chamber 100 according to some embodiments of the present technology is shown. This figure may illustrate an overview of a system incorporated into one or more aspects of the present technology and / or may be specifically configured to perform one or more operations according to embodiments of the present technology. Additional details of the chamber 100 or the performed methods may be further described below. The chamber 100 may be used to form film layers, etch material layers, form other material layers, or combinations thereof; however, it should be understood that deposition and etching methods may also be similarly performed in any chamber in which deposition and etching processes can be performed. The processing chamber 100 may include a chamber body 102, a substrate support 104 disposed within the chamber body 102, and a cover assembly 106 coupled to the chamber body 102 and enclosing the substrate support 104 within a processing volume 120. A substrate 103 may be provided to the processing volume 120 through an opening 126, which may conventionally be sealed using a slit valve or door for processing. During processing, the substrate 103 may be seated on a surface 105 of the substrate support. In some embodiments, the substrate support 104 can be rotated along a vertical axis, wherein the axis 144 of the substrate support 104 can be located on this axis, or it can be stationary. Alternatively, the substrate support 104 can be lifted and rotated as needed during the deposition process.

[0024] Gas distributor 112 may define an orifice 118 for dispensing process precursors into processing volume 120. Gas distributor 112 may be coupled to a first power source 142, such as an RF generator, RF power supply, DC power supply, pulsed DC power supply, pulsed RF power supply, or any other power source that may be coupled to the processing chamber. In some embodiments, the first power source 142 may be an RF power supply.

[0025] The gas distributor 112 can be a conductive or non-conductive gas distributor. The gas distributor 112 can also be formed from both conductive and non-conductive components. For example, the body of the gas distributor 112 can be conductive, while the panel of the gas distributor 112 can be non-conductive. The gas distributor 112 can be powered, for example, by means of... Figure 1 As shown, it is powered by a first power source 142, or in some embodiments, the gas distributor 112 may be coupled to the ground.

[0026] The first electrode 122 may be coupled to the substrate support 104. The first electrode 122 may be embedded within the substrate support 104 or coupled to the surface of the substrate support 104. The first electrode 122 may be a plate, perforated plate, mesh, wire mesh, or any other distributed arrangement of conductive elements. The first electrode 122 may be a tuning electrode and may be coupled to a tuning circuit 136 via, for example, a conduit 146 (e.g., a cable with a selected resistance, such as 50 ohms) disposed in a shaft 144 of the substrate support 104. The tuning circuit 136 may have an electronic sensor 138 and an electronic controller 140, the electronic controller 140 being a variable capacitor. The electronic sensor 138 may be a voltage or current sensor and may be coupled to the electronic controller 140 to provide further control over plasma conditions in the processing volume 120.

[0027] The second electrode 124 may be a bias electrode and / or an electrostatic clamping electrode, and the second electrode 124 may be coupled to the substrate support 104. The second electrode may be coupled to the second power source 150 via a filter 148, which may be an impedance matching circuit. The second power source 150 may be a DC power supply, a pulsed DC power supply, an RF bias power supply, a pulsed RF power supply, or a bias power supply, or a combination of these or other power sources. In some embodiments, the second power source 150 may be an RF bias power supply. The substrate support 104 may also include one or more heating elements configured to heat the substrate to a processing temperature, which may be between about 25°C and about 800°C or higher.

[0028] Figure 1 The cover assembly 106 and substrate support 104 can be used with any processing chamber for plasma or thermal processing. In operation, the processing chamber 100 can provide real-time control of plasma conditions in the processing volume 120, such as via a system controller 101 that may be contained within the processor 107. The substrate 103 can be mounted on the substrate support 104, and process gases can be flowed through the cover assembly 106 via inlet 114 according to any desired flow pattern. The gas can exit the processing chamber 100 through outlet 152. A power supply can be coupled to a gas distributor 112 to establish plasma in the processing volume 120. In some embodiments, a second electrode 124 can be used to apply an electrical bias to the substrate.

[0029] When plasma is excited in processing volume 120, a potential difference can be established between the plasma and the first electrode 122. The flow properties of the ground path, represented by tuning circuit 136, can then be adjusted using electronic controller 140. A setpoint can be delivered to tuning circuit 136 to provide independent control over the deposition rate and the uniformity of plasma density from center to edge. In embodiments where the electronic controller may be a variable capacitor, electronic sensors can adjust the variable capacitor to independently maximize the deposition rate and minimize thickness non-uniformity.

[0030] The tuning circuit 136 may have a variable impedance that can be adjusted using the electronic controller 140. In the case where the electronic controller 140 is a variable capacitor, the capacitance range of each of the variable capacitors can be selected to provide an impedance range. This range may depend on the frequency and voltage characteristics of the plasma, which may have a minimum value within the capacitance range of each variable capacitor. Therefore, when the capacitance of the electronic controller 140 is at its minimum or maximum, the impedance of the tuning circuit 136 may be high, resulting in a plasma shape with minimal air or lateral coverage above the substrate support. When the capacitance of the electronic controller 140 approaches a value that minimizes the impedance of the tuning circuit 136, the air coverage of the plasma can be maximized, effectively covering the entire operating area of ​​the substrate support 104. When the capacitance of the electronic controller 140 deviates from the minimum impedance setting, the plasma shape may shrink from the chamber wall, and the air coverage of the substrate support may decrease.

[0031] Electronic sensor 138 can be used in tuning circuit 136 within a tuning closed loop. Depending on the type of sensor used, a current or voltage setpoint can be installed in each sensor, and control software can be provided to the sensor to determine adjustments to electronic controller 140 to minimize deviations from the setpoint. Therefore, the plasma shape can be selectively and dynamically controlled during processing. It should be understood that while the foregoing discussion is based on electronic controller 140, which can be a variable capacitor, any electronic component with adjustable characteristics can be used to provide adjustable impedance to tuning circuit 136.

[0032] Processing chamber 100 can be used in some embodiments of the present technology for a bottom-up deposition process of materials that may include semiconductor structures. It should be understood that the described chamber should not be considered limiting, and any chamber that can be configured to perform the operations described can be used similarly.

[0033] Processing chamber 100 can be used in some embodiments of the present technology for processing methods that may include the formation, etching, or material transfer of semiconductor structures. It should be understood that the described chamber should not be considered limiting, and any chamber that can be configured to perform the operations described can be used similarly. Figures 2A to 2D The illustrations schematically depict exemplary operations in processing methods according to some embodiments of the present technology. These methods can be performed in various processing chambers and on one or more host machines or tools, including the processing chamber 100 described above. The processing methods may include a large number of optional operations, which may or may not be specifically associated with some embodiments of the methods according to the present technology. For example, many of these operations are described to provide a broader scope of structure formation, but these operations are not critical to the present technology, or, as readily understood, can be performed by other alternative methods. It should be understood that the figures illustrate only partial schematics, and structure 200 or substrate 205 may contain any number of additional materials and features having the various characteristics and aspects shown in the figures.

[0034] Substrate 205 may include any number of materials used in semiconductor processing. The substrate material may be or include silicon, germanium, dielectric materials including silicon oxide or silicon nitride, metallic materials, or any combination of these materials. Substrate 205 may include one or more substrate features formed therein. Substrate 205 may include one or more materials 210 in which one or more features can be formed. Features may be characterized as any shape or configuration according to the art. In some embodiments, features may be or include trench structures 208 or holes formed within the substrate. In some embodiments, features may be characterized as any aspect ratio (or height-to-width ratio of the structure), but in some embodiments, the material may be characterized as a larger aspect ratio, which may not allow for seamless or void-free deposition using known techniques or methods. For example, in some implementations, the aspect ratio of any layer of the exemplary structure may be greater than or about 10:1, greater than or about 11:1, greater than or about 12:1, greater than or about 13:1, greater than or about 14:1, greater than or about 15:1, greater than or about 16:1, or greater. Additionally, the feature may be characterized as a reduced width, such as less than or about 2.0 micrometers, less than or about 1.9 micrometers, less than or about 1.8 micrometers, less than or about 1.7 micrometers, less than or about 1.6 micrometers, less than or about 1.5 micrometers, less than or about 1.4 micrometers, less than or about 1.3 micrometers, less than or about 1.2 micrometers, less than or about 1.1 micrometers, less than or about 1.0 micrometers, less than or about 0.9 micrometers, less than or about 0.8 micrometers, less than or about 0.7 micrometers, less than or about 0.6 micrometers, less than or about 0.5 micrometers, less than or about 0.4 micrometers, less than or about 0.3 micrometers, less than or about 0.2 micrometers, less than or about 0.1 micrometers, or smaller, including any portion of any of the stated figures. Therefore, a feature can be characterized by its height, such as less than or about 20.0 micrometers, less than or about 19.0 micrometers, less than or about 18.0 micrometers, less than or about 17.0 micrometers, less than or about 16.0 micrometers, less than or about 15.0 micrometers, less than or about 14.0 micrometers, less than or about 13.0 micrometers, less than or about 12.0 micrometers, less than or about 11.0 micrometers, less than or about 10.0 micrometers, less than or about 9.0 micrometers, less than or about 8.0 micrometers, less than or about 7.0 micrometers, less than or about 6.0 micrometers, less than or about 5.0 micrometers, less than or about 4.0 micrometers, less than or about 3.0 micrometers, less than or about 2.0 micrometers, less than or about 1.0 micrometer, less than or about 0.8 micrometers, or smaller, including any part of any of the stated figures. This combination of high aspect ratio and minimum width can make it difficult for many conventional deposition operations to bond the deposited material on one side of the feature to the deposited material on the other side of the feature.

[0035] The methods described herein may include additional operations prior to initiating operations for gap-filling joints. For example, additional processing operations may include forming a structure on the semiconductor substrate 205, which may include forming and removing material. For example, a transistor structure, a memory structure, or any other structure may be formed. The prior processing operations may be performed in a chamber where the methods for gap-filling joints described herein are performed, or in one or more other processing chambers before delivering the substrate to one or more semiconductor processing chambers where the methods for gap-filling joints described herein can be performed. In any case, the methods for gap-filling joints described herein may, as appropriate, include delivering the semiconductor substrate 205 to a processing region of a semiconductor processing chamber, such as processing chamber 100 described above, or other chambers that may include components as described above. The substrate 205 may be deposited on a substrate support, which may be a base such as substrate support 104, and may reside in a processing region of the semiconductor processing chamber, such as a processing volume.

[0036] Embodiments of this disclosure can form silicon-containing and / or silicon-and-oxygen-containing materials via atomic layer deposition. The material can be formed by alternately providing precursors, thus forming the material intermittently. For depositing the silicon-and-oxygen-containing material, the precursor may include silicon and oxygen. A precursor including silicon may be referred to as a silicon-containing precursor. A precursor including oxygen may be referred to as an oxygen-containing precursor. In some embodiments, the silicon-and-oxygen-containing material can be formed via atomic layer deposition. To incorporate oxygen, the precursor may further include oxygen. For example, an oxygen-containing precursor may be provided intermittently during formation. Alternatively, the silicon-containing precursor may further include oxygen. For example, the silicon-containing precursor may be a silicon-and-oxygen-containing precursor.

[0037] Embodiments of this disclosure can be used to fill gaps formed along the side surfaces of a silicon- and oxygen-containing material. In some embodiments, the gap-filling gap can be accomplished by atomic layer deposition. The gap-filling gap can be formed by alternately providing precursors, thus the material is formed intermittently. One precursor may include silicon and may be referred to as a silicon-containing precursor. Another precursor may include oxygen and may be referred to as an oxygen-containing precursor.

[0038] In embodiments, the silicon-containing precursor may be any silicon-containing material useful in semiconductor processing, such as in atomic layer deposition processes. Exemplary silicon-containing precursors may be, or include, but are not limited to, silanes, disilanes, or other aminosilanes, or other organosilanes, including cyclohexylsilane, silicon tetrafluoride, silicon tetrachloride, dichlorosilane, tetraethyl orthosilicate (TEOS), tetramethyldisiloxane (TMDSO), hexamethyldisiloxane (HMDSO), hexamethyldisilazane (HMDSN), and tetra(ethylmethylamide) (TEMASi), alkylaminosilanes, trisilymines, alkylaminodisilanes, alkylsilanes, alkyloxysilanes, alkylsilanols, and alkyloxysilanols, as well as any other silicon-containing precursors that can be used for the formation of silicon-containing materials. In some embodiments, the silicon-containing precursor may include halogens, such as chlorine, bromine, iodine, or any other halogen. Additional silicon-containing precursors may be, or include, any of the following materials:

[0039] In the above materials, each X can be independently selected from chlorine, bromine, iodine, hydrogen, OR, NR2, NCO, NCS or CN, wherein R can be an alkyl group.

[0040] The oxygen-containing precursor can be any oxygen-containing material useful in semiconductor processing, such as in atomic layer deposition processes. For example, the oxygen-containing precursor can be molecular oxygen (O2), ozone (O3), N2O, and / or other similar materials. In embodiments, to maintain the oxygen content in the forming material, the oxygen-containing precursor can be diluted with another precursor (such as an inert precursor). Based on the oxygen-containing precursor and the inert precursor, the oxygen-containing precursor can be less than or about 50%.

[0041] The method described herein for filling gaps may include providing a first precursor to a semiconductor processing chamber, such as a processing region of the semiconductor processing chamber. Where appropriate, a plasma of the first precursor may be generated. It is also contemplated that the plasma of the first precursor may be generated prior to providing the plasma of the first precursor to the semiconductor processing chamber. In some embodiments, the first precursor is a silicon-containing precursor. (See also...) Figure 2A The first precursor may have at least one reactive group that can bond with groups on the surface of the substrate 205 or one or more materials 210 attached to the processing area. Molecules of the first precursor 215 (e.g., a silicon-containing precursor) can react with surface groups to form bonds connecting the first precursor molecules to the surface of the substrate 205 or one or more materials 210. The reaction between the molecules of the first precursor 215 and the groups on the surface of the substrate 205 or one or more materials 210 can continue until most or all of the surface groups are bonded to the reactive groups on the molecules of the first precursor 215. Figure 2BAs shown, a first portion of the silicon-containing material 220 can be formed from the first precursor. The formation of the silicon and oxygen-containing material 220 can prevent further reaction between the molecules of the first precursor 215 in the first precursor effluent and the substrate 205 or one or more materials 210.

[0042] The first precursor can be held in the processing region for a period of time to almost or completely form the silicon-containing material 220. To form the silicon-containing material according to embodiments of the present invention, the precursor can be delivered by alternating pulses to allow material growth. In some embodiments, the pulse duration of the first precursor can be greater than or about 0.5 seconds, greater than or about 1 second, greater than or about 2 seconds, greater than or about 3 seconds, greater than or about 4 seconds, greater than or about 5 seconds, greater than or about 10 seconds, greater than or about 20 seconds, greater than or about 40 seconds, greater than or about 60 seconds, greater than or about 80 seconds, greater than or about 100 seconds, or longer.

[0043] The methods described herein may also include operations such as purging or removing the first precursor from the processing region after the formation of the silicon-containing material 220. The methods described herein may include stopping the flow of the first precursor before purging it from the semiconductor processing chamber. The first precursor can be removed by pumping it out of the processing region for a time period ranging from about 10 seconds to about 100 seconds. Additional exemplary time ranges may include about 20 seconds to about 50 seconds and about 25 seconds to about 45 seconds, among others. However, in some embodiments, the increased purge time may begin to remove reaction sites, which may reduce uniform formation. Therefore, in some embodiments, purge may be performed for less than or about 60 seconds, and may be performed for less than or about 50 seconds, less than or about 40 seconds, less than or about 30 seconds, or less. In some embodiments, a purge gas may be introduced into the processing region to assist in the removal of effluent. Exemplary purge gases include helium and nitrogen, among others.

[0044] After removing the first precursor, as Figure 2CAs shown, a second precursor can be provided to a semiconductor processing chamber. Depending on the situation, a plasma of the second precursor can be generated. It is also conceivable that the plasma of the second precursor can be generated before it is provided to the semiconductor processing chamber. The second precursor may have at least one reactive group that can form a bond with an unreacted reactive group of the first precursor forming the silicon-containing material 220. In some embodiments, the second precursor is an oxygen-containing precursor. Molecules of the second precursor 225 can react with unreacted reactive groups of the first precursor to form bonds that link the molecules of the second precursor 225 to the molecules of the first precursor 215. The reaction between the molecules of the second precursor 225 and the molecules of the first precursor 215 can continue until most or all of the unreacted reactive groups on the molecules of the first precursor 215 have reacted with the molecules of the second precursor 225. Figure 2D As shown, the contact between the second precursor and the silicon-containing material 220 can form a silicon- and oxygen-containing material 230, such as silicon oxide (SiO or SiO2). The formation of the silicon- and oxygen-containing material 230 can prevent further reaction between the molecules of the second precursor 225 and the silicon- and oxygen-containing material 220 in the second precursor effluent.

[0045] Similar to the first precursor, the second precursor can be held in the processing region for a period of time to almost or completely form the silicon and oxygen-containing material 230. As previously discussed, to form the silicon and oxygen-containing material according to embodiments of the present technology, the precursor can be delivered by alternating pulses to allow material growth. In some embodiments, the pulse duration of the second precursor can be greater than or about 0.5 seconds, greater than or about 1 second, greater than or about 2 seconds, greater than or about 3 seconds, greater than or about 4 seconds, greater than or about 5 seconds, greater than or about 10 seconds, greater than or about 20 seconds, greater than or about 40 seconds, greater than or about 60 seconds, greater than or about 80 seconds, greater than or about 100 seconds, or longer.

[0046] In some embodiments, the first precursor can be pulsed for a longer period than the second precursor. By increasing the residence time of the first precursor, improved adhesion can be achieved across substrate 205 or one or more materials 210. The second precursor can then react more readily with the ligands of the first precursor, and therefore the second precursor can be pulsed for a shorter time, which can improve throughput. For example, in some embodiments, the second precursor can be pulsed for less than or about 90% of the pulsed time of the first precursor. The second precursor can also be pulsed for less than or about 80%, less than or about 70%, less than or about 60%, less than or about 50%, less than or about 40%, less than or about 30%, or less than the pulsed time of the first precursor.

[0047] The methods described herein may also include operations to purify or remove the second precursor effluent from the processing area after the formation of the silicon-containing material 230. The methods described herein may include stopping the flow of the second precursor before purifying it. The second precursor can be removed by pumping it out of the processing area for a time period ranging from about 10 seconds to about 100 seconds. Additional exemplary time ranges may include about 20 seconds to about 50 seconds and about 25 seconds to about 45 seconds, among others. In some embodiments, a purging gas may be introduced into the processing area to assist in the removal of the effluent. Exemplary purging gases include helium and nitrogen, among others.

[0048] In an implementation, after one or more cycles of forming the silicon and oxygen-containing material 230, it can be determined whether the target thickness of the as-deposited material on the substrate 205 or one or more materials 210 has been achieved. If the target thickness of the as-deposited material has not been achieved, another cycle providing the first and second precursors can be performed. If the target thickness of the as-deposited material has been achieved, another cycle providing the first and second precursors may not be started. The exemplary number of cycles used to form the silicon and oxygen-containing material 230 may include one cycle, or may include more than two cycles, five cycles, ten cycles, twenty-five cycles, fifty cycles, one hundred cycles, one thousand hundred cycles, two thousand cycles, three thousand cycles, four thousand cycles, five thousand cycles, six thousand cycles, seven thousand cycles, eight thousand cycles, nine thousand cycles, ten thousand cycles, or more. Additional illustrative ranges for the number of cycles may include 50 to 2000 cycles, 50 to 1000 cycles, and 100 to 750 cycles, 1000 to 2000 cycles, 2000 to 3000 cycles, 3000 to 4000 cycles, 4000 to 5000 cycles, 5000 to 6000 cycles, 6000 to 7000 cycles, 7000 to 8000 cycles, 8000 to 9000 cycles, 9000 to 10000 cycles, and / or any combination of these ranges. For example, for a 1 μm wide gap structure, some embodiments may use between 6000 and 8000 cycles. An illustrative range for the target thickness used to interrupt further cycles of forming the silicon and oxygen-containing material 230 includes less than or about 1.0 micrometer. Additional illustrative thickness ranges may include less than or about 1.0 micrometer, less than or about 0.9 micrometer, less than or about 0.8 micrometer, less than or about 0.7 micrometer, less than or about 0.6 micrometer, less than or about 0.5 micrometer, less than or about 0.4 micrometer, less than or about 0.3 micrometer, less than or about 0.2 micrometer, less than or about 0.1 micrometer, or smaller, including any fraction of any of the stated figures.

[0049] Figures 3A to 3B The diagram schematically illustrates how seams can be formed during processing according to some embodiments of the present technology. Cross sections 302 and 304 schematically illustrate how a seam 350 is formed from a silicon- and oxygen-containing material 330 (e.g., silicon- and oxygen-containing material 230 in Figure 2) deposited into one or more materials 310 (e.g., one or more materials 210 in Figure 2). Figure 3A In the image, the space 340 between the two sides of the silicon and oxygen-containing material 330 deposited in the feature can be seen. The silicon and oxygen-containing material 330 may span the surface of one or more materials 310 and is generally uniform.

[0050] exist Figure 3B During deposition, as more silicon and oxygen-containing material 330 is deposited, seams 350 may form, causing the two sides of the silicon and oxygen-containing material 330 to become unbonded. Seams 350 may form because the layer of silicon and oxygen-containing material 330 accumulates starting from the characteristic side. As mentioned above, seams 350 may be undetectable because they may be at the atomic and / or molecular level. However, if an etchant (e.g., a buffered oxide etchant for etching the silicon and oxygen-containing material 330) is applied along the seam 350 to the silicon and oxygen-containing material 330, the seam 350 becomes detectable as the silicon and oxygen-containing material 330 surrounding the seam 350 is etched away.

[0051] Figure 4 An exemplary flowchart 400 illustrates a method for filling features on a semiconductor substrate in a manner that reduces or eliminates seams, as described herein. This method can be performed by a controller that generates signals for controlling a processing chamber and other components, as described above. Figures 2A to 2D and Figures 3A to 3B As illustrated. This method can be performed by a controller with a processor, which executes instructions to perform these operations.

[0052] The method may include performing a process in a semiconductor processing chamber to fill features on a semiconductor substrate. The process may include repeatedly performing a first operation, as described herein. For example, the first operation may be repeated up to a plurality of cycles, as described herein. Additionally, portions of the first operation may be repeated up to a different number of cycles, such that a portion of the first operation may be repeated up to a first number of cycles, and a second portion of the first operation may be repeated up to a second number of cycles. In some embodiments, the feature may be characterized as having an aspect ratio greater than or about 10:1, as described herein.

[0053] The first operation may include providing a silicon-containing precursor (402) to a semiconductor processing chamber (e.g., Figure 1 The processing chamber 100), as per at least Figures 2A to 2DAs described herein. Silicon-containing precursors may be the first precursors, as described herein.

[0054] The first operation may include contacting a substrate with a silicon-containing precursor to form a silicon-containing material (404) within a feature defined on the substrate, as described herein. Forming the silicon-containing material within the feature may include forming a layer of silicon atoms on an exposed surface of the feature. The exposed surface of the feature may include two or more sides of the feature, for example, sides opposite to each other.

[0055] The formation of the silicon-containing material 220 (either providing a silicon-containing precursor and contacting the substrate with the silicon-containing precursor, or both) can be performed at various temperatures (e.g., the temperature of the substrate 205, the temperature of the processing chamber, and / or the temperature of the precursor flowing into the processing area). Exemplary temperatures of the substrate, processing chamber, and / or precursor during the operations described herein can be above or about 50°C, above or about 75°C, above or about 100°C, above or about 125°C, above or about 150°C, above or about 175°C, above or about 200°C, above or about 250°C, above or about 300°C, above or about 350°C, above or about 400°C, above or about 425°C, above or about 450°C, above or about 475°C, above or about 500°C, above or about 525°C, and higher. The temperature may be at or above 550°C, above or about 575°C, above or about 600°C, above or about 625°C, above or about 650°C, above or about 675°C, above or about 700°C, above or about 725°C, above or about 750°C, above or about 775°C, above or about 800°C, above or about 825°C, above or about 850°C, above or about 875°C, above or about 900°C, above or about 925°C, above or about 950°C, above or about 975°C, above or about 1000°C, or higher. In some embodiments, the exemplary temperature may be in the range of 400°C to 1000°C. In some embodiments, the exemplary temperature may be in the range of 400°C to 700°C. In some embodiments, the exemplary temperature may be in the range of 600°C to 1000°C. By maintaining the substrate temperature at an elevated level, such as above or about 400°C in some embodiments, an increased number of nucleation sites along the substrate 205 can be made available, which can improve formation and reduce void formation by improving coverage at each location.

[0056] The formation of silicon-containing material 220 (either providing a silicon-containing precursor or contacting a substrate with the silicon-containing precursor) can be performed at various pressures within the processing chamber. Exemplary pressures in the processing region can range from about 1 Torr to about 100 Torr. In some embodiments, the pressure in the processing region can range from 2 to 20 Torr. In embodiments, the pressure can be less than or about 20 Torr, such as less than or about 19 Torr, less than or about 18 Torr, less than or about 17 Torr, less than or about 16 Torr, less than or about 15 Torr, less than or about 14 Torr, less than or about 13 Torr, less than or about 12 Torr, less than or about 11 Torr, less than or about 10 Torr, less than or about 9 Torr, less than or about 8 Torr, less than or about 7 Torr, less than or about 6 Torr, less than or about 5 Torr, less than or about 4 Torr, less than or about 3 Torr, less than or about 2 Torr, less than or about 1 Torr, or less. In some embodiments, a portion of the process in the processing chamber can be performed at approximately atmospheric pressure, as described herein.

[0057] The formation of the silicon-containing material 220 (either providing a silicon-containing precursor or contacting the substrate with the silicon-containing precursor) can be performed at various power and frequencies of the plasma power source. Exemplary power can range from about 100 watts to about 5000 watts. In some embodiments, the power can range from 1000 watts to 3000 watts. In embodiments, the power can be less than or about 5000 watts, such as less than or about 4500 watts, less than or about 4000 watts, less than or about 3500 watts, less than or about 3000 watts, less than or about 2500 watts, less than or about 2000 watts, less than or about 1500 watts, less than or about 1000 watts, less than or about 500 watts, or less. Exemplary frequencies can range from 1 kHz to 100 MHz. In some embodiments, the frequency can range from 1 kHz to 30 MHz. In implementations, the power may be less than or about 100 MHz, such as less than or about 95 MHz, less than or about 90 MHz, less than or about 85 MHz, less than or about 80 MHz, less than or about 75 MHz, less than or about 70 MHz, less than or about 65 MHz, less than or about 60 MHz, less than or about 55 MHz, less than or about 50 MHz, less than or about 45 MHz, less than or about 40 MHz, less than or about 35 MHz, less than or about 30 MHz, less than or about 27 MHz, less than or about 25 MHz, less than or about 20 MHz, less than or about 15 MHz, less than or about 13.56 MHz, less than or about 10 MHz, less than or about 5 MHz, less than or about 1 MHz, less than or about 750 kHz, less than or about 500 kHz, less than or about 350 kHz, less than or about 250 kHz, less than or about 100 kHz, less than or about 10 kHz, or less. In some instances, industry standards may use approximately 27 MHz, approximately 13.56 MHz, and / or approximately 350 kHz.

[0058] The first operation may include purifying the semiconductor processing chamber (406), as described herein. Purifying the silicon-containing precursor in the semiconductor processing chamber allows for the use of other precursors to fill features on the semiconductor substrate during the process.

[0059] The first operation may include providing an oxygen-containing precursor plasma (408), as described herein. Providing the oxygen-containing precursor may close the gaps in the feature by bonding a first side of the silicon- and oxygen-containing material within the feature to a second side of the silicon- and oxygen-containing material within the feature, as per at least Figures 3A to 3B As described. In some embodiments, the oxygen-containing precursor may include O2. In some embodiments, the oxygen-containing precursor may include, primarily include, or be solely plasma. In some embodiments, the oxygen-containing precursor may include, primarily include, or be solely gas.

[0060] The first operation may include contacting a substrate with an oxygen-containing precursor to form a silicon- and oxygen-containing material (410) within a defined feature on the substrate, as described herein. Forming the silicon- and oxygen-containing material within the feature may include supplying oxygen to atomic layers of silicon.

[0061] In some instances, the oxygen-containing precursor plasma is provided with power characteristics and under pressure characteristics. In some instances, the values ​​of the power and pressure characteristics are at least partially based on the frequency characteristics of the plasma power source in the semiconductor processing chamber. In some instances, the values ​​of the power and pressure characteristics are at least partially based on the frequency characteristics of the oxygen-containing precursor plasma. The power, pressure, and frequency characteristics can be configured to increase the radical density (e.g., the radical density of the oxygen-containing precursor plasma and / or the silicon- and oxygen-containing materials) to a sufficient threshold value. The power, pressure, and frequency characteristics can be configured to provide kinetic energy (e.g., provided to the oxygen-containing precursor plasma and / or the silicon- and oxygen-containing materials) within a range having minimum and maximum threshold values.

[0062] As described herein, gap-filling operations minimize seams (and / or precursors and / or formed materials), which may require a minimum amount of radical density and sufficiently optimal (e.g., neither too much nor too little) kinetic energy. Therefore, power, pressure, and frequency characteristics need to minimize seam formation and / or improve seam performance within certain ranges. In some instances, increasing the frequency characteristic increases radical density. In some instances, decreasing the frequency characteristic decreases radical density. In some instances, increasing the frequency characteristic decreases kinetic energy. In some instances, decreasing the frequency characteristic increases kinetic energy. In some instances, increasing the pressure characteristic decreases kinetic energy. In some instances, decreasing the pressure characteristic increases kinetic energy. In some instances, increasing the power characteristic increases both radical density and kinetic energy. In some instances, decreasing the power characteristic decreases both radical density and kinetic energy.

[0063] In this way, an increase in power characteristics can be paired with an increase in pressure characteristics, so that the power characteristics provide an increased (up to exceeding the threshold) free radical density and kinetic energy, while the increased pressure characteristics can reduce the kinetic energy to the range between the lowest and highest thresholds. Similarly, an increase in power characteristics can be paired with an increase in frequency characteristics, so that the power characteristics provide an increased (up to exceeding the threshold) free radical density and kinetic energy, while the increased frequency characteristics can reduce the kinetic energy to the range between the lowest and highest thresholds. The increased frequency characteristics can also increase free radical density, thus helping to raise the free radical density above the threshold.

[0064] In some instances, multiple frequency characteristics can be used. For example, a first power source may have a first frequency characteristic, while a second power source may have a second frequency characteristic. The first frequency characteristic can be a higher frequency to increase the free radical density. The second frequency characteristic can be a lower frequency to increase kinetic energy. The combination of these frequency characteristics can simultaneously provide the benefits of increased kinetic energy and increased free radical density.

[0065] As previously discussed, plasma effluents containing silicon precursors and / or oxygen precursors can be generated. In some embodiments, plasma effluents containing only oxygen precursors can be generated, while silicon precursors may not contain plasma. By generating plasma effluents containing one or more precursors, the directionality of the effluent can be improved, which can help promote seamless and void-free material deposition. When generating plasma, one or more inert precursors (such as argon, helium, or nitrogen) can be provided together with the precursors to assist in generating plasma effluents and distributing the precursors. The plasma of the inert precursors can be capacitively coupled plasma (CCP), plasma formed in a remote plasma source (RPS), or microwave plasma.

[0066] After forming the silicon- and oxygen-containing material 230, the methods described herein may include performing a post-formation processing. The post-formation processing may include providing an inert precursor to a semiconductor processing chamber, generating a plasma effluent of the inert precursor, and contacting the silicon- and oxygen-containing material 230 with the plasma effluent of the inert precursor. The inert precursor may be or include any inert precursor, such as argon, helium, or nitrogen. Similar to the optional plasmas of the first, second, and / or third precursors, the plasma of the inert precursor may be a capacitively coupled plasma (CCP) plasma, a plasma formed in a remote plasma source (RPS), or a microwave plasma. The plasma effluent of the inert precursor can regenerate reactive species on the surface of the exposed material, which may allow continued growth to occur. The plasma effluent of the inert precursor can densify the material by venting hydrogen.

[0067] The formation of the silicon and oxygen-containing material 230 (either providing an oxygen-containing precursor or contacting the substrate with the oxygen-containing precursor, or both) can be carried out at various temperatures (e.g., the temperature of the substrate 205, the temperature of the processing chamber, and / or the temperature of the precursor flowing into the processing area). Exemplary temperatures of the substrate, processing chamber, and / or precursor during the operations described herein can be above or about 50°C, above or about 75°C, above or about 100°C, above or about 125°C, above or about 150°C, above or about 175°C, above or about 200°C, above or about 250°C, above or about 300°C, above or about 350°C, above or about 400°C, above or about 425°C, above or about 450°C, above or about 475°C, above or about 500°C, above or about 525°C, and higher. The temperature may be at or above 550°C, above or about 575°C, above or about 600°C, above or about 625°C, above or about 650°C, above or about 675°C, above or about 700°C, above or about 725°C, above or about 750°C, above or about 775°C, above or about 800°C, above or about 825°C, above or about 850°C, above or about 875°C, above or about 900°C, above or about 925°C, above or about 950°C, above or about 975°C, above or about 1000°C, or higher. In some embodiments, the exemplary temperature may be in the range of 400°C to 1000°C. In some embodiments, the exemplary temperature may be in the range of 400°C to 700°C. In some embodiments, the exemplary temperature may be in the range of 600°C to 1000°C. In some embodiments, the exemplary temperature may be in the range of 500°C to 600°C. In some embodiments, the exemplary temperature may be 550°C. By maintaining the substrate temperature at an elevated level, such as above or about 400°C in some embodiments, an increased number of nucleation sites along the substrate 205 can be made available, which can improve formation and reduce void formation by improving coverage at each location.

[0068] The formation of the silicon- and oxygen-containing material 230 (either providing an oxygen-containing precursor or contacting the substrate with the oxygen-containing precursor) can be performed at various pressures within the processing chamber. The formation rate of the silicon- and oxygen-containing material 230 can also depend on the pressure within the processing chamber. An exemplary pressure in the processing region can range from about 1 Torr to about 100 Torr. In some embodiments, the pressure in the processing region can range from 2 to 20 Torr. In embodiments, the pressure can be less than or about 20 Torr, such as less than or about 19 Torr, less than or about 18 Torr, less than or about 17 Torr, less than or about 16 Torr, less than or about 15 Torr, less than or about 14 Torr, less than or about 13 Torr, less than or about 12 Torr, less than or about 11 Torr, less than or about 10 Torr, less than or about 9 Torr, less than or about 8 Torr, less than or about 7 Torr, less than or about 6 Torr, less than or about 5 Torr, less than or about 4 Torr, less than or about 3 Torr, less than or about 2 Torr, less than or about 1 Torr, or less. In some embodiments, a portion of the process within the processing chamber may be carried out at approximately atmospheric pressure, as described herein.

[0069] The formation of the silicon- and oxygen-containing material 230 (either providing a silicon-containing precursor or contacting the substrate with the silicon-containing precursor) can be performed at various power and frequencies of the plasma power source. Exemplary power can range from about 100 watts to about 5000 watts. In some embodiments, the power can range from 1000 watts to 3000 watts. In embodiments, the power can be less than or about 5000 watts, such as less than or about 4500 watts, less than or about 4000 watts, less than or about 3500 watts, less than or about 3000 watts, less than or about 2500 watts, less than or about 2000 watts, less than or about 1500 watts, less than or about 1000 watts, less than or about 500 watts, or less. Exemplary frequencies can range from 1 kHz to 100 MHz. In some embodiments, the frequency can range from 1 kHz to 30 MHz. In implementations, the power may be less than or about 100 MHz, such as less than or about 95 MHz, less than or about 90 MHz, less than or about 85 MHz, less than or about 80 MHz, less than or about 75 MHz, less than or about 70 MHz, less than or about 65 MHz, less than or about 60 MHz, less than or about 55 MHz, less than or about 50 MHz, less than or about 45 MHz, less than or about 40 MHz, less than or about 35 MHz, less than or about 30 MHz, less than or about 27 MHz, less than or about 25 MHz, less than or about 20 MHz, less than or about 15 MHz, less than or about 13.56 MHz, less than or about 10 MHz, less than or about 5 MHz, less than or about 1 MHz, less than or about 750 kHz, less than or about 500 kHz, less than or about 350 kHz, less than or about 250 kHz, less than or about 100 kHz, less than or about 10 kHz, or less. In some instances, industry standards may use approximately 27 MHz, approximately 13.56 MHz, and / or approximately 350 kHz.

[0070] In some instances, the frequency response may be between 10 MHz and 15 MHz (e.g., 13.56 MHz). In such instances with a frequency response between 10 MHz and 15 MHz, the power response may be between 1000 watts and 2000 watts. In such instances with a frequency response between 10 MHz and 15 MHz, the pressure response may be between 8 Torr and 15 Torr. In some instances, the frequency response is approximately 13.56 MHz, the power response is approximately 1000 watts, and the pressure response is approximately 10 Torr. In some instances, the frequency response may be between 25 MHz and 30 MHz (e.g., 27 MHz). In such instances with a frequency response between 25 MHz and 30 MHz, the power response may be between 1500 watts and 3000 watts. In such instances with a frequency response between 25 MHz and 30 MHz, the pressure response may be between 4 Torr and 15 Torr. In some instances, the frequency response is approximately 27 MHz, the power response is approximately 2000 watts, and the pressure response is between 4 Torr and 10 Torr.

[0071] In some instances, the first frequency characteristic may be between 25 MHz and 30 MHz (e.g., 27 MHz), and the second frequency characteristic may be between 1 kHz and 1 MHz (e.g., 350 kHz). The first power associated with a first power source having the first frequency characteristic and the second power associated with a second power source having the second frequency characteristic may be the same or different. For example, the first power may be greater than the second power. Alternatively, the second power may be greater than the first power. In some instances, the total power (some operations combining the first and second power, such as adding the power) may be equal to 1000 to 5000 watts. In some instances, each power (the first power and the second power) may be equal to 1000 to 5000 watts.

[0072] In some instances, the final set of cycles for forming the silicon- and oxygen-containing material 230 (specifically, providing either or both of a silicon-containing precursor and contacting a substrate with the silicon-containing precursor) can be performed with the specific pressure, power, and frequency characteristics described herein (e.g., frequency characteristics between 10 MHz and 15 MHz, power characteristics between 1000 watts and 2000 watts, and pressure characteristics between 8 Torr and 15 Torr). For example, if the total number of cycles for forming the silicon- and oxygen-containing material is 1000 cycles, the first 900 cycles can be performed without using the specific pressure, power, and frequency characteristics described herein, but the last 100 cycles can be performed with the specific pressure, power, and frequency characteristics described herein. In some instances, the last 50% or less of the cycles are performed with specific pressure, power, and frequency characteristics. In some instances, the percentage of cycles performed with specific pressure, power, and frequency characteristics may be the last 50% or less of the cycles, the last 45% or less of the cycles, the last 40% or less of the cycles, the last 35% or less of the cycles, the last 30% or less of the cycles, the last 25% or less of the cycles, the last 20% or less of the cycles, the last 15% or less of the cycles, the last 10% or less of the cycles, or the last 5% or less of the cycles, or less. In some instances, the number of cycles performed with specific pressure, power, and frequency characteristics may be the last 1000 cycles or less. In some instances, the number of cycles performed with specific pressure, power, and frequency characteristics may be the last 1000 cycles or less, the last 900 cycles or less, the last 900 cycles or less, the last 800 cycles or less, the last 700 cycles or less, the last 600 cycles or less, the last 500 cycles or less, the last 400 cycles or less, the last 300 cycles or less, the last 200 cycles or less, the last 100 cycles or less, the last 50 cycles or less, or less.

[0073] Figures 5A to 5B The diagram schematically illustrates a treatment method for improving joint performance according to some embodiments of the present technology. Cross-section 502 illustrates the formation of a silicon- and oxygen-containing material 530 (e.g., the silicon- and oxygen-containing material 230 of Figure 2) deposited into one or more materials 510 (e.g., one or more materials 210 of Figure 2). Figure 5A In the image, the space 540 between the two sides of the silicon and oxygen-containing material 530 deposited in the feature can be seen. The silicon and oxygen-containing material 530 may span substantially uniformly across the surface of one or more materials 510.

[0074] exist Figure 5BIn this process, a silicon-containing, non-oxide-containing material 550 can be deposited to fill space 540. The silicon-containing, non-oxide-containing material 550 may not contain oxygen. The silicon-containing, non-oxide-containing material 550 can be deposited using any conformal process (e.g., atomic layer deposition or chemical vapor deposition). The silicon-containing, non-oxide-containing material 550 can be silicon (e.g., high-purity silicon), silicon carbide, or silicon nitride. When an etchant (such as a buffer oxide etchant that etches the silicon-containing and oxygen-containing material 530) is applied to both the silicon-containing and oxygen-containing material 530 and the silicon-containing, non-oxide-containing material 550, the seam may be imperceptible. Atomic layer deposition of the silicon-containing and oxygen-containing material 530 can be used to form a sufficiently compressed gap filler. Conformal deposition of the silicon-containing, non-oxide-containing material 550 can be used to give the sufficiently compressed gap filler good seam performance, which is achieved by not forming a seam.

[0075] Figure 6 An exemplary flowchart 600 illustrating a method for filling features on a semiconductor substrate is shown, as described herein. This method can be performed by a controller that generates signals for controlling a processing chamber and other components, as described above. Figures 2A to 2D and Figures 5A to 5B As illustrated. This method can be implemented using a controller with a processor that executes instructions for performing the operation.

[0076] The method may include performing a process in a semiconductor processing chamber to fill features on a semiconductor substrate. The process may include repeatedly performing a second operation (601), as described herein. For example, the second operation may be repeated up to a plurality of cycles, as described herein. Additionally, portions of the second operation may be repeated up to a different number of cycles, such that a portion of the second operation may be repeated up to a first number of cycles, and a second portion of the second operation may be repeated up to a second number of cycles. In some embodiments, the feature may be characterized as having an aspect ratio greater than or about 10:1, as described herein.

[0077] In some embodiments, the second operation may be performed at the first pressure level. In some embodiments, the first pressure level may be less than or about 100 torr, as described herein. Indicative pressures in the processing area may range from about 1 to about 100 torr. In some embodiments, pressures in the processing area may range from 2 to 20 torr. In embodiments, pressures may be less than or about 20 torr, such as less than or about 19 torr, less than or about 18 torr, less than or about 17 torr, less than or about 16 torr, less than or about 15 torr, less than or about 14 torr, less than or about 13 torr, less than or about 12 torr, less than or about 11 torr, less than or about 10 torr, less than or about 9 torr, less than or about 8 torr, less than or about 7 torr, less than or about 6 torr, less than or about 5 torr, less than or about 4 torr, less than or about 3 torr, less than or about 2 torr, less than or about 1 torr, or less. In some embodiments, a portion of the process in the processing chamber may be performed at approximately atmospheric pressure, as described herein.

[0078] In some embodiments, the second operation may be performed at the first temperature. In some embodiments, the first temperature may be a temperature above or about 400°C, as described herein. In some embodiments, the second operation may be performed at a temperature above or about 400°C, as described herein. During the operations described herein, the exemplary temperatures of the substrate, processing chamber, and / or precursor may be above or about 400°C, above or about 425°C, above or about 450°C, above or about 475°C, above or about 500°C, above or about 525°C, above or about 550°C, above or about 575°C, above or about 600°C, above or about 625°C, above or about 650°C, above or about 675°C, above or about 700°C, above or about 725°C, above or about 750°C, above or about 775°C, above or about 800°C, above or about 825°C, above or about 850°C, above or about 875°C, above or about 900°C, above or about 925°C, above or about 950°C, above or about 975°C, above or about 1000°C, or higher. In some embodiments, the exemplary temperature may be in the range of 400°C to 1000°C. In some embodiments, the exemplary temperature may be in the range of 400°C to 700°C. In some embodiments, the exemplary temperature may be in the range of 600°C to 1000°C.

[0079] The second operation may include providing a silicon-containing precursor (602) to a semiconductor processing chamber (e.g., Figure 1 The processing chamber 100), as per at least Figures 2A to 2D As described herein. Silicon-containing precursors may be the first precursors, as described herein.

[0080] The second operation may include contacting the substrate with a silicon-containing precursor to form a silicon-containing material (604) within a feature defined on the substrate, as described herein. Forming the silicon-containing material within the feature may include forming an atomic layer of silicon on an exposed surface of the feature. The exposed surface of the feature may include two or more sides of the feature, for example, sides opposite to each other.

[0081] The second operation may include purifying the semiconductor processing chamber (606), as described herein. Purifying the silicon-containing precursor in the semiconductor processing chamber allows for the use of other precursors to fill features on the semiconductor substrate during the process.

[0082] The second operation may include providing an oxygen-containing precursor (608), as described herein. In some embodiments, the oxygen-containing precursor may include, primarily include, or be solely a plasma. In some embodiments, the oxygen-containing precursor may include, primarily include, or be solely a gas.

[0083] The second operation may include contacting the substrate with an oxygen-containing precursor to form a silicon- and oxygen-containing material (610) within a defined feature on the substrate, as described herein. Forming the silicon- and oxygen-containing material within the feature may include supplying oxygen to atomic layers of silicon.

[0084] The process may also include repeatedly performing the third operation (613), as described herein. For example, the third operation may be repeated up to several cycles, as described herein. Additionally, portions of the third operation may be repeated up to different numbers of cycles, such that a portion of the third operation may be repeated up to a first number of cycles, and a second portion of the third operation may be repeated up to a second number of cycles. In some embodiments, the feature may be characterized as an aspect ratio greater than or about 10:1, as described herein. The third operation may be performed in the same semiconductor processing chamber as the second operation.

[0085] In some embodiments, the third operation may be performed at a second pressure level. In some embodiments, the second pressure level may be less than or equal to 100 tors. An exemplary pressure in the processing area may range from about 1 to about 100 tors. In some embodiments, the pressure in the processing area may range from 2 to 20 tors. In embodiments, the pressure may be less than or about 20 tors, such as less than or about 19 tors, less than or about 18 tors, less than or about 17 tors, less than or about 16 tors, less than or about 15 tors, less than or about 14 tors, less than or about 13 tors, less than or about 12 tors, less than or about 11 tors, less than or about 10 tors, less than or about 9 tors, less than or about 8 tors, less than or about 7 tors, less than or about 6 tors, less than or about 5 tors, less than or about 4 tors, less than or about 3 tors, less than or about 2 tors, less than or about 1 tors, or less. In some embodiments, a portion of the process in the processing chamber may be performed at approximately atmospheric pressure, as described herein.

[0086] In some embodiments, the third operation may be performed at a second temperature. In some embodiments, the second temperature may be a temperature above or about 400°C, as described herein. In some embodiments, the first temperature and the second temperature may be different. In some embodiments, the third operation may be performed at a temperature above or about 400°C, as described herein. During the operations described herein, the exemplary temperatures of the substrate, processing chamber, and / or precursor may be above or about 400°C, above or about 425°C, above or about 450°C, above or about 475°C, above or about 500°C, above or about 525°C, above or about 550°C, above or about 575°C, above or about 600°C, above or about 625°C, above or about 650°C, above or about 675°C, above or about 700°C, above or about 725°C, above or about 750°C, above or about 775°C, above or about 800°C, above or about 825°C, above or about 850°C, above or about 875°C, above or about 900°C, above or about 925°C, above or about 950°C, above or about 975°C, above or about 1000°C, or higher. In some embodiments, the exemplary temperature may be in the range of 400°C to 1000°C. In some embodiments, the exemplary temperature may be in the range of 400°C to 700°C. In some embodiments, the exemplary temperature may be in the range of 600°C to 1000°C.

[0087] The third operation may include applying a silicon-containing, non-oxide-containing material (614) via a conformal process, as described herein. For example, the silicon-containing, non-oxide-containing material may be... Figure 5B The silicon-containing and non-oxide-containing material 550. In some embodiments, the silicon-containing and non-oxide-containing material 550 may include silicon (Si), such as high-purity silicon or single-crystal silicon. In some embodiments, the silicon-containing and non-oxide-containing material 550 may include silicon carbide (SiC). In some embodiments, the silicon-containing and non-oxide-containing material 550 may include silicon nitride (SiN). In some embodiments, the oxygen-containing precursor may include, primarily include, or only include plasma. In some embodiments, the oxygen-containing precursor may include, primarily include, or only include gas.

[0088] Silicon-containing and non-oxide-containing materials can be applied using any conformal process. In some instances, silicon-containing and non-oxide-containing materials can be applied using chemical vapor deposition. In some instances, silicon-containing and non-oxide-containing materials can be applied using atomic layer deposition. For example, atomic layer deposition of silicon-containing and non-oxide-containing materials may include alternately providing and contacting different precursors, as described herein. In some embodiments, the second operation as described herein may be performed prior to the third operation. For example, the second operation may be repeated prior to the third operation. In some embodiments, the percentage of the total cycle for the second and third operations may be allocated such that the second operation accounts for about 90% of the total cycle, about 80% of the total cycle, about 70% of the total cycle, about 60% of the total cycle, about 50% of the total cycle, about 40% of the total cycle, about 30% of the total cycle, about 20% of the total cycle, and the first operation accounts for about 10% of the total cycle, or less.

[0089] In some implementations, a target thickness for the silicon- and oxygen-containing material and / or a target thickness for the silicon- and non-oxide-containing material can be determined. If the target thickness for the silicon- and oxygen-containing material is not reached, another cycle of the second operation can be performed. If the target thickness for the silicon- and oxygen-containing material has been reached, a cycle of the third operation can be performed. If the target thickness for the silicon- and non-oxide-containing material has been reached, the third operation can be stopped. The exemplary number of cycles used for the second operation may include one cycle, or may include more than two cycles, five cycles, ten cycles, twenty-five cycles, fifty cycles, one hundred cycles, one thousand hundred cycles, two thousand cycles, three thousand cycles, four thousand cycles, five thousand cycles, six thousand cycles, seven thousand cycles, eight thousand cycles, nine thousand cycles, ten thousand cycles, or more. Additional illustrative ranges for the number of cycles may include 50 to 2000 cycles, 50 to 1000 cycles, and 100 to 750 cycles, 1000 to 2000 cycles, 2000 to 3000 cycles, 3000 to 4000 cycles, 4000 to 5000 cycles, 5000 to 6000 cycles, 6000 to 7000 cycles, 7000 to 8000 cycles, 8000 to 9000 cycles, 9000 to 10000 cycles, and / or any combination of these ranges. For example, for a 1 μm wide gap structure, some embodiments may use between 6000 and 8000 cycles. Illustrative ranges for the target thickness used to interrupt further cycles of forming the silicon and oxygen-containing material include less than or about 1.0 micrometer. Additional exemplary thickness ranges may include less than or about 1.0 micrometer, less than or about 0.9 micrometer, less than or about 0.8 micrometer, less than or about 0.7 micrometer, less than or about 0.6 micrometer, less than or about 0.5 micrometer, less than or about 0.4 micrometer, less than or about 0.3 micrometer, less than or about 0.2 micrometer, less than or about 0.1 micrometer, or smaller, including any portion of any of the stated figures. The exemplary number of cycles for the third operation may include 1 cycle, or may include more than 2 cycles, 5 cycles, 10 cycles, 25 cycles, 50 cycles, 100 cycles, 1000 cycles, 2000 cycles, 3000 cycles, 4000 cycles, 5000 cycles, 6000 cycles, 7000 cycles, 8000 cycles, 9000 cycles, 10000 cycles, or more.Additional illustrative ranges for the number of cycles may include 50 to 2000 cycles, 50 to 1000 cycles, and 100 to 750 cycles, 1000 to 2000 cycles, 2000 to 3000 cycles, 3000 to 4000 cycles, 4000 to 5000 cycles, 5000 to 6000 cycles, 6000 to 7000 cycles, 7000 to 8000 cycles, 8000 to 9000 cycles, 9000 to 10000 cycles, and / or any combination of these ranges. For example, for a 1 μm wide gap structure, some embodiments may use between 6000 and 8000 cycles. An illustrative range for the target thickness used to interrupt further cycles of forming the silicon-containing and non-oxide-containing material includes less than or about 1.0 micrometer. Additional illustrative thickness ranges may include less than or about 1.0 micrometer, less than or about 0.9 micrometer, less than or about 0.8 micrometer, less than or about 0.7 micrometer, less than or about 0.6 micrometer, less than or about 0.5 micrometer, less than or about 0.4 micrometer, less than or about 0.3 micrometer, less than or about 0.2 micrometer, less than or about 0.1 micrometer, or smaller, including any portion of any of the stated figures.

[0090] In the preceding description, numerous details have been set forth for illustrative purposes to provide an understanding of various embodiments of the present technology. However, it will be apparent to those skilled in the art that certain embodiments may be practiced without some of these details or with additional details.

[0091] Having disclosed several embodiments, those skilled in the art will recognize that various modifications, alternative constructions, and equivalents can be used without departing from the spirit of these embodiments. Furthermore, many well-known processes and components have not been described to avoid unnecessarily obscuring the technology. Therefore, the above description should not be considered as limiting the scope of the technology.

[0092] When a range of values ​​is provided, unless the context explicitly indicates otherwise, it should be understood that interpolations up to the smallest fractional unit between the upper and lower limits of that range are also specifically disclosed. Any narrower range between any stated value or unstated interpolation within the stated range and any other stated or interpolated value within that stated range is included therein. The upper and lower limits of such narrower ranges may be independently included in or excluded from that range, and each range in which any limit, no limit, or both limits are included is also covered by this technique, subject to any explicitly excluded limits within the stated range. If a stated range includes one or both of such limits, it also includes ranges excluding any or both of the included limits.

[0093] As used herein and in the appended claims, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” include plural references. Thus, for example, a reference to “a precursor” includes multiple such precursors, and a reference to “the material” includes reference to one or more materials and their equivalents known to a person skilled in the art, and so on.

[0094] Furthermore, when the terms “comprise(s) / comprising,” “contain(s) / containing,” and “include(s) / including” are used in this specification and the following claims, they are intended to specify the presence of the stated features, integers, components, or operations, but do not exclude the presence or addition of one or more other features, integers, components, operations, actions, or groups.

Claims

1. A method for filling features on a semiconductor substrate, the method comprising: Performing a process in a semiconductor processing chamber to fill the features on the semiconductor substrate, wherein the process includes repeatedly performing a first operation, the first operation including: Provide silicon-containing precursors; The substrate is brought into contact with the silicon-containing precursor to form a silicon-containing material within the features defined on the substrate; Purify the semiconductor processing chamber; Based at least in part on the frequency characteristics of the plasma power supply of the semiconductor processing chamber, an oxygen-containing precursor plasma is provided with power characteristics and under pressure characteristics, wherein the power characteristics, the pressure characteristics and the frequency characteristics are configured to increase the radical density of the oxygen-containing precursor plasma and provide kinetic energy within the range to the ions of the oxygen-containing precursor plasma. as well as The substrate is brought into contact with the oxygen-containing precursor to form a silicon- and oxygen-containing material within the features defined on the substrate.

2. The method of claim 1, wherein the oxygen-containing precursor provided by the power characteristics, the pressure characteristics, and the frequency characteristics closes the gap in the feature by bonding a first side of the silicon- and oxygen-containing material within the feature to a second side of the silicon- and oxygen-containing material within the feature.

3. The method of claim 1, wherein forming the silicon-containing material within the feature comprises: A silicon atom layer is formed on the exposed surface of the feature; and The silicon- and oxygen-containing material formed within the feature includes: providing oxygen to the silicon atom layer.

4. The method of claim 1, wherein the frequency characteristics are in the range of about 25 MHz to 30 MHz.

5. The method of claim 4, wherein the pressure characteristics are in a second range of about 4 to about 15 Torr.

6. The method of claim 5, wherein the power characteristics are in a third range of about 1,500 watts to about 3,000 watts.

7. The method of claim 4, wherein providing the oxygen-containing precursor plasma comprises: The oxygen-containing precursor plasma is provided under the second frequency characteristics of the second plasma power supply in the semiconductor processing chamber, the second frequency characteristics being in a fourth range of about 1 kHz to 1 MHz.

8. The method of claim 1, wherein the feature is characterized as an aspect ratio greater than or about 10:

1.

9. The method of claim 1, wherein the oxygen-containing precursor comprises O2.

10. A method for filling features on a semiconductor substrate, the method comprising: Performing a process in a semiconductor processing chamber to fill the features on the semiconductor substrate, wherein the process includes repeatedly performing a first operation, the first operation including: Provide silicon-containing precursors; The substrate is brought into contact with the silicon-containing precursor to form a silicon-containing material within the features defined on the substrate; Purify the semiconductor processing chamber; Provides oxygen-containing precursors; as well as The substrate is brought into contact with the oxygen-containing precursor by forming plasma with frequency and power characteristics and under pressure characteristics, wherein the power characteristics, pressure characteristics and frequency characteristics are configured to provide sufficient free radical density and kinetic energy, wherein bringing the substrate into contact with the oxygen-containing precursor will form a silicon- and oxygen-containing material within the features defined on the substrate.

11. The method of claim 10, wherein contacting the silicon- and oxygen-containing material with the oxygen-containing precursor under the frequency characteristics, the power characteristics, and the pressure characteristics will close the gap in the feature by bonding a first side of the silicon- and oxygen-containing material within the feature to a second side of the silicon- and oxygen-containing material within the feature.

12. The method of claim 10, wherein the power characteristics are in the range of about 1,000 watts to about 2,000 watts.

13. The method of claim 10, wherein the pressure characteristics are in a second range of about 8 to about 15 Torr.

14. The method of claim 10, wherein the frequency characteristic is in a third range of about 10 MHz to 15 MHz.

15. The method of claim 10, wherein the process is performed at a temperature above or about 400°C.

16. A method for filling features on a semiconductor substrate, the method comprising: Performing a process in a semiconductor processing chamber to fill the features on the semiconductor substrate, wherein the process includes repeatedly performing a first operation at a first pressure level, the first operation including: Provide silicon-containing precursors; The substrate is brought into contact with the silicon-containing precursor to form a silicon-containing material within the features defined on the substrate; Purify the semiconductor processing chamber; Provides oxygen-containing precursors; and Provides oxygen-containing precursors; and The process of filling the feature further includes a second operation, which includes applying a silicon-containing and non-oxide-containing material by a conformal coating process.

17. The method of claim 16, wherein the conformal coating process is a chemical vapor deposition process.

18. The method of claim 16, wherein the conformal coating process is an atomic layer deposition process.

19. The method of claim 16, wherein the silicon-containing and non-oxide-containing material comprises at least one of the following: SiC, SiN, and high-purity silicon.

20. The method of claim 16, wherein the second operation is performed in the semiconductor processing chamber.

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