Stacked metal-oxide-metal (mOm) capacitors in front and back metallization layers of semiconductor dies and methods of manufacture

Abstract

Stacked metal-oxide-metal (MoM) capacitors in front and back metallization layers of a semiconductor die and related methods of manufacture. The stacked MoM capacitor includes a first front MoM capacitor formed in a front metallization layer in a front surface of a semiconductor layer and a front interconnect structure of the die. The stacked MoM capacitor also includes a second back MoM capacitor formed in a back metallization layer in a back surface of the semiconductor layer and a back interconnect structure. The front MoM capacitor and the back MoM capacitor are coupled to each other through a conductive structure in a second vertical direction between the front interconnect structure and the back interconnect structure to form the stacked MoM capacitor. In this way, the capacitance density in the die can be maintained or increased while providing sufficient area for signal routing in the front metallization layer.

Description

Priority application

[0001] This application claims priority to U.S. Patent Application Serial No. 18 / 604,993, filed March 14, 2024, entitled “STACKED METAL-OXIDE-METAL (MOM) CAPACITOR(S) IN FRONT SIDE AND BACK SIDE METALLIZATION LAYER(S) OF SEMICONDUCTOR DIE, AND RELATED INTEGRATED CIRCUIT (IC) PACKAGES AND FABRICATION METHODS”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to a semiconductor die (“die”) that can be incorporated into an integrated circuit (IC) package, wherein the die includes a metal-oxide-metal (MoM) capacitor in a metallization layer of an interconnect structure formed thereon. Background Technology

[0003] Computing devices have become increasingly ubiquitous in modern society. Early computers were the size of a room and used vacuum tubes to provide basic mathematical calculations. In contrast, modern computing devices offer a multitude of multimedia, telephony, word processing, and other functions in relatively small packages that rely on integrated circuits (ICs). The industry feels market pressure to provide more and more processing options for increasingly smaller products. While ICs generally follow Moore's Law, the continued advancements in IC functionality within smaller packages increasingly emphasize manufacturing capabilities.

[0004] Current IC manufacturing processes rely on a sequence of masks used in stages to create multi-level ICs. ICs provided in the form of semiconductor dies (“dies”) include active semiconductor layers traditionally manufactured in the front-end (FEOL) process. The active semiconductor layers include semiconductor devices (e.g., transistors). The die also includes interconnect structures formed adjacent to the semiconductor layers, located on the “front side” of the semiconductor layers, typically formed via back-end (BEOL) manufacturing processes. The interconnect structures include multiple metallization layers, each with metal lines (e.g., metal traces) disposed within the respective metallization layer to provide interconnects between different semiconductor devices and / or external interconnects (e.g., solder balls). Vertical interconnect pathways (vias), such as metal pillars and through-silicon vias (TSVs), are disposed in the metallization layers to provide interconnects between adjacent metal lines in adjacent metallization layers. Power distribution networks (PDNs), including power nodes and ground nodes, may also be provided in the interconnect structures, using multiple metal lines spanning multiple metallization layers to distribute power to the active devices formed in the semiconductor layers. Metal lines formed in the metallization layer of interconnects can also be used to form passive devices, such as capacitors (e.g., metal-oxide-metal (MoM) capacitors). As an example, the structure of a MoM capacitor can provide high capacitance in a reduced area of ​​the die, thus providing high capacitance density within the die. For example, these capacitors can be used to provide decoupling capacitance between the power and ground nodes of a PDN within the die, or otherwise to provide capacitance coupled to active devices formed as part of a circuit in a semiconductor layer. Summary of the Invention

[0005] The aspects disclosed herein include stacked metal-oxide-metal (MoM) capacitors in the front and back metallization layers of a semiconductor die (“die”). Related methods for fabricating stacked MoM capacitors in the die are also disclosed. In one example, a MoM capacitor is a structure having generally intersecting conductive fingers formed by metal lines or traces in a metallization layer extending in a first horizontal direction. Multiple MoM capacitors may be formed in multiple metallization layers and coupled to each other to increase capacitance density. In this regard, in an exemplary aspect, the stacked MoM capacitor includes a first front MoM capacitor formed adjacent to the front side of the semiconductor layer of the die and serving as at least a portion of the front metallization layer of a front interconnect structure (e.g., a back-end process (BEOL) interconnect structure formed by a BEOL process). The stacked MoM capacitor also includes a second back MoM capacitor formed adjacent to the back side of the semiconductor layer and serving as at least a portion of the back metallization layer of a back interconnect structure. A first front-side MoM capacitor and a second back-side MoM capacitor are coupled to each other via conductive structures (e.g., metal contacts, vias, gates, semiconductor devices) extending in a second vertical direction between the front-side and back-side interconnect structures to form a stacked MoM capacitor. By using both front-side and back-side metallization layers to form a stacked MoM capacitor in a die, an area in the front-side metallization layer of the die that would otherwise be used as part of the stacked MoM capacitor can be saved and used for other signal routing in the die. In this way, for example, capacitance density in the die can be maintained or increased while providing sufficient area in the front-side metallization layer for signal routing. Manufacturing processes used to form metal lines in the front-side and back-side interconnect structures of a die having through-vias and / or contacts in other ways can be used to form the stacked MoM capacitor.

[0006] Furthermore, as another example, if a power distribution network (PDN) is provided in the back metallization layer of the die, a second back MoM capacitor formed in the back metallization layer can be closer to the nodes of the PDN. This PDN can be located in the back metallization layer of the die, saving area consumed in the front metallization layer of the die and avoiding the need to add or increase the metallization layer on the front. Forming the MoM capacitor, as part of a stacked MoM capacitor, as at least a portion of the back interconnect structure (close to the PDN formed in the back interconnect structure) can provide lower coupling resistance and inductance between the stacked MoM capacitor and the PDN, improving decoupling capacitance and reducing current-resistance (IR) drop.

[0007] In one exemplary aspect, a first front MoM capacitor and a second back MoM capacitor of a stacked MoM capacitor are directly coupled to each other via metal contacts coupled to a via extending in a second vertical direction between the front interconnect structure and the back interconnect structure.

[0008] In another exemplary aspect, the first front-side MoM capacitor and the second back-side MoM capacitor of the stacked MoM capacitor can be coupled to each other via a semiconductor device formed in a semiconductor layer of a die between the front-side interconnect structure and the back-side interconnect structure. For example, the semiconductor device can be formed as a junction device of P-type and N-type semiconductor materials (e.g., a PN junction capacitor). The semiconductor device can also be formed as a gate-controlled device (e.g., a variable capacitor). If the semiconductor device formed in the semiconductor layer for coupling the first front-side MoM capacitor and the second back-side MoM capacitor is a capacitor, then the capacitor can provide additional capacitance in the stacked MoM capacitor to provide even higher capacitance density.

[0009] In another exemplary aspect, a first front MoM capacitor and a second back MoM capacitor of a stacked MoM capacitor are coupled to each other by a fixed metal contact that extends directly between the front interconnect structure and the back interconnect structure.

[0010] In another exemplary aspect, a first front-side MoM capacitor and a second back-side MoM capacitor of a stacked MoM capacitor are coupled to each other via a deep via structure that extends directly between the front-side interconnect structure and the back-side interconnect structure.

[0011] In another exemplary aspect, a first front-side MoM capacitor and a second back-side MoM capacitor of a stacked MoM capacitor are coupled to each other via a through-silicon via (TSV) that extends in a second vertical direction between the front-side interconnect structure and the back-side interconnect structure and passes through the semiconductor layer of the die.

[0012] In another exemplary aspect, the first front MoM capacitor and the second back MoM capacitor of the stacked MoM capacitor are coupled to each other using a gate in a semiconductor layer, wherein the gate is coupled to the front interconnect structure and the back interconnect structure via metal contacts.

[0013] In this regard, in one exemplary aspect, a semiconductor die is provided. The semiconductor die includes a semiconductor layer extending in a first direction. The semiconductor layer includes a front side and a back side opposite the front side in a second direction orthogonal to the first direction. The semiconductor die also includes a front interconnect structure adjacent to the front side of the semiconductor layer in the second direction. The semiconductor die also includes a back interconnect structure adjacent to the back side of the semiconductor layer in the second direction. The semiconductor die further includes a stacked MoM capacitor, the stacked MoM capacitor including a first MoM capacitor as at least part of the front interconnect structure and a second MoM capacitor as at least part of the back interconnect structure and coupled to the first MoM capacitor.

[0014] In another exemplary aspect, a method of manufacturing a semiconductor die is provided. The method includes forming a semiconductor layer extending in a first direction, the semiconductor layer including a front side and a back side opposite the front side in a second direction orthogonal to the first direction. The method further includes forming a front interconnect structure adjacent to the front side of the semiconductor layer in the second direction. The method further includes forming a back interconnect structure adjacent to the back side of the semiconductor layer in the second direction. The method further includes forming a stacked metal-oxide-metal (MoM) capacitor, including a first MoM capacitor formed as at least part of the front interconnect structure, and a second MoM capacitor formed as at least part of the back interconnect structure and coupled to the first MoM capacitor. Attached Figure Description

[0015] Figure 1 This is a side view of an integrated circuit (IC) including a stack of semiconductor dies (“dies”) comprising a front back-end process (BEOL) interconnect structure (which includes a first front metallization layer for signal routing) and a back interconnect structure (which includes a second back metallization layer for signal routing).

[0016] Figure 2 Is it possible to... Figure 1 A top view of an exemplary stacked metal-oxide-metal (MoM) capacitor provided in the interconnect structure of the die, wherein the stacked MoM capacitor includes a first overlay metallization layer, the first overlay metallization layer including a first MoM capacitor electrically coupled to a second MoM capacitor in an adjacent second underlay metallization layer;

[0017] Figure 3A This is a top view of an exemplary die, which includes... Figure 2Similar to the stacked MoM capacitor in the above, but the die includes a front side of the semiconductor layer adjacent to the die and a first front MoM capacitor formed in the front metallization layer in the front interconnect structure, which is coupled to a second back MoM capacitor formed in the back metallization layer in the back interconnect structure.

[0018] Figure 3B yes Figure 3A A cross-sectional side view of the die in the image illustrates a first conductive finger structure of a first front-side MoM capacitor of a stacked MoM capacitor coupled to a first metallic finger structure of a second back-side MoM capacitor of the stacked MoM capacitor via a semiconductor device in the form of a capacitor (which has a diffusion region in the semiconductor layer).

[0019] Figure 3C yes Figure 3A A cross-sectional side view of the die in the image illustrates a second conductive finger structure of a first front-side MoM capacitor of a stacked MoM capacitor coupled to a second conductive finger structure of a second back-side MoM capacitor of the stacked MoM capacitor via a gate.

[0020] Figure 3D yes Figure 3A A cross-sectional side view of the die in the image illustrates a first conductive finger structure of a first front-side MoM capacitor of a stacked MoM capacitor coupled to a first metal finger structure of a second back-side MoM capacitor of the stacked MoM capacitor via a fixed metal contact.

[0021] Figure 3E yes Figure 3A A cross-sectional side view of the die in the image illustrates how the second conductive finger structure of the first front-side MoM capacitor of the stacked MoM capacitor is coupled to the second metal finger structure of the second back-side MoM capacitor of the stacked MoM capacitor through a deep strip-shaped via.

[0022] Figure 4A and Figure 4B This is a top view, illustrating what can be seen from above. Figure 3A The exemplary loose and tight process margins provided in the die for coupling a first front MoM capacitor of a stacked MoM capacitor to a second back MoM capacitor.

[0023] Figure 5A This is a top view of another exemplary die, which includes... Figures 3A to 3DThe stacked MoM capacitor is similar to another stacked MoM capacitor, but the die includes a front side of the semiconductor layer adjacent to the die and a first front MoM capacitor formed in the front metallization layer in the front interconnect structure. The first front MoM capacitor is coupled outside the diffusion region to a back side of the semiconductor layer adjacent to the die and a second back MoM capacitor formed in the back metallization layer in the back interconnect structure.

[0024] Figure 5B yes Figure 5A The cross-sectional side view of the die in the image illustrates a first front MoM capacitor of a stacked MoM capacitor coupled to a second back MoM capacitor of the stacked MoM capacitor via a deep strip via.

[0025] Figure 5C yes Figure 5A Another cross-sectional side view of the die in the image illustrates a first front MoM capacitor of a stacked MoM capacitor coupled to a second back MoM capacitor of the stacked MoM capacitor via a deep strip-shaped via.

[0026] Figure 6 This is a flowchart illustrating an exemplary process for manufacturing a die, which includes manufacturing a stacked MoM capacitor. The stacked MoM capacitor includes a first front-side MoM capacitor formed in a front-side metallization layer of a semiconductor layer adjacent to the die, and a second back-side MoM capacitor formed in a back-side metallization layer of a semiconductor layer adjacent to the die. The stacked MoM capacitor includes, but is not limited to, […]. Figures 3A to 5C Stacked MoM capacitors in the middle;

[0027] Figures 7A to 7H This is an example of manufacturing. Figures 3A to 5C A flowchart illustrating an exemplary manufacturing process for a stacked MoM capacitor in a die.

[0028] Figures 8A to 8H It is based on Figures 7A to 7H The exemplary manufacturing process in the example is an exemplary manufacturing stage during the manufacture of a stacked MoM capacitor;

[0029] Figure 9 This is a block diagram of an exemplary wireless communication device including one or more dies, the one or more dies including stacked MoM capacitors, the stacked MoM capacitors including a first front MoM capacitor formed in a front metallization layer in a front interconnect structure adjacent to the front side of a semiconductor layer of the die, the first front MoM capacitor coupled to a second back MoM capacitor formed in a back metallization layer in a back interconnect structure adjacent to the back side of a semiconductor layer of the die, the stacked MoM capacitors including but not limited to Figures 3A to 5C and Figure 8H The stacked MoM capacitor in the figure, and the stacked MoM capacitor can be manufactured according to a manufacturing process, including but not limited to... Figures 6 to 7H Exemplary manufacturing processes in; and

[0030] Figure 10 This is a block diagram of an exemplary electronic device in the form of a processor-based system. The exemplary electronic device includes one or more dies, each including a stacked MoM capacitor. The stacked MoM capacitor includes a first front-side MoM capacitor formed in a front-side metallization layer in a front-side interconnect structure, adjacent to a front-side semiconductor layer of the die. The first front-side MoM capacitor is coupled to a second back-side MoM capacitor formed in a back-side metallization layer in a back-side interconnect structure, adjacent to a back-side semiconductor layer of the die. The stacked MoM capacitor includes, but is not limited to, […]. Figures 3A to 5C and Figure 8H The stacked MoM capacitor in the figure, and the stacked MoM capacitor can be manufactured according to a manufacturing process, including but not limited to... Figures 6 to 7H An exemplary manufacturing process is shown in the figure. Detailed Implementation

[0031] Several exemplary aspects of this disclosure will now be described with reference to the accompanying drawings. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0032] The aspects disclosed herein include stacked metal-oxide-metal (MoM) capacitors in the front and back metallization layers of a semiconductor die (“die”). Related methods for fabricating stacked MoM capacitors in the die are also disclosed. In one example, a MoM capacitor is a structure having generally intersecting conductive fingers formed by metal lines or traces in a metallization layer extending in a first horizontal direction. Multiple MoM capacitors may be formed in multiple metallization layers and coupled to each other to increase capacitance density. In this regard, in an exemplary aspect, the stacked MoM capacitor includes a first front MoM capacitor formed adjacent to the front side of the semiconductor layer of the die and serving as at least a portion of the front metallization layer of a front interconnect structure (e.g., a back-end process (BEOL) interconnect structure formed by a BEOL process). The stacked MoM capacitor also includes a second back MoM capacitor formed adjacent to the back side of the semiconductor layer and serving as at least a portion of the back metallization layer of a back interconnect structure. A first front-side MoM capacitor and a second back-side MoM capacitor are coupled to each other via conductive structures (e.g., metal contacts, vias, gates, semiconductor devices) extending in a second vertical direction between the front-side and back-side interconnect structures to form a stacked MoM capacitor. By using both front-side and back-side metallization layers to form a stacked MoM capacitor in a die, an area in the front-side metallization layer of the die that would otherwise be used as part of the stacked MoM capacitor can be saved and used for other signal routing in the die. In this way, for example, capacitance density in the die can be maintained or increased while providing sufficient area in the front-side metallization layer for signal routing. Manufacturing processes used to form metal lines in the front-side and back-side interconnect structures of a die having through-vias and / or contacts in other ways can be used to form the stacked MoM capacitor.

[0033] Examples of stacked MoM capacitor cores begin with those discussed below. Figure 3A The stacked MoM capacitor includes a first front-side MoM capacitor formed in a front-side metallization layer adjacent to the front side of the die's semiconductor layer, coupled to a second back-side MoM capacitor formed in a back-side metallization layer adjacent to the back side of the die's semiconductor layer. Before discussing these examples of dies including such stacked MoM capacitors, refer first to the discussion below. Figure 1 and Figure 2 Let's discuss examples that may include the core of a MoM capacitor.

[0034] In this regard, Figure 1This is a side view of an integrated circuit (IC) 100 including a semiconductor die (“die”) 102, the semiconductor die including interconnect structures 104F formed by a back-end process (BEOL) and disposed on a front-end process (FEOL) structure 106. The FEOL structure 106 includes an active semiconductor layer 108. The semiconductor layer 108 extends in a first horizontal direction, which is as follows: Figure 1 The X-axis and Y-axis directions are shown. Semiconductor layer 108 has a first front side 112F and a second back side 112B opposite to the first front side 112F in the second vertical direction (Z-axis direction). P-type field-effect transistors (FETs) 114P and N-type field-effect transistors (FETs) 114N are formed in semiconductor layer 108. An interconnect structure 104F, serving as a front interconnect structure 104, is disposed adjacent to the front side 112F of semiconductor layer 108 in the second vertical direction (Z-axis direction). The front interconnect structure 104F facilitates signal routing in die 102 on the front side 112F of semiconductor layer 108. In this regard, the front interconnect structure 104F includes a plurality of front metallization layers 116(1)-116(10), each of which includes one or more metal lines 118(1)-118(10) that can provide direct or indirect interconnects between the FETs 114P and 114N and external interconnects 120 (e.g., solder bumps) adjacent to the upper metallization layer 116(10) of the front interconnect structure 104F. The metal lines 118(1)-118(10) extend in a first horizontal direction (X-axis direction and / or Y-axis direction). The front interconnect structure 104F also includes vias 122(1)-122(10) disposed through the front metallization layers 116(1)-116(10) to provide interconnection between metal lines 118(1)-118(10) in adjacent metallization layers 116(1)-116(10).

[0035] Continue to refer to Figure 1The die 102 also includes a back interconnect structure 104B disposed adjacent to the back side 112B of the semiconductor layer 108 in a second vertical direction (Z-axis direction). The back interconnect structure 104B includes a plurality of back metallization layers 124(1)-124(2) that provide direct or indirect interconnects between the FETs 114P, 114N and external interconnects 120 (e.g., solder bumps). The back metallization layers 124(1)-124(2) facilitate signal routing in the die 102 on the back side 112B of the semiconductor layer 108. For example, the back interconnect structure 104B may facilitate the provision of a power distribution network (PDN) with power nodes and ground nodes in the back metallization layers 124(1)-124(2) to facilitate power distribution to the FETs 114P, 114N and / or to other front metallization layers 116(1)-116(10) in the front interconnect structure 104F. The back-side interconnect structure 104B includes vias 126(1)-126(2) disposed through the back-side metallization layers 124(1)-124(2) to provide interconnection to the back-side metallization layers 124(1)-124(2). For example, in this example, the NFET 114N is coupled to the back-side metallization layer 124(1) via vias 126(1) through its source / drain S / D. The metal line 118(4) is coupled to the back-side metallization layer 124(2) through the front-side interconnect structure 104F (via vias 126(2)).

[0036] Figure 2 Is it possible to... Figure 1 A top view of an exemplary stacked metal-oxide-metal (MoM) capacitor 200 provided in an interconnect structure such as the front interconnect structure 104F in die 102. Figure 2 As shown, the MoM capacitor 200 is formed in the interconnect structure 202 of the die 204, wherein the interconnect structure 202 includes metal lines in adjacent metallization layers 206(1), 206(2). The adjacent metallization layers 206(1), 206(2) can be Figure 1 The adjacent metallization layers in the front metallization layers 116(1)-116(10) in the front interconnect structure 104F of the die 102. The MoM capacitor 200 is a structure with intersecting conductive fingers formed by metal lines or traces in the metallization layers extending in a first horizontal direction to increase capacitance density.

[0037] In this example, such as Figure 2As shown, the first metallization layer 206(1) of the MoM capacitor 200 is a lower metallization layer 206U, which is disposed below the second metallization layer 206(2) which is the overlay metallization layer 206O in the second vertical direction (Z-axis direction). The lower metallization layer 206U includes a first lower conductive finger structure 208U(1), which includes a first lower metal line 210U(1) and a second lower metal line 210U(2) extending parallel to each other in the third horizontal direction (Y-axis direction). The first lower metal line 210U(1) and the second lower metal line 210U(2) are coupled together by a first lower metal line 212U(1) disposed in the first horizontal direction (X-axis direction). The underlying metallization layer 206U also includes a second underlying conductive finger structure 208U(2), which includes a third underlying metal line 210U(3) and a fourth underlying metal line 210U(4) extending parallel to each other in a third horizontal direction (Y-axis direction). The third underlying metal line 210U(3) and the fourth underlying metal line 210U(4) are coupled together by a second underlying metal line 212U(2) disposed in a first horizontal direction (X-axis direction).

[0038] Continue to refer to Figure 2 The first underlying conductive finger structure 208U(1) and the second underlying conductive finger structure 208U(2) intersect each other. In this regard, the first underlying metal wire 210U(1) and the second underlying metal wire 210U(2) of the first underlying conductive finger structure 208U(1) intersect each other with the corresponding third underlying metal wire 210U(3) and fourth underlying metal wire 210U(4) of the second underlying conductive finger structure 208U(2). The first underlying metal wire 210U(1) is arranged to be adjacent to and between the third underlying metal wire 210U(3) and the fourth underlying metal wire 210U(4). The second underlying metal wire 210U(2) is arranged to be adjacent to the fourth underlying metal wire 210U(4). The fourth underlying metal wire 210U(4) is arranged to be adjacent to and between the first underlying metal wire 210U(1) and the second underlying metal wire 210U(2).

[0039] In addition, such as Figure 2As shown, the overlying metallization layer 206O includes a first overlying conductive finger structure 208O(1), which includes a first overlying metal line 210O(1) and a second overlying metal line 210O(2) extending parallel to each other in a third horizontal direction (Y-axis direction). The first overlying metal line 210O(1) and the second overlying metal line 210O(2) are coupled together by a first overlying metal line 212O(1) disposed in a first horizontal direction (X-axis direction). The overlying metallization layer 206O also includes a second overlying conductive finger structure 208O(2), which includes a third overlying metal line 210O(3) and a fourth overlying metal line 210O(4) extending parallel to each other in the third horizontal direction (Y-axis direction). The third and fourth top metal wires 210O(3) and 210O(4) are coupled together by a second top metal wire 212O(2) disposed in the first horizontal direction (X-axis direction). The first and second top conductive finger structures 208O(1) intersect each other. In this respect, the first and second top metal wires 210O(1) and the corresponding third and fourth top metal wires 210O(4) of the first and second top conductive finger structures 208O(1) intersect each other. The third top metal wire 210O(3) is disposed adjacent to and between the first and second top metal wires 210O(1) and the second top metal wire 210O(2). The fourth top metal wire 210O(4) is disposed adjacent to the second top metal wire 210O(2). The second overlay metal line 210O(2) is arranged adjacent to and between the third overlay metal line 210O(3) and the fourth overlay metal line 210O(4). As an example, the first underlay conductive finger structure 208U(1) and the second overlay conductive finger structure 208O(2) may have the same polarity (+), while the second underlay conductive finger structure 208U(2) and the first overlay conductive finger structure 208O(1) may have a second different polarity (-).

[0040] Continue to refer to Figure 2The first overlying conductive finger structure 208O(1) intersects with the first underlying conductive finger structure 208U(1) in the first connection region 214(1) along the first horizontal direction and the third horizontal direction (X-axis direction and Y-axis direction). The first overlying conductive finger structure 208O(1) is coupled to the first underlying conductive finger structure 208U(1) through a via 216(1) in the first connection region 214(1). In this example, the third overlying metal wire 210O(3) intersects and couples with the first underlying metal wire 210U(1) and the second underlying metal wire 210U(2) in the first horizontal direction and the third horizontal direction (X-axis direction and Y-axis direction). The second overlying conductive finger structure 208O(2) intersects with the second underlying conductive finger structure 208U(2) in the second connection region 214(2) along the first horizontal direction and the third horizontal direction (X-axis direction and Y-axis direction). The second overlying conductive finger structure 208O(2) is coupled to the second underlying conductive finger structure 208U(2) through a via 216(2) in the second connection region 214(2). In this example, the first overlying metal line 210O(1) and the second overlying metal line 210O(2) intersect and couple with the third underlying metal line 210U(3) and the fourth underlying metal line 210U(4) in the horizontal X-axis direction and Y-axis direction, respectively.

[0041] Even if it is possible Figure 1 The front interconnect structure 104F of die 102 is integrated Figure 2 The MoM capacitor 200 is used in the die 102, but as the die area continues to shrink, it becomes increasingly difficult to provide sufficient area for passive devices (including the MoM capacitor) in the die 102 layout. As the coverage area of ​​die 102 decreases, the front interconnect structure 104F of die 102 also decreases, leaving less area for forming metal lines 118(1)-118(10) in the front metallization layers 116(1)-116(10) of the front interconnect structure 104F to provide the necessary signal routing. This, in turn, consumes additional area in the front interconnect structure 104F, which now becomes available for forming passive devices, such as… Figure 2 The MoM capacitor 200 is used in this example.

[0042] In this regard, Figure 3A This is a top view of an exemplary die 300, which includes a unit circuit 302 comprising a semiconductor layer 304 extending in a first direction and a third direction (X-axis direction and Y-axis direction). Die 300 is compatible with... Figure 1 The die 102 in the example is similar. In this example, the cell circuit 302 can be a metal-oxide-semiconductor (MOS) cell circuit, which includes a structure providing the formation of the MOS circuit. However, as discussed in more detail below, Figure 3AThe die 300 includes a stacked MoM capacitor 306, which includes a first MoM capacitor 308(1) disposed on the front side 310F of the semiconductor layer 304 of the die 300, and a second MoM capacitor 306(2) disposed on the back side 310B of the semiconductor layer 304 and coupled to the first MoM capacitor 308(1). The first MoM capacitor 308(1) is formed in a second vertical direction (Z-axis direction) on or adjacent to a front metallization layer 314 in the front side interconnect structure 316F of the semiconductor layer 304. In other words, in this example, the first MoM capacitor 308(1) is formed wholly or partially by a component that is part of the front interconnect structure 316F. For example, the front metallization layer 314 may be a metal O (Mo) layer in the die directly adjacent to the semiconductor layer 304. The back surface 310B of the semiconductor layer 304 is located on the opposite side of the front surface 310F of the semiconductor layer 304 in the second vertical direction (Z-axis direction).

[0043] In this example, the front interconnect structure 316F completely includes the first MoM capacitor 308(1), meaning that the metal structure forming the first MoM capacitor 308(1) is completely disposed (i.e., contained) within the front interconnect structure 316F. However, in an alternative example, the front interconnect structure 316F may partially include the first MoM capacitor 308(1), meaning that the metal structure forming the first MoM capacitor 308(1) is partially disposed (i.e., contained) within the front interconnect structure 316F, but other metal structures forming part of the first MoM capacitor 308(1) may be located outside the front interconnect structure 316F, such as in adjacent cell circuits or other adjacent structures.

[0044] Continue to refer to Figure 3A The second MoM capacitor 308(2) is formed in the second vertical direction (Z-axis direction) on the back side 310B of the semiconductor layer 304 or adjacent to at least a portion of the back side metallization layer 318 of the back side interconnect structure 316B formed thereon. In other words, in this example, the second MoM capacitor 308(2) is formed wholly or partially by a component that is part of the back side interconnect structure 316B. It should be noted that because the die 300 is in Figure 3A It is shown in a top view, so in Figure 3A Only the first MoM capacitor 308(1) on the front side 310F of semiconductor layer 304 is shown. In this example, in Figure 3A In the top view of the die 300, the back interconnect structure 316B and the second MoM capacitor 308(2) of the back interconnect structure 316B are hidden below the first MoM capacitor 308(1) on the back side 310B of the semiconductor layer 304.

[0045] In this example, the back interconnect structure 316B completely includes the second MoM capacitor 308(2), meaning that the metal structure forming the second MoM capacitor 308(2) is completely disposed (i.e., contained) within the back interconnect structure 316B. However, in an alternative example, the back interconnect structure 316B may partially include the second MoM capacitor 308(1), meaning that the metal structure forming the second MoM capacitor 308(2) is partially disposed (i.e., contained) within the back interconnect structure 316B, but other metal structures forming part of the second MoM capacitor 308(2) may be located outside the back interconnect structure 316B, such as in adjacent cell circuits or other adjacent structures.

[0046] As discussed in more detail below, in this example, the structure of unit circuit 302 is advantageously used to form the structure of a first MoM capacitor 308(1) and a second MoM capacitor 308(2), and couples them together via semiconductor layer 304. In this way, as an example, by providing a stacked MoM capacitor 306 as the first MoM capacitor 308(1) of the front interconnect structure 316F of the die 300 coupled to the second MoM capacitor 308(2) of the back interconnect structure 316B of the die 300, the capacitance density in the die 300 can be maintained or increased, while providing sufficient area for signal routing in the front interconnect structure 316F. The back interconnect structure 316B is used to provide the second MoM capacitor 308(2) as part of the stacked MoM capacitor 306 to save area in the front interconnect structure 316F. Furthermore, manufacturing processes used to form metal wires in the front interconnect structure and back interconnect structure of the die having through-holes and / or contacts in other ways can be used to form the stacked MoM capacitor 306 in the die 300. Furthermore, as another example, if a power distribution network (PDN) is provided in the back interconnect structure 316B of die 300, the second MoM capacitor 308(2) can be closer to the node of the PDN to reduce the coupling resistance and inductance between the stacked MoM capacitor 306 and the PDN, thereby improving decoupling capacitance and reducing current-resistance (IR) drop.

[0047] Figure 3B and Figure 3C yes Figure 3A A cross-sectional side view of die 300 is provided to provide further illustration of exemplary components of the first MoM capacitor 308(1) and the second MoM capacitor 308(2) of the stacked MoM capacitors 306 formed in die 300 and its unit circuit 302. Figure 3B Examples are shown as follows Figure 3A The top view of the die 300 shows a cross-sectional view of the die 300 across the cross-sectional line A1-A1'. Figure 3C Examples are shown as follows Figure 3A The top view of the die 300 shows a cross-sectional view of the die 300 across the cross-sectional line A2-A2'. Figure 3B and Figure 3C The diagram shows the front side 320F and the back side 320B of the die 300. The front side 320F of the die 300 is the region extending away from the semiconductor layer 304 in the second vertical direction (Z-axis direction) from the front side 310F of the semiconductor layer 304. The back side 320B of the die 300 is the region extending away from the semiconductor layer 304 in the second vertical direction (Z-axis direction) from the back side 310B of the semiconductor layer 304.

[0048] Figure 3B The first conductive finger structure 322A of the first MoM capacitor 308(1) on the front side 320F of the die 300 is illustrated, and the second conductive finger structure 322A' of the second MoM capacitor 308(2) on the back side 320F of the die 300 is illustrated. Figure 3C Example 322B is shown as the third conductive finger structure 322B of the first MoM capacitor 308(1) on the front side 320F of the die 300, and the fourth conductive finger structure 322B' of the second MoM capacitor 308(2) on the back side 320F of the die 300. Figure 3A As shown, the first conductive finger structure 322A and the third conductive finger structure 322B of the first MoM capacitor 308(1) intersect each other. Although from Figure 3A The die 300 is hidden in the top view, but like the first MoM capacitor 308(1), the second conductive finger structure 322A' of the second MoM capacitor 308(2) intersects with the fourth conductive finger structure 322B' of the second MoM capacitor 308(2). This forms a stacked MoM capacitor 306 formed by the first MoM capacitor 308(1) on the front side 320F of the die 300 and the second MoM capacitor 308(2) on the back side 320B of the die 300.

[0049] In this example, such as Figure 3A and Figure 3BAs shown, the first conductive finger structure 322A of the first MoM capacitor 308(1) is formed by a first metal line 324A extending in a first horizontal direction (X-axis direction) in the front metallization layer 314. The first metal line 324A is coupled to a plurality of first finger metal lines 326A that also extend orthogonally in a third horizontal direction (Y-axis direction) in the front metallization layer 314. In this example, the first finger metal lines 326A are front first metal contacts 328A formed adjacent to the semiconductor layer 304 to couple the first MoM capacitor 308(1) to the second MoM capacitor 308(2). The first metal line 324A is coupled to the front first metal contact 328A, which is the first finger metal line 326A, through a via 329A (e.g., a mid-process (MOL) via).

[0050] Similarly, in this example, such as Figure 3A and Figure 3C As shown, the second conductive finger structure 322B of the first MoM capacitor 308(1) is formed by a second metal line 324B extending in a first horizontal direction (X-axis direction) in the front metallization layer 314. The second metal line 324B is coupled to a plurality of second finger metal lines 326B that also extend orthogonally in a third horizontal direction (Y-axis direction) in the front metallization layer 314. In this example, the second finger metal lines 326B include gates 330 as second metal lines, which are coupled to front second metal gate contacts 328B (“second gate contacts 328B”) formed adjacent to the semiconductor layer 304 to couple the second metal lines 324B to the gates 330. The gates 330 provide a second conductive structure 334(2) to couple the first MoM capacitor 308(1) to the second MoM capacitor 308(2), as shown. Figure 3A As shown. In this regard, the first conductive finger structure 322A and the second conductive finger structure 322B of the first MoM capacitor 308(1), and their finger metal lines 326A, 326B, intersect each other in the front metallization layer 314. The first MoM capacitor 308(1) has a... Figure 2 The first overlying conductive finger structure 208O(1) and the second overlying conductive finger structure 208O(2) in the MoM capacitor 200 are similar to the first conductive finger structure 322A and the second conductive finger structure 322B. In this way, the structure fabricated in the unit circuit can be used to form the first MoM capacitor 308(1) in the front side 320F of the die 300.

[0051] Similarly, in this example, such as Figure 3BAs shown, the third conductive finger structure 322A' of the second MoM capacitor 308(2) is formed by a third metal line 324A' extending in the first horizontal direction (X-axis direction) in the back metallization layer 318. The third metal line 324A' is coupled to multiple third finger metal lines 326A' that also extend orthogonally in the third horizontal direction (Y-axis direction) in the back metallization layer 318. In this example, the third finger metal line 326A' is a back third metal contact 328A' formed adjacent to the semiconductor layer 304 to couple the first MoM capacitor 308(1) to the second MoM capacitor 308(2). The back third metal contact 328A' is coupled to the third metal line 324A' through a via 329A' (e.g., a MOL via).

[0052] Similarly, in this example, such as Figure 3A and Figure 3C As shown, the fourth conductive finger structure 322B' of the second MoM capacitor 308(2) is formed by a fourth metal line 324B' extending in a first horizontal direction (X-axis direction) in the back metallization layer 318. The fourth metal line 324B' is coupled to multiple fourth finger metal lines 326B' that also extend orthogonally in a third horizontal direction (Y-axis direction) in the back metallization layer 318. In this example, the fourth finger metal lines 326B' include gates 330 as fourth metal lines, which are coupled to back fourth metal gate contacts 328B' ("fourth gate contacts 328B'") formed adjacent to the semiconductor layer 304 to couple the fourth metal lines 324B' to the gates 330. The gates 330 provide a second conductive structure 334(2) to couple the first MoM capacitor 308(1) to the second MoM capacitor 308(2), as shown. Figure 3A As shown. In this regard, the third conductive finger structure 322A' and the fourth conductive finger structure 322B' of the second MoM capacitor 308(2), and their finger metal lines 326A' and 326B', intersect each other as part of the back metallization layer 318. The second MoM capacitor 308(2) has a... Figure 2 The first lower volt conductive finger structure 208U(1) and the second lower volt conductive finger structure 208U(2) in the MoM capacitor 200 are similar to the third conductive finger structure 322A' and the fourth conductive finger structure 322B'. In this way, the structure fabricated in the unit circuit can be used to form the second MoM capacitor 308(2) on the back side 320B of the die 300.

[0053] Continue to refer to Figure 3AIn this example, the first metal line 324A of the first MoM capacitor 308(1) and the third metal line 324A' of the second MoM capacitor 308(2) partially intersect the diffusion region 332 of the unit circuit 302 in the second vertical direction (Z-axis direction). For example, the diffusion region 332 can be an N-type diffusion region forming a PFET or a P-type diffusion region forming an NFET. Also in this example, the second metal line 324B of the first MoM capacitor 308(1) and the fourth metal line 324B' of the second MoM capacitor 308(2) do not intersect the diffusion region 332 of the unit circuit 302 in the second vertical direction (Z-axis direction) because the second metal line 324B and the fourth metal line 324B' are formed in the region outside the diffusion region 332 where the gate cutout in the gate 330 exists. Furthermore, in this example, the second gate contact 328B and the fourth gate contact 328B' do not intersect the diffusion region 332.

[0054] refer to Figure 3A and Figure 3B The provision of stacked MoM capacitors 306 in unit circuit 302 provides several methods for coupling the first MoM capacitor 308(1) and the second MoM capacitor 338(2) on the corresponding front 320F and back 320B of die 300 together. For example, as Figure 3B As shown, the first metal contacts 328A and third metal contacts 328A' of the corresponding first conductive finger structures 322A and third conductive finger structures 322A' of the first MoM capacitor 308(1) and the second MoM capacitor 308(2) are coupled by a first conductive structure 334(1) extending in a second vertical direction (Z-axis direction). The first conductive structure 334(1) couples the front first metal contact 328A of the first MoM capacitor 308(1) to the back third metal contact 328A' of the second MoM capacitor 308(2). In this example, the first conductive structure 334(1) includes a first conductive structure 334(1) in a diffusion region 332, as is the structure formed for a FET. As an example, the first conductive structure 334(1) may be epitaxially grown as an epitaxial layer 335(1), as would be grown to form an epitaxial layer for the source and / or drain when the first conductive structure 334(1) is formed as part of a FET. In this way, the manufacturing method used to manufacture the device in unit circuit 302 can be used to couple the first MoM capacitor 308(1) to the second MoM capacitor 308(2). Also in this example, by forming the first conductive structure 334(1) as an epitaxial layer 335(1), the first conductive structure 334(1) being a semiconductor capacitor formed by each epitaxial layer 335(1) of the gates 330 in the plurality of gates 330, more capacitance is added to the stacked MoM capacitor 306.

[0055] Continue to refer to Figure 3A and Figure 3C The second metal contacts 328B and fourth metal contacts 328B' of the corresponding second conductive finger structures 322B and fourth conductive finger structures 322B' of the first MoM capacitor 308(1) and the second MoM capacitor 308(2) are coupled by a second conductive structure 334(2) extending in the second vertical direction (Z-axis direction). The second conductive structure 334(2) couples the front second metal contact 328B of the first MoM capacitor 308(1) to the back fourth metal contact 328B' of the second MoM capacitor 308(2). In this example, the second conductive structure 334(2) includes a via 336(2) coupled to the second gate contact 328B and the fourth gate contact 328B'. In this way, the manufacturing method for manufacturing the device in the unit circuit 302 can be used to couple the first MoM capacitor 308(1) to the second MoM capacitor 308(2).

[0056] There are also other methods that provide a first conductive structure 334(1) and a second conductive structure 334(2) to couple together the first conductive finger structure 322A and the third conductive finger structure 322A', as well as the second conductive finger structure 322B and the fourth conductive finger structure 322B' of the first MoM capacitor 308(1) and the second MoM capacitor 308(2) of the stacked MoM capacitor 306.

[0057] For example, Figure 3D Examples of cross Figure 3A An alternative side view of the cross-sectional lines A1-A1' of unit circuit 302 is shown, but it illustrates a first conductive structure 334(1) where a first conductive finger structure 322A is coupled to a third conductive finger structure 322A' as a fixed metal contact 338, which is coupled to both the first metal contact 328A and the third metal contact 328A'. It should be noted that other first conductive structures 334(1) may also be configured as fixed metal contacts 328.

[0058] Figure 3E Examples of cross Figure 3AAnother alternative side view of the cross-sectional line A2-A2' of the unit circuit 302 in the diagram illustrates a second conductive structure 334(2) coupling the second conductive finger structure 322B to the fourth conductive finger structure 322B' as a via 340 directly coupled to the second metal line 324B. For example, the via 340 may be a through-silicon via (TSV) formed through the semiconductor layer 304. It should be noted that the via 340 may also be formed as directly coupled to the fourth metal line 324B', but in this example, the via 340 is coupled to the fourth metal line 324B' via a back via 329B'. In the case where the via 340 is a nano-TSV (nTSV), a back via 329B' may be provided. As another example, such as Figure 3E A direct TSV like via 340 can also be used to couple the first metal line 324A to the third metal line 324A' for use Figure 3D The first MoM capacitor 308(1) is shown.

[0059] Figure 4A and Figure 4B This is a top view, illustrating what can be seen from above. Figure 3A and Figure 3B An exemplary loose and tight process margin is provided in die 300 for coupling a first front MoM capacitor 308(1) of a stacked MoM capacitor 306 to a second back MoM capacitor 308(2).

[0060] Figure 4A Examples are shown as follows Figures 3A to 3D The alternative die 300 (1) is like the die 300 in the die 300, which includes a unit circuit 302 (1) like the unit circuit 302 in the die 300. Figure 4A The 300(1) core in the middle and Figures 3A to 3D The common components among the dies 300 are shown by common component numbers. For example... Figure 4A As shown in die 300(1), the first finger metal line 326A(1) of the first MoM capacitor 308(1) does not extend outside the diffusion region 332, and the process margin is loose in the unit circuit 302(1). As an example, this is... Figure 3AThe configuration of the unit circuit 302 in the middle. This provides more process margin and space to form the front second gate contact 328B, which is used to form the second finger metal line 326B of the first MoM capacitor 308(1) located outside the diffusion region 332. The front second gate contact 328B of the second finger metal line 326B is not adjacent to the front first metal contact 328A of the first finger metal line 326A(1) in the first horizontal direction (X-axis direction). It should be noted that there is the same process margin between the third finger metal line 326A' and the fourth finger metal line 326B' of the second MoM capacitor 408(2), but this is in Figure 4A It is hidden in the top view.

[0061] Figure 4B Examples are shown as follows Figures 3A to 3D Another alternative die 300 (2) is like die 300 in the die 300, which includes unit circuit 302 (2) like unit circuit 302 in die 300. Figure 4B The 300(2) core in the middle and Figures 3A to 3D The common components among the dies 300 are shown by common component numbers. For example... Figure 4B As shown in die 300(2), the process margin in unit circuit 302(2) is greater than that in die 300(2). Figure 4A The process margin in unit circuit 302(1) is tighter. The first finger metal line 326A(2) of the first MoM capacitor 308(1) extends outside the diffusion region 332 and is coupled adjacent to the front second gate contact 328B of the second finger metal line 326B in the first horizontal direction (X-axis direction). It should be noted that there is the same process margin between the third finger metal line 326A' and the fourth finger metal line 326B' of the second MoM capacitor 308(2), but this is in Figure 4A It is hidden in the top view.

[0062] Figure 5A This is a top view of another exemplary die 500, which includes... Figures 3A to 3D The stacked MoM capacitor 306 is similar to another stacked MoM capacitor 506, but the die includes metal wires with conductive finger-like structures located outside the diffusion region 332. Figure 5A The 500 core in the middle and Figures 3A to 3D The common components among the dies 300 are shown by common component numbers.

[0063] Figure 5AThe die 500 includes a stacked MoM capacitor 506, which includes a first MoM capacitor 508(1) disposed on the front side 310F of the semiconductor layer 304 of the die 500, and a second MoM capacitor 508(2) disposed on the back side 310B of the semiconductor layer 304 and coupled to the first MoM capacitor 508(1). The first MoM capacitor 508(1) is formed as a part of the front metallization layer 314 in the front side 310F of the semiconductor layer 304 or adjacent to the front interconnect structure 316F formed thereon in the second vertical direction (Z-axis direction). The back side 310B of the semiconductor layer 304 is located on the opposite side of the front side 310F of the semiconductor layer 304 in the second vertical direction (Z-axis direction). The second MoM capacitor 308(2) is formed as a part of the back metallization layer 318 in the back side 310B of the semiconductor layer 304 or adjacent to the back interconnect structure 316B formed thereon in the second vertical direction (Z-axis direction). It should be noted that because the 500 die is in Figure 5A It is shown in a top view, so in Figure 5A Only the first MoM capacitor 508(1) on the front side 310F of semiconductor layer 304 is shown. In this example, in Figure 5A In the top view of die 500, the back interconnect structure 316B and the second MoM capacitor 508(2), which is part of the back interconnect structure 316B, are hidden below the first MoM capacitor 508(1) on the back side 310B of the semiconductor layer 304.

[0064] Figure 5B and Figure 5C yes Figure 5A A cross-sectional side view of die 500 is provided to further illustrate exemplary components of a first MoM capacitor 508(1) and a second MoM capacitor 508(2) of stacked MoM capacitors 506 formed in die 500 and its unit circuit 502. Unit circuit 502 may be a MOS unit circuit. Figure 5B Examples are shown as follows Figure 5A The top view of the die 500 shows a cross-sectional view of the die 500 across the cross-sectional line A3-A3'. Figure 5C Examples are shown as follows Figure 5A The top view of the die 500 shows a cross-sectional view of the die 500 across the A4-A4' cross-sectional line. Figure 5B and Figure 5CThe diagram shows the front side 520F and the back side 520B of the die 500. The front side 520F of the die 500 is the region extending away from the semiconductor layer 304 in the second vertical direction (Z-axis direction) from the front side 310F of the semiconductor layer 304. The back side 520B of the die 500 is the region extending away from the semiconductor layer 304 in the second vertical direction (Z-axis direction) from the back side 310B of the semiconductor layer 304.

[0065] Figure 5A and Figure 5B Example 522A is shown as a first conductive finger structure 522A of a first MoM capacitor 508(1) on the front side 520F of die 500, and a second conductive finger structure 522A' of a second MoM capacitor 508(2) on the back side 520B of die 500. Figure 5A and Figure 5C Example 522B is shown as the third conductive finger structure 522B of the first MoM capacitor 508(1) on the front side 520F of the die 500, and the fourth conductive finger structure 522B' of the second MoM capacitor 508(2) on the back side 520B of the die 500. Figure 5A As shown, the first conductive finger structure 522A and the second conductive finger structure 522B of the first MoM capacitor 508(1) intersect each other. Although from Figure 5A The die 500 is hidden in the top view, but like the first MoM capacitor 508(1), the third conductive finger structure 522A' of the second MoM capacitor 508(2) intersects with the fourth conductive finger structure 522B' of the second MoM capacitor 508(2). This forms a stacked MoM capacitor 506 formed by the first MoM capacitor 508(1) on the front side 520F of the die 500 and the second MoM capacitor 508(2) on the back side 520B of the die 500.

[0066] In this example, such as Figure 5A and Figure 5BAs shown, the first conductive finger structure 522A of the first MoM capacitor 508(1) is formed by a first metal line 524A extending in a first horizontal direction (X-axis direction) in the front metallization layer 314. The first metal line 524A is coupled to a plurality of first finger metal lines 526A that also extend orthogonally in a third horizontal direction (Y-axis direction) in the front metallization layer 314. The first finger metal lines 526A are coupled to the first metal line 524A through a front via 529A. In this example, the first metal line 524A is located outside the diffusion regions 332(1), 332(2), which can be P-type and / or N-type diffusion regions. For example, the first metal line 524A can be designated as a metal line distributing power as part of a PDN. In this example, the first finger metal line 526A is a first metal line formed adjacent to the semiconductor layer 304.

[0067] Similarly, in this example, such as Figure 5A and Figure 5C As shown, the second conductive finger structure 522B of the first MoM capacitor 508(1) is formed by a second metal line 524B extending in a first horizontal direction (X-axis direction) in the front metallization layer 314. The second metal line 524B is coupled to multiple second finger metal lines 526B that also extend orthogonally in a third horizontal direction (Y-axis direction) in the front metallization layer 314. The second finger metal lines 526B are coupled to the second metal lines 524B through a front via 529B. In this example, the second metal lines 524B are also located outside the diffusion regions 332(1), 332(2). For example, the second metal lines 524B may be designated as metal lines distributing power as part of a PDN. In this example, the second finger metal lines 526B include a gate 330 formed as a second metal line adjacent to the semiconductor layer 304. In this regard, the first conductive finger structure 522A and the second conductive finger structure 522B of the first MoM capacitor 508(1), along with their finger metal lines 526A and 526B, intersect each other in the front metallization layer 314. The first MoM capacitor 508(1) has a... Figure 2 The first conductive finger structure 208O(1) and the second conductive finger structure 208O(2) in the MoM capacitor 200 are similar to the first conductive finger structure 522A and the second conductive finger structure 522B. In this way, the structure fabricated in the unit circuit can be used to form the first MoM capacitor 508(1) in the front side 520F of the die 500.

[0068] Similarly, in this example, such as Figure 5B As shown, the third conductive finger structure 522A' of the second MoM capacitor 508(2) is formed by a third metal line 524A' extending in the first horizontal direction (X-axis direction) in the back metallization layer 318 (in Figure 5B (Hidden in the cross-sectional view) A third metal line 524A' is formed. The third finger-shaped metal lines 526A' are coupled to the third metal line 524A' and also extend orthogonally in the third horizontal direction (Y-axis direction) within the back metallization layer 318. In this example, the third finger-shaped metal lines 526A' are third metal lines formed adjacent to the semiconductor layer 304. In this example, the third metal line 524A' is coupled to the third finger-shaped metal lines 526A' via a via 529A'.

[0069] Similarly, in this example, such as Figure 5A and Figure 5C As shown, the fourth conductive finger structure 522B' of the second MoM capacitor 508(2) is formed by a fourth metal line 524B' extending in the first horizontal direction (X-axis direction) in the back metallization layer 318 (in Figure 5C The fourth metal line 524B' is formed (shown as hidden in the cross-sectional view). A plurality of fourth finger-shaped metal lines 526B', also orthogonally extending in the third horizontal direction (Y-axis direction) in the back metallization layer 318, are coupled to the fourth finger-shaped metal lines 526B'. In this example, the fourth metal line 524B' is coupled to the fourth finger-shaped metal lines 526B' via a via 529B'. Also in this example, the fourth finger-shaped metal lines 526B' include a gate 330 formed as a fourth metal line adjacent to the semiconductor layer 304. In this regard, the third conductive finger structure 522A' and the fourth conductive finger structure 522B' of the second MoM capacitor 508(2), and their finger-shaped metal lines 526A', 526B', intersect each other in the back metallization layer 318. The second MoM capacitor 508(2) has a... Figure 2 The first lower volt conductive finger structure 208U(1) and the second lower volt conductive finger structure 208U(2) of the MoM capacitor 200 are similar to the third conductive finger structure 522A' and the fourth conductive finger structure 522B'. In this way, the structure fabricated in the unit circuit can be used to form the second MoM capacitor 508(2) on the back side 520B of the die 500.

[0070] Continue to refer to Figure 5AIn this example, the first metal line 524A of the first MoM capacitor 508(1) and the third metal line 524A' of the second MoM capacitor 508(2) do not intersect with the diffusion regions 332(1) and 332(2) of the unit circuit 502 in the second vertical direction (Z-axis direction). The diffusion regions 332(1) and 332(2) can be N-type diffusion regions forming a PFET or P-type diffusion regions forming an NFET. Similarly, in this example, the second metal line 524B of the first MoM capacitor 508(1) and the fourth metal line 524B' of the second MoM capacitor 308(2) do not intersect with the diffusion regions 332(1) and 332(2) of the unit circuit 502 in the second vertical direction (Z-axis direction).

[0071] refer to Figures 5A to 5C The stacked MoM circuit 506 provided in unit circuit 502 provides several methods for coupling the first MoM capacitor 508(1) and the second MoM capacitor 508(2) on the corresponding front side 520F and back side 520B of die 500 together. For example, as Figure 5B As shown, the first metal contacts 528A and third metal contacts 528A' of the corresponding first conductive finger structures 522A and third conductive finger structures 522A' of the first MoM capacitor 508(1) and the second MoM capacitor 508(2) are coupled by a first conductive structure 534(1) extending in the second vertical direction (Z-axis direction). The first metal contacts 528A and third metal contacts 528A' are coupled to corresponding first metal lines 524A and third metal lines 524A'. The first conductive structure 534(1) couples the first metal contact 528A of the first MoM capacitor 508(1) to the third metal contact 528A' of the second MoM capacitor 508(2), thereby coupling the first MoM capacitor 508(1) to the second MoM capacitor 508(1). In this example, the first conductive structure 534(1) may include a deep via 536(1) (e.g., a strip via) coupled to the first metal contact 528A and the third metal contact 528A'. In this way, the manufacturing method for manufacturing the device in the unit circuit 502 may be used to couple the first MoM capacitor 508(1) to the second MoM capacitor 508(2).

[0072] Continue to refer to Figures 5A to 5CThe second metal contacts 528B and fourth metal contacts 528B' of the corresponding second conductive finger structures 522B and fourth conductive finger structures 522B' of the first MoM capacitor 508(1) and the second MoM capacitor 508(2) are coupled by a second conductive structure 534(2) extending in the second vertical direction (Z-axis direction). For example, the second metal contacts 528B and fourth metal contacts 528B' can be gate contacts of the gate 330 coupled as second metal lines 524B and fourth metal lines 524B'. In this way, the second conductive structure 534(2) couples the second metal contacts 528B of the first MoM capacitor 508(1) to the fourth metal contacts 528B' of the second MoM capacitor 508(2) to couple the first MoM capacitor 508(1) to the second MoM capacitor 508(1). In this example, the second conductive structure 534(2) includes a deep via 536(2) (e.g., a strip via) coupled to the second metal gate contact 528B and the fourth metal gate contact 528B'. In this way, the manufacturing method for manufacturing the device in the cell circuit 502 can be used to couple the first MoM capacitor 508(2) to the second MoM capacitor 508(2).

[0073] The die, including the stacked MoM capacitor, can be manufactured according to a manufacturing process. The stacked MoM capacitor includes a first front-side MoM capacitor formed on the front side of the die's semiconductor layer and in a front-side metallization layer of the front-side interconnect structure. This first front-side MoM capacitor is coupled to a second back-side MoM capacitor formed on the back side of the die's semiconductor layer and in a back-side metallization layer of the back-side interconnect structure. The die and the stacked MoM capacitor include, but are not limited to, […]. Figures 3A to 5C The components include 300, 300(1), 300(2), 500 cores and stacked MoM capacitors 306, 506. In this regard, Figure 6 This is a flowchart illustrating an exemplary manufacturing process 600 for fabricating a die having a stacked MoM capacitor having a first front MoM capacitor coupled to a second back MoM capacitor. The die and the stacked MoM capacitor include, but are not limited to, [other methods]. Figures 3A to 5C The cores are 300, 300(1), 300(2), 500 and stacked MoM capacitors 306, 506. Figure 6 Manufacturing process 600 reference Figures 3A to 5CThe dies 300, 300(1), 300(2), 500 and the stacked MoM capacitors 306, 506 are discussed, but this is not limiting, and they can be used to manufacture another die having a stacked MoM capacitor having a first front MoM capacitor coupled to a second back MoM capacitor. The die and the stacked MoM capacitor include, but are not limited to, the following: Figures 5A to 5C The 500 core and the 506 stacked MoM capacitor are included.

[0074] In this regard, such as Figure 6 As shown, the manufacturing process 600 for fabricating a die 300 including a stacked MoM capacitor 306 includes forming a semiconductor layer 304 extending in a first direction (X-axis direction and / or Y-axis direction), the semiconductor layer 304 including a front side 310F and a back side 310B opposite to the front side 310F in a second direction (Z-axis direction) orthogonal to the first direction (X-axis direction and / or Y-axis direction). Figure 6 (See box 602 in the middle). The manufacturing process 600 for manufacturing die 300 also includes forming a front interconnect structure 316F, which includes a first MoM capacitor 308(1) and a front 310F adjacent to the semiconductor layer 304 in a second direction (Z-axis direction). Figure 6 (See box 604 in the image). The manufacturing process 600 for manufacturing die 300 also includes forming a back-side interconnect structure 316B, which includes a second MoM capacitor 308(2) and is adjacent to the back side 310B of semiconductor layer 304 in a second direction (Z-axis direction). Figure 6 The manufacturing process 600 for manufacturing die 300 also includes forming a stacked MoM capacitor 306. Figure 6 (in box 608). Forming a stacked MoM capacitor 306 includes coupling a first MoM capacitor 308(1) to a second MoM capacitor 308(2). Figure 6 (Box 610 in the middle).

[0075] The die, including the stacked MoM capacitor, can be manufactured in other manufacturing processes. The stacked MoM capacitor includes a first front-side MoM capacitor formed on the front side of the die's semiconductor layer and in a front-side metallization layer within a front-side interconnect structure. This first front-side MoM capacitor is coupled to a second back-side MoM capacitor formed on the back side of the die's semiconductor layer and in a back-side metallization layer within a back-side interconnect structure. The die and the stacked MoM capacitor include, but are not limited to, [other types of components]. Figures 3A to 5C The cores are 300, 300(1), 300(2), 500 and stacked MoM capacitors 306, 506.

[0076] For example, Figures 7A to 7HThis is a flowchart illustrating a manufacturing process 700 for fabricating a die including a stacked MoM capacitor. The stacked MoM capacitor includes a first front-side MoM capacitor formed on the front side of the die's semiconductor layer and in a front-side metallization layer of the front-side interconnect structure. The first front-side MoM capacitor is coupled to a second back-side MoM capacitor formed on the back side of the die's semiconductor layer and in a back-side metallization layer of the back-side interconnect structure. The die and the stacked MoM capacitor include, but are not limited to, […]. Figures 3A to 5C The cores are 300, 300(1), 300(2), 500 and stacked MoM capacitors 306, 506. Figures 8A to 8H It is based on Figures 7A to 7H The exemplary manufacturing process 700 in the example refers to exemplary manufacturing stages 800A-800H during the manufacture of the die and its MoM capacitor. Figures 7A to 7H The manufacturing process 700 is referenced below. Figures 3A to 3D The exemplary die 300 and its stacked MoM capacitor 306 are discussed, but this is not limiting and can be used to manufacture Figures 3A to 5C The cores are 300, 300(1), 300(2), 500 and stacked MoM capacitors 306, 506.

[0077] In this regard, such as Figure 8A As shown in the exemplary manufacturing stage 800A, the first step in the manufacturing process 700 for manufacturing the die 300 and its stacked MoM capacitor 306 is to perform FEOL and BEOL processing to form a semiconductor layer 304 on the substrate 802 and to form a front interconnect structure 316F adjacent to the semiconductor layer 304, including the first MoM capacitor 308(1). Figure 7A (See box 702 in the diagram). The formation of semiconductor layer 304 also includes forming semiconductor device 803, which may include structures to be fabricated in a FET, such as epitaxial layer 335 (1). A first MoM capacitor 308 (1) is formed in front-side interconnect structure 316F. As previously discussed, epitaxial layer 335 (1) may be used as a first conductive structure 334 (1) to couple the first MoM capacitor 308 (1) to a second back-side MoM capacitor 308 (2).

[0078] Then, as Figure 8B As shown in the exemplary manufacturing stage 800B, the next step in the manufacturing process 700 for manufacturing the die 300 and its stacked MoM capacitor 306 may be attaching a carrier wafer 804 to the front interconnect structure 316F to support the die 300 for further processing, thereby forming a back interconnect structure 316B on the back side 310B of the semiconductor layer 304. Figure 7B (Box 704 in the text). Then, as... Figure 8CAs shown in exemplary manufacturing stage 800C, the next step in the manufacturing process 700 for manufacturing die 300 and its stacked MoM capacitor 306 is to grind and thin substrate 802 to substrate 802A. Figure 7C (See box 706 in the image). For example, substrate 802A can be thinned by grinding substrate 802 and then chemically or mechanically polishing it. Then, as... Figure 8D As shown in the exemplary manufacturing stage 800D, the next step in the manufacturing process 700 for manufacturing the die 300 and its stacked MoM capacitor 306 may be forming a third back metal contact 328A', which can be used to couple to a metallization layer in the back interconnect structure 316B to be formed, so as to couple the first MoM capacitor 308(1) to the second MoM capacitor 308(2). Figure 7D (See box 708 in the image). This may involve etching substrate 802A to form a third metal contact 328A' on the back side using barrier deposition with metal filling and chemical or mechanical polishing.

[0079] Then, as Figure 8E As shown in exemplary manufacturing stage 800E, the next step in the manufacturing process 700 for manufacturing die 300 and its stacked MoM capacitor 306 may be removing substrate 802A and backfilling it with dielectric material 806, followed by chemical or mechanical polishing to form dielectric layer 806A between semiconductor layer 304 and the back interconnect structure 316B to be formed. Figure 7E (Frame 710 in the diagram). This is to prepare a metallization layer for forming the back-side interconnect structure 316B on the back side 320B of the die 300. Then, as... Figure 8F As shown in the exemplary manufacturing stage 800F, the next step in the manufacturing process 700 for manufacturing the die 300 and its stacked MoM capacitor 306 may be forming a back third metal contact 328A' and a via 329A' adjacent to the dielectric layer 806A for coupling a third metal line 324A' in the back metallization layer 318 as part of a third conductive finger structure 322A' for forming the second MoM capacitor 308(2). Figure 7F (Box 712 in the middle). Then, as... Figure 8G As shown in the exemplary manufacturing stage 800G, the next step in the manufacturing process 700 for manufacturing the die 300 and its stacked MoM capacitor 306 may be forming a back fourth gate contact 328B' and a back via 329B' to couple to the gate 330 as part of the second MoM capacitor 308(2). Figure 7G (Box 714 in the middle).

[0080] Then, as Figure 8HAs shown in the exemplary manufacturing stage 800H, the next step in the manufacturing process 700 for manufacturing die 300 and its stacked MoM capacitor 306 may be forming a back metallization layer 318 as part of forming a back interconnect structure 316B, and forming a back third metal line 324A' and a fourth metal line 324B' therein, coupled to corresponding vias 329A', 329B' to couple to a second MoM capacitor 308(2). Other back metallization layers 318(1), 318(2) may also be formed on the back side 320B adjacent to the back metallization layer 318 to complete the manufacturing of die 300 having its stacked MoM capacitor 306, wherein the first MoM capacitor 308(1) of the stacked MoM capacitor is coupled to the second MoM capacitor 308(2). Figure 7G (Box 716 in the middle).

[0081] It should be noted that in some examples, the MoM capacitors discussed above may be formed as part of an interconnect structure, meaning that certain metal lines and structures interconnecting each other in the interconnect structure form MoM capacitors. It should be noted that the interconnect structure may contain MoM capacitors wholly or partially. If the interconnect structure completely contains the MoM capacitor, the metal structure forming the MoM capacitor is entirely disposed (i.e., contained) within the interconnect structure. If the interconnect structure partially contains the MoM capacitor, the metal structure forming the MoM capacitor is partially disposed (i.e., contained) within the interconnect structure, but other metal structures forming part of the MoM capacitor may be located outside the interconnect structure, such as in adjacent cell circuits or other adjacent structures. In the examples discussed above, and when it is stated that the interconnect structure at least partially includes the MoM capacitor, this means that the interconnect structure completely or partially includes the MoM capacitor. Furthermore, when it is stated that the interconnect structure “includes” the MoM capacitor, this means that the interconnect structure may completely or partially include the MoM capacitor.

[0082] It should be understood that the terms “first,” “second,” “third,” etc., used herein are relative terms and do not imply limitation or a strict orientation. It should also be understood that the terms “front,” “top,” “above,” “over,” and “back,” “bottom,” “lower,” “below,” as used herein, are relative terms and do not imply limitation or a strict orientation. An element referred to as “front,” “top,” or “above” or “over” does not always need to be oriented above an element referred to as “back,” “bottom,” or “lower,” or “below,” relative to the ground, and vice versa. An element referred to as “front,” “top,” “above,” or “over” may be located at the top or bottom relative to an element referred to as “back,” “bottom,” “lower,” or “below,” and may be located at the top or bottom only relative to the example and the specific illustrated example. An element referred to as “front,” “top,” “above,” or “over,” or “back,” “bottom,” “lower,” or “below” in another element is not necessarily relative to the ground, and vice versa. An element referred to as “front,” “top,” “above,” or “over” may be above or below such other referenced elements only relative to the example and the specific illustrated example.

[0083] Additionally, as discussed in this paper, object "proximity" refers to an object being next to or adjacent to another stated object. Adjacent objects may not be directly physically coupled to each other. An object may be directly adjacent to another object, meaning that such an object is directly next to or adjacent to another object, without any other object or layer situated between the directly adjacent objects. An object may be indirectly or indirectly adjacent to another object, meaning that such objects are not directly next to or directly close to each other, but rather that an intermediate object or layer is situated between the non-directly adjacent objects.

[0084] Dies including stacked MoM capacitors can be provided in or integrated into any processor-based device. The stacked MoM capacitors include a first front-side MoM capacitor formed on the front side of the die's semiconductor layer and in a front-side metallization layer of the front-side interconnect structure. The first front-side MoM capacitor is coupled to a second back-side MoM capacitor formed on the back side of the die's semiconductor layer and in a back-side metallization layer of the back-side interconnect structure. The die and the stacked MoM capacitors include, but are not limited to, […]. Figures 3A to 5C and Figure 8H The components include die 300, 300(1), 300(2), 500 and stacked MoM capacitors 306, 506, and can be manufactured according to the manufacturing process (including but not limited to) Figure 6 and Figures 7A to 7H as well as Figure 10 A to Figure 10Exemplary manufacturing processes 600, 700 in B) and manufactured according to any aspect disclosed herein. Examples not intended to be limiting include: set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smartphones, Session Initiation Protocol (SIP) phones, tablet devices, tablet phones, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multirotor aircraft.

[0085] In this regard, Figure 9 An exemplary wireless communication device 900 is illustrated, comprising one or more IC packages 902, 902(1), 902(2), each of which includes a die 903, 903(1), 903(2), including but not limited to... Figures 3A to 5C and Figure 8H The components 300, 300(1), 300(2), 500 and stacked MoM capacitors 306, 506, wherein components 903, 903(1), 903(2) may include stacked MoM capacitors, such as, for example Figures 3A to 5C and Figure 8H The stacked MoM capacitors 306 and 506 in the IC package include a first front MoM capacitor formed on the front side of the semiconductor layer of the die and in the front metallization layer of the front interconnect structure, which is coupled to a second back MoM capacitor formed on the back side of the semiconductor layer of the die and in the back metallization layer of the back interconnect structure. The IC packages 902, 902(1), 902(2) and their dies 903, 903(1), 903(2) can be manufactured according to the manufacturing process (including but not limited to...) Figure 6 and Figures 7A to 7H The exemplary manufacturing processes 600, 700 in this document are used to manufacture the product and any aspects disclosed herein.

[0086] As an example, wireless communication device 900 may include any of the devices mentioned above or be provided in any of the devices mentioned above. Figure 9As shown, the wireless communication device 900 includes a transceiver 904 and a data processor 906. The data processor 906 may include memory for storing data and program code. The transceiver 904 includes a transmitter 908 and a receiver 910 supporting bidirectional communication. Generally, the wireless communication device 900 may include any number of transmitters 908 and / or receivers 910 for any number of communication systems and frequency bands. All or part of the transceiver 904 may be implemented on one or more analog ICs, RF ICs (RFICs), mixed-signal ICs, etc.

[0087] The transmitter 908 or receiver 910 can be implemented using either a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal undergoes multi-stage frequency conversion between RF and baseband; for example, for receiver 910, it is converted from RF to intermediate frequency (IF) in one stage and then from IF to baseband in another stage. In a direct conversion architecture, the signal is converted between RF and baseband in a single stage. Superheterodyne and direct conversion architectures can use different circuit blocks and / or have different requirements. Figure 9 In the wireless communication device 900, the transmitter 908 and receiver 910 are implemented using a direct frequency conversion architecture.

[0088] In the transmission path, data processor 906 processes the data to be transmitted and provides I and Q analog output signals to transmitter 908. In the exemplary wireless communication device 900, data processor 906 includes digital-to-analog converters (DACs) 912(1), 912(2) to convert the digital signals generated by data processor 906 into I and Q analog output signals (e.g., I and Q output currents) for further processing.

[0089] Within transmitter 908, low-pass filters 914(1) and 914(2) filter the I and Q analog output signals, respectively, to remove unwanted signals caused by the previous digital-to-analog conversion. Amplifiers (AMPs) 916(1) and 916(2) amplify the signals from low-pass filters 914(1) and 914(2), respectively, and provide I and Q baseband signals. Upconverter 918 upconverts the I and Q baseband signals using mixers 920(1) and 920(2) from the transmit (TX) local oscillator (LO) signal generator 922 to provide upconverted signal 924. Filter 926 filters the upconverted signal 924 to remove unwanted signals caused by upconversion and noise in the receive band. Power amplifier (PA) 928 amplifies the upconverted signal 924 from filter 926 to obtain the desired output power level and provide the transmit RF signal. The RF signal is routed through the duplexer or switch 930 and transmitted via the antenna 932.

[0090] In the receiving path, antenna 932 receives the signal transmitted by the base station and provides the received RF signal, which is routed through duplexer or switch 930 and provided to low-noise amplifier (LNA) 934. Duplexer or switch 930 is designed to operate using a specific receive (RX) to TX duplexer frequency separation, such that the RX signal is isolated from the TX signal. The received RF signal is amplified by LNA 934 and filtered by filter 936 to obtain the desired RF input signal. Downconversion mixers 938(1), 938(2) mix the output of filter 936 with the I and Q RX LO signals (i.e., LO_I and LO_Q) from RX LO signal generator 940 to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMP 942(1), 942(2) and further filtered by low-pass filters 944(1), 944(2) to obtain I and Q analog input signals, which are provided to data processor 906. In this example, the data processor 906 includes analog-to-digital converters (ADCs) 946(1) and 946(2) to convert analog input signals into digital signals to be further processed by the data processor 906.

[0091] exist Figure 9 In the wireless communication device 900, a TX LO signal generator 922 generates I and Q TX LO signals for up-conversion, while an RX LO signal generator 940 generates I and Q RX LO signals for down-conversion. Each LO signal is a periodic signal with a specific base frequency. A TX phase-locked loop (PLL) circuit 948 receives timing information from a data processor 906 and generates control signals for adjusting the frequency and / or phase of the TX LO signals from the TX LO signal generator 922. Similarly, an RXILL circuit 950 receives timing information from a data processor 906 and generates control signals for adjusting the frequency and / or phase of the RX LO signals from the RX LO signal generator 940.

[0092] Figure 10 An example of a processor-based system 1000 is illustrated, comprising one or more IC packages 1002, 1002(1)-1002(8), each of which comprises a die 1004, 1004(1)-1004(8), including but not limited to Figures 3A to 5C and Figure 8H The components 300, 300(1), 300(2), 500 and stacked MoM capacitors 306, 506, wherein the components 1004, 1004(1)-1004(8) may include stacked MoM capacitors, such as, for example Figures 3A to 5C and Figure 8HThe stacked MoM capacitors 306 and 506 in the IC package include a first front MoM capacitor formed on the front side of the semiconductor layer of the die and in the front metallization layer of the front interconnect structure, which is coupled to a second back MoM capacitor formed on the back side of the semiconductor layer of the die and in the back metallization layer of the back interconnect structure. The IC packages 902, 902(1), 902(2) and their dies 903, 903(1), 903(2) can be manufactured according to the manufacturing process (including but not limited to...) Figure 6 and Figures 7A to 7H The exemplary manufacturing processes 600, 700 in this document are used to manufacture the product and any aspects disclosed herein.

[0093] In this example, the processor-based system 1000 may include a die 1004 contained in an IC package 1002 (such as a system-on-a-chip (SoC) 1006). The processor-based system 1000 includes a CPU 1008, which includes one or more processors 1010, which may also be referred to as a CPU core or processor core. The CPU 1008 may be disposed in the IC package 1002(1) including the die 1004(1). The CPU 1008 may have a cache memory 1012 coupled to the CPU 1008 for fast access to data in temporary storage. The CPU 1008 is coupled to a system bus 1014 and may be coupled to master and slave devices included in the processor-based system 1000. As is well known, the CPU 1008 communicates with these other devices by exchanging address, control, and data information via the system bus 1014. For example, the CPU 1008 may communicate a bus transaction request to a memory controller 1016, which is an example of a slave device. Figure 10 Not illustrated, but multiple system buses 1014 may be provided, each of which constitutes a different structure.

[0094] Other master and slave devices can be connected to system bus 1014. For example... Figure 10As illustrated, by way of example, these devices may include a memory system 1020, one or more input devices 1022, one or more output devices 1024, one or more network interface devices 1026, and one or more display controllers 1028, the memory system including a memory controller 1016 and a memory array 1018. The memory system 1020 may be disposed in an IC package 1002(2) including a die 1004(2). The network interface device 1026 may be disposed in an IC package 1002(3) including a die 1004(3). Each of the memory system 1020, one or more input devices 1022, one or more output devices 1024, one or more network interface devices 1026, and one or more display controllers 1028 may be disposed in the same or different circuit packages. The input devices 1022 and / or the output devices 1024 may be disposed in corresponding IC packages 1002(4), 1002(5) including corresponding dies 1004(4), 1004(5). Input device 1022 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. Output device 1024 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. Network interface device 1026 may be any device configured to allow the exchange of data to and from network 1030. Network 1030 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), Bluetooth, etc. ™ Networks and the Internet. The network interface device 1026 can be configured to support any type of communication protocol desired.

[0095] CPU 1008 may also be configured to access display controller 1028 via system bus 1014 to control information transmitted to one or more displays 1032. Display 1032 may be housed in IC package 1002(6) including die 1004(6). Display controller 1028 transmits information to be displayed to display 1032 via one or more video processors 1034, which process the information to be displayed into a format suitable for display 1032. As an example, display controller 1028 and video processor 1034 may be housed in corresponding IC packages 1002(7), 1002(8) including dies 1004(7), 1004(8), or in the same IC package 1002, or in the same IC package 1002(1) containing CPU 1008. Display 1032 may include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, light-emitting diode (LED) display, etc.

[0096] Those skilled in the art will further understand that the various exemplary logic blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein can be implemented as electronic hardware, stored in memory or another computer-readable medium and executed by a processor or other processing device, or a combination of both. The memory disclosed herein can be of any type and size and can be configured to store any type of information desired. To clearly illustrate this interchangeability, the functionality of the various exemplary components, blocks, modules, circuits, and steps has been generally described above. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be construed as departing from the scope of this disclosure.

[0097] The various exemplary logic blocks, modules, and circuits described in conjunction with the aspects disclosed herein may be implemented or executed using a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic unit, discrete hardware component, or any combination thereof, designed to perform the functions described herein. The processor may be a microprocessor, but in alternative embodiments, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors cooperating with a DSP core, or any other such configuration).

[0098] The aspects disclosed herein may be embodied in hardware and instructions stored in the hardware, and may reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Alternatively, the storage medium may be integral with the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and storage medium may reside as discrete components in a remote station, base station, or server.

[0099] It should also be noted that the operational steps described in any of the exemplary aspects of this document are described for the purpose of providing examples and discussion. The described operations may be performed in many different orders other than the order illustrated. Furthermore, the operations described in a single operational step may actually be performed in multiple different steps. In addition, one or more operational steps discussed in the exemplary aspects may be combined. It should be understood that, as will be apparent to those skilled in the art, many different modifications may be made to the operational steps illustrated in the flowcharts. Those skilled in the art will also understand that any of a variety of different techniques and arts can be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0100] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0101] Specific implementation examples are described in the following numbered clauses: 1. A semiconductor die, the semiconductor die comprising: A semiconductor layer extending in a first direction, the semiconductor layer including a front side and a back side opposite to the front side in a second direction orthogonal to the first direction; A front-side interconnect structure, wherein the front-side interconnect structure is adjacent to the front side of the semiconductor layer in the second direction. The front-side interconnect structure includes a first metal-oxide-metal (MoM) capacitor; A back-side interconnect structure, wherein the back-side interconnect structure is adjacent to the back side of the semiconductor layer in the second direction. The back-side interconnect structure includes a second MoM capacitor; and A stacked MoM capacitor, the stacked MoM capacitor comprising: The first MoM capacitor; and The second MoM capacitor is coupled to the first MoM capacitor. 2. The semiconductor die according to Clause 1, wherein: The front interconnect structure further includes a front metallization layer, which includes the first MoM capacitor and extends in the first direction; and The back-side interconnect structure further includes a back-side metallization layer, which includes the second MoM capacitor and extends in the first direction. 3. The semiconductor die according to Clause 2, wherein: The first MoM capacitor includes: The first metal line in the front metallization layer; and The first conductive finger structure in the front metallization layer includes multiple first finger metal lines that are parallel to each other and coupled to the first metal line. The second metal line in the front metallization layer; and The second conductive finger structure in the front metallization layer includes multiple second finger metal lines that are parallel to each other and coupled to the second metal lines. The first conductive finger structure and the second conductive finger structure intersect each other; and The second MoM capacitor includes: The third metal line in the back metallization layer; and The third conductive finger structure in the back metallization layer includes multiple third finger metal lines that are parallel to each other and coupled to the third metal lines. The fourth metal line in the back metallization layer; and The fourth conductive finger structure in the back metallization layer includes multiple fourth finger metal lines that are parallel to each other and coupled to the fourth metal lines. The third conductive finger structure and the fourth conductive finger structure intersect each other. 4. The semiconductor die according to any one of Clauses 1 to 3, wherein the stacked MoM capacitor further comprises one or more first conductive structures, each of the one or more first conductive structures extending in the second direction and coupled to the first MoM capacitor and the second MoM capacitor. 5. The semiconductor die according to any one of Clauses 1 to 4, wherein the one or more first conductive structures include one or more vias. 6. The semiconductor die according to any one of Clauses 1 to 4, wherein the one or more first conductive structures comprise one or more metal contacts. 7. The semiconductor die according to any one of clauses 1, 2, and 4 to 6, wherein the semiconductor die further comprises: Unit circuit, the unit circuit comprising: The diffusion region in the semiconductor layer; The first metal line in the front interconnect structure; The second metal line in the front interconnect structure; The third metal line in the back-side interconnect structure; The fourth metal line in the back-side interconnect structure; Multiple first finger-shaped metal lines coupled to the first metal line and adjacent to the semiconductor layer; and Multiple second finger-shaped metal lines coupled to the second metal line and adjacent to the semiconductor layer The plurality of second finger-shaped metal wires intersect with the plurality of first finger-shaped metal wires; Multiple third finger-shaped metal lines coupled to the third metal line and the semiconductor layer; and Multiple fourth finger-shaped metal lines coupled to the fourth metal line and the semiconductor layer The plurality of fourth finger-shaped metal wires intersect with the plurality of third finger-shaped metal wires; in: The first MoM capacitor includes: A first conductive finger structure, the first conductive finger structure comprising the first metal wire and the plurality of first finger-shaped metal wires; and The second conductive finger structure includes the second metal wire and the plurality of second finger-shaped metal wires; and The second MoM capacitor includes: A third conductive finger structure, the third conductive finger structure comprising the third metal wire and the plurality of third finger-shaped metal wires; and The fourth conductive finger structure includes the fourth metal wire and the plurality of fourth finger metal wires. 8. The semiconductor die according to Clause 7, wherein the stacked MoM capacitor further comprises one or more through-silicon vias (TSVs), each of the one or more TSVs extending through the semiconductor layer in the second direction and coupled to the first MoM capacitor and the second MoM capacitor. 9. The semiconductor die according to any one of clauses 1, 2, and 4 to 6, wherein the semiconductor die further comprises: Unit circuit, the unit circuit comprising: The diffusion region in the semiconductor layer; The first metal line in the front interconnect structure intersects the diffusion region at least partially in the second direction; The second metal line in the front interconnect structure; The third metal line in the back-side interconnect structure intersects the diffusion region at least partially in the second direction; The fourth metal line in the back-side interconnect structure; A plurality of first metal fingers coupled to the first metal line and the semiconductor layer; and A plurality of second metal fingers coupled to the second metal line and the semiconductor layer The plurality of second metal fingers intersect with the plurality of first metal fingers; A plurality of third metal fingers coupled to the third metal line and the semiconductor layer; and Multiple fourth metal fingers coupled to the fourth metal line and the semiconductor layer, The plurality of fourth metal fingers intersect with the plurality of third metal fingers; The first MoM capacitor comprises: A first conductive finger-like structure, the first conductive finger-like structure comprising the first metal wire and the plurality of first metal fingers; and The second conductive finger structure includes the second metal wire and the plurality of second metal fingers; and The second MoM capacitor comprises: A third conductive finger structure, the third conductive finger structure comprising the third metal wire and the plurality of third metal fingers; and The fourth conductive finger structure includes the fourth metal wire and the plurality of fourth metal fingers. 10. The semiconductor die according to Clause 9, wherein: The first metal line and the third metal line at least partially intersect the diffusion region in the second direction; and The second metal line and the fourth metal line do not intersect the diffusion region in the second direction. 11. The semiconductor die according to Clause 9 or 10, wherein the semiconductor die further comprises: A plurality of first conductive structures, the plurality of first conductive structures extending in the second direction and coupling the plurality of first metal fingers to the plurality of third metal fingers; and A plurality of second conductive structures, the plurality of second conductive structures extending in the second direction and coupling the plurality of second metal fingers to the plurality of fourth metal fingers. 12. The semiconductor die according to Clause 11, wherein: The plurality of first conductive structures include a plurality of first epitaxial layers in the diffusion region; The plurality of first metal fingers include a plurality of first metal contacts coupled to the plurality of first epitaxial layers; and The plurality of third metal fingers include a plurality of second metal contacts coupled to the plurality of first epitaxial layers. 13. The semiconductor die according to Clause 12, wherein: The unit circuit also includes multiple gates; The plurality of second metal fingers include the plurality of gates; and The plurality of fourth metal fingers include the plurality of second metal contacts. 14. The semiconductor die according to Clause 13, wherein the stacked MoM capacitor further comprises a plurality of first semiconductor capacitors, each of the plurality of first semiconductor capacitors comprising a first epitaxial layer of the plurality of first epitaxial layers adjacent to each of the plurality of gates. 15. The semiconductor die according to Clause 9, wherein: The unit circuit also includes multiple gates; The plurality of second metal fingers include the plurality of gates; and The plurality of fourth metal fingers include a plurality of second metal contacts. 16. The semiconductor die according to Clause 15, wherein: The first MoM capacitor further includes a plurality of first gate contacts coupled to the plurality of gates; and The second MoM capacitor also includes a plurality of second gate contacts coupled to the plurality of gates. 17. The semiconductor die according to any one of Clauses 9 to 16, wherein the diffusion region includes an N-type semiconductor material (N) field-effect transistor (FET) (NFET) diffusion region. 18. The semiconductor die according to any one of Clauses 9 to 16, wherein the diffusion region includes a P-type semiconductor material (P) field-effect transistor (FET) (PFET) diffusion region. 19. The semiconductor die according to any one of clauses 1, 2, and 4 to 6, wherein the semiconductor die further comprises: Unit circuit, the unit circuit comprising: The first diffusion region in the semiconductor layer; The first metal line in the front interconnect structure does not intersect the first diffusion region in the second direction; The second metal line in the front interconnect structure does not intersect the first diffusion region in the second direction; The third metal line in the back interconnect structure does not intersect with the first diffusion region in the second direction; The fourth metal line in the back-side interconnect structure does not intersect the first diffusion region in the second direction; A plurality of fifth metal lines coupled to the first metal line and adjacent to the semiconductor layer, the plurality of fifth metal lines intersecting the first diffusion region in the second direction; and A plurality of gates are coupled to the second metal line and the semiconductor layer, the plurality of gates intersecting the first diffusion region in the second direction; The plurality of gates intersect with the plurality of fifth metal lines; Multiple sixth metal lines coupled to the third metal line and adjacent to the semiconductor layer, the multiple sixth metal lines intersecting with the multiple gates; and The first MoM capacitor comprises: A first conductive finger structure, the first conductive finger structure comprising the first metal wire and the plurality of fifth metal wires; and The second conductive finger structure includes the second metal line and the plurality of gates; and The second MoM capacitor comprises: A third conductive finger structure, the third conductive finger structure including the third metal wire and the plurality of sixth metal wires; and The fourth conductive finger structure includes the fourth metal line and the plurality of gates. 20. The semiconductor die according to Clause 19, wherein the semiconductor die further comprises: A first conductive structure extends in the second direction and couples the first metal wire to the third metal wire; and A second conductive structure extends in the second direction and couples the second metal wire to the fourth metal wire. 21. The semiconductor die according to Clause 20, wherein: The first conductive structure includes a first strip-shaped via coupled to the first metal line and the third metal line; and The second conductive structure includes a second strip via coupled to the second metal line and the fourth metal line. 22. The semiconductor die according to clause 20 or 21, wherein: The first MoM capacitor further includes: A plurality of first gate contacts coupled to the plurality of gates and the second metal line; and The second MoM capacitor also includes: Multiple second gate contacts coupled to the plurality of gates and the fourth metal line. 23. The semiconductor die according to any one of clauses 19 to 22, wherein: The first diffusion region includes a first N-type semiconductor material (N) field-effect transistor (FET) (NFET) diffusion region; and The second diffusion region includes the second NFET diffusion region. 24. The semiconductor die according to any one of clauses 19 to 22, wherein: The first diffusion region includes a first P-type semiconductor material (P) field-effect transistor (FET) (PFET) diffusion region; and The second diffusion region includes the second PFET diffusion region. 25. A semiconductor die according to any one of Clauses 1 to 24, said semiconductor die integrated into a device selected from the group consisting of: set-top boxes; entertainment units; navigation devices; communication devices; fixed location data units; mobile location data units; global positioning system (GPS) devices; mobile phones; cellular phones; smartphones; session initiation protocol (SIP) phones; tablet computers; tablet phones; servers; computers; portable computers; mobile computing devices; wearable computing devices; desktop computers; personal digital assistants (PDAs); computer monitors; televisions; tuners; radios; satellite radios; music players; digital music players; portable music players; digital video players; video players; digital video disc (DVD) players; portable digital video players; automobiles; vehicle components; avionics systems; unmanned aerial vehicles; and multirotor aircraft. 26. A method for manufacturing a semiconductor die, the method comprising: A semiconductor layer is formed, the semiconductor layer extending in a first direction, the semiconductor layer including a front side and a back side opposite to the front side in a second direction orthogonal to the first direction; A front-side interconnect structure is formed, the front-side interconnect structure including a first metal-oxide-metal (MoM) capacitor and adjacent to the front side of the semiconductor layer in the second direction; A back-side interconnect structure is formed, the back-side interconnect structure including a second MoM capacitor and adjacent to the back side of the semiconductor layer in the second direction; and Forming a stacked MoM capacitor includes coupling the first MoM capacitor to the second MoM capacitor. 27. The method according to Clause 26, wherein: Forming the front interconnect structure includes forming a front metallization layer, the front metallization layer including the first MoM capacitor and extending in the first direction and adjacent to the front side of the semiconductor layer in the second direction; Forming the back-side interconnect structure includes forming a back-side metallization layer, the back-side metallization layer including the second MoM capacitor and adjacent to the back side of the semiconductor layer in the second direction; and The first MoM capacitor includes: The first metal line in the front metallization layer; and The first conductive finger structure in the front metallization layer includes multiple first finger metal lines that are parallel to each other and coupled to the first metal line. The second metal line in the front metallization layer; and The second conductive finger structure in the front metallization layer includes multiple parallel second finger metal lines coupled to the second metal lines, such that the first conductive finger structure and the second conductive finger structure intersect each other; and The second MoM capacitor includes: The third metal line in the back metallization layer; and The third conductive finger structure in the back metallization layer includes multiple third finger metal lines that are parallel to each other and coupled to the third metal lines. The fourth metal line in the back metallization layer; and The fourth conductive finger structure in the back metallization layer includes multiple fourth conductive finger metal lines that are parallel to each other and coupled to the fourth metal line, such that the third conductive finger structure and the fourth conductive finger structure intersect each other. 28. The method according to Clause 26, further comprising: Forming a unit circuit, including: A diffusion region is formed in the semiconductor layer; A first metal line is formed in the front interconnect structure; A second metal line is formed in the front interconnect structure; A third metal line is formed in the back-side interconnect structure; A fourth metal line is formed in the back-side interconnect structure; Forming a plurality of first finger-shaped metal lines coupled to the first metal line and adjacent to the semiconductor layer; and Multiple second finger-shaped metal lines are formed that are coupled to the second metal line and adjacent to the semiconductor layer, such that the multiple second finger-shaped metal lines intersect with the multiple first finger-shaped metal lines; Forming multiple third finger-shaped metal lines coupled to the third metal line and the semiconductor layer; and Multiple fourth finger-shaped metal lines are coupled to the fourth metal line and the semiconductor layer, such that the multiple fourth finger-shaped metal lines intersect with the multiple third finger-shaped metal lines. in: The first MoM capacitor includes: A first conductive finger structure, the first conductive finger structure including the first metal line in the front interconnect structure and the plurality of first finger metal lines; and The second conductive finger structure includes the second metal line in the front interconnect structure and the plurality of second finger metal lines; and The second MoM capacitor includes: A third conductive finger structure, the third conductive finger structure including the third metal line in the back interconnect structure and the plurality of third finger metal lines; and The fourth conductive finger structure includes the fourth metal line and the plurality of fourth finger metal lines in the back interconnect structure. 29. The method according to Clause 26, further comprising: Forming a unit circuit, including: A diffusion region is formed in the semiconductor layer; A first metal line is formed in the front interconnect structure, and the first metal line intersects the diffusion region at least partially in the second direction; A second metal line is formed in the front interconnect structure; A third metal line is formed in the back-side interconnect structure, the third metal line intersecting at least partially with the diffusion region in the second direction; A fourth metal line is formed in the back-side interconnect structure; Forming a plurality of first metal fingers coupled to the first metal line and the semiconductor layer; and A plurality of second metal fingers are formed that are coupled to the second metal line and the semiconductor layer, such that the plurality of second metal fingers intersect with the plurality of first metal fingers; Forming a plurality of third metal fingers coupled to the third metal line and the semiconductor layer; and A plurality of fourth metal fingers are formed and coupled to the fourth metal line and the semiconductor layer, such that the plurality of fourth metal fingers intersect with the plurality of third metal fingers; in: The first MoM capacitor includes: A first conductive finger structure, the first conductive finger structure including the first metal line in the front interconnect structure and the plurality of first metal fingers; and The second conductive finger structure includes the second metal line in the front interconnect structure and the plurality of second metal fingers; and The second MoM capacitor includes: A third conductive finger structure, the third conductive finger structure including the third metal line and the plurality of third metal fingers in the back interconnect structure; and A fourth conductive finger structure, the fourth conductive finger structure including the fourth metal line and the plurality of fourth metal fingers in the back interconnect structure. 30. The method according to Clause 26, further comprising: Forming a unit circuit, including: A first diffusion region is formed in the semiconductor layer; A first metal line is formed in the front interconnect structure, and the first metal line does not intersect with the first diffusion region in the second direction; A second metal line is formed in the front interconnect structure, and the second metal line does not intersect with the first diffusion region in the second direction; A third metal line is formed in the back-side interconnect structure, and the third metal line does not intersect with the first diffusion region in the second direction; A fourth metal line is formed in the back-side interconnect structure, the fourth metal line not intersecting the first diffusion region in the second direction; Forming a plurality of fifth metal lines coupled to the first metal line and adjacent to the semiconductor layer, the plurality of fifth metal lines intersecting the first diffusion region in the second direction; and A plurality of gates are formed coupled to the second metal line and the semiconductor layer, the plurality of gates intersecting the first diffusion region in the second direction, such that the plurality of gates intersect with the plurality of fifth metal lines; Multiple sixth metal lines are formed, coupled to the third metal line and adjacent to the semiconductor layer, such that the multiple sixth metal lines intersect with the multiple gates; and in: The first MoM capacitor includes: A first conductive finger structure, comprising the first metal line and the plurality of fifth metal lines in the front interconnect structure; and The second conductive finger structure includes the second metal line and the plurality of gates in the front interconnect structure; and The second MoM capacitor includes: A third conductive finger structure, the third conductive finger structure including the third metal line and the plurality of sixth metal lines in the back interconnect structure; and A fourth conductive finger structure, the fourth conductive finger structure including the fourth metal line and the plurality of gates in the back interconnect structure.

Claims

1. A semiconductor die, the semiconductor die comprising: A semiconductor layer extending in a first direction, the semiconductor layer including a front side and a back side opposite to the front side in a second direction orthogonal to the first direction; A front-side interconnect structure, wherein the front-side interconnect structure is adjacent to the front side of the semiconductor layer in the second direction. The front-side interconnect structure includes a first metal-oxide-metal (MoM) capacitor; A back-side interconnect structure, wherein the back-side interconnect structure is adjacent to the back side of the semiconductor layer in the second direction. The back-side interconnect structure includes a second MoM capacitor; and A stacked MoM capacitor, the stacked MoM capacitor comprising: The first MoM capacitor; and The second MoM capacitor is coupled to the first MoM capacitor.

2. The semiconductor die according to claim 1, wherein: The front interconnect structure further includes a front metallization layer, which includes the first MoM capacitor and extends in the first direction; and The back-side interconnect structure further includes a back-side metallization layer, which includes the second MoM capacitor and extends in the first direction.

3. The semiconductor die according to claim 2, wherein: The first MoM capacitor includes: The first metal line in the front metallization layer; and The first conductive finger structure in the front metallization layer includes multiple first finger metal lines that are parallel to each other and coupled to the first metal line. The second metal line in the front metallization layer; and The second conductive finger structure in the front metallization layer includes multiple second finger metal lines that are parallel to each other and coupled to the second metal lines. The first conductive finger structure and the second conductive finger structure intersect each other; and The second MoM capacitor includes: The third metal line in the back metallization layer; and The third conductive finger structure in the back metallization layer includes multiple third finger metal lines that are parallel to each other and coupled to the third metal lines. The fourth metal line in the back metallization layer; and The fourth conductive finger structure in the back metallization layer includes multiple fourth finger metal lines that are parallel to each other and coupled to the fourth metal lines. The third conductive finger structure and the fourth conductive finger structure intersect each other.

4. The semiconductor die of claim 1, wherein the stacked MoM capacitor further comprises one or more first conductive structures, each of the one or more first conductive structures extending in the second direction and coupled to the first MoM capacitor and the second MoM capacitor.

5. The semiconductor die according to claim 1, further comprising: Unit circuit, the unit circuit comprising: The diffusion region in the semiconductor layer; The first metal line in the front interconnect structure; The second metal line in the front interconnect structure; The third metal line in the back-side interconnect structure; The fourth metal line in the back-side interconnect structure; Multiple first finger-shaped metal lines coupled to the first metal line and adjacent to the semiconductor layer; and Multiple second finger-shaped metal lines coupled to the second metal line and adjacent to the semiconductor layer The plurality of second finger-shaped metal wires intersect with the plurality of first finger-shaped metal wires; Multiple third finger-shaped metal lines coupled to the third metal line and the semiconductor layer; and Multiple fourth finger-shaped metal lines coupled to the fourth metal line and the semiconductor layer The plurality of fourth finger-shaped metal wires intersect with the plurality of third finger-shaped metal wires; in: The first MoM capacitor includes: A first conductive finger structure, the first conductive finger structure comprising the first metal wire and the plurality of first finger-shaped metal wires; and The second conductive finger structure includes the second metal wire and the plurality of second finger-shaped metal wires; and The second MoM capacitor includes: A third conductive finger structure, the third conductive finger structure comprising the third metal wire and the plurality of third finger-shaped metal wires; and The fourth conductive finger structure includes the fourth metal wire and the plurality of fourth finger metal wires.

6. The semiconductor die according to claim 1, further comprising: Unit circuit, the unit circuit comprising: The diffusion region in the semiconductor layer; The first metal line in the front interconnect structure intersects the diffusion region at least partially in the second direction; The second metal line in the front interconnect structure; The third metal line in the back-side interconnect structure intersects the diffusion region at least partially in the second direction; The fourth metal line in the back-side interconnect structure; A plurality of first metal fingers coupled to the first metal line and the semiconductor layer; and Multiple second metal fingers coupled to the second metal line and the semiconductor layer The plurality of second metal fingers intersect with the plurality of first metal fingers; A plurality of third metal fingers coupled to the third metal line and the semiconductor layer; and Multiple fourth metal fingers coupled to the fourth metal line and the semiconductor layer, The plurality of fourth metal fingers intersect with the plurality of third metal fingers; The first MoM capacitor comprises: A first conductive finger-like structure, the first conductive finger-like structure comprising the first metal wire and the plurality of first metal fingers; and The second conductive finger structure includes the second metal wire and the plurality of second metal fingers; and The second MoM capacitor comprises: A third conductive finger structure, the third conductive finger structure comprising the third metal wire and the plurality of third metal fingers; and The fourth conductive finger structure includes the fourth metal wire and the plurality of fourth metal fingers.

7. The semiconductor die according to claim 6, wherein: The first metal line and the third metal line intersect the diffusion region at least partially in the second direction; and The second metal line and the fourth metal line do not intersect the diffusion region in the second direction.

8. The semiconductor die according to claim 6, further comprising: A plurality of first conductive structures, the plurality of first conductive structures extending in the second direction and coupling the plurality of first metal fingers to the plurality of third metal fingers; and A plurality of second conductive structures, the plurality of second conductive structures extending in the second direction and coupling the plurality of second metal fingers to the plurality of fourth metal fingers.

9. The semiconductor die according to claim 8, wherein: The unit circuit also includes multiple gates; The plurality of second metal fingers include the plurality of gates; and The plurality of fourth metal fingers include a plurality of second metal contacts.

10. The semiconductor die of claim 9, wherein the stacked MoM capacitor further comprises a plurality of first semiconductor capacitors, each of the plurality of first semiconductor capacitors comprising a first epitaxial layer of a plurality of first epitaxial layers adjacent to each of the plurality of gates.

11. The semiconductor die according to claim 6, wherein: The unit circuit also includes multiple gates; The plurality of second metal fingers include the plurality of gates; and The plurality of fourth metal fingers include a plurality of second metal contacts.

12. The semiconductor die according to claim 11, wherein: The first MoM capacitor further includes a plurality of first gate contacts coupled to the plurality of gates; and The second MoM capacitor also includes a plurality of second gate contacts coupled to the plurality of gates.

13. The semiconductor die according to claim 1, further comprising: Unit circuit, the unit circuit comprising: The first diffusion region in the semiconductor layer; The first metal line in the front interconnect structure does not intersect the first diffusion region in the second direction; The second metal line in the front interconnect structure does not intersect the first diffusion region in the second direction; The third metal line in the back interconnect structure does not intersect with the first diffusion region in the second direction; The fourth metal line in the back-side interconnect structure does not intersect the first diffusion region in the second direction; A plurality of fifth metal lines coupled to the first metal line and adjacent to the semiconductor layer, the plurality of fifth metal lines intersecting the first diffusion region in the second direction; and A plurality of gates are coupled to the second metal line and the semiconductor layer, the plurality of gates intersecting the first diffusion region in the second direction; The plurality of gates intersect with the plurality of fifth metal lines; Multiple sixth metal lines coupled to the third metal line and adjacent to the semiconductor layer, the multiple sixth metal lines intersecting with the multiple gates; and The first MoM capacitor comprises: A first conductive finger structure, the first conductive finger structure comprising the first metal wire and the plurality of fifth metal wires; and The second conductive finger structure includes the second metal line and the plurality of gates; and The second MoM capacitor comprises: A third conductive finger structure, the third conductive finger structure including the third metal wire and the plurality of sixth metal wires; and The fourth conductive finger structure includes the fourth metal line and the plurality of gates.

14. The semiconductor die according to claim 13, further comprising: A first conductive structure extends in the second direction and couples the first metal wire to the third metal wire; and A second conductive structure extends in the second direction and couples the second metal wire to the fourth metal wire.

15. The semiconductor die according to claim 14, wherein: The first conductive structure includes a first strip-shaped via coupled to the first metal line and the third metal line; and The second conductive structure includes a second strip via coupled to the second metal line and the fourth metal line.

16. The semiconductor die according to claim 14, wherein: The first MoM capacitor further includes: A plurality of first gate contacts coupled to the plurality of gates and the second metal line; and The second MoM capacitor also includes: Multiple second gate contacts coupled to the plurality of gates and the fourth metal line.

17. The semiconductor die of claim 1, wherein the semiconductor die is integrated into a device selected from the group consisting of: set-top boxes; entertainment units; navigation devices; communication devices; fixed location data units; mobile location data units; global positioning system (GPS) devices; mobile phones; cellular phones; smartphones; session initiation protocol (SIP) phones; tablet computers; tablet phones; servers; computers; portable computers; mobile computing devices; wearable computing devices; desktop computers; personal digital assistants (PDAs); computer monitors; televisions; tuners; radios; satellite radios; music players; digital music players; portable music players; digital video players; video players; digital video disc (DVD) players; portable digital video players; automobiles; vehicle components; avionics systems; unmanned aerial vehicles; and multirotor aircraft.

18. A method for manufacturing a semiconductor die, the method comprising: A semiconductor layer is formed, the semiconductor layer extending in a first direction, the semiconductor layer including a front side and a back side opposite to the front side in a second direction orthogonal to the first direction; A front-side interconnect structure is formed, the front-side interconnect structure including a first metal-oxide-metal (MoM) capacitor and adjacent to the front side of the semiconductor layer in the second direction; A back-side interconnect structure is formed, the back-side interconnect structure including a second MoM capacitor and being adjacent to the back side of the semiconductor layer in the second direction; as well as Forming a stacked MoM capacitor includes coupling the first MoM capacitor to the second MoM capacitor.

19. The method of claim 18, wherein: Forming the front interconnect structure includes forming a front metallization layer, the front metallization layer including the first MoM capacitor and extending in the first direction and adjacent to the front side of the semiconductor layer in the second direction; Forming the back-side interconnect structure includes forming a back-side metallization layer, the back-side metallization layer including the second MoM capacitor and adjacent to the back side of the semiconductor layer in the second direction; and The first MoM capacitor includes: The first metal line in the front metallization layer; and The first conductive finger structure in the front metallization layer includes multiple first finger metal lines that are parallel to each other and coupled to the first metal line. The second metal line in the front metallization layer; and The second conductive finger structure in the front metallization layer includes multiple parallel second finger metal lines coupled to the second metal lines, such that the first conductive finger structure and the second conductive finger structure intersect each other; and The second MoM capacitor includes: The third metal line in the back metallization layer; and The third conductive finger structure in the back metallization layer includes multiple third finger metal lines that are parallel to each other and coupled to the third metal lines. The fourth metal line in the back metallization layer; and The fourth conductive finger structure in the back metallization layer includes multiple fourth conductive finger metal lines that are parallel to each other and coupled to the fourth metal line, such that the third conductive finger structure and the fourth conductive finger structure intersect each other.

20. The method according to claim 18, further comprising: Forming a unit circuit, including: A diffusion region is formed in the semiconductor layer; A first metal line is formed in the front interconnect structure; A second metal line is formed in the front interconnect structure; A third metal line is formed in the back-side interconnect structure; A fourth metal line is formed in the back-side interconnect structure; Forming a plurality of first finger-shaped metal lines coupled to the first metal line and adjacent to the semiconductor layer; and Multiple second finger-shaped metal lines are formed that are coupled to the second metal line and adjacent to the semiconductor layer, such that the multiple second finger-shaped metal lines intersect with the multiple first finger-shaped metal lines; Forming multiple third finger-shaped metal lines coupled to the third metal line and the semiconductor layer; and Multiple fourth finger-shaped metal lines are coupled to the fourth metal line and the semiconductor layer, such that the multiple fourth finger-shaped metal lines intersect with the multiple third finger-shaped metal lines. in: The first MoM capacitor includes: A first conductive finger structure, the first conductive finger structure including the first metal line in the front interconnect structure and the plurality of first finger metal lines; and The second conductive finger structure includes the second metal line in the front interconnect structure and the plurality of second finger metal lines; and The second MoM capacitor includes: A third conductive finger structure, the third conductive finger structure including the third metal line in the back interconnect structure and the plurality of third finger metal lines; and The fourth conductive finger structure includes the fourth metal line and the plurality of fourth finger metal lines in the back interconnect structure.

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