Integrated circuit device including a multi-chip package

Abstract

A multi-chip package includes a first chiplet (120A) that includes power amplifier (PA) (108) circuitry. The multi-chip package also includes a second chiplet (120B) that includes low noise amplifier (LNA) circuitry (110). The multi-chip package also includes an electromagnetic interference (EMI) shield (106) between the first chiplet and the second chiplet. The multi-chip package also includes a molding compound (104) that at least partially encapsulates the first chiplet, the second chiplet, and the EMI shield.

Description

Cross-references to related applications

[0001] This application claims the benefit of priority to jointly owned U.S. non-provisional patent application No. 18 / 605,749, filed March 14, 2024, the entire contents of which are expressly incorporated herein by reference. Technical Field

[0002] Various features are involved in integrated circuit devices. Background Technology

[0003] Electrical connections exist at every level of a system hierarchy. This hierarchy includes the interconnections of active devices at the lowest system level, all the way up to the system-level interconnections at the highest level. For example, interconnect layers connect different devices on an integrated circuit. As integrated circuits become more complex, more interconnect layers are used to provide electrical connections between devices. Recently, due to the sheer number of interconnected devices in modern electronics, the number of interconnect layers in a circuit has substantially increased. The increasing number of interconnect layers to support the growing number of devices involves more complex processes.

[0004] Existing mobile application devices require small form factor, low cost, tight power budget, and high electrical performance. Mobile packaging designs have evolved to meet these different goals to enable mobile applications that support multimedia enhancements. However, such mobile applications are susceptible to power and signal routing issues when multiple dies are arranged side-by-side within a small form factor. Summary of the Invention

[0005] Various features are involved in integrated circuit devices.

[0006] One example provides a multi-chip package including a first chiplet that includes power amplifier (PA) circuitry. The multi-chip package also includes a second chiplet that includes low-noise amplifier (LNA) circuitry. The multi-chip package further includes an electromagnetic interference (EMI) shield located between the first and second chiplets. The multi-chip package also includes a molding compound that at least partially encapsulates the first chiplet, the second chiplet, and the EMI shield.

[0007] Another example provides a packaged integrated circuit device including a first chiplet that includes PA circuitry. The packaged integrated circuit device also includes a second chiplet that includes LNA circuitry. The packaged integrated circuit device further includes a third chiplet that includes radio frequency (RF) circuitry, a first contact on a first surface, a second contact on a second surface, and a conductor electrically connecting one or more of the first contacts to one or more of the second contacts. A first subset of the first contacts is electrically connected to the first chiplet, and a second subset of the first contacts is electrically connected to the second chiplet. The second contacts are configured to be electrically connected to an external component.

[0008] Another example provides a stacked integrated circuit device comprising a multi-chip package stacked with an RF interposer chiplet. The multi-chip package includes: a first chiplet including first circuitry; a second chiplet including second circuitry; and a molding compound that at least partially encapsulates the first and second chiplets. The RF interposer chiplet includes RF circuitry. The RF interposer chiplet also includes a first contact on a first surface electrically connected to the first and second chiplets of the multi-chip package.

[0009] Another example provides a manufacturing method. The method includes attaching a first chip including PA circuitry to a carrier substrate. The method further includes attaching a second chip including LNA circuitry to the carrier substrate. The method further includes forming an EMI shield between the first chip and the second chip. The method further includes encapsulating the first chip, the second chip, and the EMI shield at least partially in a molding compound to form a multi-chip package. Attached Figure Description

[0010] The various features, essence, and advantages will become apparent when the detailed description set forth below is understood in conjunction with the accompanying drawings, in which similar reference characters are used for corresponding identification throughout.

[0011] Figure 1 A cross-sectional profile view of an exemplary IC device including an embedded multi-chip package is shown.

[0012] Figure 2 Examples Figure 1 An example of an EMI shielding in an embedded multi-chip package.

[0013] Figure 3 A top view of the reconstructed wafer and a cross-sectional profile of an exemplary IC device including an embedded multi-chip package obtained from the reconstructed wafer are illustrated.

[0014] Figure 4 Examples Figure 3 The cross-sectional profile of the reconstructed wafer.

[0015] Figure 5 A cross-sectional profile view of an exemplary IC device including an embedded multi-chip package is shown.

[0016] Figure 6 (which extends across multiple pages) illustrates exemplary procedures for manufacturing exemplary IC devices including embedded multi-chip packages.

[0017] Figure 7 (which extends across multiple pages) illustrates an exemplary process for manufacturing another exemplary IC device, including an embedded multi-chip package.

[0018] Figure 8 An exemplary flowchart illustrating a method for manufacturing an exemplary IC device including an embedded multi-chip package is provided.

[0019] Figure 9 An exemplary flowchart illustrates another method for manufacturing an exemplary IC device including an embedded multi-chip package.

[0020] Figure 10 Examples of various electronic devices that can integrate the embedded multi-chip packages and / or device packages described herein are illustrated. Detailed Implementation

[0021] In the following description, specific details are set forth to provide a thorough understanding of the various aspects of this disclosure. However, those skilled in the art will understand that these aspects can be practiced without these specific details. For example, circuits may be shown as block diagrams to avoid complicating these aspects with unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail to avoid complicating these aspects of this disclosure.

[0022] Specific aspects of this disclosure are described below with reference to the accompanying drawings. In this description, common features are designated by common reference numerals. As used herein, various terms are used only for the purpose of describing particular embodiments and are not intended to limit the scope of the embodiments. For example, the singular forms “a,” “an,” and “the” are intended to also include the plural forms, unless the context clearly indicates otherwise. Furthermore, some features described herein are singular in some embodiments and plural in others. For ease of reference herein, such features are generally introduced as “one or more” features and are subsequently referred to in the singular or optional plural form (as indicated by “(multiple)”), unless the aspect relating to multiples of features is being described.

[0023] As used herein, the term “comprising” may be used interchangeably with “including”. As used herein, “exemplary” indicates an example, specific implementation, and / or aspect, and should not be construed as restrictive or indicating a preference or preferred implementation. As used herein, ordinal terms used to modify elements (such as structures, components, operations, etc.) (e.g., “first,” “second,” “third,” etc.) do not in themselves indicate any priority or order of that element relative to another element, but merely distinguish that element from another element with the same name (but using ordinal terms). As used herein, the term “set” refers to one or more specific elements among specific elements, while the term “multiple” refers to multiple (e.g., two or more) specific elements.

[0024] Improvements in manufacturing technology and the demand for lower-cost and more capable electronic devices have led to increased complexity in ICs. Typically, more complex ICs have more complex interconnect schemes to enable interaction between ICs within a device. Due to the sheer number of interconnected devices in today's state-of-the-art mobile applications, the number of interconnect layers in the circuitry has also increased substantially.

[0025] These interconnects include back-end process (BEOL) interconnect layers, which can refer to conductive interconnect layers used for electrical coupling to front-end process (FEOL) active devices of the IC. Various BEOL interconnect layers are formed at corresponding BEOL interconnect levels, where lower BEOL interconnect levels typically use a thinner metal layer than upper BEOL interconnect levels. BEOL interconnect layers can be electrically coupled to middle-end process (MOL) interconnect layers, which interconnect to the IC's FEOL active devices.

[0026] Existing mobile application devices require small form factor, low cost, tight power budgets, and high electrical performance. Mobile packaging designs have evolved to meet these diverse objectives, enabling multimedia-enhanced mobile applications. For example, fan-out (FO) wafer-level packaging (WLP), or FO-WLP process technology, is an evolution of packaging technologies useful for mobile applications. This chip-first FO-WLP process technology solution provides flexibility for fan-in and fan-out connections from the die to the package ball. Furthermore, this solution offers a significant reduction in the height of the first-level interconnect between the die and package ball for mobile application devices. However, when multiple dies are arranged within a small form factor, these mobile applications are susceptible to power and signal routing issues.

[0027] Stacked die and chiplet architectures are becoming increasingly prevalent due to the significant yield improvements in power performance area (PPA) demonstrated by stacked die and chiplet architecture product lines. Unfortunately, stacked die solutions may involve high power density targets, resulting in significant power distribution inefficiencies. Various aspects of this disclosure provide stacked IC devices arranged to provide improved integration of capacitors with power distribution networks (PDNs), thereby achieving improved PDN performance.

[0028] As used herein, the term "layer" includes films and is not construed as indicating vertical or horizontal thickness unless otherwise stated. As used herein, the term "chiplet" can refer to a block of integrated circuits, a block of functional circuitry, or other similar circuitry specifically designed to work with one or more other chiplets to form a larger, more complex chiplet architecture.

[0029] This disclosure relates to IC devices including multi-chip packages (also referred to herein as "embedded multi-chip packages"). In this context, the term "embedded multi-chip package" refers to an article comprising a plurality of chips or chiplets (wholly or partially) encapsulated in a structural matrix (e.g., a molding compound) and having external contacts that facilitate electrical connections to the individual chips or chiplets within the plurality of chips or chiplets, such that the plurality of chips or chiplets can be used as a single component during manufacturing. In some aspects of this disclosure, an embedded multi-chip package includes: a first chiplet including a first circuit (e.g., a power amplifier (PA) circuit); and a second chiplet including a second circuit (e.g., a low-noise amplifier (LNA) circuit). The embedded multi-chip package also includes an electromagnetic interference (EMI) shield between the first and second chiplets. In some aspects of this disclosure, the embedded multi-chip package is stacked with radio frequency (RF) interposer chiplets. The RF interposer chiplets include RF circuitry, such as transceiver (TRX) circuitry. The RF interposer chiplet includes first contacts on a first surface, second contacts on a second surface, and conductors (e.g., through-silicon vias (TSVs)) electrically connecting one or more of the first contacts to one or more of the second contacts. A first subset of the first contacts is electrically connected to the first chiplet, and a second subset of the first contacts is electrically connected to the second chiplet. The second contacts are configured to be electrically connected to an external package component.

[0030] Exemplary IC devices including embedded multi-chip packages Figure 1A cross-sectional profile view of an exemplary device 100 (e.g., a stacked IC device) including a package 114 (e.g., an embedded multi-chip package) stacked with an RF interposer chiplet 112 is illustrated. Package 114 includes chiplets 120A and 120B. Package 114 also includes an EMI shield 106 between chiplets 120A and 120B. The EMI shield 106 is configured to reduce (e.g., block) electromagnetic interference between chiplets 120A and 120B. In a particular aspect, the EMI shield 106 has a magnetic field strength (B) 116.

[0031] Each chiplet may include an integrated circuit, such as multiple transistors and / or other circuit elements arranged and interconnected to form logic cells, memory cells, etc. The components of the integrated circuit may be formed in and / or on a semiconductor substrate. Different implementations may use different types of transistors, such as field-effect transistors (FETs), planar FETs, finFETs, gate-all-around FETs, or a mixture of transistor types. In some implementations, the FEOL process may be used to fabricate the integrated circuit in and / or on a semiconductor substrate.

[0032] Chip 120A includes an active circuit formed in or on substrate 130, and chip 120B includes an active circuit formed in or on substrate 132. Figure 1 In the example of device 100, chiplet 120A includes a power amplifier (PA) circuit 108, and chiplet 120B includes a low-noise amplifier (LNA) circuit 110. Optionally, in some aspects, substrate 130 has a first substrate material that is different from the second substrate material of substrate 132. For example, the first substrate material includes at least one of gallium arsenide (GaAs) or indium phosphide (InP), and the second substrate material includes silicon (Si). It should be understood that chiplet 120A including PA circuit 108 and chiplet 120B including LNA circuit 110 are provided as illustrative examples, and in other examples, chiplet 120A, chiplet 120B, or both may include other types of active components, passive components, or both.

[0033] Chip 120A includes a BEOL layer 134 on a first side of chip 120A to electrically connect one or more contacts 140 on the first side to active circuitry of chip 120A (e.g., PA circuitry 108). In some aspects, BEOL layer 134 may include one or more active layers, one or more passive layers, or a combination thereof. Chip 120B includes a BEOL layer 136 on a first side of chip 120B to electrically connect one or more contacts 160 on the first side to active circuitry of chip 120B (e.g., LNA circuitry 110). In some aspects, BEOL layer 136 may include one or more active layers, one or more passive layers, or a combination thereof. EMI shield 106 includes one or more contacts 150 on a first side of EMI shield 106. Chip 120A, chip 120B, and EMI shield 106 are at least partially encapsulated in molding compound 104. In some embodiments, RF interposer chip 112 may be at least partially encapsulated in molding compound.

[0034] RF interposer chip 112 includes contacts 180, conductors 182, and a BEOL layer 184. In some aspects, the BEOL layer 184 may include one or more active layers, one or more passive layers, or a combination thereof. In a particular aspect, conductor 182 corresponds to a through-silicon via (TSV). Conductor 182 electrically connects one or more contacts of the contacts 180 on a first side 172 (e.g., a first surface) of the RF interposer chip 112 to one or more BEOL layers 184 on a second side 174 (e.g., a second surface) of the RF interposer chip 112. For example, contact 180A is electrically connected to BEOL layer 184A via conductor 182A (e.g., a through-silicon via (TSV)). As another example, contact 180B is electrically connected to BEOL layer 184B via conductor 182B (e.g., a TSV). As a further example, contact 180C is electrically connected to BEOL layer 184C via conductor 182C (e.g., a TSV). It should be understood that the BEOL layer is provided as an exemplary example of the contact type of the RF interposer chip 112, and in other examples, the RF interposer chip 112 may include another type of contact on the second side 174 that is electrically connected to the conductor 182.

[0035] The RF interposer chip 112 also includes RF circuitry (not shown). In some examples, the RF interposer chip 112 includes a transmitter chip that includes transmitter circuitry. In some examples, the RF interposer chip 112 includes a receiver chip that includes receiver circuitry. In some examples, the RF interposer chip 112 includes a transceiver chip that includes transceiver circuitry, such as transmitter circuitry and receiver circuitry. In some aspects, the RF interposer chip 112 includes one or more passive devices, such as one or more decoupling capacitors or inductors.

[0036] exist Figure 1 In device 100, package 114 is coupled on a first side of package 114 to a first side 172 of RF interposer chip 112. For example, a first subset of contacts 180 is electrically connected to one or more contacts 140 of chip 120A. For example, contact 180A is electrically connected to contact 140 of chip 120A via conductive interconnect 170A. As another example, a second subset of contacts 180 is electrically connected to one or more contacts 160 of chip 120B. For example, contact 180C is electrically connected to contact 160 of chip 120B via conductive interconnect 170C. In this example, RF interposer chip 112 is electrically connected to EMI shield 106. For example, contact 180B is electrically connected to contact 150 of EMI shield 106.

[0037] Optionally, in some aspects, one or more contacts in a first subset of contacts 180 electrically connect the active circuitry of chip 120A (e.g., PA circuit 108) to the active circuitry of RF interposer chip 112 (e.g., transmitter circuitry of transmitter chip). Optionally, in some aspects, one or more contacts in a second subset of contacts 180 electrically connect the active circuitry of chip 120B (e.g., LNA circuit 110) to the active circuitry of RF interposer chip 112 (e.g., receiver circuitry of receiver chip). In some aspects, RF interposer chip 112 operates as an interposer facilitating communication between chips 120, as referenced. Figure 3 Further description.

[0038] RF interposer chip 112 is electrically connected to substrate 102. For example, a BEOL layer 184 on a second side 174 of RF interposer chip 112 is electrically connected to a metal layer 194 of substrate 102 via one or more contacts 190 and one or more conductive interconnects 192. In some aspects, one or more BEOL layers in the BEOL layers 184 of RF interposer chip 112 are configured to be electrically connected to an external component.

[0039] RF interposer chip 112 facilitates communication between the BEOL layers 134, 136 of chip 120 and the substrate 102. In some aspects, chip 120A (e.g., PA circuit 108) is electrically connected to the substrate 102. For example, device 100 includes a conductive path from chip 120A (e.g., PA circuit 108) through BEOL layer 134, contact 140, conductive interconnect 170A, contact 180A, conductor 182A, BEOL layer 184A, contact 190, and conductive interconnect 192 to metal layer 194 of substrate 102.

[0040] In some aspects, chiplet 120B (e.g., LNA circuit 110) is electrically connected to substrate 102. For example, device 100 includes a conductive path from chiplet 120B (e.g., LNA circuit 110) through BEOL layer 136, contact 160, conductive interconnect 170C, contact 180C, conductor 182C, BEOL layer 184C, contacts, and a metal layer 194 conductively interconnected to substrate 102.

[0041] Any of the conductive interconnects and contacts described herein may include, for example, microbumps, conductive pillars, conductive pads (e.g., for pad-to-pad bonding), or other similar chiplet-to-chiplet interconnect contacts for three-dimensional (3D) chiplet stacking. In some embodiments, chiplets 120A, 120B, and RF interposer chiplet 112 are designed to operate cooperatively with each other. For illustration, in some embodiments, the active circuitry of chiplet 120A includes one or more first functional circuit blocks, the active circuitry of chiplet 120B includes one or more second functional circuit blocks, and the active circuitry of RF interposer chiplet 112 includes one or more third functional circuit blocks, wherein the one or more third functional circuit blocks are operationally dependent on one or more first functional circuit blocks, one or more second functional circuit blocks, or combinations thereof. Figure 1 The cross-sectional profile view in the figure shows an example of package 114 including two chiplets. In other views or examples, package 114 may include more than two chiplets, such as filter chiplets, switch chiplets, or both, as shown in the reference. Figure 3 Further description.

[0042] Using chiplets arranged and interconnected as a 3D stacked IC to form device 100 offers various benefits compared to providing the same functional circuitry in a single monolithic chip. For example, each chiplet is smaller than a monolithic die containing all the same functional circuitry blocks. Since yield losses in IC manufacturing tend to increase with die size, using smaller dies can reduce yield losses in the IC manufacturing process (i.e., increase yield). Another benefit is that chiplets can be manufactured in different locations and / or by different manufacturers, and in some cases, using different manufacturing technologies (e.g., different manufacturing technology nodes). As an example, one chiplet of a chiplet-based integrated device (e.g., chiplet 120A of device 100) may include components (e.g., interconnects, transistors, etc.) having a first minimum size, and another chiplet of a chiplet-based integrated device (e.g., second chiplet 120B of device 100) may include components (e.g., interconnects, transistors, etc.) having a second minimum size, where the second minimum size is larger than the first minimum size. In contrast, all circuitry on a monolithic die is manufactured using the same manufacturing technology and equipment. Therefore, when manufacturing a monolithic die, the entire die may be subject to the most stringent manufacturing constraints of the most complex components of the monolithic die. In contrast, when using chiplets, different chiplets can be manufactured using different manufacturing technologies (e.g., different manufacturing technology nodes), and only one or more chiplets containing the most complex components are subject to the most stringent manufacturing constraints. In this arrangement, chiplets manufactured using cheaper and / or higher-yield manufacturing technologies can be integrated with chiplets manufactured using more expensive and / or lower-yield manufacturing technologies to form an IC (e.g., device 100), resulting in overall savings. Furthermore, in some cases, the design of the chiplets can change as technology improves. Chiplet stacking allows the integration of such new chiplet designs with older chiplet designs to form stacked IC devices, which increases manufacturing flexibility and reduces design costs.

[0043] In certain aspects, multiple packages 114 can be formed on the reconfigured wafer, as referenced. Figure 3 Further described. For example, the reconstructed wafer can be diced to obtain a package 114 that can be bonded to the RF interposer chiplet 112, as referenced. Figure 4 As further described in Figures 6 and 7. Therefore, compared to a multi-step process of individually bonding each component in the assembly to the RF interposer chip 112, the device 100 can be formed using a single bonding process that stacks the components of package 114 (e.g., chip 120A, EMI shield 106, and chip 120B) onto the RF interposer chip 112.

[0044] While one benefit of using stacked IC devices (such as device 100) compared to similar monolithic IC devices is the reduced footprint of such devices, this reduced footprint can pose challenges for electromagnetic interference (EMI). The technical advantage of having an EMI shield 106 between chiplets 120A and 120B is that chiplets 120A and 120B can be positioned as close as possible with reduced (e.g., no) EMI, thereby achieving improved power performance area cost (PPAC) characteristics.

[0045] Figure 2 Examples Figure 1 Examples 200 and 250 are of the EMI shield 106 of the package 114. In example 200, the EMI shield 106 is a single conductive structure 206. For illustration, the single conductive structure 206 may include a wall-like structure having a metal (e.g., copper) coating.

[0046] In Example 250, the EMI shield 106 includes a plurality of conductive structures 208. For illustration, the EMI shield 106 may include an array of conductive structures 208. In a particular embodiment, the conductive structures 208 may include metal (e.g., copper) pillars.

[0047] Figure 3 A top view of the reconstructed wafer 352 and a cross-sectional profile of the device 100 (e.g., an exemplary IC device) including a package 114 (e.g., a multi-chip package) obtained from the reconstructed wafer 352 are illustrated.

[0048] exist Figure 3 In this embodiment, package 114 is illustrated as including one or more redistribution layers (RDLs) 344 coupled to molding compound 104 and electrically connected to chiplet 120A, EMI shield 106, and chiplet 102B. For example, RDL 344 may include one or more contacts 140 electrically connected to BEOL layer 134 of chiplet 120A, one or more contacts 150 electrically connected to EMI shield 106, and one or more contacts 160 electrically connected to BEOL layer 136 of chiplet 120B. In some aspects, RDL 344 may include one or more additional contacts, such as representative contact 342. It should be understood that any embodiment of package 114 described herein may optionally include RDL 344, even if not illustrated.

[0049] exist Figure 3In this embodiment, RF interposer chip 112 is illustrated as being included on a first side 172 of RF interposer chip 112 and configured to be electrically connected to chip 120A, EMI shield 106, chip 120B, and BEOL layer 184, forming an RDL 346. For example, RDL 346 includes one or more contacts 180A configured to be electrically connected via one or more conductive interconnects 170A to one or more contacts 140 electrically connected to the BEOL layer 134 of chip 120A. As another example, RDL 346 includes one or more contacts 180B configured to be electrically connected via one or more conductive interconnects 170B to one or more contacts 150 electrically connected to the EMI shield 106 of RDL 344. In yet another example, RDL 346 includes one or more contacts 180C configured to be electrically connected via one or more conductive interconnects 170C to one or more contacts 160 electrically connected to the BEOL layer 136 of chiplet 120B in RDL 344. In some aspects, one or more contacts 180 are electrically connected via conductors 182 (e.g., TSV) to one or more BEOL layers in BEOL layer 184. In some aspects, RF interposer chiplet 112 operates as an interposer facilitating communication between chiplet 120A and chiplet 120B via RDL 346. RF interposer chiplet 112 also facilitates communication between chiplet 120 and substrate 102. It should be understood that any embodiment of the RF interposer chiplet 112 described herein may optionally include RDL 346, even if not illustrated.

[0050] Multiple packages 114 are formed on the reconstructed wafer 352. Each package 114 includes multiple chips 120, such as chip 120A, chip 120B, chip 120C, and chip 120D, wherein at least one pair of chips 120 are separated by an EMI shield 106. It should be understood that a package 114 including four chips 120 and one EMI shield 106 is provided as an illustrative example; in other examples, a package 114 may include fewer than four chips 120 or more chips 120 having one or more EMI shields 106.

[0051] In Example 350, chip 120A corresponds to a power amplifier chip. In some embodiments, the active circuitry of chip 120A includes at least one of gallium arsenide (GaAs), indium phosphide (InP), or gallium nitride (GaN) as the semiconductor material. In certain aspects, the power amplifier circuit 108 of chip 120A increases the power level of the input signal to drive an output load, such as an antenna or transmit line. In some embodiments, the power amplifier circuit 108 can operate across a wide frequency range. In some embodiments, the power amplifier circuit 108 can operate to amplify signals within a specific frequency band.

[0052] In Example 350, chip 120B corresponds to a silicon-on-insulator (SOI) LNA chip. For illustration, LNA circuit 110 is formed on substrate 132, which includes a silicon layer separated from the silicon substrate by an insulating layer to reduce parasitic capacitance and leakage current, thereby improving the performance of LNA circuit 110. In some specific embodiments, the insulating layer comprises silicon dioxide. In some aspects, the LNA circuit 110 of chip 120B is designed to amplify very weak signals while introducing as little noise as possible.

[0053] In Example 350, chip 120C corresponds to a filter chip. For example, in some embodiments, chip 120C includes an inductor-capacitor (LC) filter. For illustration, an LC filter is designed to filter out certain frequencies from a signal while allowing other frequencies to pass through. In some embodiments, the LC filter includes a gold (Au) connector (e.g., a contact).

[0054] In Example 350, chiplet 120D corresponds to a switching chiplet. In some specific implementations, chiplet 120 includes a microelectromechanical system (MEMS) switch. For illustration, the switching chiplet operates to perform at least one of signal routing, impedance matching, tunability, beamforming, or antenna switching.

[0055] Figure 4 A cross-sectional profile view 400 of the reconstructed wafer 352 is illustrated. Multiple packages 114 (such as packages 114A, 114B, and 114C) are formed on a carrier substrate 408 of the reconstructed wafer 352.

[0056] It should be understood that the three packages 114 formed on the carrier substrate 408 are provided as an illustrative example; in other examples, fewer or more than three packages 114 may be formed on the carrier substrate 408. A dicing operation is performed on the reconstructed wafer 352 to separate the packages 114.

[0057] In some aspects, for example, electrical testing of package 114 is performed using chip probes. Package 114, which passes the electrical test, is bonded to RF interposer chip 112, as further described with reference to Figures 6 and 7. Thus, a single bonding process can be used to stack package 114 onto RF interposer chip 112. Attaching package 114 to RF interposer chip 112 after testing (rather than attaching individual components of package 114) improves yield.

[0058] Figure 5 A cross-sectional profile view of a device 500 (e.g., an exemplary IC device) including a package 114 (e.g., a multi-chip package) is illustrated. In a particular aspect, the orientation of the RF interposer chip 112 is flipped vertically relative to the device 100 within the device 500. For example, a BEOL layer 184 on a second side 174 of the RF interposer chip 112 is electrically connected to the package 114, and a contact 180 on a first side 172 of the RF interposer chip 112 is electrically connected to the substrate 102.

[0059] In the example, BEOL layer 184A is electrically connected to contact 140 on a first side of chiplet 120A via conductive interconnect 170, and contact 180A is electrically connected to substrate 102 via contact 190 and conductive interconnect 192. In a particular aspect, substrate 102 is used as ground, and Figure 1 Metal layer 194 does not exist Figure 5 In the substrate 102.

[0060] The stacked IC devices disclosed herein can be integrated with or included within a wide variety of other devices. For example, a device that includes one or more integrated devices disclosed herein may include components such as power management integrated circuits (PMICs), application processors, modems, radio frequency (RF) devices, passive devices, filters, capacitors, inductors, transmitters, receivers, gallium arsenide (GaAs)-based integrated devices, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, light-emitting diode (LED) integrated devices, silicon (Si)-based integrated devices, silicon carbide (SiC)-based integrated devices, memories, power management processors, and / or combinations thereof. In such devices, the stacked IC devices can operate as any (or a combination of) these components that include active circuitry.

[0061] Exemplary process for manufacturing IC devices including multi-chip packages In some specific implementations, manufacturing an IC device, including a multi-chip package (e.g., any device in device 100 or 500), involves several processes. Figure 6 (which continues across multiple pages) illustrates the processes used to provide or manufacture (as referenced) Figure 1The exemplary process described includes a multi-chip packaged stacked IC device (e.g., device 100).

[0062] It should be noted that the processes in Figure 6 may be combined in one or more stages to simplify and / or clarify the processes used to provide or manufacture integrated devices. In some embodiments, the order of the processes may be changed or modified. In some embodiments, one or more processes may be substituted or replaced without departing from the scope of this disclosure. In the following description, reference is made to various exemplary stages of the processes, which are numbered in Figure 6 (using circled numbers).

[0063] Phase 1 of Figure 6 illustrates at least a portion of the reconstructed wafer 352. In a particular aspect, Phase 1 illustrates the state after the reconstructed wafer 352 has been diced into multiple portions. A portion of the reconstructed wafer 352 includes a package 114 formed on a carrier substrate 408. The package 114 includes an EMI shield 106 between chiplets 120A and 120B. Chiplets 120A, EMI shield 106, and chiplets 120B are at least partially encapsulated in a molding compound 104. In a particular aspect, temporary bonding is used to bond chiplets 120A and EMI shield 106 to the carrier substrate 408. In some embodiments, a redistribution layer (e.g., Figure 3 The RDL 344 is formed on the reconstructed wafer, in which contacts 140, 150, and 160 are contacts of the redistribution layer.

[0064] Phase 2 illustrates the state after a portion of the reconstructed wafer 352 has been vertically flipped and positioned relative to the RF interposer chiplet 112. The RF interposer chiplet 112 includes contacts 180 on or at a first side 172 of the RF interposer chiplet 112, wherein conductive interconnects 170 are formed (e.g., deposited) on the contacts 180. In a particular aspect, a portion of the reconstructed wafer 352 is positioned such that contacts 140, 150, and 160 of package 114 are aligned with conductive interconnects 170 on the RF interposer chiplet 112. For example, contacts 140 of chiplet 120A are aligned with conductive interconnects 170A, contacts 150 of EMI shield 106 are aligned with conductive interconnects 170B, and contacts 160 of chiplet 120B are aligned with conductive interconnects 170.

[0065] Phase 3 illustrates the state after contacts 140, 150, and 160 of the reconstructed wafer 352 are aligned and bonded to conductive interconnects 170 on the RF interposer chiplet 112. In some embodiments, hybrid bonding is used to bond contacts 140, 150, and 160 to conductive interconnects 170. For example, the surfaces of contacts 140, 150, and 160 and the conductive interconnects 170 are activated through various processes, such as plasma treatment or chemical modification. A high-precision alignment system is used to align contacts 140, 150, and 160 with conductive interconnects 170. Once aligned, the surfaces of contacts 140, 150, and 160 are brought into contact with the surface of conductive interconnects 170 under controlled conditions, such as pressure, temperature, and sometimes electrical or ultrasonic assistance. After bonding, annealing may be performed to improve the bonding strength and stability of the interface.

[0066] Stage 4 illustrates the state after the removal of carrier substrate 408. Carrier substrate 408 can be removed using mechanical delamination, etching processes, laser ablation operations, thermal release, other targeted carrier substrate removal operations, or combinations thereof. The formation of device 650 (e.g., a stacked IC device) is completed after stage 4 of FIG. 6. However, in some specific embodiments, device 650 can be used to form… Figure 1 Device 100.

[0067] Phase 5 illustrates the state after the device 650 is positioned relative to the substrate 102. The substrate 102 includes conductive interconnects 192 on or at a first side of the substrate 102, the conductive interconnects being electrically connected to a metal layer 194 of the substrate 102. Contacts 190 are formed on the conductive interconnects 192.

[0068] Phase 6 illustrates the state after the BEOL layer 184 on or at the second side 174 of the RF interposer chip 112 of device 650 is aligned and bonded with the contact 190. For example, heating / reflow can be applied to bond the BEOL layer 184 of the RF interposer chip 112 to the metal layer 194 of the substrate 102 via the contact 190 and the conductive interconnect 192 to form Figure 1 Device 100.

[0069] As another example, device 650 can be disposed on substrate 102 with BEOL layer 184 on second side 174 bonded to conductive interconnect 170, and heating / reflow can be applied to bond contacts 180 of RF interposer chip 112 to substrate 102 via contacts 190 and conductive interconnect 192 to form Figure 5 500 devices.

[0070] Figure 7 (which continues across multiple pages) illustrates the methods used for providing or manufacturing (as referenced). Figure 5The description includes exemplary processes for stacked IC devices (e.g., device 500) in multi-chip packages. It should be noted that the processes in FIG7 may combine one or more stages to simplify and / or clarify the processes used to provide or manufacture integrated devices. In some embodiments, the order of processes may be changed or modified. In some embodiments, one or more processes may be substituted or replaced without departing from the scope of this disclosure. In the following description, reference is made to various exemplary stages of the processes, which are numbered in FIG7 (using circled numbers).

[0071] Phase 1 of Figure 7 illustrates at least a portion of the reconstructed wafer 352. In a particular aspect, Phase 1 illustrates the state after the reconstructed wafer 352 has been diced into multiple portions. A portion of the reconstructed wafer 352 includes a package 114 formed on a carrier substrate 408. The package 114 includes an EMI shield 106 between chiplets 120A and 120B. Chiplets 120A, EMI shield 106, and chiplets 120B are at least partially encapsulated in a molding compound 104. In a particular aspect, temporary bonding is used to bond chiplets 120A and EMI shield 106 to the carrier substrate 408. In some embodiments, a redistribution layer (e.g., Figure 3 The RDL 344 is formed on the reconstructed wafer, in which contacts 140, 150, and 160 are contacts of the redistribution layer.

[0072] Phase 2 illustrates the state after a portion of the reconstructed wafer 352 has been vertically flipped and positioned relative to the RF interposer chiplet 112. The RF interposer chiplet 112 includes a BEOL layer 184 on or at a second side 174 of the RF interposer chiplet 112, wherein conductive interconnects 170 are formed (e.g., deposited) on the BEOL layer 184. In a particular aspect, a portion of the reconstructed wafer 352 is positioned such that contacts 140, 150, and 160 of package 114 are aligned with conductive interconnects 170 on the RF interposer chiplet 112. For example, contacts 140 of chiplet 120A are aligned with conductive interconnects 170A, contacts 150 of EMI shield 106 are aligned with conductive interconnects 170B, and contacts 160 of chiplet 120B are aligned with conductive interconnects 170.

[0073] Phase 3 illustrates the state after contacts 140, 150, and 160 of the reconstructed wafer 352 are aligned and bonded to conductive interconnects 170 on the RF interposer chiplet 112. In some embodiments, hybrid bonding is used to bond contacts 140, 150, and 160 to conductive interconnects 170.

[0074] Stage 4 illustrates the state after the carrier substrate 408 has been removed. The formation of the device 750 (e.g., a stacked IC device) is completed after stage 4 of FIG. 7. However, in some specific embodiments, device 750 can be used to form... Figure 1 500 devices.

[0075] Phase 5 illustrates the state after the device 750 is positioned relative to the substrate 102. The substrate 102 includes conductive interconnects 192 on or at a first side of the substrate 102. In the example of FIG. 7, the metal layer 194 is not present in the substrate 102. Contacts 190 are formed on the conductive interconnects 192.

[0076] Phase 6 illustrates the state after contacts 180 and 190 on or at the first side 172 of the RF interposer chip 112 of device 650 are aligned and bonded. For example, heating / reflow can be applied to bond the contacts 180 of the RF interposer chip 112 to the substrate 102 via contacts 190 and conductive interconnects 192 to form Figure 5 500 devices.

[0077] An exemplary flowchart of a method for manufacturing integrated circuit devices including multi-chip packages. In some specific implementations, manufacturing IC devices involves several processes. Figure 8 An exemplary flowchart illustrating a method 800 for providing or manufacturing a stacked IC device including a multi-chip package is shown. In some specific implementations, Figure 8 Method 800 can be used to provide or manufacture Figure 1 Any of the stacked IC devices 100, 500, 650 or 750 in Figure 7.

[0078] It should be noted that Figure 8 Method 800 may combine one or more processes to simplify and / or clarify the methods used to provide or manufacture integrated circuit devices. In some specific implementations, the order of the processes may be changed or modified.

[0079] Method 800 includes attaching a first chip including power amplifier (PA) circuitry to a carrier substrate at block 802. For example, a chip 120A including PA circuitry 108 is attached to carrier substrate 408 as part of package 114.

[0080] Method 800 includes attaching a second chip including low-noise amplifier (LNA) circuitry to a carrier substrate at block 804. For example, a chip 120B including LNA circuitry 110 is attached as part of package 114 to carrier substrate 408.

[0081] Method 800 includes forming an electromagnetic interference (EMI) shield at block 806 between a first chiplet and a second chiplet. For example, the EMI shield 106 positioned between chiplets 120A and 120B is attached to a carrier substrate 408. For illustration, the EMI shield 106 may be attached to the carrier substrate 408 using a temporary bonding operation.

[0082] Method 800 includes, at block 808, at least partially encapsulating a first chiplet, a second chiplet, and an EMI shield in a molding compound to form a multi-chip package. For example, chiplet 120A, chiplet 120B, and EMI shield 106 are at least partially encapsulated in a molding compound 104 to form a package 114 (e.g., a multi-chip package).

[0083] Figure 9 An exemplary flowchart illustrating a method 900 for providing or manufacturing a stacked IC device including a multi-chip package is shown. In some specific implementations, Figure 9 Method 900 can be used to provide or manufacture Figure 1 Any of the stacked IC devices 100, 500, 650 or 750 in Figure 7.

[0084] It should be noted that Figure 9 Method 900 may combine one or more processes to simplify and / or clarify the methods used to provide or manufacture integrated circuit devices. In some specific implementations, the order of the processes may be changed or modified.

[0085] Method 900 includes, at block 902, obtaining a multi-chip package comprising: a first chiplet including first circuitry; a second chiplet including second circuitry; and a molding compound at least partially encapsulating the first and second chiplets. For example, package 114 is obtained by dicing a reconstructed wafer 352. Package 114 includes: chiplet 120A including first circuitry (e.g., PA circuitry 108); and chiplet 120B including second circuitry (e.g., LNA circuitry 110), as referenced. Figure 3 As described.

[0086] Method 900 includes obtaining a radio frequency (RF) interposer chip at block 904, the RF interposer chip including RF circuitry. For example, obtaining an RF interposer chip 112. RF interposer chip 112 includes RF circuitry, such as a receiver, a transmitter, or both.

[0087] Method 900 includes electrically connecting contacts of a multi-chip package and contacts of an RF interposer chiplet at block 906 to form a stacked integrated circuit device. For example, contacts 140, 150, and 160 of package 114 are electrically connected to contacts 180 of RF interposer chiplet 112, as referenced. Figure 1 As described in Figure 6. As another example, contacts 140, 150, and 160 of package 114 are electrically connected to the BEOL layer 184 of RF interposer chip 112, as referenced. Figure 5 As described in Figure 7.

[0088] Exemplary electronic devices Figure 10 Examples of devices that may include or be integrated with any of devices 100, 500, 650, or 750 are illustrated. For example, mobile phone device 1002, laptop computer device 1004, fixed-location terminal device 1006, wearable device 1008, or vehicle 1010 (e.g., automotive or aircraft equipment) may include device 1000. Device 1000 may include any of the devices 100, 500, or 650 described herein, for example. Figure 10 The illustrated devices 1002, 1004, 1006, and 1008, as well as vehicle 1010, are merely exemplary. Other electronic devices may also feature device 1000, including but not limited to the group of devices (e.g., electronic devices) comprising: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading devices), communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0089] Figures 1 to 10 One or more of the components, processes, features, and / or functions illustrated herein may be rearranged and / or combined into a single component, process, feature, or function, or implemented in several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from this disclosure. It should also be noted that... Figures 1 to 10 The corresponding descriptions herein are not limited to dies and / or ICs. In some specific implementations, Figures 1 to 10The descriptions and their corresponding information can be used to manufacture, create, provide, and / or produce equipment and / or integrated devices. In some specific implementations, equipment may include dies, integrated devices, multi-chip packages, integrated passive devices (IPDs), die packages, integrated circuit (IC) devices, device packages, integrated circuit (IC) packages, wafers, semiconductor devices, and / or stacked package (PoP) devices.

[0090] It should be noted that the accompanying drawings in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some instances, the drawings may not be to scale. In some instances, not all components and / or parts are shown for clarity. In some instances, the positioning, location, size, and / or shape of the various parts and / or components in the drawings may be exemplary. In some specific embodiments, the various components and / or parts in the drawings may be optional.

[0091] The term “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any specific implementation or aspect described herein as “exemplary” is not necessarily to be construed as superior to or better than other aspects of this disclosure. Similarly, the term “aspect” does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed. The term “coupling” is used herein to refer to direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically contacts object B, and object B contacts object C, objects A and C can still be considered coupled to each other, even if they are not in direct physical contact. Object A coupled to object B may be coupled to at least a portion of object B. The term “electrical coupling” may mean that two objects are directly or indirectly coupled together such that current (e.g., signal, power, ground) can flow between the two objects. Electrically coupled objects may or may not have current traveling between them. The use of the terms “first,” “second,” “third,” and “fourth” (and / or anything above the fourth) is arbitrary. Any component described can be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component can be a first component, a second component, a third component, or a fourth component. The terms “enclosing,” “enclosing,” and / or any derivative meaning can refer to an object that partially or completely encloses another object. The terms “top” and “bottom” are arbitrary. A component located at the top can be above a component located at the bottom. A top component can be considered a bottom component, and vice versa. As described in this disclosure, a first component located “above” a second component can mean that the first component is located above or below the second component, depending on how bottom or top is arbitrarily defined. In another example, a first component can be located above (e.g., above) a first surface of a second component, and a third component can be located above (e.g., below) a second surface of a second component, where the second surface is opposite to the first surface. It should also be noted that the term “above” as used in this application in the context of one component being above another component can be used to mean that a component is on and / or in another component (e.g., on the surface of a component or embedded in a component). Therefore, for example, "the first component is on top of the second component" can mean: (1) the first component is on top of the second component but does not directly contact the second component; (2) the first component is on the second component (e.g., on the surface of the second component); and / or (3) the first component is in the second component (e.g., embedded in the second component). A first component located "in" the second component can be partially or completely located in the second component. Values ​​from about X to XX can refer to values ​​between X and XX, including both X and XX. Values ​​between X and XX can be discrete or continuous. As used in this disclosure, the terms "about 'value X'" or "approximately value X" mean within 10% of "value X".For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9 to 1.1. "Multiple" components can include all possible components or only some of all possible components. For example, if a device comprises ten components, the term "multiple components" can refer to all ten components or only some of those ten components.

[0092] In some embodiments, an interconnect is an element or assembly in a device or package that allows or facilitates an electrical connection between two points, elements, and / or components. In some embodiments, an interconnect may include traces, vias, pads, pillars, metallization layers, redistribution layers, and / or under-bump metallization (UBM) layers / interconnects. In some embodiments, an interconnect may include a conductive material configured to provide an electrical path for signals (e.g., data signals), ground, and / or power. An interconnect may include more than one element or assembly. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different embodiments may use different processes and / or steps to form interconnects. In some embodiments, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spraying, and / or plating processes may be used to form interconnects.

[0093] It should also be noted that the various disclosures contained herein can be described as processes depicted as work diagrams, flowcharts, structure diagrams, or block diagrams. Although flowcharts may describe operations as sequential processes, many operations within an operation can be performed in parallel or concurrently. Furthermore, the order of operations can be rearranged. A process terminates when its operations are completed.

[0094] Further examples are described below to facilitate understanding of this disclosure.

[0095] According to Example 1, a multi-chip package includes: a first chiplet including a power amplifier (PA) circuit; a second chiplet including a low-noise amplifier (LNA) circuit; an electromagnetic interference (EMI) shield located between the first chiplet and the second chiplet; and a molding compound that at least partially encapsulates the first chiplet, the second chiplet, and the EMI shield.

[0096] Example 2 includes a multi-chip package according to Example 1, wherein the multi-chip package further includes a filter chiplet.

[0097] Example 3 includes a multi-chip package according to Example 1 or Example 2, wherein the multi-chip package further includes a switching chiplet.

[0098] Example 4 includes a multi-chip package according to any one of Examples 1 to 3, wherein the EMI shield comprises a plurality of conductive structures.

[0099] Example 5 includes a multi-chip package according to any one of Examples 1 to 3, wherein the EMI shield is a single conductive structure.

[0100] Example 6 includes a multi-chip package according to any one of Examples 1 to 5, and the multi-chip package further includes contacts configured to electrically connect the PA circuit to the transmitter chiplet.

[0101] Example 7 includes a multi-chip package according to any one of Examples 1 to 6, and the multi-chip package further includes contacts configured to electrically connect the LNA circuitry to the receiver chiplet.

[0102] Example 8 includes a multi-chip package according to any one of Examples 1 to 7, and the multi-chip package further includes one or more redistribution layers coupled to the molding compound and electrically connected to the first chiplet, the EMI shield and the second chiplet.

[0103] Example 9 includes a multi-chip package according to any one of Examples 1 to 8, wherein the first chiplet includes a first substrate having a first substrate material that is different from the second substrate material of the second chiplet.

[0104] Example 10 includes a multi-chip package according to Example 9, wherein the first substrate material comprises at least one of gallium arsenide (GaAs) or indium phosphide (InP), and the second substrate material comprises silicon (Si).

[0105] According to Example 11, a packaged integrated circuit device includes: a first chiplet including a power amplifier (PA) circuit; a second chiplet including a low-noise amplifier (LNA) circuit; a third chiplet including: radio frequency (RF) circuitry; a first contact on a first surface, wherein a first subset of the first contact is electrically connected to the first chiplet and a second subset of the first contact is electrically connected to the second chiplet; a second contact on a second surface configured to be electrically connected to an external component; and a conductor electrically connecting one or more of the first contacts to one or more of the second contacts.

[0106] Example 12 includes an integrated circuit device packaged according to Example 11, the packaged integrated circuit device further including a filter chiplet.

[0107] Example 13 includes an integrated circuit device packaged according to Example 11 or Example 12, the packaged integrated circuit device further including a switching chiplet.

[0108] Example 14 includes an integrated circuit device packaged according to any one of Examples 11 to 13, and the packaged integrated circuit device further includes an electromagnetic interference (EMI) shield between the first chiplet and the second chiplet.

[0109] Example 15 includes an integrated circuit device packaged according to Example 14, wherein the EMI shield includes a plurality of conductive structures.

[0110] Example 16 includes an integrated circuit device packaged according to Example 14, wherein the EMI shield is a single conductive structure.

[0111] Example 17 includes an integrated circuit device packaged according to any one of Examples 11 to 16, wherein one or more first contacts in the first subset of the first contacts electrically connect the PA circuit to the RF circuit.

[0112] Example 18 includes an integrated circuit device packaged according to any one of Examples 11 to 17, wherein one or more first contacts in the second subset of the first contacts electrically connect the LNA circuit to the RF circuit.

[0113] Example 19 includes an integrated circuit device packaged according to any one of Examples 11 to 18, wherein the first chiplet, the second chiplet, and the third chiplet are at least partially encapsulated in a molding compound.

[0114] Example 20 includes an integrated circuit device packaged according to any one of Examples 11 to 19, wherein the first chiplet includes a first substrate having a first substrate material that is different from the second substrate material of the second chiplet.

[0115] Example 21 includes an integrated circuit device packaged according to Example 20, wherein the first substrate material comprises gallium arsenide (GaAs) or indium phosphide (InP), and the second substrate material comprises silicon (Si).

[0116] According to Example 22, a stacked integrated circuit device includes a multi-chip package stacked with a radio frequency (RF) interposer chiplet, the multi-chip package including: a first chiplet including a first circuit; a second chiplet including a second circuit; and a molding compound that at least partially encapsulates the first chiplet and the second chiplet; and the RF interposer chiplet including: RF circuitry; and a first contact on a first surface electrically connected to the first chiplet and the second chiplet of the multi-chip package.

[0117] Example 23 includes a stacked integrated circuit device according to Example 22, wherein the multi-chip package includes an electromagnetic interference (EMI) shield between the first chiplet and the second chiplet.

[0118] Example 24 includes a stacked integrated circuit device according to Example 22 or Example 23, wherein the RF interposer chiplet includes: a second contact on a second surface configured to be electrically connected to an external package component; and a conductor electrically connecting one or more of the first contacts to one or more of the second contacts.

[0119] According to Example 25, a manufacturing method includes: attaching a first chip including power amplifier (PA) circuitry to a carrier substrate; attaching a second chip including low noise amplifier (LNA) circuitry to the carrier substrate; forming an electromagnetic interference (EMI) shield between the first chip and the second chip; and encapsulating the first chip, the second chip, and the EMI shield at least partially in a molding compound to form a multi-chip package.

[0120] Example 26 includes the method according to Example 25, the method further comprising attaching a plurality of small chips to the carrier substrate to form a reconstructed wafer.

[0121] Example 27 includes the method according to Example 25 or Example 26, wherein the plurality of chips includes a plurality of PA chips, a plurality of LNA chips, or a combination thereof.

[0122] Example 28 includes the method according to any one of Examples 25 to 27, the method further comprising: removing the carrier substrate; and, after removing the carrier substrate, separating the multi-chip package from other portions of the reconstructed wafer.

[0123] Example 29 includes the method according to any one of Examples 25 to 28, wherein forming the EMI shield includes forming a plurality of conductive structures between the first chiplet and the second chiplet.

[0124] Example 30 includes the method according to any one of Examples 25 to 29, the method further comprising attaching the multi-chip package to a third chiplet, wherein the third chiplet includes radio frequency (RF) circuitry.

[0125] Example 31 includes the method according to any one of Examples 25 to 30, wherein forming the EMI shield includes forming a single conductive structure between the first chiplet and the second chiplet.

[0126] According to Example 32, a method of manufacturing an integrated device includes: obtaining a multi-chip package, the multi-chip package including: a first chiplet including a first circuit; a second chiplet including a second circuit; and a molding compound that at least partially encapsulates the first chiplet and the second chiplet; obtaining a radio frequency (RF) interposer chiplet including RF circuitry; and electrically connecting contacts of the multi-chip package and contacts of the RF interposer chiplet to form a stacked integrated circuit device.

[0127] Example 33 includes the method according to Example 32, wherein the first circuit includes a power amplifier (PA) circuit and the second circuit includes a low noise amplifier (LNA) circuit.

[0128] Example 34 includes the method according to Example 32 or Example 33, wherein the embedded multi-chip package includes an electromagnetic interference (EMI) shield between the first chiplet and the second chiplet.

[0129] Example 35 includes a method according to any one of Examples 32 to 34, wherein the RF interposer chip includes a conductor that electrically connects the contacts of the RF interposer chip on a first surface to second contacts of the RF interposer chip on a second surface.

[0130] The various features of this disclosure described herein can be implemented in different systems without departing from this disclosure. It should be noted that the foregoing aspects of this disclosure are merely illustrative and should not be construed as limiting the scope of this disclosure. The description of aspects of this disclosure is intended to be illustrative and not to limit the scope of the appended claims. Therefore, the teachings herein are readily applicable to other types of devices, and many substitutions, modifications, and variations will be apparent to those skilled in the art.

Claims

1. A multi-chip package, the multi-chip package comprising: The first chip includes a power amplifier (PA) circuit. The second chip includes a low-noise amplifier (LNA) circuit. An electromagnetic interference (EMI) shield is located between the first chip and the second chip; and A molding compound that at least partially encapsulates the first chiplet, the second chiplet, and the EMI shield.

2. The multi-chip package according to claim 1, wherein the multi-chip package further comprises a filter chip.

3. The multi-chip package according to claim 1, wherein the multi-chip package further includes a switching chip.

4. The multi-chip package according to claim 1, wherein the EMI shield comprises a plurality of conductive structures.

5. The multi-chip package according to claim 1, wherein the EMI shield is a single conductive structure.

6. The multi-chip package of claim 1, wherein the multi-chip package further comprises contacts configured to electrically connect the PA circuit to the transmitter chiplet.

7. The multi-chip package of claim 1, wherein the multi-chip package further comprises contacts configured to electrically connect the LNA circuitry to the receiver chiplet.

8. The multi-chip package of claim 1, wherein the multi-chip package further comprises one or more redistribution layers coupled to the molding compound and electrically connected to the first chiplet, the EMI shield and the second chiplet.

9. The multi-chip package according to claim 1, wherein the first chiplet includes a first substrate having a first substrate material, the first substrate material being different from the second substrate material of the second chiplet.

10. The multi-chip package of claim 9, wherein the first substrate material comprises at least one of gallium arsenide (GaAs) or indium phosphide (InP), and the second substrate material comprises silicon (Si).

11. A packaged integrated circuit device, the packaged integrated circuit device comprising: The first chip includes a power amplifier (PA) circuit. The second chip includes a low-noise amplifier (LNA) circuit. and The third small chip, the third small chip comprising: Radio frequency (RF) circuits; A first contact on a first surface, wherein a first subset of the first contact is electrically connected to the first chiplet, and a second subset of the first contact is electrically connected to the second chiplet; A second contact on the second surface, the second contact being configured to be electrically connected to an external package component; and A conductor that electrically connects one or more first contacts of the first contacts to one or more second contacts of the second contacts.

12. The packaged integrated circuit device according to claim 11, wherein the packaged integrated circuit device further comprises a filter chip.

13. The packaged integrated circuit device according to claim 11, wherein the packaged integrated circuit device further comprises a switching chip.

14. The packaged integrated circuit device of claim 11, further comprising an electromagnetic interference (EMI) shield between the first chiplet and the second chiplet.

15. The packaged integrated circuit device of claim 14, wherein the EMI shield comprises a plurality of conductive structures.

16. The packaged integrated circuit device of claim 14, wherein the EMI shield is a single conductive structure.

17. The packaged integrated circuit device of claim 11, wherein one or more first contacts in the first subset of the first contacts electrically connect the PA circuit to the RF circuit.

18. The packaged integrated circuit device of claim 11, wherein one or more first contacts in the second subset of the first contacts electrically connect the LNA circuit to the RF circuit.

19. The packaged integrated circuit device of claim 11, wherein the first chiplet, the second chiplet, and the third chiplet are at least partially encapsulated in a molding compound.

20. The packaged integrated circuit device of claim 11, wherein the first chiplet includes a first substrate having a first substrate material, the first substrate material being different from the second substrate material of the second chiplet.

21. The packaged integrated circuit device of claim 20, wherein the first substrate material comprises at least one of gallium arsenide (GaAs) or indium phosphide (InP), and the second substrate material comprises silicon (Si).

22. A stacked integrated circuit device, the stacked integrated circuit device comprising: A multi-chip package, wherein the multi-chip package is stacked with a radio frequency (RF) interposer chiplet, the multi-chip package comprising: The first chip includes a first circuit. The second chip, the second chip including a second circuit; and A molding compound, said molding compound at least partially encapsulating the first chiplet and the second chiplet; and The RF interposer chip includes: RF circuits; and A first contact is located on a first surface and is electrically connected to the first chiplet and the second chiplet of the multi-chip package.

23. The stacked integrated circuit device of claim 22, wherein the multi-chip package includes an electromagnetic interference (EMI) shield between the first chiplet and the second chiplet.

24. The stacked integrated circuit device of claim 22, wherein the RF interposer chip comprises: A second contact on the second surface, the second contact being configured to be electrically connected to an external package component; and A conductor that electrically connects one or more first contacts of the first contacts to one or more second contacts of the second contacts.

25. A manufacturing method, the method comprising: The first small chip, including the power amplifier (PA) circuit, is attached to the carrier substrate; A second small chip, including a low-noise amplifier (LNA) circuit, is attached to the carrier substrate; An electromagnetic interference (EMI) shield is formed between the first chip and the second chip; as well as The first chip, the second chip, and the EMI shield are at least partially encapsulated in a molding compound to form a multi-chip package.

26. The method of claim 25, further comprising attaching a plurality of small chips to the carrier substrate to form a reconstructed wafer.

27. The method of claim 26, wherein the plurality of chips comprises a plurality of PA chips, a plurality of LNA chips, or a combination thereof.

28. The method of claim 25, further comprising: Remove the carrier substrate; as well as After removing the carrier substrate, the multi-chip package is separated from the rest of the reconstructed wafer.

29. The method of claim 25, wherein forming the EMI shield comprises forming a plurality of conductive structures between the first chip and the second chip.

30. The method of claim 25, further comprising attaching the multi-chip package to a third chiplet, wherein the third chiplet includes radio frequency (RF) circuitry.

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