A chip testing method, system, intelligent terminal and storage medium

Abstract

The application relates to a chip testing method and system, an intelligent terminal and a storage medium, and relates to the technical field of semiconductor testing.The application comprises the following steps: obtaining a chip model of a chip to be tested, and determining a target testing posture according to the chip model; placing the chip to be tested on a transfer station according to the target testing posture; in response to the number of chips to be tested on the transfer station reaching a preset number, taking the chips to be tested on the transfer station as a chip group to be tested; performing electrical testing and surface morphology testing on the chip group to be tested; judging whether there is a problem chip in the chip group to be tested according to the electrical testing and the surface morphology testing, wherein the problem chip refers to a chip that does not pass the electrical testing or the surface morphology testing; if there is a problem chip, the problem chip is transferred to a scrap area, and the chips in the chip group to be tested except the problem chip are transferred to a qualified product area; if there is no problem chip, the chip group to be tested is transferred to the qualified product area.The application has the effect of improving the chip testing efficiency.

Description

Technical Field

[0001] This application relates to the field of semiconductor testing technology, and in particular to a chip testing method, system, smart terminal, and storage medium. Background Technology

[0002] With the rapid development of semiconductor technology, the types and integration levels of chips are increasing daily. Chip testing, as a crucial step in ensuring product quality, directly impacts production costs and yield rates in terms of efficiency and accuracy. After chip manufacturing and packaging are completed, each chip needs to undergo electrical performance testing and appearance defect inspection to screen out defective products and ensure that the chips leaving the factory meet specifications.

[0003] In related technologies, chip testing typically follows this process: Operators first consult the corresponding test specifications based on the chip's model number, manually adjust the chip to the preset placement position, and then place them one by one into the test socket for electrical performance testing. After the electrical test is completed, the chips are transferred to a visual inspection device, where a camera captures images of the chip surface to check for defects such as scratches, dirt, or pin deformation. After inspection, operators manually classify the chips into either the qualified or unqualified areas based on the electrical test results and the visual inspection results.

[0004] Regarding the aforementioned technologies, the applicant believes that the chips are circulated between various testing stations in single-chip form, and electrical testing and appearance inspection are performed independently in different stations. During the testing process, the chips need to be picked up, transferred, and repositioned multiple times, resulting in a slow overall testing cycle and a long testing cycle for a single chip, which restricts the improvement of chip testing efficiency. Summary of the Invention

[0005] To improve chip testing efficiency, this application provides a chip testing method, system, smart terminal, and storage medium.

[0006] Firstly, this application provides a chip testing method, which adopts the following technical solution: A chip testing method, comprising: Obtain the chip model of the chip to be tested, and determine the target test posture based on the chip model; According to the target test posture, place the chip under test in the transfer station; In response to the number of chips to be inspected on the transfer station reaching a preset number, the chips to be inspected on the transfer station are regarded as a group of chips to be inspected. Electrical and surface morphology tests were performed on the chip group under test. Based on the electrical test and the surface morphology test, it is determined whether there are any problematic chips in the chip group to be tested. The problematic chip refers to the chip that fails the electrical test or the surface morphology test. If present, the problematic chip will be transferred to the scrap area, and the chips in the chip group to be inspected, excluding the problematic chip, will be transferred to the qualified product area. If not, the chip group to be inspected is transferred to the qualified product area.

[0007] By adopting the above technical solution, the target test posture is automatically determined by obtaining the chip model, and the chips are batched into a group of chips to be inspected at the transfer station. Then, dual electrical and surface morphology tests are performed, which reduces the number of times the chips are repeatedly picked up and moved, significantly improving testing efficiency. At the same time, based on the test results, problematic chips are automatically diverted to the scrap area and qualified chips are assigned to the qualified product area, realizing multi-dimensional quality inspection and automated sorting, ensuring product output quality and reducing the risk of human error.

[0008] Optionally, the chip group to be tested includes at least two sets of chip groups to be tested, each set of chip groups to be tested includes a pair of first chip to be tested and second chip to be tested, the first chip to be tested and the second chip to be tested working together; The electrical testing of the chip group under test includes: The chip group to be tested is moved to the individual unit testing equipment by the gripping device. The individual unit testing equipment includes a first individual unit testing equipment and a second individual unit testing equipment. The first individual unit testing equipment is used to perform electrical testing on the first chip to be tested, and the second individual unit testing equipment is used to perform electrical testing on the second chip to be tested. The first electrical test is performed on the first chip under test and the second chip under test using the single-unit testing equipment, and the chip that fails the first electrical test is marked as the first problem chip. The grasping device moves the chip group to be tested to the combined testing equipment. The combined testing equipment is used to perform a second electrical test on the combination of the first chip under test and the second chip under test, and the chips that fail the second electrical test are marked as the second problem chip and the third problem chip.

[0009] By adopting the above technical solution, when the chip group under test includes paired chips that work together, the first electrical test is performed on each chip individually using a single-chip testing device, and then a second electrical test is performed on the paired combination using a combined testing device. This approach verifies both the independent performance of a single chip and the performance of the paired chips working together. This step-by-step testing method can accurately identify defects in paired operation scenarios, avoiding missed detections of misalignment issues caused by relying solely on single-chip testing, and significantly improving the delivery reliability of paired chips.

[0010] Optionally, if the first problematic chip exists, then another chip in the chip group to be tested, which contains the first problematic chip, is considered as a candidate chip to be tested. Within the qualified product area, the first transmission mechanism is determined based on the location of the first problematic chip; A first qualified chip of the same type as the first problematic chip is retained on the first transmission mechanism; The grasping device moves the chip group to be inspected to the scrap area and puts the first problematic chip into the scrap area. The grasping device moves the chip group to be inspected to the qualified product area. Using the gripping device, the chips other than the candidate chips to be inspected from the chip group to be inspected are placed in the qualified product area, and the first qualified chip is gripped. The candidate chip to be tested and the first qualified chip are moved to the combined testing equipment.

[0011] By adopting the above technical solution, when a chip in a group fails the individual chip test and is marked as the first problematic chip, another normal candidate chip in the same group is automatically re-paired with the first qualified chip in the qualified product area and sent to the combined testing equipment for secondary verification. This fully utilizes existing qualified chips to salvage the undamaged paired chips, avoiding the scrapping of the entire chip group due to a single defective chip, effectively improving material utilization and yield, while automating the retesting process.

[0012] Optionally, if the second problematic chip and the third problematic chip exist, the chip group to be inspected is moved to the qualified product area by the gripping device; The group of chips to be inspected is placed in the qualified product area, such that the second problematic chip is located on the second transmission mechanism and the third problematic chip is located on the third transmission mechanism; The second transmission mechanism is controlled to move a preset length along a preset direction, so that the second problematic chip is opposite to the second qualified chip on the third transmission mechanism, and the third problematic chip is opposite to the second qualified chip on the second transmission mechanism. The grasping device grasps the second problematic chip, the second qualified chip, the third problematic chip, and the second qualified chip, and moves the grasping device to the combined testing equipment.

[0013] By adopting the above technical solution, when both chips fail the combined test, a new test pair is formed by cross-placing and picking up the second and third problematic chips with the second qualified chip on the transmission mechanism, and then re-sending them into the combined testing equipment. This method can quickly construct the comparison pair required for fault diagnosis, accurately identify the specific faulty chip, and has the potential to directly replace one of the problematic chips with a qualified chip to achieve a successful retest. This greatly reduces the probability of complete scrapping of paired chips and improves fault handling efficiency and yield.

[0014] Optionally, if the yield rate of the chips to be inspected is greater than a preset threshold, the gripping device moves the group of chips to be inspected to the qualified product area, and places the chips in the group of chips to be inspected, except for the second problematic chip and the third problematic chip, in the qualified product area. The newly added chip to be inspected is placed in the transfer station; The second problematic chip and the third problematic chip are placed in the transfer station; Adjust the position of the second problematic chip in the transfer station so that the second problematic chip is opposite to the newly added chip to be inspected; Fill the empty spaces within the transfer station; The gripping device grips the chip in the transfer station and moves it sequentially to the individual testing equipment and the combined testing equipment.

[0015] By adopting the above technical solution, when the overall yield rate of the chips under inspection is high, the second and third problematic chips that failed the combination test are returned to the transfer station, re-paired with newly added chips under inspection to fill the empty slots, and then subjected to individual and combination tests in sequence. In this way, without interrupting the normal production cycle, the faulty chips are retested and reused in a mobile manner, avoiding separate rework steps, significantly improving the flexibility of the production line and the overall testing efficiency, and is especially suitable for adaptive scheduling in scenarios with fluctuating yield rates.

[0016] Optionally, a first chip image of the chip to be inspected is acquired; If the chip under test is rectangular, then the long side and short side of the chip under test are determined based on the first chip image. Adjust the orientation of the chip under test according to the positions of the long side and the short side; Obtain a second chip image of the chip under test; Based on the second chip image, adjust the orientation of the chip under test so that the chip under test is consistent with the target test orientation; If the chip under test is square, then the orientation of the chip under test is adjusted according to the first chip image so that the chip under test is consistent with the target test orientation. The chip under test, which is in the target test posture, is placed at the transfer station.

[0017] By adopting the above technical solution, chip images are acquired, and different posture adjustment strategies are applied based on whether the chip is rectangular: for rectangular chips, initial adjustment is performed on both the long and short sides, followed by fine-tuning based on a second image; for square chips, the chip is directly adjusted to the target posture. This method ensures that chips of different shapes can be accurately placed in the transfer station with the target test posture, eliminating poor electrical contact or misjudgment of surface inspection caused by placement posture deviations, enhancing the accuracy and consistency of pre-test positioning, and improving the robustness of subsequent tests.

[0018] Optionally, a preset orientation mark on the surface of the chip under test in the second chip image is identified; Determine the deflection angle of the orientation mark relative to the reference direction; Rotate the chip under test according to the deflection angle until the orientation mark is aligned with the reference direction, so that the pin arrangement direction of the chip under test is consistent with the test interface direction of the transfer station.

[0019] By adopting the above technical solution, the identification of chip surface orientation marks and the precise alignment of deflection angles upgrade the attitude adjustment from simple geometric matching to orientation registration based on functional characteristics. This ensures that the pin arrangement direction of the chip is completely consistent with the test interface direction of the transfer station, eliminating the risk of poor electrical contact or test misjudgment caused by rotational deviation. It is especially suitable for chips with symmetrical shape but directional pins, significantly improving the accuracy of attitude adjustment and the pass rate of subsequent tests.

[0020] Secondly, this application provides a chip testing system, which adopts the following technical solution: A chip testing system, comprising: The acquisition module is used to acquire the chip model of the chip to be tested and determine the test posture based on the chip model. The transmission module is used to place the chip under test at the transfer station according to the test posture; in response to the number of chips under test on the transfer station reaching a preset number, the chips under test on the transfer station are regarded as a group of chips under test. The testing module is used to perform electrical testing and surface morphology testing on the chip group under test; based on the electrical testing and the surface morphology testing, it determines whether there are any problematic chips in the chip group under test, wherein the problematic chip refers to a chip that fails the electrical testing or the surface morphology testing; The transmission module is further configured to, if present, transfer the problematic chip to the scrap area and transfer the chips in the chip group to be inspected, excluding the problematic chip, to the qualified product area; if not present, transfer the chip group to be inspected to the qualified product area.

[0021] By adopting the above technical solution, the target test posture is automatically determined by obtaining the chip model, and the chips are batched into a group of chips to be inspected at the transfer station. Then, dual electrical and surface morphology tests are performed, which reduces the number of times the chips are repeatedly picked up and moved, significantly improving testing efficiency. At the same time, based on the test results, problematic chips are automatically diverted to the scrap area and qualified chips are assigned to the qualified product area, realizing multi-dimensional quality inspection and automated sorting, ensuring product output quality and reducing the risk of human error.

[0022] Thirdly, this application provides a smart terminal, which adopts the following technical solution: A smart terminal includes a memory and a processor, wherein the memory stores a computer program that can be loaded by the processor and executed by any of the chip testing methods described above.

[0023] Fourthly, this application provides a computer storage medium capable of storing corresponding programs, which facilitates improving chip testing efficiency, and adopts the following technical solution: A computer-readable storage medium storing a computer program that can be loaded by a processor and executed by any of the above-described chip testing methods.

[0024] In summary, this application includes at least one of the following beneficial technical effects: By automatically determining the target test posture based on the chip model, and batching the chips into a group of chips to be inspected at a transfer station, dual electrical and surface morphology tests are then performed. This reduces the number of times chips are repeatedly picked up and moved, significantly improving testing efficiency. Simultaneously, based on the test results, problematic chips are automatically diverted to the scrap area, while qualified chips are grouped into the qualified product area. This achieves multi-dimensional quality inspection and automated sorting, ensuring product output quality and reducing the risk of human error. When the chip group under test includes paired chips that work together, the first electrical test is performed on each chip individually using a single-chip testing device. Then, the second electrical test is performed on the paired combination using a combined testing device. This approach verifies both the independent performance of a single chip and the performance of the paired chips working together. This step-by-step testing method can accurately identify defects in paired operation scenarios, avoiding missed detections of failures due to relying solely on single-chip testing, and significantly improving the reliability of paired chip delivery. When a chip in a group fails the individual chip test and is marked as the first problematic chip, the system automatically re-pairs another normal candidate chip in the same group with the first qualified chip in the qualified product area and sends it to the combined testing equipment for secondary verification. This fully utilizes existing qualified chips to salvage the paired chips that are not faulty, avoiding the scrapping of the entire chipset due to a single defective chip, effectively improving material utilization and yield, while also automating the retesting process. Attached Figure Description

[0025] Figure 1 This is a schematic flowchart of a chip testing method disclosed in an embodiment of this application.

[0026] Figure 2 This is a schematic flowchart of a chip mating test method disclosed in an embodiment of this application.

[0027] Figure 3 This is a flowchart illustrating a method for replacing a faulty chip as disclosed in an embodiment of this application.

[0028] Figure 4 This is a schematic diagram of a replacement process for a problematic chip disclosed in an embodiment of this application.

[0029] Figure 5 This is a flowchart illustrating a second method for replacing a faulty chip, as disclosed in an embodiment of this application.

[0030] Figure 6 This is a schematic diagram of a replacement process for a problematic chip disclosed in an embodiment of this application.

[0031] Figure 7 This is a flowchart illustrating a third method for replacing a faulty chip, as disclosed in an embodiment of this application.

[0032] Figure 8 This is a schematic diagram of a replacement process for a problematic chip disclosed in an embodiment of this application.

[0033] Figure 9 This is a flowchart illustrating a chip attitude adjustment method disclosed in an embodiment of this application.

[0034] Figure 10This is a schematic diagram of chip posture adjustment disclosed in an embodiment of this application.

[0035] Figure 11 This is a flowchart illustrating a second chip attitude adjustment method disclosed in an embodiment of this application.

[0036] Figure 12 This is a schematic diagram of a chip testing system disclosed in an embodiment of this application. Detailed Implementation

[0037] To make the purpose, technical solution, and advantages of this application clearer, the following description is provided in conjunction with the appendix. Figure 1 To be continued Figure 12 The present application will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the application.

[0038] This application discloses a chip testing method. (Refer to...) Figure 1 The method includes: Step S101: Obtain the chip model of the chip to be tested, and determine the target test posture based on the chip model.

[0039] A chip model number is a code or string used to identify the type, specifications, and functional version of a chip. Typically, different chip models correspond to different package sizes, pin arrangements, and electrical characteristics, thus requiring different test configurations.

[0040] Optionally, the chip model can be manually entered by a technician or obtained through optical identification of the markings on the chip surface.

[0041] Different chip models have different pin positions, so when testing a chip, it is necessary to pay attention to the pin positions to ensure that the chip test is carried out normally. The target test posture refers to the posture required by the chip when testing a specific chip model.

[0042] Optionally, the target test posture may include at least one of the chip's placement orientation, rotation angle, and flip state in the test socket. The target test posture can be stored in a database in a one-to-one correspondence with the chip model and determined by a table lookup; alternatively, the target test posture can be parsed according to the chip model's naming rules.

[0043] Step S102: Place the chip to be tested in the transfer station according to the target test posture.

[0044] A transfer station is a carrier or platform used for temporary storage and batch accumulation of chips to be tested. A transfer station can have multiple placement slots or positions, and can accommodate multiple chips at the same time. The transfer station plays a role in buffering and batching in the testing process.

[0045] Step S103: In response to the number of chips to be inspected on the transfer station reaching a preset number, the chips to be inspected on the transfer station are taken as a group of chips to be inspected.

[0046] The preset quantity refers to the maximum number of chips that the transfer station can hold, which is equal to the total capacity of the transfer station. On the other hand, the preset quantity can also be set according to the parallel processing capability of the test equipment, such as matching the number of chipsets that the combined test equipment can hold at one time.

[0047] Step S104: Perform electrical and surface morphology tests on the chip group under test.

[0048] Electrical testing refers to the process of verifying the electrical performance of a chip by applying electrical signals to its pins and measuring the response. Electrical testing can include continuity testing, leakage current testing, functional testing, and parameter testing. In a specific example, the testing equipment contacts each pin of the chip with spring probes, sends a specific waveform, and measures the output level; the chip's qualification is determined based on the output level.

[0049] Surface morphology testing refers to the process of inspecting a chip's appearance for defects using optical inspection methods. Surface morphology testing can detect appearance problems such as scratches, cracks, dirt, pin deformation, and unclear printing. In a specific example, an industrial camera is used to photograph the top surface of the chip, and an edge detection algorithm is used to identify whether the pins on the chip are misaligned.

[0050] Step S105: Based on electrical testing and surface morphology testing, determine whether there are any problematic chips in the chip group to be tested. Problematic chips refer to chips that have failed electrical testing or surface morphology testing.

[0051] A defective chip is a chip that fails to meet the qualification standard in either electrical testing or surface morphology testing. Defective chips cannot be shipped as qualified products and need to be scrapped or further analyzed.

[0052] Step S106: If present, transfer the problematic chip to the scrap area and transfer all chips in the chip group to be inspected except the problematic chip to the qualified chip area.

[0053] The scrap area refers to a designated area or container used for the centralized storage and collection of chips that have failed testing.

[0054] Step S107: If not, transfer the chip group to be inspected to the qualified product area.

[0055] The qualified product area is a designated area or container for the centralized storage and collection of chips that have passed all tests. Chips in the qualified product area can proceed to the next process, such as tape packaging or shipping. Meanwhile, the scrap product area and the qualified product area are physically separated to prevent mixing.

[0056] By adopting the above technical solution, the target test posture is automatically determined by obtaining the chip model, and the chips are batched into a group of chips to be inspected at the transfer station. Then, dual electrical and surface morphology tests are performed, which reduces the number of times the chips are repeatedly picked up and moved, significantly improving testing efficiency. At the same time, based on the test results, problematic chips are automatically diverted to the scrap area and qualified chips are assigned to the qualified product area, realizing multi-dimensional quality inspection and automated sorting, ensuring product output quality and reducing the risk of human error.

[0057] In actual production, semiconductor manufacturing plants sometimes produce chips that work together, such as RF transmitter and receiver chips, or Bluetooth master control chips for the left and right earphones. In such cases, when testing the chips, it is necessary to organize the working chips in pairs during the testing phase to simulate real-world working scenarios and verify their performance in a coordinated state. Therefore, this application discloses a method for testing chip coordination. (Refer to...) Figure 2 The method includes: Step S201: The chip group to be tested is moved to the individual chip testing equipment by the gripping device. The individual chip testing equipment includes a first individual chip testing equipment and a second individual chip testing equipment. The first individual chip testing equipment is used to perform electrical tests on the first chip to be tested, and the second individual chip testing equipment is used to perform electrical tests on the second chip to be tested.

[0058] The chip group under test includes at least two sets of chips under test. Each set of chips under test includes a pair of first chips under test and second chips under test, which work together. The first chips under test and the second chips under test are complementary in function or need to work together.

[0059] A gripping device is an automated actuator capable of picking up, transporting, and releasing chips. Optionally, the gripping device can have end effectors such as vacuum suction cups, mechanical grippers, or electrostatic adsorption heads. For example, the gripping device can be a vacuum suction cup assembly mounted at the end of a multi-axis robotic arm, picking up chips by adsorbing them onto the chip surface using negative pressure. Simultaneously, the gripping device needs to have multiple suction cups to be able to grip multiple chips at once.

[0060] A single-chip test device is used to perform electrical tests on a single chip independently. It tests only one chip at a time to determine whether the chip's electrical performance is up to standard. The first and second single-chip test devices can be two independent devices or two different test channels on the same device.

[0061] Step S202: Perform a first electrical test on the first chip under test and the second chip under test respectively using a single-unit testing device, and mark the chip that fails the first electrical test as the first problem chip.

[0062] The first electrical test refers to the independent electrical performance test performed on a single chip on a single test device; the first electrical test focuses on the chip's own functions and parameters, without considering its compatibility with other chips.

[0063] The first problematic chip refers to a chip that fails the first electrical test on the individual testing equipment. The failure of the first problematic chip is related to the chip's own manufacturing or design defects and is unrelated to other chips.

[0064] Step S203: Move the chip group to be tested to the combined testing equipment using the gripping device.

[0065] Combination test equipment is used to perform electrical tests on pairs of chips in a coordinated operating state. Combination test equipment can connect two or more chips at the same time and provide communication channels or signal interaction conditions between the chips.

[0066] For example, a combined test device can have two or more test sockets with electrical connections between them, which can simulate the interconnection state of chips on a circuit board. Therefore, the combined test device can simultaneously detect whether the signal transmission between two chips is correct.

[0067] Step S204: Perform a second electrical test on the combination of the first chip under test and the second chip under test using a combined testing device, and mark the chips that fail the second electrical test as the second problem chip and the third problem chip.

[0068] The second electrical test refers to the electrical test performed on paired chips in a coordinated operating state on a combined test equipment; the second electrical test focuses on whether the interface communication, timing coordination and collaborative functions between the chips are normal.

[0069] The second problematic chip refers to one of the two chips that failed the second electrical test during the assembly test. The third problematic chip refers to the other one of the two chips that failed the second electrical test during the assembly test, in contrast to the second problematic chip.

[0070] By adopting the above technical solution, when the chip group under test includes paired chips that work together, the first electrical test is performed on each chip individually using a single-chip testing device, and then a second electrical test is performed on the paired combination using a combined testing device. This approach verifies both the independent performance of a single chip and the performance of the paired chips working together. This step-by-step testing method can accurately identify defects in paired operation scenarios, avoiding missed detections of misalignment issues caused by relying solely on single-chip testing, and significantly improving the delivery reliability of paired chips.

[0071] This application discloses a method for replacing faulty chips. (Refer to...) Figure 3 The method includes: Step S301: If a first problematic chip exists, then another chip in the chip group to be tested, where the first problematic chip is located, is considered a candidate chip to be tested.

[0072] The candidate chip under test refers to the other chip that is paired with the first problematic chip. Since the first problematic chip has been identified as a problematic chip, although the candidate chip under test has passed the individual unit test, its operational status has not been verified and it needs to be re-paired and tested.

[0073] Step S302: Within the qualified product area, determine the first transmission mechanism based on the location of the first problematic chip.

[0074] The first transmission mechanism refers to a device used to transport or position qualified chips in the qualified product area. Its position corresponds to the position of the first problematic chip, facilitating the direct acquisition of a qualified replacement chip later. For example, if the qualified product area contains two parallel narrow conveyor belts, each corresponding to one row of placement positions at a transfer station, and the first problematic chip is located in the second row of the transfer station, then the qualified product conveyor belt corresponding to the second row is identified as the first transmission mechanism.

[0075] Step S303: Retain a first qualified chip of the same type as the first problematic chip on the first transmission mechanism.

[0076] The first qualified chip refers to a qualified chip that has passed all tests and is stored in the qualified product area, and whose chip type is the same as the first problematic chip. At this time, the first qualified chip is used to replace the first problematic chip and form a new test group with the candidate chips to be tested.

[0077] Step S304: Using a gripping device, move the chip group to be inspected to the scrap area and put the first problematic chip into the scrap area.

[0078] For example, when the gripping device uses a vacuum suction cup to grip, the gripping device is moved above the scrap area; the vacuum suction cup corresponding to the first problematic chip is released to put the first problematic chip into the scrap area.

[0079] For example, please refer to Figure 4 The first problematic chip 42 is placed into the scrap area using the gripping device 41.

[0080] Step S305: Move the chip group to be inspected to the qualified product area using the gripping device.

[0081] For example, please refer to Figure 4 The chip group to be inspected is moved above the qualified product area 44 by the gripping device.

[0082] Step S306: Using the gripping device, place the chips other than the candidate chips in the chip group to be inspected into the qualified product area, and grip the first qualified chip.

[0083] For example, please refer to Figure 4 Using the gripping device 41, the chips in the chip group to be inspected, excluding the candidate chip to be inspected 43, are placed in the qualified product area 44, and the first qualified chip 45 is gripped.

[0084] Step S307: Move the candidate chip to be tested and the first qualified chip to the combined test equipment.

[0085] By adopting the above technical solution, when a chip in a group fails the individual chip test and is marked as the first problematic chip, another normal candidate chip in the same group is automatically re-paired with the first qualified chip in the qualified product area and sent to the combined testing equipment for secondary verification. This fully utilizes existing qualified chips to salvage the undamaged paired chips, avoiding the scrapping of the entire chip group due to a single defective chip, effectively improving material utilization and yield, while automating the retesting process.

[0086] This application discloses a second method for replacing faulty chips. (Refer to...) Figure 5 The method includes: Step S501: If there are second and third problematic chips, the chip group to be inspected is moved to the qualified product area by the gripping device.

[0087] If the assembled chips fail the assembly test, it is necessary to distinguish whether the fault is due to a problem with the chip itself or a compatibility issue with the original pairing. This embodiment uses cross-pairing testing to determine whether the problematic chip can pass the test when paired with another qualified chip, thus distinguishing between them.

[0088] Step S502: Place the chip group to be inspected in the qualified product area, so that the second problematic chip is located on the second transmission mechanism and the third problematic chip is located on the third transmission mechanism.

[0089] Both the second and third transmission mechanisms are conveying or positioning devices within the qualified product area, and they are adjacent to each other. Furthermore, the second and third transmission mechanisms are physically independent and can be controlled to move independently.

[0090] For example, please refer to Figure 6 The chips to be inspected are placed in the qualified product area, so that the second problematic chip 61 is located on the second transmission mechanism and the third problematic chip 62 is located on the third transmission mechanism.

[0091] Step S503: Control the second transmission mechanism to move a preset length along a preset direction, so that the second problematic chip is opposite to the second qualified chip on the third transmission mechanism, and the third problematic chip is opposite to the second qualified chip on the second transmission mechanism.

[0092] The preset direction and preset length can be set by technicians according to the chip model.

[0093] For example, please refer to Figure 6 The second transmission mechanism is controlled to move a preset length along a preset direction, so that the second problematic chip 61 is opposite to the second qualified chip 63 on the third transmission mechanism, and the third problematic chip 62 is opposite to the second qualified chip 64 on the second transmission mechanism.

[0094] Step S504: Using the gripping device, grip the second problematic chip, the second qualified chip, the third problematic chip, and the second qualified chip, and move the gripping device to the combined testing equipment.

[0095] The grasping device picks up two new sets of cross-paired chips at a time. One set consists of a second problematic chip and a second qualified chip from a third transmission mechanism, while the other set consists of a third problematic chip and a second qualified chip from a second transmission mechanism. Both sets are then sent to the combined testing equipment for testing.

[0096] By adopting the above technical solution, when both chips fail the combined test, a new test pair is formed by cross-placing and picking up the second and third problematic chips with the second qualified chip on the transmission mechanism, and then re-sending them into the combined testing equipment. This method can quickly construct the comparison pair required for fault diagnosis, accurately identify the specific faulty chip, and has the potential to directly replace one of the problematic chips with a qualified chip to achieve a successful retest. This greatly reduces the probability of complete scrapping of paired chips and improves fault handling efficiency and yield.

[0097] This application discloses a third method for replacing faulty chips. (Refer to...) Figure 7 The method includes: Step S701: If the yield rate of the chips to be inspected is greater than the preset threshold, the chip group to be inspected is moved to the qualified product area by the gripping device, and the chips in the chip group to be inspected, except for the second and third problematic chips, are placed in the qualified product area.

[0098] Yield rate refers to the proportion of qualified chips that pass all tests in a batch or group of chips to be inspected, out of the total number of chips in that batch or group. The preset threshold is a pre-set empirical value that needs to be sufficiently high; for example, a preset threshold of 98%.

[0099] For example, when the gripping device uses a vacuum suction cup to grip, the gripping device is moved to the qualified product area; the vacuum suction cups corresponding to the chips other than the second and third problematic chips are used to keep these chips in the qualified product area. At the same time, the vacuum suction cups corresponding to the second and third problematic chips are not released, but continue to move with the gripping device.

[0100] Step S702: Place the newly added chip to be tested in the transfer station.

[0101] The newly added chip to be tested refers to the chip that is taken out from the material to be tested and placed in the transfer station. It is used to fill the empty space in the transfer station caused by the removal of the problematic chip, and to re-form a test pair with the problematic chip. The newly added chip to be tested is the same model as the second or third problematic chip.

[0102] For example, please refer to Figure 8 The newly added chip to be inspected, 81, is placed in the transfer station.

[0103] Step S703: Place the second and third problematic chips in the transfer station.

[0104] For example, please refer to Figure 8 The second problem chip 82 and the third problem chip 83 are placed in the transfer station.

[0105] Step S704: Adjust the position of the second problematic chip in the transfer station so that the second problematic chip is opposite to the newly added chip to be inspected.

[0106] For example, please refer to Figure 8 Adjust the position of the second problematic chip 82 in the transfer station so that the second problematic chip 82 is opposite to the newly added chip to be inspected 81.

[0107] Step S705: Fill the empty spaces in the transfer station.

[0108] For example, please refer to Figure 8 The system controls the chips under test to continue entering the transfer station to fill the empty slots in the transfer station.

[0109] Step S706: Using the gripping device, grab the chip in the transfer station and move it sequentially to the individual test equipment and the combined test equipment.

[0110] By adopting the above technical solution, when the overall yield rate of the chips under inspection is high, the second and third problematic chips that failed the combination test are returned to the transfer station, re-paired with newly added chips under inspection to fill the empty slots, and then subjected to individual and combination tests in sequence. In this way, without interrupting the normal production cycle, the faulty chips are retested and reused in a mobile manner, avoiding separate rework steps, significantly improving the flexibility of the production line and the overall testing efficiency, and is especially suitable for adaptive scheduling in scenarios with fluctuating yield rates.

[0111] This application discloses a chip attitude adjustment method. (Refer to...) Figure 9 The method includes: Step S901: Obtain the first chip image of the chip to be inspected.

[0112] The first chip image refers to the chip appearance image acquired by an image acquisition device before the chip posture is adjusted.

[0113] For example, if the chip to be inspected moves along the conveyor belt and enters the transfer station, an industrial camera is used to capture the chip image during the movement of the chip along the conveyor belt to obtain the first chip image.

[0114] Step S902: If the chip to be tested is rectangular, then determine the long side and short side of the chip to be tested based on the first chip image.

[0115] Optionally, edge detection is performed on the first chip image to obtain the outer contour edge of the chip to be inspected; the shape of the chip to be inspected is determined based on the outer contour edge.

[0116] Step S903: Adjust the orientation of the chip under test according to the positions of the long and short sides.

[0117] For example, please refer to Figure 10 According to the orientation of the chip under test 1001, the long side of the chip under test 1001 is controlled to be parallel to the side of the conveyor belt 1002.

[0118] Step S904: Obtain the second chip image of the chip to be inspected.

[0119] The second chip image refers to the chip image acquired again by an image acquisition device after the initial orientation adjustment. For example, after the chip is initially rotated, the same camera is used to capture another image of the chip as the second chip image.

[0120] Step S905: Adjust the orientation of the chip under test according to the second chip image so that the chip under test is consistent with the target test orientation.

[0121] For example, please refer to Figure 10 A circular marker is set on the chip under test 1001, and the orientation of the chip under test is adjusted according to the position of the marker.

[0122] Step S906: If the chip under test is square, adjust the orientation of the chip under test according to the first chip image so that the chip under test is consistent with the target test orientation.

[0123] For square chips, since all sides are of equal length, the orientation cannot be distinguished by the side length. Therefore, other directional features of the chip surface are directly extracted from the first chip image for a one-time orientation adjustment.

[0124] Step S907: Place the chip under test in the target test posture at the transfer station.

[0125] Optionally, the chip under test, which is in the target test posture, moves to the transfer station along the conveyor belt.

[0126] By adopting the above technical solution, chip images are acquired, and different posture adjustment strategies are applied based on whether the chip is rectangular: for rectangular chips, initial adjustment is performed on both the long and short sides, followed by fine-tuning based on a second image. For square chips, the chip is directly adjusted to the target posture. This method ensures that chips of different shapes can be accurately placed in the transfer station with the target test posture, eliminating poor electrical contact or misjudgment of surface inspection caused by placement posture deviations. This enhances the accuracy and consistency of pre-test positioning and improves the robustness of subsequent tests.

[0127] This application discloses a second method for chip attitude adjustment. (Refer to...) Figure 11 The method includes: Step S1101: Identify the preset orientation marks on the surface of the chip to be inspected in the second chip image.

[0128] Orientation marks are specific graphics or symbols pre-made on the surface of a chip to indicate the orientation of the chip or the position of its pins. Optionally, orientation marks can be any of the following: laser-engraved dots, triangles, notches, or silkscreened identifiers.

[0129] Step S1102: Determine the deflection angle of the orientation mark relative to the reference direction.

[0130] The reference direction refers to the predefined reference direction in the image coordinate system or the transfer station coordinate system.

[0131] The deflection angle refers to the angle between the current direction of the orientation mark on the chip surface and the reference direction; the magnitude and direction of the deflection angle determine how much the chip needs to be rotated to align its orientation mark with the reference direction.

[0132] Optionally, the geometric center of the oriented marker contour and the chip center can be calculated using an image processing algorithm, and the angle between the line and the reference direction can be measured.

[0133] Step S1103: Rotate the chip under test according to the deflection angle until the orientation mark is aligned with the reference direction, so that the pin arrangement direction of the chip under test is consistent with the test interface direction of the transfer station.

[0134] The test interface orientation refers to the spatial orientation of the test socket, probe, or connector used to contact or connect with the chip pins at the transfer station. The pin arrangement orientation refers to the spatial distribution direction of each pin of the chip around or at the bottom of the package.

[0135] By adopting the above technical solution, the identification of chip surface orientation marks and the precise alignment of deflection angles upgrade the attitude adjustment from simple geometric matching to orientation registration based on functional characteristics. This ensures that the pin arrangement direction of the chip is completely consistent with the test interface direction of the transfer station, eliminating the risk of poor electrical contact or test misjudgment caused by rotational deviation. It is especially suitable for chips with symmetrical shape but directional pins, significantly improving the accuracy of attitude adjustment and the pass rate of subsequent tests.

[0136] Based on the same inventive concept, embodiments of the present invention provide a chip testing system, please refer to... Figure 12 The system includes: The acquisition module 1201 is used to acquire the chip model of the chip to be tested and determine the test posture based on the chip model. The transmission module 1202 is used to place the chip under test at the transfer station according to the test posture; in response to the number of chips under test at the transfer station reaching a preset number, the chips under test at the transfer station are regarded as a group of chips under test. Test module 1203 is used to perform electrical and surface morphology tests on the chip group under test; based on the electrical and surface morphology tests, it is determined whether there are any problematic chips in the chip group under test. Problematic chips refer to chips that have failed the electrical or surface morphology tests. The transmission module 1202 is also used to transfer the problematic chip to the scrap area and transfer the chips in the chip group to be inspected, excluding the problematic chip, to the qualified chip area if the problematic chip exists; otherwise, it transfers the chip group to be inspected to the qualified chip area.

[0137] By adopting the above technical solution, the target test posture is automatically determined by obtaining the chip model, and the chips are batched into a group of chips to be inspected at the transfer station. Then, dual electrical and surface morphology tests are performed, which reduces the number of times the chips are repeatedly picked up and moved, significantly improving testing efficiency. At the same time, based on the test results, problematic chips are automatically diverted to the scrap area and qualified chips are assigned to the qualified product area, realizing multi-dimensional quality inspection and automated sorting, ensuring product output quality and reducing the risk of human error.

[0138] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional modules is used as an example. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. The specific working process of the system, device, and unit described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0139] This invention provides a computer-readable storage medium storing a computer program that can be loaded by a processor and executed as a chip testing method.

[0140] Computer storage media include, for example, USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, optical disks, and other media that can store program code.

[0141] Based on the same inventive concept, embodiments of the present invention provide a smart terminal, including a memory and a processor, wherein the memory stores a computer program that can be loaded by the processor and executed as a chip testing method.

[0142] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional modules is used as an example. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. The specific working process of the system, device, and unit described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0143] The above are all preferred embodiments of this application and are not intended to limit the scope of protection of this application. Any feature disclosed in this specification (including the abstract and drawings) may be replaced by other equivalent or similar features unless specifically stated otherwise. That is, unless specifically stated otherwise, each feature is only one example of a series of equivalent or similar features.

Claims

1. A chip testing method, characterized in that, include: Obtain the chip model of the chip to be tested, and determine the target test posture based on the chip model; According to the target test posture, place the chip under test in the transfer station; In response to the number of chips to be inspected on the transfer station reaching a preset number, the chips to be inspected on the transfer station are regarded as a group of chips to be inspected. Electrical and surface morphology tests were performed on the chip group under test. Based on the electrical test and the surface morphology test, it is determined whether there are any problematic chips in the chip group to be tested. The problematic chip refers to the chip that fails the electrical test or the surface morphology test. If present, the problematic chip will be transferred to the scrap area, and the chips in the chip group to be inspected, excluding the problematic chip, will be transferred to the qualified product area. If not, the chip group to be inspected is transferred to the qualified product area.

2. The chip testing method according to claim 1, characterized in that, The chip group to be tested includes at least two groups of chips to be tested, and each group of chips to be tested includes a pair of first chips to be tested and second chips to be tested, and the first chips to be tested and the second chips to be tested work together. The electrical testing of the chip group under test includes: The chip group to be tested is moved to the individual unit testing equipment by the gripping device. The individual unit testing equipment includes a first individual unit testing equipment and a second individual unit testing equipment. The first individual unit testing equipment is used to perform electrical testing on the first chip to be tested, and the second individual unit testing equipment is used to perform electrical testing on the second chip to be tested. The first electrical test is performed on the first chip under test and the second chip under test using the single-unit testing equipment, and the chip that fails the first electrical test is marked as the first problem chip. The grasping device moves the chip group to be tested to the combined testing equipment. The combined testing equipment is used to perform a second electrical test on the combination of the first chip under test and the second chip under test, and the chips that fail the second electrical test are marked as the second problem chip and the third problem chip.

3. The chip testing method according to claim 2, characterized in that, The method further includes: If the first problematic chip exists, then another chip in the chip group to be tested, which contains the first problematic chip, will be considered as a candidate chip to be tested. Within the qualified product area, the first transmission mechanism is determined based on the location of the first problematic chip; A first qualified chip of the same type as the first problematic chip is retained on the first transmission mechanism; The grasping device moves the chip group to be inspected to the scrap area and puts the first problematic chip into the scrap area. The grasping device moves the chip group to be inspected to the qualified product area. Using the gripping device, the chips other than the candidate chips to be inspected from the chip group to be inspected are placed in the qualified product area, and the first qualified chip is gripped. The candidate chip to be tested and the first qualified chip are moved to the combined testing equipment.

4. The chip testing method according to claim 2, characterized in that, The method further includes: If the second and third problematic chips exist, the group of chips to be inspected is moved to the qualified product area by the gripping device. The group of chips to be inspected is placed in the qualified product area, such that the second problematic chip is located on the second transmission mechanism and the third problematic chip is located on the third transmission mechanism; The second transmission mechanism is controlled to move a preset length along a preset direction, so that the second problematic chip is opposite to the second qualified chip on the third transmission mechanism, and the third problematic chip is opposite to the second qualified chip on the second transmission mechanism. The grasping device grasps the second problematic chip, the second qualified chip, the third problematic chip, and the second qualified chip, and moves the grasping device to the combined testing equipment.

5. The chip testing method according to claim 4, characterized in that, The method further includes: If the yield rate of the chips to be inspected is greater than a preset threshold, the grasping device moves the group of chips to be inspected to the qualified product area, and places the chips in the group of chips to be inspected, except for the second problematic chip and the third problematic chip, in the qualified product area. The newly added chip to be inspected is placed in the transfer station; The second problematic chip and the third problematic chip are placed in the transfer station; Adjust the position of the second problematic chip in the transfer station so that the second problematic chip is opposite to the newly added chip to be inspected; Fill the empty spaces within the transfer station; The gripping device grips the chip in the transfer station and moves it sequentially to the individual testing equipment and the combined testing equipment.

6. The chip testing method according to claim 1, characterized in that, The step of placing the chip under test in the transfer station according to the target test posture includes: Obtain the first chip image of the chip to be inspected; If the chip under test is rectangular, then the long side and short side of the chip under test are determined based on the first chip image. Adjust the orientation of the chip under test according to the positions of the long side and the short side; Obtain a second chip image of the chip under test; Based on the second chip image, adjust the orientation of the chip under test so that the chip under test is consistent with the target test orientation; If the chip under test is square, then the orientation of the chip under test is adjusted according to the first chip image so that the chip under test is consistent with the target test orientation. The chip under test, which is in the target test posture, is placed at the transfer station.

7. The chip testing method according to claim 6, characterized in that, The step of adjusting the orientation of the chip under test according to the second chip image to make the chip under test consistent with the target test orientation includes: Identify the preset orientation marks on the surface of the chip under test in the second chip image; Determine the deflection angle of the orientation mark relative to the reference direction; Rotate the chip under test according to the deflection angle until the orientation mark is aligned with the reference direction, so that the pin arrangement direction of the chip under test is consistent with the test interface direction of the transfer station.

8. A chip testing system, characterized in that, The system is used to perform the chip testing method as described in any one of claims 1 to 7, including: The acquisition module is used to acquire the chip model of the chip to be tested and determine the test posture based on the chip model. The transmission module is used to place the chip under test at the transfer station according to the test posture; in response to the number of chips under test on the transfer station reaching a preset number, the chips under test on the transfer station are regarded as a group of chips under test. The testing module is used to perform electrical testing and surface morphology testing on the chip group under test; based on the electrical testing and the surface morphology testing, it determines whether there are any problematic chips in the chip group under test, wherein the problematic chip refers to a chip that fails the electrical testing or the surface morphology testing; The transmission module is further configured to, if present, transfer the problematic chip to the scrap area and transfer the chips in the chip group to be inspected, excluding the problematic chip, to the qualified product area; if not present, transfer the chip group to be inspected to the qualified product area.

9. A smart terminal, characterized in that, It includes a memory and a processor, wherein the memory stores a computer program that can be loaded by the processor and executed as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer program is stored that can be loaded by a processor and executed as described in any one of claims 1 to 7.

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