A miniature MEMS inertial measurement module and its manufacturing and calibration method

Abstract

The application belongs to the technical field of micro-electro-mechanical system (MEMS) inertial sensor packaging and calibration, and particularly relates to a micro MEMS inertial measurement module and a manufacturing and calibration method thereof, which comprises a substrate, an upper surface of the substrate is provided with an electrical connection part, and a bottom of the substrate is provided with an external terminal; a MEMS inertial sensor chip assembly, which at least comprises a three-axis accelerometer and a three-axis gyroscope; and a first fixing layer, which is arranged between the MEMS inertial sensor chip assembly and the substrate, cooperatively defines a bottom fixing interface area with a bottom surface of the MEMS inertial sensor chip assembly and an upper surface of the substrate, is used for fixing the MEMS inertial sensor chip assembly to the substrate, and rigidly transmits a motion load from the substrate to the MEMS inertial sensor chip assembly through the bottom fixing interface area. The application adopts a double-path separation packaging structure, effectively reduces packaging thermal stress error, and realizes error physical source tracing and batch maintenance by combining post-packaging layered parameter solving and external UID management of parameters.

Description

Technical Field

[0001] This invention belongs to the field of MEMS inertial sensor packaging and calibration technology, specifically relating to a micro MEMS inertial measurement module and its manufacturing and calibration method. Background Technology

[0002] MEMS inertial sensors, especially six-axis inertial measurement units that integrate both a three-axis accelerometer and a three-axis gyroscope, are highly sensitive to external mechanical stress, packaging thermal stress, and mounting stress. For micro-modules, the small chip size, high structural flexibility, and coupling between sensitive axes mean that thermomechanical loads from the substrate, die-bonding layer, cap, peripheral sealing layer, and the reflow soldering process can all alter the equivalent boundary conditions of the resonant structure, mass block, or detection circuit, thereby causing changes in systematic errors such as zero bias, scaling factor, non-orthogonality error, cross-axis coupling error, and thermal hysteresis error.

[0003] Existing packaging solutions typically focus on reducing overall stress levels. This can be achieved through methods such as placing buffer materials around the chip, absorbing external forces by encapsulating it with low-modulus materials, adjusting the bottom die-bonding contact area, employing multi-layer buffer structures, or implementing localized stress isolation measures at the chip level. However, these solutions often only optimize from the perspective of "reducing the absolute value of stress" or "increasing the number of buffer layers," failing to address the physical paths of stress sources and to functionally separate and geometrically isolate stresses from different sources. This is particularly crucial in micro-IMU (Inertial Measurement Unit) modules, where the actual motion load from the substrate needs to be transmitted to the chip as accurately as possible to ensure the correspondence between inertial input and electrical output. Meanwhile, packaging stresses from the cover, peripheral sealing layers, and thermal expansion mismatch within the packaging cavity should be dissipated or passivated as much as possible without interfering with this actual motion transmission. If the bottom fixed interface simultaneously performs both "motion load transmission" and "packaging thermomechanical stress coupling," these two paths overlap spatially. Subsequent error changes will include both substrate input effects and packaging-induced effects, making structural separation difficult.

[0004] Furthermore, some existing solutions cover the entire top, sidewalls, or even the adjacent area to the bottom of the chip with low-modulus material. While this may reduce local stress peaks to some extent, because the low-modulus material participates in force transmission in multiple directions simultaneously, it often forms a complete encapsulation or parallel coupling structure within the package cavity. It remains difficult to clearly distinguish which transmissions are genuine motion loads beneficial for inertial measurement and which couplings are adverse packaging stresses caused by mismatches in the cover, sealing layer, or CTE (coefficient of thermal expansion). Some solutions reduce bottom stress by reducing the contact area of ​​the bottom die-bonding region or introducing release patterns. However, these solutions may simultaneously weaken the rigid transmission of substrate motion loads to the chip, which is detrimental to maintaining the authenticity of input transmission under vibration, shock, or high-speed dynamic attitude change conditions.

[0005] Some solutions attempt to reduce packaging stress transmitted to the chip by making the sealing structure itself more compliant, such as using elastic sealing frames, flexible cover edges, or introducing local flexible regions in the sealing layer. However, these "sealing layer / cover body compliance" solutions modify the mechanical properties of the sealing structure itself. Their main purpose is to reduce the overall stress level at the sealing interface, rather than establishing an independent flexible dissipation path within the packaging cavity that does not intersect with the bottom rigid motion load transmission path. Therefore, while these solutions may reduce overall stress to some extent, they are not equivalent to the technical solution pursued by this invention: "setting a second stress dissipation component structurally independent of the sealing layer and cover within the packaging cavity to spatially separate the motion load path from the packaging stress path."

[0006] Besides structural issues, existing calibration processes often have significant limitations. First, many products undergo calibration only once at the bare die stage or before chip-level packaging, and the calibration parameters are directly used as the module's factory parameters. This approach cannot cover the systematic errors introduced during die bonding, bonding, capping, secondary filling, curing, thermal aging, and reflow soldering. Therefore, the error state of each module after actual packaging and assembly may deviate from the chip-level calibration results. Second, while some solutions perform a comprehensive calibration again after packaging, they typically treat the obtained parameters as a single absolute compensation parameter table, failing to distinguish the physical source differences between "intrinsic bare die errors" and "packaging-induced incremental errors," and also failing to further identify the subsequent level of "errors added after surface mount assembly."

[0007] Therefore, at least two long-standing technical issues remain unresolved in the existing technology. First, the stress path aliasing problem: the motion load transmission path on the substrate side and the packaging stress coupling path on the cover / sealing layer side overlap within the packaging space. This makes it difficult to clearly distinguish between the actual motion input and the unfavorable packaging stress, even with low-stress materials or multi-layer buffer structures. Second, the inability to trace individual errors after packaging: chip-level calibration parameters cannot cover new errors added after packaging. Storing and recalling post-packaging parameters as a single parameter set makes it impossible to identify which errors originate from the chip itself, which from the packaging stack, and which from board-level mounting. This hinders parameter updates, failure tracing, secondary corrections after board-level reassembly, and aging compensation during subsequent service life.

[0008] Therefore, there is an urgent need to propose a new packaging structure for micro MEMS inertial measurement modules and its manufacturing and calibration methods, so that the transmission of motion loads from the substrate and the dissipation of packaging stress from the cover / peripheral sealing layer can be clearly separated geometrically, and the errors after packaging and mounting can be solved and managed in layers according to their physical sources, thereby improving the consistency and traceability of the module under full temperature range, dynamic operating conditions and mass production conditions. Summary of the Invention

[0009] The purpose of this invention is to provide a micro MEMS inertial measurement module and its manufacturing and calibration method, which can effectively reduce packaging thermal stress error through a dual-path separation packaging structure; and achieve error physical source tracing and batch maintenance by combining post-packaging layered parameter solving and external parameter UID management.

[0010] The specific technical solution adopted by this invention is as follows: A miniature MEMS inertial measurement module and its manufacturing and calibration method are disclosed, comprising a substrate having an electrical connection portion on its upper surface and an external terminal for connection to an external circuit board at its bottom. MEMS inertial sensor chip assembly, including at least a three-axis accelerometer and a three-axis gyroscope; A first fixing layer is disposed between the MEMS inertial sensor chip assembly and the substrate, and together with the bottom surface of the MEMS inertial sensor chip assembly and the upper surface of the substrate, defines a bottom fixing interface area. The first fixing layer is used to fix the MEMS inertial sensor chip assembly to the substrate and rigidly transmit the motion load from the substrate to the MEMS inertial sensor chip assembly through the bottom fixing interface area. An electrical interconnect structure is provided for electrically connecting the MEMS inertial sensor chip assembly to the electrical connection portion; A peripheral sealing layer is disposed on the substrate and located around the MEMS inertial sensor chip assembly and the electrical interconnection structure; A cover body, wherein the cover body is formed by the peripheral sealing layer and the substrate to create an encapsulation cavity; A second stress dissipation component is disposed within the encapsulation cavity. The second stress dissipation component is an independent component within the encapsulation cavity and is structurally distinct from the peripheral sealing layer and the cover. It is used to dissipate the encapsulation stress introduced by the cover and / or the peripheral sealing layer. Wherein, the overall planar projection of the second stress dissipation member is located within the area enclosed by the peripheral sealing layer and does not enter the bottom fixing interface area; the second stress dissipation member is located on the top side and / or near the peripheral sub-area of ​​the peripheral sealing layer within the encapsulation cavity, and its extension along the corresponding chip sidewall in the MEMS inertial sensor chip assembly terminates above the bottom fixing interface area, thereby not forming a continuous stress transmission body with the bottom fixing interface area; thereby spatially separating the rigid path of the motion load from the substrate transmitted to the MEMS inertial sensor chip assembly through the first fixing layer from the flexible path of the encapsulation stress from the cover and / or the peripheral sealing layer coupled to the MEMS inertial sensor chip assembly through the second stress dissipation member.

[0011] In a preferred embodiment, the ratio of the Young's modulus and / or storage modulus of the first fixing layer at a reference temperature to the Young's modulus and / or storage modulus of the second stress dissipation member at the same reference temperature is not less than 100:1, wherein the reference temperature is any temperature between 20°C and 30°C.

[0012] In a preferred embodiment, the first fixing layer is a cured layer of an epoxy-based adhesive material, and the second stress dissipation component is a cured layer of a silicone-based, ketone-based, or other elastomer-filled material.

[0013] In a preferred embodiment, the second stress dissipation member includes a continuous layer located between the inner surface of the cover body and the top surface of at least one chip in the MEMS inertial sensor chip assembly and / or the electrical interconnect structure, the continuous layer at least covering the top surface of the at least one chip and at least partially covering the arc of the electrical interconnect structure.

[0014] In a preferred embodiment, the second stress dissipation component includes a plurality of island-shaped sub-components and / or lattice support sub-components that are locally spaced within the area enclosed by the peripheral sealing layer.

[0015] In a preferred embodiment, the extension of the second stress dissipation member along the corresponding chip sidewall of the MEMS inertial sensor chip assembly terminates before reaching the bottom fixing interface region, and does not form a continuous stress transfer body with the bottom fixing interface region through sidewall protrusion, capillary climbing residue, post-curing shrinkage bridging, or partial skirt coverage; a continuous free buffer gap, not filled with solid or colloidal material, is maintained between the termination boundary of the second stress dissipation member along the chip sidewall and the bottom fixing interface region, and between the lower boundary of the second stress dissipation member and the upper surface of the substrate, to reduce the shear pull exerted by the second stress dissipation member on the bottom fixing interface region and / or the bonding root of the electrical interconnect structure during high and low temperature cycling.

[0016] In a preferred embodiment, the second stress dissipation member has a local thickness greater than and / or a local modulus lower in the peripheral sub-region near the peripheral sealing layer than in the central sub-region above the corresponding central region of the MEMS inertial sensor chip assembly, so that the encapsulation stress introduced by the cover and / or the peripheral sealing layer is preferentially dissipated in the peripheral sub-region.

[0017] In a preferred embodiment, the first fixing layer has a Young's modulus of 1 GPa to 10 GPa at 25°C, and the second stress dissipation component has a Young's modulus of 0.001 MPa to 10 MPa at 25°C.

[0018] A method for manufacturing and calibrating a miniature MEMS inertial measurement module, characterized by the following steps: Applied to a miniature MEMS inertial measurement module. Step 1: Calibrate the MEMS inertial sensor chip assembly during the bare chip stage and / or the pre-packaging stage to obtain the intrinsic parameter block P_die; Step 2: Fix the MEMS inertial sensor chip assembly to the substrate through the first fixing layer, and form an electrical interconnection structure between the MEMS inertial sensor chip assembly and the substrate; Step 3: The cover and the substrate are enclosed by the peripheral sealing layer to form an encapsulation cavity, and a second stress dissipation component is provided in the encapsulation cavity. The second stress dissipation component is an independent component in the encapsulation cavity, which is structurally different from the peripheral sealing layer and the cover. It is used to dissipate the encapsulation stress introduced by the cover and / or the peripheral sealing layer. The second stress dissipation component is located on the top side and / or near the peripheral sub-region of the peripheral sealing layer in the encapsulation cavity, and is implemented by at least one of the following: continuous layer, local island layer, lattice support layer or partitioned composite layer. The second stress dissipation component does not enter the bottom fixing interface area enclosed by the bottom surface of the MEMS inertial sensor chip assembly, the upper surface of the substrate and the first fixing layer, and its extension along the chip sidewall terminates before reaching the bottom fixing interface area. It does not form a continuous stress transfer body with the bottom fixing interface area by extending down along the sidewall, capillary climbing residue, post-curing shrinkage bridging or local skirt coverage. Step 4: After the first fixing layer, the peripheral sealing layer and the second stress dissipation component have all been cured, the packaged module is subjected to thermal aging and / or stress stabilization treatment. Step 5: After the encapsulation response stabilizes, perform overall calibration on the module to obtain the original inertial output data after encapsulation. Step 6: Based on the difference between the intrinsic parameter block P_die and the original inertial output data after packaging, solve for the packaging-induced error increment parameter block ΔP_pkg, which is expressed in increment form relative to the intrinsic parameter block P_die. Step 7: After the module is mounted to the external circuit board and undergoes reflow soldering, while keeping the intrinsic parameter block P_die and the package-induced error increment parameter block ΔP_pkg unchanged, solve for the board-level mounting error increment parameter block ΔP_brd; Step 8: On the host side and / or in the processing entity used to perform error compensation, the intrinsic parameter block P_die, the package-induced error increment parameter block ΔP_pkg, and the board-level mounting error increment parameter block ΔP_brd are used as parameter blocks that are independently generated according to their physical source, each carrying a source identifier, version identifier, and scope identifier, and can be independently updated. After performing at least one compatibility check and / or conflict arbitration, they are combined for error compensation of the raw inertial data output by the module.

[0019] This invention also provides a method for manufacturing and calibrating a micro MEMS inertial measurement module. The stable packaging response in step five means that at least one of the following criteria is met: the rate of change of zero bias drift is lower than a preset threshold, the rate of change of stress surrogate characteristics is lower than a preset threshold, the change of calibration residual before and after temperature cycling is lower than a preset threshold, a preset thermal aging time is reached, which can be determined by previous process verification, sampling calibration or historical batch stability data, the change of Allan variance bias instability estimation under zero input conditions is lower than a preset threshold, or the difference in power spectral density of the stress surrogate characteristics between adjacent observation windows is lower than a preset threshold.

[0020] The present invention also provides a method for manufacturing and calibrating a micro MEMS inertial measurement module. The overall calibration in step five is performed within a preset temperature range of -40℃ to +125℃ and is completed on a multi-axis turntable and / or a multi-degree-of-freedom excitation device.

[0021] The present invention also provides a method for manufacturing and calibrating a micro MEMS inertial measurement module. The thermal aging and / or stress stabilization treatment in step four includes baking, heat preservation and / or temperature cycling of the module under preset temperature range and preset time conditions to accelerate the curing shrinkage, stress relaxation and creep of the encapsulation material to a steady state.

[0022] The present invention also provides a method for manufacturing and calibrating a micro MEMS inertial measurement module, wherein the packaged induced error increment parameter block ΔP_pkg includes at least one of zero bias increment, scaling factor increment, non-orthogonal error increment, cross-axis coupling increment, and thermal hysteresis error increment.

[0023] The present invention also provides a method for manufacturing and calibrating a micro MEMS inertial measurement module. In the embodiment of solving by physical source, the package-induced error increment parameter block ΔP_pkg is not constructed as an absolute calibration coefficient table that can be used independently of the intrinsic parameter block P_die.

[0024] The present invention also provides a method for manufacturing and calibrating a micro MEMS inertial measurement module, which further includes obtaining an aging error increment parameter block ΔP_age based on the difference between historical output and reference state during the service phase, and using the aging error increment parameter block ΔP_age as a parameter block independently generated according to physical source in combination with the intrinsic parameter block P_die, the package-induced error increment parameter block ΔP_pkg, and the board-level mounting error increment parameter block ΔP_brd.

[0025] The present invention also provides a method for manufacturing and calibrating a micro MEMS inertial measurement module, wherein the compatibility verification is performed on at least one of the following: installation description, applicable temperature range, applicable shaft group, version relationship, and generation time point; and the conflict arbitration, when it is found that a parameter block is only valid for some shafts, some temperature ranges, or some installation descriptions, restricts the parameter block to only act on the corresponding subspace and does not cover parameter blocks from other sources.

[0026] The present invention also provides a method for manufacturing and calibrating a micro MEMS inertial measurement module. The plate-level mounting error increment parameter block ΔP_brd in step seven is identified by at least one of the following methods: short-time self-test response analysis, gravity field attitude determination test, vibration stimulation offset test, and challenge-response matching test.

[0027] The present invention also provides a method for manufacturing and calibrating a micro MEMS inertial measurement module, which further includes setting a unique identifier that is inseparable from the physical entity of the module, and uniquely associating the package-induced error increment parameter block ΔP_pkg with the unique identifier, wherein a complete set of parameters sufficient for the module to independently complete error compensation of the original inertial data is not written back to the module.

[0028] This invention also provides a method for manufacturing and calibrating a micro MEMS inertial measurement module. When it is not required to trace back separately according to the physical source of "chip intrinsic / package induced", step one can be omitted. After the packaging response reaches stability, the module is calibrated as a whole. The obtained parameters are directly stored and called as the overall parameter block P_pkg_total after packaging. P_pkg_total, in the form of a single parameter block, represents the combined state of the intrinsic error and packaging induced error of the MEMS inertial sensor chip component. In this case, the board-level mounting error increment parameter block ΔP_brd is still solved independently according to step seven while keeping P_pkg_total unchanged. It is generated independently according to the physical source, carries the source identifier, version identifier and applicable scope identifier, and can be updated independently. After performing a compatibility check and / or conflict arbitration, it is used in combination with P_pkg_total to compensate for the error of the original inertial data output by the module.

[0029] The technical effects achieved by this invention are as follows: This invention employs a dual-path spatially separated packaging structure. First, a high-modulus first fixing layer at the bottom rigidly transfers the motion load from the substrate to the MEMS inertial sensor chip assembly via the bottom fixing interface region. Simultaneously, a second stress dissipation component, independent of the peripheral sealing layer and the cover, is provided on the top side and / or peripheral sub-region within the packaging cavity. This component is strictly limited to not entering the bottom fixing interface region, terminating its extension along the chip sidewall above this region, and maintaining a free buffer gap. This allows the packaging stress from the cover and / or peripheral sealing layer to be preferentially dissipated in the top side and / or peripheral region, thereby spatially separating the motion load transmission path from the packaging stress coupling path. This effectively reduces zero-bias drift, scale factor drift, cross-axis coupling error, and thermal hysteresis error caused by packaging thermomechanical stress. Experimental data shows that after temperature cycling aging, the module using this structure (Group A) exhibits approximately 16.7% lower gyroscope zero-bias change and approximately 17.1% lower acceleration zero-bias change compared to the control group (Group B), with a significantly reduced in-batch standard deviation. This invention employs a method of overall calibration and layered parameter solving after the packaged response stabilizes. Specifically, the intrinsic parameter block P_die is obtained at the bare chip stage. After packaging is completed and the packaging response stabilizes (judged by criteria such as convergence of the Frobenius norm of the comprehensive error matrix, the rate of change of orthogonal error components, the rate of change of zero-bias drift, and thermal aging time), the module undergoes overall calibration with multiple temperature points, multiple orientations, and / or multiple axis inputs. Based on the difference between the intrinsic parameter block and the measured data, the packaging-induced error increment parameter block ΔP_pkg (expressed in incremental form and not used independently of the intrinsic parameter block) is solved. After the module is mounted to an external circuit board and undergoes reflow soldering, the board-level mounting error increment parameter block ΔP_brd is solved while keeping P_die and ΔP_pkg unchanged. This achieves layered identification, independent updating, and on-demand combination of the physical sources of error, thereby overcoming the shortcomings of traditional chip-level calibration in covering newly added errors after packaging and mounting. It also makes board-level rework and aging compensation (ΔP_age) during service possible. This invention employs an external parameter and unique identifier association management method. Specifically, a unique identifier (UID, which can be implemented using laser-engraved QR codes, indelible serial numbers, OTP identifiers, or physical non-clonable fingerprints, etc.) is assigned to each module and inseparable from its physical entity. At least the encapsulated error-inducing increment parameter block ΔP_pkg is uniquely associated with this UID and stored in an external parameter database or a local cache on the host side. The module itself does not store a parameter set sufficient to independently complete complete error compensation. When the module powers on or initializes, the host controller reads the UID and calls the corresponding parameter block for combination. Optionally, a challenge-response verification unit can be used to improve mapping reliability. This method facilitates parameter version management, failure tracing, incremental correction after board-level reinstallation, and service life aging compensation, making it particularly suitable for mass production, automotive-grade functional safety, and cloud-edge collaborative systems. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the encapsulation cross-section structure of an embodiment of the present invention; Figure 2 This is a schematic diagram of dual-path stress transfer according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the geometric boundary constraints of the second stress dissipation component according to an embodiment of the present invention; Figure 4 This is a flowchart illustrating the manufacturing and calibration process of an embodiment of the present invention; Figure 5 This is a schematic diagram of the encapsulation response stability criterion of an embodiment of the present invention; Figure 6 This is a schematic diagram illustrating the layered parameter solution of an embodiment of the present invention; Figure 7 This is a system architecture diagram of external parameter binding and unique identifier binding according to an embodiment of the present invention; Figure 8 This is a comparison of the performance of different process structures in the embodiments of the present invention.

[0031] The attached diagram lists the components represented by each number as follows: 10. Substrate; 11. Electrical connection part; 12. External terminal; 20. MEMS inertial sensor chip assembly; 21. Chip top surface; 22. Chip bottom surface; 23. Chip sidewall; 30. First fixing layer; 40. Electrical interconnection structure; 50. Cover; 51. Inner surface of cover; 60. Peripheral sealing layer; 70. Encapsulation cavity; 80. Second stress dissipation component; 81. Free buffer gap. Detailed Implementation

[0032] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0033] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention can also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0034] Secondly, the term "an embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in a preferred embodiment" appearing in different places throughout this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that mutually excludes other embodiments.

[0035] Secondly, the present invention is described in detail with reference to the schematic diagrams. When detailing the embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not according to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.

[0036] Please see Figures 1 to 8 As shown, the present invention provides a micro MEMS inertial measurement module and its manufacturing and calibration method, including a substrate 10, an electrical connection portion 11 on its upper surface and an external terminal 12 on its bottom. MEMS inertial sensor chip assembly 20 includes at least a three-axis accelerometer and a three-axis gyroscope; The first fixing layer 30 is disposed between the MEMS inertial sensor chip assembly 20 and the substrate 10. Together with the bottom surface 22 of the MEMS inertial sensor chip assembly 20 and the upper surface of the substrate 10, it defines the bottom fixing interface area, which is used to fix the MEMS inertial sensor chip assembly 20 to the substrate 10 and rigidly transmit the motion load from the substrate 10 to the MEMS inertial sensor chip assembly 20 through the bottom fixing interface area. Electrical interconnect structure 40 is used to electrically connect MEMS inertial sensor chip assembly 20 and electrical connection part 11. Electrical interconnect structure 40 can be formed by wire bonding, with the wire arc spanning between the pads of MEMS inertial sensor chip assembly 20 and the pads of substrate 10. A peripheral sealing layer 60 is disposed on the substrate 10 and located around the MEMS inertial sensor chip assembly 20 and the electrical interconnection structure 40. The cover 50 is formed by surrounding the substrate 10 with the peripheral sealing layer 60 to form an encapsulation cavity 70; and the second stress dissipation member 80 is disposed in the encapsulation cavity 70. The second stress dissipation member 80 is an independent component of the encapsulation cavity 70 and is structurally different from the peripheral sealing layer 60 and the cover 50. It is used to dissipate the encapsulation stress introduced by the cover 50 and / or the peripheral sealing layer 60.

[0037] It is important to emphasize that the second stress dissipation component 80 is an independent component disposed within the encapsulation cavity 70, structurally distinct from the peripheral sealing layer 60 and the cover 50. The peripheral sealing layer 60 functions to connect the cover 50 to the substrate 10 to form the encapsulation cavity 70, primarily undertaking sealing and mechanical connection tasks. The function of the second stress dissipation component 80 is to dissipate or passivate the encapsulation stress transmitted from the cover 50 and / or the peripheral sealing layer 60 towards the chip within the encapsulation cavity 70. These are different components with different functions and independent structures. Making the peripheral sealing layer 60 itself a low-modulus material or making the frame of the cover 50 elastic are both different from the technical solution of this invention of setting an independent second stress dissipation component 80 within the encapsulation cavity 70.

[0038] The overall planar projection of the second stress dissipation member 80 is located within the area enclosed by the peripheral sealing layer 60 and does not enter the bottom fixing interface area. The second stress dissipation member 80 is located on the top side and / or near the peripheral sub-area of ​​the peripheral sealing layer 60 within the encapsulation cavity 70. Its extension along the corresponding chip sidewall 23 in the MEMS inertial sensor chip assembly 20 terminates above the bottom fixing interface area, thereby not forming a continuous stress transmission body with the bottom fixing interface area. As a result, the rigid path of the motion load from the substrate 10 transmitted through the first fixing layer 30 is spatially separated from the flexible path of the encapsulation stress from the cover 50 and / or the peripheral sealing layer 60 coupled through the second stress dissipation member 80.

[0039] It should be noted that, in this invention, the MEMS inertial sensor chip assembly 20 can be implemented using a single-chip six-axis inertial sensor device, or it can be implemented using at least one three-axis accelerometer chip and at least one three-axis gyroscope chip working collaboratively within the same package. When the chip assembly 20 includes multiple chips, the terms "bottom surface 22," "top surface 21," or "sidewall 23" of the chip assembly 20 as used in this specification can refer to the corresponding surface of one or more chips, depending on the context.

[0040] Specifically, the micro MEMS inertial measurement module includes a substrate 10, a MEMS inertial sensor chip assembly 20 disposed on the upper surface of the substrate 10, a first fixing layer 30 located between the bottom surface 22 of the MEMS inertial sensor chip assembly 20 and the upper surface of the substrate 10, an electrical interconnect structure 40, a cover 50, a peripheral sealing layer 60, and a second stress dissipation member 80 located in the encapsulation cavity 70.

[0041] The upper surface of the substrate 10 is provided with an electrical connection portion 11, and the bottom is provided with an external terminal 12 for connection to an external circuit board.

[0042] The substrate 10 can be a ceramic substrate, a glass substrate, a silicon substrate, a metal substrate, or a composite substrate thereof.

[0043] The MEMS inertial sensor chip assembly 20 can be a single-chip six-axis device, or it can be a combination of a three-axis accelerometer chip and a three-axis gyroscope chip working together in the same package, as long as it functions as a six-axis inertial sensor.

[0044] The first fixing layer 30 is disposed between the bottom surface 22 of the MEMS inertial sensor chip assembly 20 and the upper surface of the substrate 10. Its main function is to mechanically fix the MEMS inertial sensor chip assembly 20 to the substrate 10 and to transmit the motion loads corresponding to the acceleration, vibration and attitude changes from the substrate 10 to the MEMS inertial sensor chip assembly 20 in a highly rigid manner.

[0045] The electrical interconnect structure 40 is used to electrically connect the MEMS inertial sensor chip assembly 20 to the electrical connection portion 11 on the substrate 10. In this embodiment, it is preferably a metal bonding wire, such as a gold wire, copper wire, aluminum wire, or an alloy wire thereof. The electrical interconnect structure 40 can be formed by wire bonding, with the wire arc spanning between the pads of the MEMS inertial sensor chip assembly 20 and the pads of the substrate 10.

[0046] The cover 50 can be a metal cover, a ceramic cover, a silicon cover or a glass cover. The cover 50 is connected to the substrate 10 through a peripheral sealing layer 60, forming an encapsulation cavity 70.

[0047] In this embodiment, the cover 50 is preferably a metal cover, and the external terminals 12 are preferably a terminal array suitable for surface mounting, so that the module can be installed as a whole onto the system motherboard or carrier board.

[0048] The peripheral sealing layer 60 can be made of glass, solder, epoxy sealing material, brazing material or other materials suitable for forming a peripheral seal.

[0049] The second stress dissipation component 80 is an independent component disposed inside the encapsulation cavity 70, and is structurally distinct from the peripheral sealing layer 60 and the cover 50. The function of the peripheral sealing layer 60 is to connect the cover 50 to the substrate 10 to form the encapsulation cavity 70, and it mainly undertakes the tasks of sealing and mechanical connection.

[0050] The function of the second stress dissipation component 80 is to dissipate or passivate the packaging stress transmitted from the cover 50 and / or the peripheral sealing layer 60 to the chip direction within the packaging cavity 70.

[0051] The two are different components with different functions and independent structures. Even though the second stress dissipation component 80 is located in the peripheral sub-region near the peripheral sealing layer 60, it is still an independent entity inside the encapsulation cavity 70, rather than a modification or extension of the peripheral sealing layer 60 body.

[0052] Please see Figures 1 to 3 As shown, the ratio of the Young's modulus and / or storage modulus of the first fixing layer 30 at a reference temperature to the Young's modulus and / or storage modulus of the second stress dissipation member 80 at a reference temperature is not less than 100:1, and the reference temperature is any temperature between 20°C and 30°C.

[0053] The modulus ratio between the first fixing layer 30 and the second stress dissipation member 80 is not an arbitrary and replaceable value. When the ratio of their Young's modulus and / or storage modulus at the reference temperature is in the range of approximately 10:1 to 30:1, even if the second stress dissipation member 80 is only locally wetted near the chip sidewall 23, it is more likely to form additional shear bridging near the sidewall during temperature cycling, causing the packaging stress to still be significantly transmitted back to the bottom fixing interface area, thus greatly reducing the dual-path spatial separation effect.

[0054] When the modulus ratio is increased to about 50:1, the zero bias and thermal hysteresis are improved, but the improvement in cross-axis coupling and orthogonality error is still unstable.

[0055] When the modulus ratio reaches approximately 100:1, without significantly compromising the authenticity of the bottom motion load transmission, the orthogonal error drift, cross-axis coupling drift, and thermal hysteresis error enter a significant decreasing region, and the module's zero-bias stability and full-temperature consistency after temperature cycling are significantly improved.

[0056] When the modulus ratio continues to increase to about 300:1 or higher, the improvement tends to plateau, and the additional benefits brought by further increasing the modulus ratio are limited.

[0057] Therefore, setting the lower limit of the modulus ratio to not less than 100:1 is the critical balance point between achieving the dual objectives of "preserving the rigid motion load transmission at the bottom and dissipating the encapsulation stress introduced by the cover 50 and the peripheral sealing layer 60 by directing it to the top side and / or the peripheral flexible path".

[0058] By constraining the modulus ratio, it is possible to ensure that the first fixing layer 30 and the second stress dissipation component 80 have a clear and stable division of functions. This allows the motion load from the substrate 10 to be rigidly transmitted to the MEMS inertial sensor chip assembly 20 through the first fixing layer 30, while the encapsulation stress from the cover 50 and / or the peripheral sealing layer 60 is preferentially dissipated through the second stress dissipation component 80. This effectively reduces zero-bias drift, scale factor drift, non-orthogonal error increment, and thermal hysteresis error caused by encapsulation stress, thereby improving the consistency and reliability of the module under mass production and full-temperature operating conditions.

[0059] Please see Figures 1 to 3 As shown, the first fixing layer 30 is a cured layer of epoxy-based adhesive material, and the second stress dissipation component 80 is a cured layer of silicone-based, ketone-based, or other elastomer-filled material.

[0060] The selection of a cured layer of epoxy-based adhesive material as the first fixing layer 30 and a cured layer of silicone-based, ketone-based, or other elastomer-filled material as the second stress dissipation component 80 is based on the advantages of both in terms of mechanical properties, process compatibility, and long-term stability.

[0061] First, epoxy-based adhesives (such as filler-modified epoxy resins, epoxy / silica systems, or epoxy / metal filler systems) exhibit high Young's modulus (typically 1 GPa to 10 GPa) and high adhesive strength after curing. This allows them to firmly fix the MEMS inertial sensor chip assembly 20 onto the substrate 10, while rigidly transmitting the motion loads corresponding to acceleration, vibration, and attitude changes from the substrate 10 to the MEMS inertial sensor chip assembly 20 in a high-fidelity, low-loss manner. The high-modulus, high-rigidity transmission path ensures that the correspondence between inertial input and electrical output is not disturbed by intermediate interface deformation or creep, making it particularly suitable for harsh operating conditions such as vibration, shock, and high-speed dynamic attitude changes.

[0062] Secondly, silicone-based, silicone-based, or other elastomer-filled materials have extremely low Young's modulus (typically 0.001 MPa to 10 MPa) and excellent flexibility after curing, which can effectively absorb and dissipate the encapsulation stress caused by thermal expansion mismatch in the cover 50, peripheral sealing layer 60, and encapsulation cavity 70. These low-modulus materials generate very little reaction force when subjected to deformation, and will not transmit the encapsulation stress in the reverse to the sensitive structure of the MEMS inertial sensor chip assembly 20. At the same time, silicone-based and silicone-based materials have a wide operating temperature range (typically -50℃ to +200℃), good chemical stability, and low moisture absorption, which can maintain their flexible dissipation function for a long time in high and low temperature cycling and humid heat environments.

[0063] Furthermore, epoxy-based materials and silicone-based / silicone-based materials naturally exhibit a significant difference in modulus; their Young's modulus ratio at the reference temperature can easily reach over 100:1, and even as high as 10. 3 With a strength of 1 or higher, this provides an ideal material combination for achieving dual-path spatial separation of "rigid transmission at the bottom and flexible dissipation at the top / periphery".

[0064] If other types of materials (such as polyurethane, acrylate, etc.) are used as the second stress dissipation component 80, the modulus may not be low enough, the modulus ratio with the epoxy group may be insufficient, or the adhesion characteristics with the chip surface and bonding lines may be poor, resulting in unexpected stress coupling with the bottom fixed interface area during temperature cycling, which will destroy the dual-path separation effect.

[0065] Furthermore, both epoxy-based die-bonding materials and silicone-based / silicone-based fillers are mature materials widely used in the semiconductor packaging field. Their dispensing, curing, and thermal aging process parameters are well-defined, and they are highly compatible with existing production line equipment. They do not require the introduction of special or expensive material systems, which helps control manufacturing costs and improve mass production yield. At the same time, the curing temperature ranges of the two are compatible (epoxy curing is typically 120℃-180℃, while silicone curing can be from room temperature to 150℃). By arranging a reasonable curing sequence, such as completing epoxy curing first, followed by silicone filling and curing, process conflicts can be avoided.

[0066] It should be noted that the first fixing layer 30 is not limited to a single-layer structure, but can also be a combination of the main bearing layer and the local wetting layer, as long as the whole exhibits the high modulus rigidity transmission function that meets the requirements of this invention.

[0067] Please see Figures 1 to 3 As shown, the second stress dissipation component 80 includes multiple island-shaped sub-components and / or lattice support sub-components that are locally spaced within the area enclosed by the peripheral sealing layer 60. The second stress dissipation component 80 can also be implemented using a partitioned composite layer, that is, different regions within the same encapsulation cavity use material layers with different moduli or different thicknesses to adapt to differences in local stress distribution.

[0068] The continuous layer is implemented as follows: The second stress dissipation component 80 includes a continuous layer located between the inner surface 51 of the cover and at least one chip top surface 21 and / or electrical interconnect structure 40 in the MEMS inertial sensor chip assembly 20. The continuous layer covers at least one chip top surface 21 and at least partially covers the arc of the electrical interconnect structure 40. When the cover 50 and / or the peripheral sealing layer 60 generate encapsulation stress due to thermal expansion mismatch, the stress is first transferred to the continuous layer. The low-modulus material dissipates the mechanical energy into internal energy through its own compression, shearing, or creep, thereby significantly reducing the stress amplitude transferred to the chip top surface 21 and the sensitive structure. At the same time, the continuous layer covering the chip top surface 21 can form a flexible buffer barrier above the chip, uniformly dispersing the stress from above and avoiding local stress concentration. The continuous layer covers at least part of the wire arc. Low-modulus silicone or silicone material encapsulates and supports the bonding wire, transferring the shear and tensile loads borne by the wire arc to the flexible material for dissipation. This significantly improves the fatigue resistance and long-term reliability of the bonding wire. Simultaneously, the encapsulation structure prevents short-circuit contacts between bonding wires and provides some moisture and contamination protection. Although the continuous layer covers the chip top surface 21 and part of the wire arc, its extension along the chip sidewall 23 is explicitly defined to terminate above the bottom fixing interface region and not enter that region, thus ensuring that the continuous layer does not form a continuous stress transfer body with the bottom first fixing layer 30. By controlling the material viscosity, dispensing amount, curing time, or surface energy, it can be automatically terminated before reaching the bottom fixing interface region, thereby satisfying geometric constraints without introducing additional process steps. Furthermore, the adhesion interface between the continuous layer and the chip top surface 21 and the wire arc is relatively stable, and delamination or peeling is not easily caused during temperature cycling.

[0069] Island-like layer or lattice support layer implementation: The second stress dissipation component 80 includes multiple island-like sub-components and / or lattice support sub-components that are locally spaced within the area enclosed by the peripheral sealing layer 60. The overall planar projection of each sub-component is confined to the area enclosed by the peripheral sealing layer 60 and does not enter the bottom fixed interface area. Each island-like sub-component or lattice support sub-component can independently make local contact with the top surface 21 of the chip, the electrical interconnect structure 40, or the inner surface 51 of the cover, but its extension along the chip sidewall 23 also terminates before reaching the bottom fixed interface area, and does not form a continuous stress transfer body with the bottom fixed interface area through methods such as extending down along the sidewall, capillary climbing residue, post-curing shrinkage bridging, or local skirt coverage. Unfilled gaps are maintained between each sub-component to provide free space for expansion and contraction during temperature cycling. This implementation is particularly suitable for applications that are sensitive to module weight or require reserved airflow channels.

[0070] Partitioned Composite Layer Implementation: The second stress dissipation component 80 can also be implemented using a partitioned composite layer. This means that within the same encapsulation cavity, different regions use material layers with different moduli or thicknesses to accommodate differences in local stress distribution. For example, a lower modulus or thicker material layer can be used in the peripheral sub-region near the peripheral sealing layer 60, while a relatively higher modulus or thinner material layer can be used in the central sub-region, thus forming a stress management gradient of "strong dissipation at the periphery and weak interference in the center." This implementation can be achieved through multiple dispensing, molding transfer, or layered curing processes, optimizing the overall material usage while ensuring effective stress dissipation.

[0071] Common constraint: In any of the above implementations, a free buffer gap 81 is preferably maintained between the bottom edge of the second stress dissipation member 80 and the upper surface of the substrate 10, so as to provide free deformation space for the expansion, contraction and creep of the second stress dissipation member 80 during temperature cycling, which helps to avoid the soft material from applying additional shear loads to the bonding root and the bottom fixing interface.

[0072] The local contact between the second stress dissipation component 80 and the corresponding chip sidewall 23 in the MEMS inertial sensor chip assembly 20 is not inherently harmful. What truly degrades the technical effect is that the second stress dissipation component 80 extends continuously along the chip sidewall 23 to the vicinity of the bottom fixed interface region, or forms a continuous stress transfer body with this region in the form of capillary creep residue, solidified bridging, skirt coverage, etc. The former still falls within the local geometric adaptation permitted by this invention, while the latter will cause the top and / or peripheral flexible dissipation path to recouple with the bottom rigid transfer path, thereby disrupting the spatial separation of the two paths.

[0073] Furthermore, without departing from the concept of the present invention, the second stress dissipation member 80 may be implemented as a continuous layer, a local island layer, a lattice support layer or a partitioned composite layer, as long as it generally satisfies the constraints of not entering the bottom fixed interface region, terminating its extension along the sidewall before reaching the region, and not forming a continuous stress transfer body with the region.

[0074] Please see Figure 3 As shown, the second stress dissipation member 80 has a continuous free buffer gap 81 between the termination boundary of the chip sidewall 23 and the bottom fixed interface region, and between the lower boundary of the second stress dissipation member 80 and the upper surface of the substrate 10, in order to reduce shear traction during high and low temperature cycles.

[0075] The free buffer gap 81 serves as a clear geometric boundary constraint, which can effectively release the additional shear load caused by thermal expansion, contraction and creep of the second stress dissipation component 80 during high and low temperature cycling. This prevents the low modulus material from transferring shear force to the lower part of the chip sidewall, the root of the bonding line and the bottom fixing interface area under repeated thermal stress, thereby protecting the structural integrity of the bonding root and the bottom fixing interface. At the same time, this gap forms a structured boundary line to prevent the second stress dissipation component 80 from accidentally bridging to the bottom fixed interface area under long-term use or extreme temperature shock, ensuring that the long-term stability of the dual-path spatial separation is not compromised. In addition, the free buffer gap 81 provides free deformation space for the second stress dissipation component 80, so that it will not squeeze the bottom fixed interface area when expanding, and will not generate traction force when contracting, thereby significantly reducing the adverse effects of packaging stress on the chip sensitive structure and zero bias stability, and further improving the reliability and consistency of the module under full temperature range operating conditions.

[0076] Please see Figure 3 As shown, the local thickness of the second stress dissipation member 80 in the peripheral sub-region near the peripheral sealing layer 60 is greater than and / or the local modulus is lower than that in the central sub-region above the corresponding central region of the MEMS inertial sensor chip assembly 20.

[0077] Since the main sources of encapsulation stress, the cover 50 and the peripheral sealing layer 60, are located in the peripheral area of ​​the module, by increasing the thickness of the second stress dissipation member 80 or reducing its modulus in this area, the encapsulation stress can be preferentially intercepted and dissipated in the peripheral sub-region, while the relatively high modulus or small thickness in the central sub-region avoids excessive flexibility, thereby ensuring effective protection of the sensitive structure in the center of the chip while maintaining the stability of its mechanical boundary conditions. Meanwhile, the design creates a stress management gradient with strong dissipation at the periphery and weak interference at the center, which significantly reduces the proportion of packaging stress transmitted to the sensitive structure at the center of the chip, and further suppresses zero-bias drift, cross-axis coupling error and thermal hysteresis error caused by packaging stress. Meanwhile, this structure does not require changes to the chip's layout or the addition of extra isolation rings; it can be achieved simply by adjusting the local geometry and material properties of the second stress dissipation component 80, thus exhibiting good process feasibility.

[0078] Please see Figures 1 to 3 As shown, the Young's modulus of the first fixing layer 30 at 25°C is 1 GPa to 10 GPa, and the Young's modulus of the second stress dissipation member 80 at 25°C is 0.001 MPa to 10 MPa.

[0079] The high modulus (1GPa~10GPa) of the first fixed layer 30 ensures that the motion load from the substrate 10 is transmitted to the MEMS inertial sensor chip assembly 20 in a manner with high rigidity and low fidelity loss, thus meeting the requirements for the authenticity of inertial input under vibration, shock and dynamic attitude change conditions.

[0080] On the other hand, the ultra-low modulus (0.001 MPa to 10 MPa) of the second stress-dissipating component 80 gives it extremely high flexibility, enabling it to effectively absorb and dissipate the thermomechanical stress introduced by the cover 50 and the peripheral sealing layer 60, preventing this stress from being transmitted to the chip's sensitive structures. Within this range, the Young's modulus ratio of the two components at 25°C can reach over 100:1 (typically ranging from 100:1 to 10). 6 :1), thereby stably achieving dual-path spatial separation of "rigid transmission at the bottom and flexible dissipation at the top / periphery".

[0081] Please see Figures 1 to 3 As shown, the cover 50 is a metal cover, and the external terminals 12 are a terminal array suitable for surface mounting.

[0082] The metal cap has high mechanical strength and good thermal conductivity, which can provide robust physical protection for the MEMS inertial sensor chip assembly 20 and electrical interconnect structure 40 in the encapsulation cavity 70, resisting external mechanical impact and foreign object intrusion. At the same time, the excellent thermal conductivity of the metal cap helps to quickly dissipate the heat generated by the chip operation, reducing the impact of thermal gradient on sensor accuracy. The metal cover can also form an electromagnetic shielding cavity with the grounding layer in the substrate 10, effectively suppressing the interference of external electromagnetic interference on weak inertial signals. The external terminals 12 adopt a terminal array suitable for surface mounting, enabling the module to be directly installed on the system motherboard or carrier board through standard SMT reflow soldering process without additional sockets or manual soldering. The combination of the metal cover and surface mount terminals achieves synergistic gains in mechanical protection, thermal management, electromagnetic compatibility and mass production efficiency.

[0083] Please see Figure 8As shown, the effectiveness of the packaging structure in this embodiment is further illustrated through experimental comparison. Group A adopts the dual-path spatial separation structure of the present invention, where the bottom high-modulus first fixing layer 30 bears the motion load transmission, and the top and / or peripheral low-modulus second stress dissipation component 80 does not enter the bottom fixing interface region, but only extends locally along the chip sidewall and terminates before reaching that region; Group B adopts the comparative structure, in which the second low-modulus material continuously extends down along the chip sidewall to the bottom adjacent area, or forms an integral coating around the chip, resulting in continuous coupling between the top soft material and the bottom fixing interface region. Except for the geometric boundary of the second low-modulus component, the materials, dimensions, processes and electrical connection structures of the two groups of samples are consistent. The number of samples in each group is N=12, and multiple rounds of temperature cycling and aging are applied in the range of -40℃ to +125℃. The changes in gyroscope zero bias and acceleration zero bias are measured and compared before and after aging. The measuring instruments and environment are as follows: the multi-axis turntable angular rate accuracy is better than 0.001dps, the temperature uniformity of the temperature chamber is better than 0.5℃, the gyroscope input stage covers ±300dps, and the accelerometer input stage adopts the ±1g six-attitude method.

[0084] After aging, the mean zero-bias change of the gyroscopes in group A was approximately 0.20 dps, with an in-batch standard deviation (σ) of approximately 0.031 dps; the mean zero-bias change of the gyroscopes in group B was approximately 0.24 dps, with an in-batch standard deviation (σ) of approximately 0.041 dps. The zero-bias change of the gyroscopes in group A decreased by approximately 16.7% compared to group B. Simultaneously, the mean zero-bias change of acceleration in group A was approximately 3.4 mg, with an in-batch standard deviation (σ) of approximately 0.55 mg; the mean zero-bias change of acceleration in group B was approximately 4.1 mg, with an in-batch standard deviation (σ) of approximately 0.63 mg. The zero-bias change of acceleration in group A decreased by approximately 17.1% compared to group B. These data indicate that the adoption of a dual-path spatial separation structure improves the zero-bias stability of the device after temperature cycling, with the improvement ranging from approximately 10% to 20%.

[0085] A method for manufacturing and calibrating a miniature MEMS inertial measurement module, applied to a miniature MEMS inertial measurement module, includes the following steps: Step 1: The MEMS inertial sensor chip assembly 20 is calibrated during the bare chip stage and / or the pre-packaging stage to obtain the intrinsic parameter block P_die. The intrinsic parameter block P_die may include at least one of the following: zero bias vector b_die(T), scaling factor matrix K_die(T), non-orthogonal / cross-axis coupling matrix C_die(T), and thermal hysteresis or temperature compensation coefficient H_die(T).

[0086] Step 2: Fix the MEMS inertial sensor chip assembly 20 onto the substrate 10 through the first fixing layer 30, and form an electrical interconnection structure 40.

[0087] Step 3: The cover 50 and the substrate 10 are encapsulated together by the peripheral sealing layer 60 to form an encapsulation cavity 70. A second stress dissipation component 80 is disposed within the encapsulation cavity 70. The second stress dissipation component 80 is an independent component within the encapsulation cavity 70, structurally distinct from the peripheral sealing layer 60 and the cover 50. It is used to dissipate the encapsulation stress introduced by the cover 50 and / or the peripheral sealing layer 60. The second stress dissipation component 80 is located on the top side and / or near the peripheral sub-region of the peripheral sealing layer 60 within the encapsulation cavity 70, and adopts a continuous layer and localized design. The second stress dissipation member 80 is implemented by at least one of the following: island layer, lattice support layer, or partitioned composite layer. The second stress dissipation member 80 does not enter the bottom fixing interface region surrounded by the bottom surface 22 of the MEMS inertial sensor chip assembly 20, the upper surface of the substrate 10, and the first fixing layer 30. Its extension along the chip sidewall 23 terminates before reaching the bottom fixing interface region. It does not form a continuous stress transfer body with the bottom fixing interface region by extending down along the sidewall, capillary climbing residue, post-curing shrinkage bridging, or partial skirt coverage.

[0088] Step 4: Perform thermal aging and / or stress stabilization treatment on the packaged module. Thermal aging and / or stress stabilization treatment includes baking, heat preservation and / or temperature cycling of the module under preset temperature range and preset time conditions to accelerate the curing shrinkage, stress relaxation and creep of the packaging material to a steady state.

[0089] The first fixing layer 30 can be cured for 0.5 hours to 2 hours within the range of 120°C to 180°C; The second stress dissipation component 80 can be cured in the range of room temperature to 150°C according to the selected silicone system; Subsequently, the module can be subjected to thermal aging at 70°C to 125°C for 6 to 72 hours and / or several rounds of temperature cycling at -40°C to 125°C to stabilize the curing shrinkage, stress relaxation and creep of the encapsulation material. Step 5: After the encapsulation response stabilizes, perform overall calibration of the module to obtain the original inertial output data after encapsulation. The determination of whether the package response has reached stability is made. The term "stable package response" here does not mean that the absolute value of the module error reaches a single fixed value, but rather that the additional response introduced by the package stack has converged with time, temperature cycle number, or thermal aging time, so that the package-induced error increment parameter block obtained later has repeatability and portability.

[0090] In addition to the above criteria, IMU-specific statistical stability metrics can also be introduced to assess packaging response stability: For example, the Allan variance curves for two consecutive observation windows can be calculated under zero input conditions. When the changes in the bias instability estimate and the random walk estimate are both below a preset threshold, it is considered that the encapsulation-related drift has stabilized. Alternatively, the power spectral density of orthogonal error surrogate quantity, self-test response quantity, or other stress surrogate characteristics can be compared. When the spectral difference between adjacent windows is lower than a preset threshold, it is considered that the additional response introduced by the packaging stack has entered the repeatable range.

[0091] Specifically, the stability of the encapsulation response can be determined using one or more of the following quantization criteria: (1) Convergence criterion of the comprehensive error matrix Construct the integrated error matrix E_k(T_j) when the following conditions are met between two adjacent calibrations: ||E_k-E_(k-1)||_F / max(||E_(k-1)||_F,δ)≤ε1 If ε1∈[0.5%,5%], then the comprehensive error matrix is ​​considered to have converged.

[0092] (2) Stress surrogate characteristic stability criterion The orthogonal error component q_k of the gyroscope is selected as the stress surrogate feature when: |q_k-q_(k-1)| / max(|q_(k-1)|,δ)≤ε2 If ε2∈[0.1%,2%], then the changes in the packaging stress-related characteristics are considered to be stable.

[0093] (3) Drift rate of change monitoring criteria Monitor the rate of change of zero bias drift or the rate of change of calibration residual before and after temperature cycling. When the change does not exceed the preset threshold, it is considered stable.

[0094] (4) Criteria for thermal aging duration In scenarios constrained by production line cycle time, this criterion can be used as one of the stability criteria after meeting the preset thermal aging time. The above criteria can be used individually or in combination through weighted scoring, threshold series connection, or threshold parallel connection. Overall calibration is performed within a preset temperature range of -40℃ to +125℃ on a multi-axis rotary table and / or a multi-degree-of-freedom excitation device.

[0095] Step 6: Based on the difference between the intrinsic parameter block P_die and the original inertial output data after packaging, solve for the packaging-induced error increment parameter block ΔP_pkg expressed in incremental form. The packaging-induced error increment parameter block ΔP_pkg includes at least one of the following: zero bias increment, scaling factor increment, non-orthogonal error increment, cross-axis coupling increment, and thermal hysteresis error increment. The key here is not which numerical algorithm is used, but to represent the new error after packaging as an "increment block" relative to the intrinsic parameter block P_die, rather than reconstructing an absolute compensation table decoupled from the intrinsic parameter block.

[0096] Step 7: After the module is mounted to the external circuit board and undergoes reflow soldering, the reflow soldering process can use one or more reflow profiles with peak temperatures ranging from 235°C to 260°C, depending on the application. While keeping the intrinsic parameter block P_die and the package-induced error increment parameter block ΔP_pkg constant, solve for the board-level mounting error increment parameter block ΔP_brd; the board-level mounting error increment parameter block ΔP_brd is identified through at least one of the following methods: short-time self-test response analysis, gravity field attitude determination test, vibration-induced offset test, and challenge-response matching test; It also includes setting a unique identifier for the module that is inseparable from its physical entity, and uniquely associating the encapsulated error increment parameter block ΔP_pkg with the unique identifier, wherein the complete parameter set sufficient for the module to independently complete the error compensation of the original inertial data is not written back to the module.

[0097] Step 8: On the host side and / or in the processing entity used to perform error compensation, P_die, ΔP_pkg, and ΔP_brd are used as parameter blocks that are independently generated according to physical source, each carrying a source identifier, version identifier, and scope identifier, and can be independently updated. After performing at least one compatibility check and / or conflict arbitration, they are combined to perform error compensation on the raw inertial data output by the module.

[0098] In one embodiment, if an aging error increment parameter block ΔP_age is identified during service, it can be further configured as: P_final = P_die ⊕ ΔP_pkg ⊕ ΔP_brd ⊕ ΔP_age. Each of the above parameter blocks can be configured with a version number, generation time, applicable conditions, and update history, and can be stored, updated, and combined according to its physical source. For parameter blocks combined according to their physical source, compatibility checks and conflict arbitration can be performed before combination. Compatibility checks can be performed on at least one of the following: installation description, applicable temperature zone, applicable shaft group, version relationship, and generation time. Conflict arbitration can restrict an increment block to only operate on the corresponding subspace and not cover parameter blocks from other sources if it is found that an increment block is only valid for some shafts, some temperature zones, or some installation descriptions. This avoids mistakenly combining incompatible increment blocks into one. In the embodiment of layered solution according to physical source, the encapsulated induced error increment parameter block ΔP_pkg is not constructed as an absolute calibration coefficient table that can be used independently of the intrinsic parameter block P_die. During service, at preset time intervals (e.g., monthly or every 100 hours of operation) or when performance degradation is detected, the aging error increment parameter block ΔP_age is solved by comparing the difference between the current output and the reference state (e.g., the stable output in the initial period after leaving the factory). The aging error increment parameter block ΔP_age is then used as a parameter block generated independently by physical source, in combination with the intrinsic parameter block P_die, the package-induced error increment parameter block ΔP_pkg, and the board-level mounting error increment parameter block ΔP_brd. Compatibility checks are performed on at least one of the following: installation description, applicable temperature zone, applicable axis group, version relationship, and generation time. Conflict arbitration restricts a parameter block to only apply to the corresponding subspace and does not cover parameter blocks from other sources when it is found that a parameter block is only valid for some axes, some temperature zones, or some installation descriptions. In implementations that do not require separate tracing based on the physical source of "chip intrinsic / packaging induced", step one can be omitted; after the packaging response reaches stability, the module is calibrated as a whole, and the obtained parameters are directly stored and called as the overall parameter block P_pkg_total after packaging. P_pkg_total represents the combined state of intrinsic error and packaging induced error of MEMS inertial sensor chip component 20 in the form of a single parameter block. In this case, the board-level installation error increment parameter block ΔP_brd is still solved independently according to step seven while keeping P_pkg_total unchanged. It is used as a parameter block that is independently generated according to physical source, carries source identifier, version identifier and scope identifier and can be updated independently. After performing at least one compatibility check and / or conflict arbitration, it is used in combination with P_pkg_total to perform error compensation on the original inertial data output by the module.

[0099] As another embodiment of the present invention: The module body M is equipped with a unique identifier UID that is inseparable from the physical entity. This unique identifier UID can be implemented by laser-engraved QR code / barcode, non-erasable serial number, one-time programming area (OTP) identifier, read-only memory serial number, layout physical fingerprint, physical non-clonable fingerprint (PUF) formed by process discreteness, or a combination thereof.

[0100] On the production line side or the host side, at least the encapsulation-induced error increment parameter block ΔP_pkg should be uniquely associated with the unique identifier UID. If needed, the intrinsic parameter block P_die, the board-level mounting error increment parameter block ΔP_brd, and the aging error increment parameter block ΔP_age can also be indirectly associated with this UID. Each parameter block is solved and managed hierarchically according to its physical origin, and the UID is merely one of the engineering means to establish associations and call chains.

[0101] When the module is powered on or initialized, the host controller H can read the UID and retrieve the corresponding P_die, ΔP_pkg, ΔP_brd, and optional ΔP_age from the local parameter cache L or the external parameter database D. The host controller then completes the parameter combination. The set of parameters sufficient to enable the module to independently complete the full error compensation of the original inertial data is not stored internally within the module.

[0102] In another alternative implementation, a challenge-response verification unit V may also be provided.

[0103] Before parameter invocation, the host controller H can apply predefined challenges to the module body M, such as on-chip self-test stimuli, limited attitude sequences, short-term thermal stimuli, micro-vibration stimuli, or electrical handshake challenges. The module response is then matched with reference features bound to UIDs in the database to improve the reliability of the UID-parameter block mapping. This challenge-response verification unit V is an optional module. The core innovation of this invention lies in the dual-path spatial separation structure and the hierarchical solution encapsulation of induced error increment parameter blocks and board-level installation error increment parameter blocks.

[0104] As optional embodiments and supplementary descriptions of the present invention: 1. Without departing from the concept of the present invention, the second stress dissipation member 80 may be implemented as a continuous layer, a local island layer, a lattice support layer, or a partitioned composite layer, as long as it generally satisfies the constraints of not entering the bottom fixed interface region, terminating its extension along the sidewall before reaching that region, and not forming a continuous stress transfer body with that region. When a local island layer or a lattice support layer is used, multiple island sub-members or lattice support sub-members may be locally spaced within the area enclosed by the peripheral sealing layer 60.

[0105] 2. The first fixing layer 30 is not limited to a single-layer structure, but can also be a combination of the main bearing layer and the local wetting layer; as long as the whole exhibits the high modulus rigidity transmission function that meets the requirements of this invention.

[0106] 3. The Frobenius norm convergence, orthogonal error rate of change, zero bias drift rate of change, and thermal aging time in the encapsulation response stability criteria can be used individually or in combination through weighted scoring, threshold series connection, or threshold parallel connection.

[0107] 4. Layered parameter blocks can be combined in the same host device or combined in stages by production line equipment, board-level devices, domain controllers, mobile terminals or cloud-edge collaborative systems.

[0108] 5. For different applications such as robots, AGVs, AR / VR, wearables, ADAS, and autonomous driving, the specific temperature points, attitude sets, angular rate inputs, vibration spectra, reflow soldering conditions, and challenge-response templates can all be different. Those skilled in the art can set them according to the target product level without affecting the core solution of this invention.

[0109] 6. The second stress dissipation component 80 is an independent component disposed within the encapsulation cavity 70, structurally distinct from the peripheral sealing layer 60 and the cover 50. Making the peripheral sealing layer 60 itself a low-modulus or flexible material, or making the frame of the cover 50 elastic, constitutes a modification of the mechanical properties of the sealing structure itself, unlike the present invention which uses an independent second stress dissipation component within the encapsulation cavity 70 to establish a flexible dissipation path spatially separated from the bottom rigid transmission path. Even if the second stress dissipation component 80 is located in the peripheral sub-region near the peripheral sealing layer 60, it still exists independently within the encapsulation cavity 70.

[0110] 7. In application scenarios where separate tracing based on the physical source of "chip intrinsic / packaging induced" errors is not required (e.g., cost-sensitive consumer mass applications, one-time installation applications without board-level repair requirements, or scenarios where the host side has low requirements for parameter version control granularity), the intrinsic parameter block P_die and the packaging induced error increment parameter block ΔP_pkg can be merged into a single post-packaging overall parameter block P_pkg_total. In this optional implementation, calibration at the bare chip stage or before packaging can be omitted. Only after packaging is completed and the packaging response is stable is an overall calibration of the entire module applied with multiple temperature points, multiple orientations, and / or multiple axis inputs. The results are directly stored and retrieved in the form of P_pkg_total. The board-level mounting error increment parameter block ΔP_brd (and the aging error increment parameter block ΔP_age that may be obtained during service) obtained thereafter are still independently generated and updated according to the method of this invention, and used in combination with P_pkg_total after performing compatibility checks and / or conflict arbitration. This optional implementation can be regarded as merging the two layers of "chip intrinsic - packaging induced" into one layer in the layered solution scheme of the present invention, while the two layers of "board mounting - aging" still maintain independent degradation forms; it has advantages in terms of process simplification, production line cycle time and parameter management cost, but correspondingly, it cannot support independent traceability and updating according to the physical source of "chip intrinsic / packaging induced".

[0111] In summary, the present invention achieves improvements through at least the following two aspects: First, at the packaging structure level, the spatial division of labor between the bottom high-modulus first fixing layer 30 and the top and / or peripheral low-modulus second stress dissipation components 80 separates the motion load path from the packaging stress path; Second, at the parameter solving and management level, through overall calibration after packaging is completed and the packaging response is stable, as well as the hierarchical solving and controlled combination of intrinsic parameter blocks, packaging-induced error increment parameter blocks, and board-level installation error increment parameter blocks, traceable compensation for the physical source of errors is achieved.

[0112] The working principle of this invention is as follows: by combining the dual-path spatial separation design of the packaging structure with the hierarchical parameter solution management of the manufacturing calibration method, the physical source of error in the MEMS inertial measurement module can be traced and accurately compensated.

[0113] At the packaging structure level, motion loads (acceleration, vibration, attitude changes) from the substrate 10 are rigidly transferred from the bottom fixed interface region to the MEMS inertial sensor chip assembly 20 via the high-modulus first fixing layer 30, ensuring the authenticity of the inertial input and the response sensitivity. At the same time, the packaging thermomechanical stress from the cover 50 and the peripheral sealing layer 60 is preferentially intercepted and dissipated by the low-modulus second stress dissipation member 80 located in the top side and / or peripheral sub-region of the packaging cavity 70. Since the second stress dissipation member 80 is strictly limited to not entering the bottom fixed interface region, and its extension along the chip sidewall 23 terminates before reaching this region, and a free buffer gap 81 is retained, the packaging stress is not transmitted downward along the chip sidewall 23 to the bottom fixed interface region. This achieves spatial separation between the rigid transmission path of motion loads and the flexible dissipation path of packaging stress, effectively reducing zero-bias drift, scale factor drift, cross-axis coupling error, and thermal hysteresis error caused by packaging thermomechanical stress.

[0114] At the manufacturing and calibration level, the intrinsic parameter block P_die of the chip is first obtained by calibration at the bare chip stage. After the curing of the packaging structure (including the first fixing layer 30, the peripheral sealing layer 60, and the second stress dissipation component 80) is completed, thermal aging and / or stress stabilization treatments are performed to stabilize the packaging response (judged by criteria such as convergence of the Frobenius norm of the comprehensive error matrix, the rate of change of orthogonal error components, the rate of change of zero bias drift, and the duration of thermal aging). Then, under the stable packaging response state, the module is subjected to overall calibration with multiple temperature points, multiple orientations, and / or multiple axis inputs. Based on the difference between P_die and the measured data, the solution is obtained to enhance the performance of the module. The package-induced error increment parameter block ΔP_pkg is expressed in quantitative form (not used independently of P_die); after the module is mounted to the external circuit board and undergoes reflow soldering, the board-level mounting error increment parameter block ΔP_brd is solved while keeping P_die and ΔP_pkg unchanged; finally, on the host side, P_die, ΔP_pkg, ΔP_brd, and the optional aging error increment parameter block ΔP_age are used as parameter blocks that are independently generated according to physical source, carrying source identifier, version identifier, and applicable scope identifier. After compatibility verification and conflict arbitration, they are combined and used to compensate for errors in the original inertial data output by the module.

[0115] In addition, the module is equipped with a unique identifier UID that is inseparable from the physical entity. The parameter block is uniquely associated with this UID and stored in an external parameter database or a local cache on the host side. The module does not store a complete set of parameter compensation, which facilitates parameter version management, failure tracing, incremental correction after board-level reinstallation, and service life aging compensation.

[0116] The above description is merely a preferred embodiment of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention. Structures, devices, and operating methods not specifically described or explained in this invention are implemented according to conventional methods in the art unless otherwise specified or limited.

Claims

1. A miniature MEMS inertial measurement module, characterized in that: include The substrate (10) has an electrical connection part (11) on its upper surface and an external terminal (12) at its bottom for connection with an external circuit board. MEMS inertial sensor chip assembly (20) includes at least a three-axis accelerometer and a three-axis gyroscope; A first fixing layer (30) is disposed between the MEMS inertial sensor chip assembly (20) and the substrate (10), and together with the bottom surface (22) of the MEMS inertial sensor chip assembly (20) and the upper surface of the substrate (10), defines a bottom fixing interface area. The first fixing layer (30) is used to fix the MEMS inertial sensor chip assembly (20) to the substrate (10) and rigidly transmit the motion load from the substrate (10) to the MEMS inertial sensor chip assembly (20) through the bottom fixing interface area. Electrical interconnect structure (40) for electrically connecting the MEMS inertial sensor chip assembly (20) and the electrical connection part (11). A peripheral sealing layer (60) is disposed on the substrate (10) and located around the MEMS inertial sensor chip assembly (20) and the electrical interconnect structure (40); Cover (50), the cover (50) and the substrate (10) are arranged to form an encapsulation cavity (70) through the peripheral sealing layer (60); The second stress dissipation component (80) is disposed in the encapsulation cavity (70). The second stress dissipation component (80) is an independent component in the encapsulation cavity (70) and is structurally different from the peripheral sealing layer (60) and the cover (50). It is used to dissipate the encapsulation stress introduced by the cover (50) and / or the peripheral sealing layer (60). The overall planar projection of the second stress dissipation member (80) is located within the area enclosed by the peripheral sealing layer (60) and does not enter the bottom fixing interface area. The second stress dissipation member (80) is located on the top side of the encapsulation cavity (70) and / or near the peripheral sub-area of ​​the peripheral sealing layer (60). Its extension along the corresponding chip sidewall (23) in the MEMS inertial sensor chip assembly (20) terminates above the bottom fixing interface area, so as not to form a continuous stress transmission body with the bottom fixing interface area. Thus, the rigid path from the motion load of the substrate (10) to the MEMS inertial sensor chip assembly (20) via the first fixing layer (30) is spatially separated from the flexible path from the encapsulation stress of the cover (50) and / or the peripheral sealing layer (60) to the MEMS inertial sensor chip assembly (20) via the second stress dissipation member (80).

2. The micro-MEMS inertial measurement module according to claim 1, characterized in that: The ratio of the Young's modulus and / or storage modulus of the first fixing layer (30) at a reference temperature to the Young's modulus and / or storage modulus of the second stress dissipation member (80) at the reference temperature is not less than 100:1, and the reference temperature is any temperature between 20°C and 30°C.

3. The miniature MEMS inertial measurement module according to claim 1, characterized in that: The first fixing layer (30) is a cured layer of epoxy-based adhesive material, and the second stress dissipation component (80) is a cured layer of silicone-based, silicone-based or other elastomer-filled material.

4. A miniature MEMS inertial measurement module according to claim 1, characterized in that: The second stress dissipation member (80) includes a continuous layer located between the inner surface (51) of the cover body and at least one chip top surface (21) of the MEMS inertial sensor chip assembly (20) and / or the electrical interconnect structure (40), the continuous layer at least covering the at least one chip top surface (21) and at least partially covering the arc of the electrical interconnect structure (40).

5. A miniature MEMS inertial measurement module according to claim 1, characterized in that: The second stress dissipation component (80) includes a plurality of island-shaped sub-components and / or lattice support sub-components that are locally spaced within the area enclosed by the peripheral sealing layer (60).

6. A miniature MEMS inertial measurement module according to claim 1, characterized in that: The extension of the second stress dissipation member (80) along the corresponding chip sidewall (23) in the MEMS inertial sensor chip assembly (20) terminates before reaching the bottom fixed interface region, and does not form a continuous stress transfer body with the bottom fixed interface region by extending down along the sidewall, capillary climbing residue, post-curing shrinkage bridging, or partial skirt coverage; between the termination boundary of the second stress dissipation member (80) along the chip sidewall (23) and the bottom fixed interface region, and between the lower boundary of the second stress dissipation member (80) and the upper surface of the substrate (10), there is a continuous free buffer gap (81) not filled with solid or colloidal material, so as to reduce the shear pull applied by the second stress dissipation member (80) to the bottom fixed interface region and / or the bonding root of the electrical interconnect structure (40) during high and low temperature cycling.

7. A miniature MEMS inertial measurement module according to claim 1, characterized in that: The second stress dissipation member (80) has a local thickness greater than and / or a local modulus lower than that of the central sub-region located above the corresponding central region of the MEMS inertial sensor chip assembly (20) in the peripheral sub-region near the peripheral sealing layer (60), so that the encapsulation stress introduced by the cover (50) and / or the peripheral sealing layer (60) is preferentially dissipated in the peripheral sub-region.

8. A miniature MEMS inertial measurement module according to claim 1, characterized in that: The first fixing layer (30) has a Young's modulus of 1 GPa to 10 GPa at 25°C, and the second stress dissipation component (80) has a Young's modulus of 0.001 MPa to 10 MPa at 25°C.

9. A method for manufacturing and calibrating a miniature MEMS inertial measurement module, characterized in that: The application of a micro MEMS inertial measurement module according to any one of claims 1 to 8 includes the following steps: Step 1: Calibrate the MEMS inertial sensor chip assembly (20) during the bare chip stage and / or the pre-packaging stage to obtain the intrinsic parameter block P_die; Step 2: Fix the MEMS inertial sensor chip assembly (20) onto the substrate (10) through the first fixing layer (30) and form an electrical interconnection structure (40) between the MEMS inertial sensor chip assembly (20) and the substrate (10). Step 3: The cover (50) and the substrate (10) are enclosed by the peripheral sealing layer (60) to form an encapsulation cavity (70), and a second stress dissipation component (80) is provided in the encapsulation cavity (70). The second stress dissipation component (80) is an independent component in the encapsulation cavity (70) and is structurally different from the peripheral sealing layer (60) and the cover (50). It is used to dissipate the encapsulation stress introduced by the cover (50) and / or the peripheral sealing layer (60). The second stress dissipation component (80) is located on the top side and / or close to the peripheral sealing layer (60) in the encapsulation cavity (70). The surrounding sub-region is implemented using at least one of continuous layer, local island layer, lattice support layer or partitioned composite layer, wherein the second stress dissipation member (80) does not enter the bottom fixing interface region surrounded by the bottom surface (22) of the chip of the MEMS inertial sensor chip assembly (20), the upper surface of the substrate (10) and the first fixing layer (30), and its extension along the chip sidewall (23) terminates before reaching the bottom fixing interface region, and does not form a continuous stress transfer body with the bottom fixing interface region by probing down along the sidewall, capillary climbing residue, post-curing shrinkage bridging or local skirt coverage; Step 4: After the first fixing layer (30), the peripheral sealing layer (60) and the second stress dissipation component (80) have all been cured, the packaged module is subjected to thermal aging and / or stress stabilization treatment. Step 5: After the encapsulation response stabilizes, perform overall calibration on the module to obtain the original inertial output data after encapsulation. Step 6: Based on the difference between the intrinsic parameter block P_die and the original inertial output data after packaging, solve for the packaging-induced error increment parameter block ΔP_pkg, which is expressed in increment form relative to the intrinsic parameter block P_die. Step 7: After the module is mounted to the external circuit board and undergoes reflow soldering, while keeping the intrinsic parameter block P_die and the package-induced error increment parameter block ΔP_pkg unchanged, solve for the board-level mounting error increment parameter block ΔP_brd; Step 8: On the host side and / or in the processing entity used to perform error compensation, the intrinsic parameter block P_die, the package-induced error increment parameter block ΔP_pkg, and the board-level mounting error increment parameter block ΔP_brd are used as parameter blocks that are independently generated according to their physical source, each carrying a source identifier, version identifier, and scope identifier, and can be independently updated. After performing at least one compatibility check and / or conflict arbitration, they are combined for error compensation of the raw inertial data output by the module.

10. The method for manufacturing and calibrating a micro-MEMS inertial measurement module according to claim 9, characterized in that: The stable packaging response in step five means that at least one of the following criteria is met: the rate of change of zero bias drift is lower than a preset threshold, the rate of change of stress surrogate characteristics is lower than a preset threshold, the change of calibration residuals before and after temperature cycling is lower than a preset threshold, a preset thermal aging time is reached (this preset thermal aging time can be determined by previous process verification, sampling calibration or historical batch stability data), the change of the bias instability estimate of Allan variance under zero input conditions is lower than a preset threshold, or the difference in the power spectral density of the stress surrogate characteristics between adjacent observation windows is lower than a preset threshold.

11. The method for manufacturing and calibrating a micro-MEMS inertial measurement module according to claim 9, characterized in that: The overall calibration in step five is performed within a preset temperature range of -40℃ to +125℃ and is completed on a multi-axis rotary table and / or a multi-degree-of-freedom excitation device.

12. The method for manufacturing and calibrating a micro-MEMS inertial measurement module according to claim 9, characterized in that: The thermal aging and / or stress stabilization treatment in step four includes baking, heat preservation and / or temperature cycling of the module under preset temperature range and preset time conditions to accelerate the curing shrinkage, stress relaxation and creep of the encapsulation material to a steady state.

13. The method for manufacturing and calibrating a micro-MEMS inertial measurement module according to claim 9, characterized in that: The encapsulation-induced error increment parameter block ΔP_pkg includes at least one of the following: zero bias increment, scaling factor increment, non-orthogonal error increment, cross-axis coupling increment, and thermal hysteresis error increment.

14. The method for manufacturing and calibrating a micro-MEMS inertial measurement module according to claim 9, characterized in that: In the implementation of layered solution based on physical source, the encapsulation-induced error increment parameter block ΔP_pkg is not constructed as an absolute calibration coefficient table that can be used independently of the intrinsic parameter block P_die.

15. The method for manufacturing and calibrating a micro-MEMS inertial measurement module according to claim 9, characterized in that: It also includes obtaining the aging error increment parameter block ΔP_age based on the difference between historical output and reference state during the service phase, and using the aging error increment parameter block ΔP_age as a parameter block generated independently according to physical source in combination with the intrinsic parameter block P_die, the package-induced error increment parameter block ΔP_pkg, and the board-level mounting error increment parameter block ΔP_brd.

16. The method for manufacturing and calibrating a micro-MEMS inertial measurement module according to claim 9, characterized in that: The compatibility check is performed on at least one of the following: installation description, applicable temperature zone, applicable axis group, version relationship, and generation time. The conflict arbitration, when it is found that the parameter block to be combined is only valid for some axes, some temperature zones, or some installation descriptions, restricts the parameter block to only act on the corresponding subspace and does not cover parameter blocks from other sources.

17. The method for manufacturing and calibrating a micro-MEMS inertial measurement module according to claim 9, characterized in that: The plate-level installation error increment parameter block ΔP_brd mentioned in step seven is identified through at least one of the following methods: short-time self-test response analysis, gravity field attitude determination test, vibration stimulation offset test, and challenge-response matching test.

18. The method for manufacturing and calibrating a micro-MEMS inertial measurement module according to claim 9, characterized in that: It also includes setting a unique identifier for the module that is inseparable from its physical entity, and uniquely associating the encapsulation-induced error increment parameter block ΔP_pkg with the unique identifier, wherein a complete set of parameters sufficient for the module to independently complete the error compensation of the original inertial data is not written back to the module.

19. The method for manufacturing and calibrating a micro-MEMS inertial measurement module according to claim 9, characterized in that: When it is not required to trace back to the physical source of the chip intrinsic error or the packaging-induced error separately, after the packaging response reaches stability, the module is calibrated as a whole. The obtained parameters are directly stored and called as the overall parameter block P_pkg_total after packaging. P_pkg_total represents the combined state of the intrinsic error and the packaging-induced error of the MEMS inertial sensor chip component (20) in the form of a single parameter block. The board-level mounting error increment parameter block ΔP_brd is still solved independently according to step seven while keeping P_pkg_total unchanged. It is generated independently according to the physical source, carries the source identifier, version identifier and applicable scope identifier and can be updated independently. After performing a compatibility check and / or conflict arbitration, it is used in combination with P_pkg_total to perform error compensation on the original inertial data output by the module.

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