A method of sinter joint pull test

CN122900963APending Publication Date: 2026-10-13GUILIN UNIV OF ELECTRONIC TECH +2
View PDF 0 Cites 0 Cited by

Patent Information

Application Number
CN202611204348.1
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2026-08-10
Publication Date
2026-10-13

AI Technical Summary

Technical Problem

在功率封装的实际服役过程中,基板与芯片的热膨胀系数失配会在烧结接头内产生显著的法向剥离应力,导致烧结接头开裂、失效

Benefits of technology

本发明中烧结接头拉力测试方法包括以下内容:步骤S1,依次放置模拟基板,连接层和模拟芯片,焊接设备将三者焊接固定形成烧结接头;步骤S2,固定模拟基板的位置,并留存操作窗口,操作窗口用于拔针伸入(操作窗口为拔针伸入,与模拟芯片焊接固定,以及拉拔模拟芯片提供了所需的操作空间);步骤S3,将拔针的拉拔端与模拟芯片对准,采用焊接设备将二者焊接固定在一起,随后,驱动设备自模拟基板朝模拟芯片的方向拉动拔针,直至烧结接头断裂;拔针与驱动设备的输出端传动连接,拔针连接有与模拟芯片避让设置的拉力传感器(避让设置是指拉力传感器不会阻挡拔针与模拟芯片的连接),通过拉力传感器检测的拉力数据计算得出烧结接头的连接强度;

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure CN122900963A_ABST
    Figure CN122900963A_ABST
Patent Text Reader

Abstract

The application discloses a sintering joint tension test method, and relates to the technical field of sintering joint testing.The sintering joint tension test method comprises the following steps: S1, sequentially placing a simulation substrate, a connecting layer and a simulation chip, and welding and fixing the three to form a sintering joint; S2, fixing the position of the simulation substrate and reserving an operation window; S3, aligning the pulling end of a pull pin with the simulation chip, welding and fixing the two together, pulling the pull pin, and stopping until the sintering joint is broken; the pull pin is connected with a tension sensor; the sintering joint is closer to the real stacking structure in the structural aspect, and the result of the sintering joint tension test can more truly reflect the welding connection strength of the stacking structure; the center line of the pull pin is coaxially arranged with the center line of the simulation chip, and the center line of the pull pin is vertically arranged with the connecting layer, which reduces the probability of the connecting layer being subjected to shearing force and bending moment during the tension test, so that the sintering joint tension test result can more truly reflect the connection strength of the sintering joint.
Need to check novelty before this filing date? Find Prior Art

Description

Technical Field

[0001] This invention relates to the field of sintered joint testing technology, and in particular to a method for testing the tensile strength of sintered joints. Background Technology

[0002] Sintering interconnect technologies, such as nano-silver sintering and nano-copper sintering, have become core interconnection solutions between power chips and substrates due to their excellent thermal and electrical conductivity and high-temperature stability. As a critical structure in power packaging that bears mechanical and thermal stresses, the bonding strength of sintered joints affects the service life and reliability of devices. During actual service, the mismatch in the thermal expansion coefficients of the substrate and the chip can generate significant normal peel stress within the sintered joint, leading to cracking and failure.

[0003] Existing tensile testing methods for sintered joints are mostly designed for the plating-substrate structure, but these methods differ significantly from the tensile testing results for the substrate-sintered interconnect layer-chip stacked structure, thus providing limited reference value for the design of the substrate-sintered interconnect layer-chip stacked structure.

[0004] Therefore, how to reduce the gap between the tensile test of sintered joints and the tensile test of the stacked structure of substrate-sintered interconnect layer-chip, and improve the engineering reference value of sintered joint tests for the design of the stacked structure of substrate-sintered interconnect layer-chip, has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide a sintered joint tensile testing method to reduce the error between sintered joint tensile testing and the tensile testing of the substrate-sintered interconnect layer-chip stacked structure, thereby improving the engineering reference value of sintered joint testing for the design of the substrate-sintered interconnect layer-chip stacked structure.

[0006] To achieve the above objectives, the present invention provides the following solution: This invention provides a method for testing the tensile strength of sintered joints, the method comprising the following: Step S1: Place the analog substrate, the interconnect layer, and the analog chip in sequence, and use welding equipment to weld and fix the three together to form a sintered joint. Step S2: Fix the position of the simulation substrate and leave an operation window, which is used for inserting the needle. Step S3: Align the pull-out end of the pin with the analog chip, and use the welding equipment to weld and fix the two together. Then, drive the device to pull the pin from the analog substrate toward the analog chip until the sintered joint breaks. When the pull-out end is aligned with the analog chip, the center line of the pull-out needle is coaxial with the center line of the analog chip, and the center line of the pull-out needle is perpendicular to the connecting layer. The output end of the drive device is connected to the needle pulling drive, and the needle pulling is connected to a tension sensor that is arranged to avoid the analog chip.

[0007] Preferably, the tensile testing method for sintered joints includes a testing fixture, which includes a positioning plate and an adjusting plate. The positioning plate is provided with a plurality of adjacent first positioning parts and first through holes, and the adjusting plate is provided with a plurality of adjacent second positioning parts and second through holes. Step S1 includes the following: Step S1.1: Align the first end of the analog substrate with the corresponding first through hole, place the analog substrate and the positioning plate sequentially from bottom to top, and align the second end of the analog chip with the corresponding second through hole. Step S1.2: Align the first end of the analog substrate with the second end of the corresponding analog chip, and adjust the distance between the first end of the analog substrate and the second end of the analog chip according to the required thickness of the connecting layer. When the distance between the first end of the analog substrate and the second end of the analog chip reaches the required thickness of the connecting layer, place the connecting layer and connect the positioning plate and the adjustment plate. Step S1.3: The analog substrate, the connecting layer, and the analog chip are soldered and fixedly connected. Wherein, the first end of the simulation substrate is in clearance fit with the first through hole, the first positioning part abuts against the simulation substrate, and can apply a downward force to the simulation substrate; the second end of the simulation chip is in clearance fit with the second through hole, the second positioning part abuts against the simulation chip, and can apply an upward force to the simulation chip. The thickness direction of the connection layer is set from the analog substrate toward the analog chip.

[0008] Preferably, the test fixture includes a limiting member, and step S1.2 includes placing the limiting member, which abuts against the positioning plate and the adjustment plate respectively, after aligning the first end of the simulation substrate with the second end of the corresponding simulation chip. The thickness of the limiting member is the distance between the positioning plate and the adjustment plate when the connecting layer reaches the required thickness.

[0009] Preferably, the test fixture includes a fixing component, which is a screw, and both the positioning plate and the adjusting plate are provided with through threaded holes.

[0010] Preferably, the test fixture includes a pad, and step S1.1 includes aligning the first end of the simulation substrate with and passing it through the corresponding first through hole, and placing the pad, the simulation substrate and the positioning plate sequentially from bottom to top. The cross-sectional area of ​​the pad is larger than that of the simulation substrate and is used to support the simulation substrate. The pad is placed horizontally and the end of the pad facing the simulation substrate is flat.

[0011] Preferably, the connecting layer is made of silver nanoparticles; and / or, the analog substrate and the analog chip are made of copper.

[0012] Preferably, both the analog substrate and the analog chip are copper bosses.

[0013] Preferably, step S3 includes: before the pull-out end of the pin is soldered and fixed to the analog chip, a solder joint of a preset size is soldered and fixed to the pull-out end of the pin; the pull-out end of the pin is brought closer to the analog chip and aligned with the analog chip; then the heating device heats the solder joint, so that the molten solder joint can hang down to the end of the analog chip away from the connecting layer under its own weight; after the solder joint cools and solidifies, the fixed connection between the pin and the analog chip is completed.

[0014] Preferably, the tensile testing method for the sintered joint includes: after fixing the position of the simulated substrate, a loading device applies corresponding thermal stress and / or current to the sintered joint.

[0015] Preferably, the diameter of the first end of the analog substrate is 0.5mm to 10mm, and the diameter of the second end of the analog chip is 200um to 800um.

[0016] The present invention achieves the following technical effects compared to the prior art: The tensile strength test method for sintered joints in this invention includes the following steps: Step S1, placing a simulation substrate, a connecting layer, and a simulation chip in sequence, and welding them together to form a sintered joint using a welding device; Step S2, fixing the position of the simulation substrate and leaving an operating window for inserting a pin (the operating window provides the necessary operating space for inserting the pin, welding it to the simulation chip, and pulling it out); Step S3, aligning the pulling end of the pin with the simulation chip, and welding them together using a welding device, then driving the device to pull the pin from the simulation substrate toward the simulation chip until the sintered joint breaks; the pin is connected to the output end of the driving device, and the pin is connected to a tensile sensor that avoids obstructing the connection between the pin and the simulation chip (the avoidance setting means that the tensile sensor will not block the connection between the pin and the simulation chip); the connection strength of the sintered joint is calculated from the tensile data detected by the tensile sensor. It should be noted that the sintered joint formed by welding and fixing the simulated substrate, the interconnect layer, and the simulated chip simulates the stacked structure of substrate-sintered interconnect layer-chip in existing power device packaging (for ease of description, the stacked structure of substrate-sintered interconnect layer-chip will be referred to as stacked structure below). Therefore, when the simulated substrate, the interconnect layer, and the simulated chip are made of the same materials or materials with similar properties as those used to prepare substrate-sintered interconnect layer-chip, compared with the method of directly welding the sintered layer on the substrate surface and pulling the sintered layer, the sintered joint in this application is closer to the stacked structure at the structural level. This reduces the gap between the tensile test results of the sintered joint and the tensile test results of the stacked structure. Furthermore, when the pull-out end of the pin is aligned with the analog chip, the centerline of the pin is coaxial with the centerline of the analog chip, and the centerline of the pin is perpendicular to the connecting layer. This reduces the probability of the connecting layer being subjected to shear force and bending moment during tensile testing, making the tensile test results of the sintered joint more realistically reflect the connection strength of the sintered joint, narrowing the gap between the tensile test results of the sintered joint and the tensile test results of the stacked structure, and improving the engineering reference value provided for the design of the stacked structure (engineering reference value refers to the reference value provided for the engineering of the stacked structure design). In summary, the tensile testing method for sintered joints in this invention narrows the gap between the tensile test results of sintered joints and the tensile test results of stacked structures, thereby improving the engineering reference value provided for the design of stacked structures. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the sintered joint fabricated using testing fixtures; Figure 2 This is a schematic diagram of the structure of the sintered joint after it has been prepared using testing fixtures. Figure 3 This is a schematic diagram of a sintered joint using a needle-pulling method. Figure 4 A schematic diagram of the structure for pulling off the sintered joint by removing the needle; The components include: 1. Pad; 2. Positioning plate; 3. Adjustment plate; 4. Simulation substrate; 5. Connecting layer; 6. Simulation chip; 7. Pin puller; 8. Solder joint; 9. Screw; and 10. Limiting component. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0021] like Figures 1-4 As shown, this invention discloses a method for testing the tensile strength of a sintered joint. The method includes the following steps: Step S1, placing a simulation substrate 4, a connecting layer 5, and a simulation chip 6 in sequence, and welding them together to form a sintered joint; Step S2, fixing the position of the simulation substrate 4 and leaving an operating window for inserting a pull pin 7 (the operating window provides the necessary operating space for inserting the pull pin 7, welding it to the simulation chip 6, and pulling the simulation chip 6); Step S3, aligning the pull end of the pull pin 7 with the simulation chip 6, welding them together, and then pulling the pull pin 7 from the simulation substrate 4 toward the simulation chip 6 until the sintered joint breaks; the pull pin 7 is connected to the output end of the driving device, and a tensile sensor is connected to the pull pin 7. The connection strength of the sintered joint is calculated from the tensile data detected by the tensile sensor. It should be noted that the sintered joint formed by welding and fixing the simulated substrate 4, the interconnect layer 5, and the simulated chip 6 simulates the stacked structure of substrate-sintered interconnect layer-chip in existing power device packaging (for ease of description, the stacked structure of substrate-sintered interconnect layer-chip will be referred to as stacked structure below). Therefore, when the simulated substrate 4, the interconnect layer 5, and the simulated chip 6 are made of the same materials or materials with similar properties as those used to prepare the substrate-sintered interconnect layer-chip, compared with the method of directly welding the sintered layer on the substrate surface and pulling the sintered layer, the sintered joint in this application is closer to the stacked structure at the structural level. This reduces the gap between the tensile test results of the sintered joint and the tensile test results of the stacked structure. Furthermore, when the pull-out end of the pin 7 is aligned with the analog chip 6, the center line of the pin 7 is coaxial with the center line of the analog chip 6, and the center line of the pin 7 is perpendicular to the connecting layer 5. This reduces the probability of the connecting layer 5 being subjected to shear force and bending moment during tensile testing, making the tensile test results of the sintered joint more realistically reflect the connection strength of the sintered joint, narrowing the gap between the tensile test results of the sintered joint and the tensile test results of the stacked structure, and improving the engineering reference value provided for the design of the stacked structure (engineering reference value refers to the reference value provided for the engineering of the stacked structure design). In summary, the tensile testing method for sintered joints in this invention narrows the gap between the tensile test results of sintered joints and the tensile test results of stacked structures, thereby improving the engineering reference value provided for the design of stacked structures.

[0022] The tensile testing method for sintered joints includes a testing fixture, which includes a positioning plate 2 and an adjusting plate 3. The positioning plate 2 has several adjacent first positioning parts and first through holes, and the adjusting plate 3 has several adjacent second positioning parts and second through holes. Step S1 includes the following: Step S1.1, align the first end of the simulation substrate 4 and pass it through the corresponding first through hole, and place the simulation substrate 4 and the positioning plate 2 sequentially from bottom to top, and align the second end of the simulation chip 6 and pass it through the corresponding second through hole; Step S1.2, align the first end of the simulation substrate 4 and the second end of the corresponding simulation chip 6, and adjust the distance between the first end of the simulation substrate 4 and the second end of the simulation chip 6 according to the required thickness of the connecting layer 5. When the distance between the first end of the simulation substrate 4 and the second end of the simulation chip 6 reaches the required thickness of the connecting layer 5, connect the positioning plate 2 and the adjusting plate 3. The thickness direction of the connecting layer 5 is set from the analog substrate 4 toward the analog chip 6; in step S1.3, the analog substrate 4, the connecting layer 5 and the analog chip 6 are welded and fixedly connected; wherein, the first end of the analog substrate 4 is in clearance fit with the first through hole, and the first positioning part abuts against the analog substrate 4 (the first positioning part refers to the area on the positioning plate 2 where there is no first through hole and abuts against the analog substrate 4, which can suppress the displacement of the analog substrate 4), which can apply a downward force to the analog substrate 4; the second end of the analog chip 6 is in clearance fit with the second through hole, and the second positioning part abuts against the analog chip 6 (the second positioning part refers to the area on the positioning plate 2 where there is no second through hole and abuts against the analog chip 6, which can support the analog chip 6), which can apply an upward force to the analog chip 6, to prevent the connecting layer 5 from being squeezed by the weight of the analog chip 6, which would affect the thickness of the connecting layer 5 and prevent it from reaching the expected thickness.

[0023] If the positioning plate 2 and adjustment plate 3 are not provided, and the analog substrate 4, the connecting layer 5, and the analog chip 6 are simply stacked sequentially, some of the material in the connecting layer 5 may fall off due to the compression of the analog chip 6 and the analog substrate 4 before the connecting layer 5 is welded and fixed to the analog chip 6 and the analog substrate 4. This results in the connecting layer 5, which connects the analog chip 6 and the analog substrate 4, having less material than the set amount, thus reducing the accuracy of the sintered joint tensile test. Furthermore, if the positioning plate 2 and adjustment plate 3 are not provided, the central axis of the partially formed stacked structure of the analog chip 6 and the analog substrate 4 may be shifted or deviated due to the internal stress during the sintering process or the minimal airflow in the nitrogen atmosphere, causing the bonding surface, i.e., the connecting layer 5, to be affected. The present invention controls the distance between the first end of the analog substrate 4 and the second end of the analog chip 6 through the positioning plate 2 and the adjustment plate 3, as well as the above steps, thereby controlling the thickness of the connecting layer 5 (after the distance between the first end of the analog substrate 4 and the second end of the analog chip 6 reaches the required thickness of the connecting layer 5, the positioning plate 2 and the adjustment plate 3 are connected together, thereby avoiding the situation where the distance between the analog substrate 4 and the analog chip 6 changes, causing the analog chip 6 and the analog substrate 4 to be unable to be connected through the connecting layer 5 of the required thickness), so that the analog substrate 4 and the analog chip 6 can be welded and fixed together with the connecting layer 5 of the required thickness, and avoids the interference of the above factors on the bonding surface, i.e., the connecting layer 5.

[0024] Furthermore, the clearance fit between the first end of the simulation substrate 4 and the first through hole, and the clearance fit between the second end of the simulation chip 6 and the second through hole, reduces the force exerted by the positioning plate 2 and the adjusting plate 3 on the simulation substrate 4 and the simulation chip 6 respectively, thus reducing interference with the tensile test results of the sintered joint. The positioning plate 2 can be fixed in the corresponding area by fasteners such as bolts or screws 9, thereby fixing the simulation substrate 4 and preventing the pin 7 from failing to break the sintered joint due to the simulation substrate 4 not being fixed. Alternatively, if the size of the simulation substrate 4 and the simulation chip 6 is small, fasteners such as bolts or screws 9 may not be required, and the simulation substrate 4 can be fixed solely by the weight of the positioning plate 2.

[0025] Furthermore, if the size of the analog substrate 4 and the analog chip 6 is small, the positioning plate 2 and the adjustment plate 3 may not be connected, and the adjustment plate 3 may simply be placed on the positioning plate 2. In this case, one of the positioning plate 2 and the adjustment plate 3 may be flat, and the other may have a flat structure with several protrusions at one end of the flat structure of the other. The length of the protrusions must be long enough to accommodate a sufficiently thick connecting layer 5. For example, when the positioning plate 2 is a rectangular plate, the adjustment plate 3 is equivalent to setting multiple limiting rods (the limiting rods are the protrusions) on the basis of the rectangular plate.

[0026] The test fixture includes a limiting member 10. Step S1.2 includes aligning the first end of the analog substrate 4 with the second end of the corresponding analog chip 6 (alignment means that the center lines of the analog substrate 4 and the analog chip 6 are aligned coaxially), placing the limiting member 10 between the positioning plate 2 and the adjustment plate 3, respectively abutting against both. The thickness of the limiting member 10 is the distance between the positioning plate 2 and the adjustment plate 3 when the connecting layer 5 reaches the required thickness, and at this time, both ends of the limiting member 10 must abut against the positioning plate 2 and the adjustment plate 3 respectively. Placing the limiting member 10 between the positioning plate 2 and the adjustment plate 3 reduces the possibility that the analog chip 6 and the analog substrate 4 cannot be welded together through the connecting layer 5 of the required thickness due to changes in the distance between the adjustment plate 3 and the positioning plate 2 when fixing them, thus ensuring the accuracy of the sintered joint tensile test. The limiting member 10 can specifically be a limiting block or a limiting plate, and can be made of materials such as stainless steel or copper that are not easily deformed under the pressure of the adjustment plate 3 and the positioning plate 2. The limiting member 10 can be prepared in multiple different sizes to accommodate the preparation of sintered joints with different thicknesses of the connecting layer 5. When bolts or screws 9 are used as fasteners, the limiting member 10 can be sleeved on the bolts or screws 9 after the bolts or screws 9 pass through the adjusting plate 3; or, the limiting member 10 can be placed directly between the analog substrate 4 and the analog chip 6.

[0027] Depending on the needs, different connection methods can be used between the positioning plate 2 and the adjustment plate 3. A connecting rod can be passed sequentially through the positioning plate 2 and the adjustment plate 3, and when the distance between the second end of the analog chip 6 and the first end of the analog substrate 4 reaches the thickness of the connecting layer 5, the connecting rod is welded to the positioning plate 2 and the adjustment plate 3 respectively. Alternatively, the test fixture includes a fixing component, which is a bolt or screw 9. Both the positioning plate 2 and the adjustment plate 3 have through threaded holes. When the distance between the second end of the analog chip 6 and the first end of the analog substrate 4 reaches the thickness of the connecting layer 5, the bolt or screw 9 is threadedly connected to the positioning plate 2 and the adjustment plate 3.

[0028] The test fixture includes a pad 1. Step S1.1 includes aligning the first end of the simulation substrate 4 with the corresponding first through hole, and placing the pad 1, the simulation substrate 4, and the positioning plate 2 sequentially from bottom to top. The cross-sectional area of ​​the pad 1 is larger than that of the simulation substrate 4 and is used to support the simulation substrate 4. Because the pad 1 is set flat, the end of the pad 1 facing the simulation substrate 4 is set flat, which ensures that the connecting layer 5 placed on the first end of the simulation substrate 4 will not be uneven due to the unevenness of the pad 1, thus improving the flatness of the connecting layer 5. The pad 1 can be placed only at the bottom of the simulation substrate 4 without being connected to the positioning plate 2. Alternatively, as needed, threaded holes can be provided on the pad 1. When the distance between the first end of the simulation substrate 4 and the second end of the simulation chip 6 reaches the required thickness of the connecting layer 5, the adjusting plate 3, the positioning plate 2, and the pad 1 are fixedly connected together by bolts or screws 9.

[0029] The analog substrate 4 and analog chip 6 may be made of copper, and / or the interconnect layer 5 may be made of silver nanoparticles. Alternatively, the analog chip 6 may be made of single-crystal silicon or a copper sheet with a silver-plated surface; the analog substrate 4 may also be a ceramic substrate. The interconnect layer 5 may be made of materials such as nano-copper or nano-nickel. Or, as... Figures 1-3 As shown, the analog substrate 4 and the analog chip 6 can also be copper bosses made of copper; or, the analog substrate 4 and the analog chip 6 can both be cylindrical structures. After the analog substrate 4 passes through the first through hole on the positioning plate 2, although there is a clearance fit between the analog substrate 4 and the positioning plate 2, existing high-temperature tape can be set on the outside of the analog substrate 4 to bond the analog substrate 4 to the positioning plate 2 and fix the position of the analog substrate 4. Alternatively, after the analog substrate 4 passes through the first through hole on the positioning plate 2, the analog substrate 4 and the positioning plate 2 can be soldered together by solder paste or other high-temperature soldering adhesive (the solder paste or high-temperature soldering adhesive needs to be able to detach the analog substrate 4 and the positioning plate 2 after heating). Alternatively, after the analog substrate 4 passes through the first through hole on the positioning plate 2, the analog substrate 4 and the positioning plate 2 can be connected together by other detachable and fixed connection methods. Similarly, after the analog chip 6 passes through the second through hole on the adjustment plate 3, although there is a clearance fit between the analog chip 6 and the adjustment plate 3, existing high-temperature tape can be applied to the outside of the analog chip 6 to bond the analog chip 6 to the adjustment plate 3 and fix its position. Alternatively, after the analog chip 6 passes through the second through hole on the adjustment plate 3, solder paste or other high-temperature soldering adhesive can be used to solder the analog chip 6 and the adjustment plate 3 together (the solder paste or high-temperature soldering adhesive must be able to detach the analog chip 6 and the adjustment plate 3 after heating). Or, after the analog chip 6 passes through the second through hole on the adjustment plate 3, other detachable and fixed connection methods can be used to connect the analog chip 6 and the adjustment plate 3 together.

[0030] Alternatively, a limiting part can be provided only on the cylindrical structure or other shapes required for the working condition. This limiting part can be held by the first positioning part to restrict the displacement of the analog substrate 4, and can be supported by the second positioning part to prevent the analog chip 6 from affecting the thickness of the interconnect layer 5. The limiting part can be a ring provided on the cylindrical structure or other shaped structure, or a number of protrusions spaced circumferentially along the cylindrical structure or other shaped structure, or other structures that can satisfy the above functions. For example Figure 4 As shown, the simulation substrate 4 is cylindrical, and the simulation chip 6 has a plate-like structure. The first end of the simulation substrate 4 and the second end of the simulation chip 6 refer to their opposite ends. The diameter of the first end of the simulation substrate 4 is 0.5mm~10mm, and the diameter of the second end of the simulation chip 6 is 200um~800um. Correspondingly, the size of the connecting layer 5 also becomes smaller, which enables the tensile testing method for sintered joints in this invention to achieve tensile testing of micro-sintered joints.

[0031] Step S3 includes: before the pull-out end of the pin 7 is soldered and fixed to the analog chip 6, a solder joint 8 of a preset size is soldered and fixed to the pull-out end of the pin 7. The pull-out end of the pin 7 is brought closer to the analog chip 6 and aligned with the analog chip 6. Then, the heating device heats the solder joint 8, so that the molten solder joint 8 can hang down to the end of the analog chip 6 away from the connecting layer 5 under its own weight. After the solder joint 8 cools and solidifies, the fixed connection between the pin 7 and the analog chip 6 is completed. The heating device can be a soldering iron or a hot air gun, etc., that can melt the solder joint 8; the solder joint 8 can be solder paste; solder paste, also known as soldering paste, is a paste-like mixture formed by mixing solder powder, flux, and other surfactants, thixotropic agents, etc., and the specific composition is in the prior art; solder paste can also be replaced by solder wire or other solder that can be used to solder the analog substrate 4 and the analog chip 6 together. The solder joint 8 can be allowed to cool and solidify naturally or a fan or other equipment can be used to supply cold air to the solder joint 8 to accelerate the cooling and solidification of the solder joint 8.

[0032] The tensile testing method for sintered joints includes: after fixing the position of the simulated substrate 4, a loading device applies corresponding thermal stress and / or current to the simulated substrate 4. The loading device includes a thermal stress loading unit and a current loading unit. The thermal stress loading unit includes heating devices such as infrared lamps or hot press welding heads. Care must be taken not to heat the solder joint 8 to a molten state during heating. The current loading unit includes a power supply connected to the simulated substrate 4 and providing the required current. The power supply can be connected to the simulated substrate 4 and the simulated chip 6 respectively through two electrode plates with opposite polarities. The pull-out needle 7 is a needle-like structure used for tensile testing; alternatively, if required by the test, the pull-out needle 7 can be replaced with a rod-like or block-like structure. The driving device can be a linear drive device such as a hydraulic cylinder or a pneumatic cylinder. The loading device applies corresponding thermal stress and / or current to the simulated substrate 4 to perform tensile testing of the sintered joint under thermal and / or electrical conditions. After the sintered joint is fabricated, when it is subjected to thermal stress or current loading within the corresponding shell, the operating window is the through hole pre-reserved on the shell; when the sintered joint is subjected to thermal stress or current loading in an open environment, the operating window is the space occupied by the moving needle. The placement, alignment, and other operations of the above structure can be completed by operators or existing multi-degree-of-freedom robots.

[0033] In this document, "several" refers to at least one. "And / or" refers to text content preceding and / or following it, which can exist simultaneously or individually. For example, A and / or B includes either only A or B, or both A and B. This invention discloses multiple technical solutions, but does not provide any contrary technical teachings. Any content not covered in this invention is applicable to existing technologies.

[0034] Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of this invention. Furthermore, those skilled in the art will recognize that, based on the ideas of this invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this invention.

Claims

1. A method for testing the tensile strength of a sintered joint, characterized in that, The tensile testing method for sintered joints includes the following: Step S1: Place the analog substrate, the interconnect layer, and the analog chip in sequence, and use welding equipment to weld and fix the three together to form a sintered joint. Step S2: Fix the position of the simulation substrate and leave an operation window, which is used for inserting the needle. Step S3: Align the pull-out end of the pin with the analog chip, and use the welding equipment to weld and fix the two together. Then, drive the device to pull the pin from the analog substrate toward the analog chip until the sintered joint breaks. When the pull-out end is aligned with the analog chip, the center line of the pull-out needle is coaxial with the center line of the analog chip, and the center line of the pull-out needle is perpendicular to the connecting layer. The output end of the drive device is connected to the needle pulling drive, and the needle pulling is connected to a tension sensor that is arranged to avoid the analog chip.

2. The tensile testing method for sintered joints according to claim 1, characterized in that, The tensile test method for sintered joints includes a test fixture, which includes a positioning plate and an adjustment plate. The positioning plate is provided with a plurality of adjacent first positioning parts and first through holes, and the adjustment plate is provided with a plurality of adjacent second positioning parts and second through holes. Step S1 includes the following: Step S1.1: Align the first end of the analog substrate with the corresponding first through hole, place the analog substrate and the positioning plate sequentially from bottom to top, and align the second end of the analog chip with the corresponding second through hole. Step S1.2: Align the first end of the analog substrate with the second end of the corresponding analog chip, and adjust the distance between the first end of the analog substrate and the second end of the analog chip according to the required thickness of the connecting layer. When the distance between the first end of the analog substrate and the second end of the analog chip reaches the required thickness of the connecting layer, place the connecting layer and connect the positioning plate and the adjustment plate. Step S1.3: The analog substrate, the connecting layer, and the analog chip are soldered and fixedly connected. Wherein, the first end of the simulation substrate is in clearance fit with the first through hole, the first positioning part abuts against the simulation substrate, and can apply a downward force to the simulation substrate; the second end of the simulation chip is in clearance fit with the second through hole, the second positioning part abuts against the simulation chip, and can apply an upward force to the simulation chip. The thickness direction of the connection layer is set from the analog substrate toward the analog chip.

3. The tensile testing method for sintered joints according to claim 2, characterized in that, The test fixture includes a limiting member. Step S1.2 includes placing the limiting member, which abuts against the positioning plate and the adjustment plate respectively, after aligning the first end of the simulation substrate with the second end of the corresponding simulation chip. The thickness of the limiting member is the distance between the positioning plate and the adjustment plate when the connecting layer reaches the required thickness.

4. The tensile testing method for sintered joints according to claim 2, characterized in that, The test fixture includes a fixing component, which is a screw, and both the positioning plate and the adjusting plate are provided with through threaded holes.

5. The tensile testing method for sintered joints according to claim 2, characterized in that, The test fixture includes a pad. Step S1.1 includes aligning the first end of the simulation substrate with the corresponding first through hole, and placing the pad, the simulation substrate, and the positioning plate sequentially from bottom to top. The cross-sectional area of ​​the pad is larger than that of the simulation substrate and is used to support the simulation substrate. The pad is placed horizontally and is flat at one end facing the simulation substrate.

6. The tensile testing method for sintered joints according to claim 1, characterized in that, The connecting layer is made of silver nanoparticles; and / or, the analog substrate and the analog chip are made of copper.

7. The tensile testing method for sintered joints according to claim 1, characterized in that, Both the analog substrate and the analog chip have copper bosses.

8. The tensile testing method for sintered joints according to claim 1, characterized in that, Step S3 includes: before the pull-out end of the pin is soldered and fixed to the analog chip, a solder joint of a preset size is soldered and fixed to the pull-out end of the pin; the pull-out end of the pin is brought closer to the analog chip and aligned with the analog chip; then the heating device heats the solder joint, so that the molten solder joint can hang down to the end of the analog chip away from the connection layer under its own weight; after the solder joint cools and solidifies, the fixed connection between the pin and the analog chip is completed.

9. The tensile testing method for sintered joints according to claim 1, characterized in that, The tensile testing method for the sintered joint includes: after fixing the position of the simulated substrate, a loading device applies corresponding thermal stress and / or current to the sintered joint.

10. The tensile testing method for sintered joints according to claim 1, characterized in that, The diameter of the first end of the analog substrate is 0.5mm to 10mm, and the diameter of the second end of the analog chip is 200um to 800um.