A mainboard working electric state test circuit

Abstract

The application discloses a mainboard working electric state test circuit, and relates to the technical field of mainboard test, which comprises a mainboard module, a micro-control module and an output test module. Compared with the prior art, the mainboard working electric state test circuit has the advantages that the micro-control module cooperates with the output test module to automatically capture twice rising edge signals during the IO port output state and perform differential error comparison, the output level distortion and timing abnormality can be accurately identified, the detection reliability is high, the signal voltage of the normal IO port is recorded and used as a reference to generate an input test voltage, the input test module is combined with the gating switch and voltage comparison to realize batch rapid screening of the multi-channel IO port input threshold response, and the working voltage and port voltage of the mainboard do not need to be known in advance, thereby realizing adaptive matching of the test conditions.

Description

Technical Field

[0001] This invention relates to the field of motherboard testing technology, specifically a motherboard operating electrical status testing circuit. Background Technology

[0002] During the manufacturing and R&D debugging of motherboards, accurate testing of the voltage characteristics of their general-purpose input / output interfaces (I / O ports) is a core aspect of ensuring the functional integrity and long-term reliability of the motherboard. Currently, the testing of the operating electrical status of motherboard I / O ports mainly employs the following methods: manual point-by-point measurement using general-purpose instruments such as digital multimeters and oscilloscopes. This method is cumbersome, time-consuming, and manual readings are easily affected by subjective factors and contact resistance, resulting in poor repeatability and consistency. Some companies use dedicated functional test fixtures or automated testing equipment based on boundary scans, which can achieve batch testing to a certain extent, but the equipment architecture is usually complex, expensive, and has a long test program development cycle, with poor compatibility with different motherboard models. In addition, for motherboard I / O input and output testing, the operating voltage of the motherboard must be known in advance to determine the voltage of the I / O ports, making independent testing impossible. Therefore, there is an urgent need for an integrated, intelligent, and cost-controllable motherboard operating electrical status testing circuit to achieve status detection of multiple I / O ports on the motherboard. Summary of the Invention

[0003] This invention provides a motherboard operating electrical status test circuit to solve the problems mentioned in the background art.

[0004] According to an embodiment of the present invention, a motherboard operating electrical state test circuit is provided, comprising:

[0005] The motherboard module is used to connect to the motherboard.

[0006] The microcontroller module connects to the motherboard module, input test module, and output test module. It communicates with the motherboard and configures multiple I / O ports of the motherboard to output or input states. During the output state, it records the time from the start to the end of the rising edge of the I / O port detected by the output test module. After the second rising edge of the I / O port reaches the recorded time, it outputs the first switching signal. Based on the error comparison output signal of the output test module, it determines whether the I / O port has an output abnormality and records the signal voltage of the normal I / O port. During the input state, it controls the input test module to output a voltage equal to the recorded signal voltage based on the recorded signal voltage of the normal I / O port, and controls the input test module to switch the signal transmission path sequentially. Based on the voltage comparison output signal of the input detection module, it determines whether the I / O port has an input abnormality.

[0007] The output test module connects to the motherboard module and is used to transmit signals output from multiple I / O ports of the motherboard. During the first rising edge of the transmitted signal from the motherboard's I / O port, real-time signal sampling is performed, and signal holding is performed after the rising edge ends. During the second rising edge of the transmitted signal from the I / O port, the real-time sampled signal and the held signal are differentially amplified and absolute value processed, and the signal after absolute value processing is compared with the set error threshold. When the first switching signal is received, the remaining I / O ports of the motherboard are selected to be transmitted in sequence, and error comparison and detection are performed.

[0008] The input test module connects to the motherboard module and is used to regulate and limit the DC power input. It sequentially switches the signal transmission path to input the processed power into multiple I / O ports of the motherboard and compares the voltage of the motherboard I / O port receiving the power with the set voltage threshold.

[0009] As a further embodiment of the present invention: the output test module includes an output gating unit and a signal self-testing unit;

[0010] The output gating unit is used to transmit signals output from multiple I / O ports of the motherboard, and when it receives the first switching signal, it will sequentially select and transmit signals output from the I / O ports of the motherboard.

[0011] The signal self-test unit, connected to the output gating unit, is used to perform real-time signal sampling during the first rising edge of the signal output from the I / O port of the transmitting motherboard, and to perform signal holding processing after the rising edge ends. During the second rising edge of the signal output from the I / O port, the real-time sampled signal and the held signal are differentially amplified and absolute value processed, and the signal after absolute value processing is compared with the set error threshold.

[0012] As a further embodiment of the present invention: the input test module includes a detection source unit, an input gating unit, and a state detection unit;

[0013] The detection source unit is used to regulate and limit the voltage of the incoming DC power.

[0014] The input gating unit, connected to the detection source unit, is used to sequentially input the processed electrical energy into multiple I / O ports of the motherboard by switching the signal transmission path in sequence.

[0015] The status detection unit, connected to the input gating unit, is used to compare the voltage of the motherboard I / O port in power receiving mode with a set voltage threshold.

[0016] As a further embodiment of the present invention: the motherboard module includes a motherboard connection interface; the output selection unit includes a first analog switch, a first logic device, a first diode, a second diode, a third diode, and a first counter; the microcontroller module includes a first controller;

[0017] Preferably, the first, second, third, and fourth IO ports of the motherboard connection interface are connected to the third, eighth, tenth, and first terminals of the first analog switch, respectively. The fourth terminal of the first analog switch is connected to the IO4 terminal, the ninth, eleventh, and second terminals of the first controller. The fifth terminal of the first analog switch is connected to the output terminal of the first logic device. The first input terminal of the first logic device is connected to the IO1 terminal of the first controller. The second input terminal of the first logic device is connected to the cathodes of the first, second, and third diodes. The anode of the first diode is connected to the sixth terminal of the first analog switch and the Q0 terminal of the first counter. The anode of the second diode is connected to the twelfth terminal of the first analog switch and the Q1 terminal of the first counter. The anode of the third diode is connected to the thirteenth terminal of the first analog switch and the Q2 terminal of the first counter. The CP terminal of the first analog switch is connected to the IO8 terminal of the first controller. The first and second communication terminals of the motherboard connection interface are connected to the SDA and SCL terminals of the first controller, respectively.

[0018] As a further embodiment of the present invention: the signal self-test unit includes a first flip-flop, a second flip-flop, a first operational amplifier, a second operational amplifier, a first inverter, a first switching transistor, a first resistor, a first regulator, and a first capacitor;

[0019] Preferably, the CP terminal of the first flip-flop is connected to the input terminal of the first inverter, the non-inverting terminal of the first operational amplifier, and the fourth terminal of the first analog switch; the inverting terminal and output terminal of the first operational amplifier are connected to the drain of the first regulating transistor; the source of the first regulating transistor is connected to the non-inverting terminal of the second operational amplifier and connected to the emitter and low-end of the first switching transistor through the first capacitor; the input terminal of the first inverter is connected to the base of the first switching transistor and the IO3 terminal of the first controller; the collector of the first switching transistor is connected to the gate of the first regulating transistor and connected to the Q2 terminal of the first flip-flop, the CP terminal of the second flip-flop, and the IO2 terminal of the first controller through the first resistor; the D terminal of the first flip-flop is connected to the Q1 terminal of the first flip-flop; the D terminal of the second flip-flop is connected to the Q1 terminal of the second flip-flop; and the inverting terminal of the second operational amplifier is connected to the output terminal of the second operational amplifier.

[0020] As a further embodiment of the present invention: the signal self-test unit further includes a second analog switch, a second resistor, a third resistor, and a signal processing device;

[0021] Preferably, the third terminal of the second analog switch is connected to the output terminal of the second operational amplifier, the eighth terminal of the second analog switch is connected to the second terminal of the first analog switch, the fifth and sixth terminals of the second analog switch are connected to the Q2 terminal of the second flip-flop, the fourth terminal of the second analog switch is connected to the first input terminal of the signal processing device through the second resistor, and the ninth terminal of the second analog switch is connected to the second input terminal of the signal processing device through the third resistor.

[0022] As a further embodiment of the present invention: the signal self-test unit includes a first comparator, a second comparator, and a first reference source;

[0023] Preferably, the non-inverting input of the first comparator is connected to the inverting input of the second comparator and the output of the signal processing device, the inverting input of the first comparator is connected to the non-inverting input of the second comparator and the first reference source, and the outputs of the first and second comparators are respectively connected to the IO6 and IO7 terminals of the first controller.

[0024] As a further embodiment of the present invention: the detection source unit includes a power interface, a first voltage regulator, a first power transistor, a fourth resistor, a fifth resistor, a sixth resistor, and a seventh resistor;

[0025] Preferably, the first end of the power interface is connected to the VIN end of the first voltage regulator, the OUT end of the first voltage regulator is connected to one end of the fifth resistor and is connected to the IO9 end of the first controller and one end of the seventh resistor through the sixth resistor, the other end of the fifth resistor is connected to the GND end of the first voltage regulator and the drain of the first power transistor, and the source of the first power transistor is connected to the other end of the seventh resistor, the second end of the power interface and the ground through the fourth resistor.

[0026] As a further embodiment of the present invention: the input gating unit includes an eighth resistor and a third analog switch;

[0027] Preferably, the first end of the eighth resistor is connected to the OUT terminal of the first voltage regulator, the second end of the eighth resistor is connected to the third, eighth, tenth and first terminals of the third analog switch, the fourth, ninth, eleventh and second terminals of the third analog switch are respectively connected to the first, second, third and fourth I / O ports of the motherboard connection interface, and the fifth, sixth, twelfth and thirteenth terminals of the third analog switch are respectively connected to the I / O 11, I / O 12, I / O 13 and I / O 14 terminals of the first controller.

[0028] As a further embodiment of the present invention: the state detection unit includes a third comparator and a second reference source;

[0029] Preferably, the inverting input of the third comparator is connected to the second terminal of the eighth resistor, the non-inverting input of the third comparator is connected to the second reference source, and the output terminal of the third comparator is connected to the IO15 terminal of the first controller.

[0030] Compared with the prior art, the beneficial effects of the present invention are as follows: The motherboard operating power status test circuit of the present invention, through the collaboration of the microcontroller module and the output test module, automatically captures two rising edge signals and performs differential error comparison during the output state of the IO port, which can accurately identify output level distortion and timing abnormalities, and has high detection reliability. By recording the signal voltage of the normal IO port and using it as a reference to generate the input test voltage, combined with the gating and switching of the input test module and voltage comparison, it can achieve batch rapid screening of the input threshold response of multiple IO ports, significantly improving the testing efficiency. Moreover, it does not require prior knowledge of the motherboard's operating voltage and port voltage, reducing the testing requirements and achieving adaptive matching of test conditions. The microcontroller module automatically completes the state configuration, channel switching and abnormal judgment without manual intervention, making it suitable for large-scale online testing scenarios in motherboard production lines. Attached Figure Description

[0031] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a schematic block diagram of a motherboard operating electrical status test circuit provided in an embodiment of the present invention.

[0033] Figure 2 This is a block diagram illustrating the principle of the output test module provided in an embodiment of the present invention.

[0034] Figure 3 This is a block diagram illustrating the principle of the input testing module provided in an embodiment of the present invention.

[0035] Figure 4 This is a circuit diagram of a motherboard operating electrical status test circuit provided in an embodiment of the present invention.

[0036] Figure 5 The circuit diagram of the detection source unit provided in the embodiment of the present invention.

[0037] Figure 6 The circuit diagram is provided for the input gating unit in an embodiment of the present invention.

[0038] Figure 7 A circuit diagram of a state detection unit provided in an embodiment of the present invention. Detailed Implementation

[0039] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0040] Please see Figure 1 , Figure 2 and Figure 3 A motherboard operating electrical status test circuit, comprising:

[0041] Motherboard module 1, used for connection to the motherboard;

[0042] Microcontroller module 2, connected to motherboard module 1, input test module 4, and output test module 3, communicates with the motherboard and configures multiple I / O ports of the motherboard to output or input states. During the output state, it records the time from the start to the end of the rising edge of the I / O port detected by output test module 3, and outputs a first switching signal after the second rising edge of the I / O port reaches the recorded time. Based on the error comparison output signal of output test module 3, it determines whether the I / O port has an output abnormality and records the signal voltage of the normal I / O port. During the input state, it controls input test module 4 to output a voltage equal to the recorded signal voltage based on the recorded signal voltage of the normal I / O port, and controls input test module 4 to switch signal transmission paths sequentially. Based on the voltage comparison output signal of input detection module, it determines whether the I / O port has an input abnormality.

[0043] Output test module 3 is connected to motherboard module 1 and is used to transmit signals output from multiple I / O ports of the motherboard. During the first rising edge of the transmitted signal output from the motherboard's I / O port, real-time signal sampling is performed and signal holding is performed after the rising edge ends. During the second rising edge of the transmitted signal output from the I / O port, the real-time sampled signal and the held signal are differentially amplified and absolute value processed, and the signal after absolute value processing is compared with the set error threshold. When the first switching signal is received, the remaining I / O ports of the motherboard will be selected sequentially for transmission and error comparison detection will be performed.

[0044] Input test module 4 is connected to motherboard module 1. It is used to regulate and limit the DC power input and input the processed power into multiple I / O ports of the motherboard by switching the signal transmission path in sequence. It also compares the voltage of the motherboard I / O port receiving power with the set voltage threshold.

[0045] Furthermore, the output test module 3 includes an output gating unit 301 and a signal self-testing unit 302;

[0046] The output gating unit 301 is used to transmit signals output from multiple I / O ports of the motherboard and, upon receiving the first switching signal, will sequentially select and transmit signals output from the I / O ports of the motherboard.

[0047] The signal self-test unit 302 is connected to the output gating unit 301. It is used to perform real-time signal sampling during the first rising edge of the signal output from the IO port of the transmitting motherboard and to perform signal holding processing after the rising edge ends. During the second rising edge of the signal output from the IO port, it performs differential amplification and absolute value processing on the real-time sampled signal and the held signal, and compares the signal after absolute value processing with the set error threshold.

[0048] Furthermore, the input test module 4 includes a detection source unit 401, an input gating unit 402, and a status detection unit 403;

[0049] The detection source unit 401 is used to regulate and limit the voltage of the incoming DC power.

[0050] The input gating unit 402 is connected to the detection source unit 401 and is used to sequentially input the processed electrical energy into multiple I / O ports of the motherboard by switching the signal transmission path in sequence.

[0051] The status detection unit 403, connected to the input gating unit 402, is used to compare the voltage of the motherboard I / O port in power receiving mode with a set voltage threshold.

[0052] In a specific embodiment, the aforementioned motherboard module 1 can be a motherboard circuit composed of motherboard connection interfaces, which can be connected to the motherboard's I / O ports and communication ports to realize the detection of the motherboard's I / O ports, communication with the motherboard's communication ports, and then control the motherboard's configured I / O ports to uniformly enter the input state or output state; the aforementioned microcontroller module 2 can be a microcontroller circuit composed of a single-chip microcomputer, integrating many components such as an arithmetic unit, a controller, a memory, and input / output devices, to realize functions such as signal processing, data storage, module control, and timing control; the aforementioned output test module 3 can be an output test circuit composed of operational amplifiers, capacitors, analog switches, flip-flops, comparators, etc., controlled by the microcontroller module 2 to select the signal transmission path, and then transmit the signals output from the motherboard's multiple I / O ports. During the first rising edge of the transmitted signal, real-time signal sampling can be performed, and after the rising edge ends, the real-time sampled signal is held. During the second rising edge of the signal output from the I / O port transmitted through this path, the real-time sampled signal during the second rising edge is... The signal and the held signal are differentially amplified and absolute value processed. The signal after absolute value processing is compared with a set error threshold, which is set as needed. This error threshold is used to detect whether there is a large difference in voltage between two rising edges. When the voltage error between the two rising edges of the signal output by the IO port is less than the error threshold, it indicates that the IO port is normal. The microcontroller module 2 counts and records the voltage of the signals output by all IO ports in normal state. Then, the microcontroller module 2 controls the input test module 4 to output a voltage equal to the recorded signal voltage based on the recorded normal IO port signal voltage. The input test module 4 can be an input test circuit composed of a voltage regulator, field-effect transistor, analog switch, comparator, etc. It regulates the voltage of the connected DC power and is controlled by the microcontroller module 2 to select the signal path and sequentially input the regulated voltage to the IO ports of the motherboard. It detects the voltage of the motherboard IO port and the voltage of the set voltage threshold. When the voltage of the motherboard IO port is less than the voltage threshold, it indicates that there is an input abnormality in the IO port.

[0053] In this embodiment, please refer to Figure 4 The motherboard module 1 includes a motherboard connection interface; the output selection unit 301 includes a first analog switch IC1, a first logic device J3, a first diode D1, a second diode D2, a third diode D3, and a first counter IC4; the microcontroller module 2 includes a first controller U1;

[0054] Specifically, the first, second, third, and fourth I / O ports of the motherboard connection interface are respectively connected to the third, eighth, tenth, and first terminals of the first analog switch IC1. The fourth terminal of the first analog switch IC1 is connected to the IO4 terminal, the ninth, eleventh, and second terminals of the first controller U1. The fifth terminal of the first analog switch IC1 is connected to the output terminal of the first logic device J3. The first input terminal of the first logic device J3 is connected to the IO1 terminal of the first controller U1. The second input terminal of the first logic device J3 is connected to the cathode of the first diode D1 and the cathode of the second diode D2. The cathodes of diodes 2 and 3 are connected. The anode of the first diode D1 is connected to the sixth terminal of the first analog switch IC1 and the Q0 terminal of the first counter IC4. The anode of the second diode D2 is connected to the twelfth terminal of the first analog switch IC1 and the Q1 terminal of the first counter IC4. The anode of the third diode D3 is connected to the thirteenth terminal of the first analog switch IC1 and the Q2 terminal of the first counter IC4. The CP terminal of the first analog switch IC1 is connected to the IO8 terminal of the first controller U1. The first communication terminal and the second communication terminal of the motherboard connection interface are respectively connected to the SDA terminal and the SCL terminal of the first controller U1.

[0055] In a specific embodiment, the first and second communication terminals of the aforementioned motherboard connection port can be connected to the motherboard's IO expansion chip to complete the communication between the first controller U1 and the motherboard. The IO expansion chip can be an MCP23017; the aforementioned first analog switch IC1 can be a CD4066; the aforementioned first controller U1 can be an STM32 microcontroller; the aforementioned first counter IC4 can be a CD4017; and the aforementioned first logic device J3 can be an XOR gate.

[0056] Furthermore, the signal self-test unit 302 includes a first flip-flop J1, a second flip-flop J2, a first operational amplifier OP1, a second operational amplifier OP2, a first inverter INV1, a first switching transistor V1, a first resistor R1, a first regulator M1, and a first capacitor C1;

[0057] Specifically, the CP terminal of the first flip-flop J1 is connected to the input terminal of the first inverter INV1, the non-inverting terminal of the first operational amplifier OP1, and the fourth terminal of the first analog switch IC1. The inverting terminal and output terminal of the first operational amplifier OP1 are connected to the drain of the first regulating transistor. The source of the first regulating transistor is connected to the non-inverting terminal of the second operational amplifier OP2 and is connected to the emitter and low end of the first switching transistor V1 through the first capacitor C1. The input terminal of the first inverter INV1 is connected to the base of the first switching transistor V1 and the IO3 terminal of the first controller U1. The collector of the first switching transistor V1 is connected to the gate of the first regulating transistor and is connected to the Q2 terminal of the first flip-flop J1, the CP terminal of the second flip-flop J2, and the IO2 terminal of the first controller U1 through the first resistor R1. The D terminal of the first flip-flop J1 is connected to the Q1 terminal of the first flip-flop J1. The D terminal of the second flip-flop J2 is connected to the Q1 terminal of the second flip-flop J2. The inverting terminal of the second operational amplifier OP2 is connected to the output terminal of the second operational amplifier OP2.

[0058] In a specific embodiment, both the first flip-flop J1 and the second flip-flop J2 can be D flip-flops. At the first rising edge of the signal, the first flip-flop J1 outputs a high level, and at the second rising edge, the second flip-flop J2 outputs a high level. Both the first operational amplifier OP1 and the second operational amplifier OP2 can be OP07 operational amplifiers. The first inverter INV1 can be a NOT gate. The first regulating transistor can be a junction N-channel field-effect transistor. The first capacitor C1 is used for signal sampling and holding. The first switching transistor V1 can be an NPN transistor.

[0059] Furthermore, the signal self-test unit 302 also includes a second analog switch IC2, a second resistor R2, a third resistor R3, and a signal processing device;

[0060] Specifically, the third terminal of the second analog switch IC2 is connected to the output terminal of the second operational amplifier OP2, the eighth terminal of the second analog switch IC2 is connected to the second terminal of the first analog switch IC1, the fifth and sixth terminals of the second analog switch IC2 are connected to the Q2 terminal of the second flip-flop J2, the fourth terminal of the second analog switch IC2 is connected to the first input terminal of the signal processing device through the second resistor R2, and the ninth terminal of the second analog switch IC2 is connected to the second input terminal of the signal processing device through the third resistor R3.

[0061] In a specific embodiment, the second analog switch IC2 can be selected as CD4066; the signal processing device can be composed of a differential amplifier circuit and an absolute value circuit to perform differential amplification processing on the input signal, and the differential amplifier circuit can output a negative value, which is then processed by the absolute value circuit.

[0062] Furthermore, the signal self-test unit 302 includes a first comparator A1, a second comparator A2, and a first reference source VF1;

[0063] Specifically, the non-inverting input of the first comparator A1 is connected to the inverting input of the second comparator A2 and the output of the signal processing device, the inverting input of the first comparator A1 is connected to the non-inverting input of the second comparator A2 and the first reference source VF1, and the output of the first comparator A1 and the output of the second comparator A2 are respectively connected to the IO6 and IO7 terminals of the first controller U1.

[0064] In a specific embodiment, both the first comparator A1 and the second comparator A2 can be selected from LM358 comparators; the first reference source VF1 can provide an error threshold.

[0065] In this embodiment, please refer to Figure 5 , Figure 6 and Figure 7 The detection source unit 401 includes a power interface, a first voltage regulator U2, a first power transistor Q1, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, and a seventh resistor R7.

[0066] Specifically, the first end of the power interface is connected to the VIN terminal of the first voltage regulator U2. The OUT terminal of the first voltage regulator U2 is connected to one end of the fifth resistor R5 and then connected to the IO9 terminal of the first controller U1 and one end of the seventh resistor R7 through the sixth resistor R6. The other end of the fifth resistor R5 is connected to the GND terminal of the first voltage regulator U2 and the drain of the first power transistor Q1. The source of the first power transistor Q1 is connected to the other end of the seventh resistor R7, the second end of the power interface, and the ground terminal through the fourth resistor R4.

[0067] In a specific embodiment, the first voltage regulator U2 can be an LM317 voltage regulator; the first power transistor Q1 can be an N-channel MOSFET, whose conduction state is controlled by the IO10 terminal of the first controller U1, and the voltage output of the first voltage regulator U2 is adjusted in conjunction with the fourth resistor R4 and the fifth resistor R5. The voltage is equal to the normal signal voltage of the IO port recorded by the first controller U1.

[0068] Furthermore, the input gating unit 402 includes an eighth resistor R8 and a third analog switch IC3;

[0069] Specifically, the first end of the eighth resistor R8 is connected to the OUT terminal of the first voltage regulator U2, the second end of the eighth resistor R8 is connected to the third, eighth, tenth and first terminals of the third analog switch IC3, the fourth, ninth, eleventh and second terminals of the third analog switch IC3 are respectively connected to the first, second, third and fourth IO ports of the motherboard connection interface, and the fifth, sixth, twelfth and thirteenth terminals of the third analog switch IC3 are respectively connected to the IO11, IO12, IO13 and IO14 terminals of the first controller U1.

[0070] In a specific embodiment, the third analog switch IC3 mentioned above can be a CD4066.

[0071] Furthermore, the state detection unit 403 includes a third comparator A3 and a second reference source VF2;

[0072] Specifically, the inverting input of the third comparator A3 is connected to the second terminal of the eighth resistor R8, the non-inverting input of the third comparator A3 is connected to the second reference source VF2, and the output terminal of the third comparator A3 is connected to the IO15 terminal of the first controller U1.

[0073] In a specific embodiment, the third comparator A3 can be an LM358 comparator; the second reference source VF2 can be set with a voltage threshold.

[0074] The working principle of a motherboard operating electrical state test circuit of the present invention is as follows: The first, second, third, and fourth I / O ports of the motherboard connection interface are respectively connected to four sets of I / O ports on the motherboard. The SDA and SCL terminals of the first controller U1 communicate with the motherboard through the first and second communication terminals of the motherboard connection interface, configuring multiple I / O ports of the motherboard into output or input states. During the output state, the I / O1 terminal of the first controller U1 controls the first input terminal of the first logic device J3 to be high, and the first logic device J3 controls the third and fourth terminals of the first analog switch IC1 to be turned on. The first analog switch IC1 transmits the signal output from a set of I / O ports of the motherboard connected to the first I / O port of the motherboard connection interface. This signal is... At the first rising edge, the Q2 terminal of the first flip-flop J1 outputs a high level. The IO2 terminal of the first controller U1 receives this signal and starts timing, triggering the second regulating transistor to conduct. The first operational amplifier OP1 performs voltage following and the signal is sampled by the first capacitor C1. This continues until the first rising edge ends. The first inverter INV1 triggers the first switching transistor V1 to conduct, and the IO3 terminal of the first controller U1 receives this signal and stops timing. The obtained timing time is the rising edge time of the signal. At the same time, the second regulating transistor is turned off, and the first capacitor C1 performs signal holding processing until the second rising edge of the IO port arrives. The Q2 terminal of the second flip-flop J2 outputs a high level, and the third and fourth terminals of the second analog switch IC2 are connected to the eighth and ninth terminals. At this time, the voltage of the second rising edge is... The voltage held by the first capacitor C1 at the first rising edge is differentially amplified and its absolute value processed by the second resistor R2, the third resistor R3, and the signal processing device. This outputs the voltage error of two sets of rising edges. When the error exceeds the error threshold provided by the first reference source VF1, the first comparator A1 outputs a high level, which is received by the IO7 pin of the first controller U1, indicating a significant difference between the two signals and an abnormality in the I / O port. If the error is less than the error threshold, the second comparator A2 outputs a high level, which is received by the IO6 pin of the first controller U1. At this time, the I / O port may be normal. The IO4 pin of the first controller U1 records the voltage of this I / O port, and when the second rising edge reaches its timing interval, the IO8 pin of the first controller U1 outputs the first switching signal, triggering the second rising edge... A high-level output from the Q0 terminal of counter IC4 triggers the conduction of the eighth and ninth terminals of the first analog switch IC1. Similarly, the self-test unit 302 compares the error of the signals output from the second group of I / O ports on the motherboard. When the error is less than the error threshold, the first controller U1 records the voltage of the I / O port. After the second rising edge of the I / O port reaches the timing time, the first switching signal is output again to control the first analog switch IC1 to switch the path again, so as to complete the output status detection of the third group of I / O ports, the fourth group of I / O ports, etc. on the motherboard. The first controller U1 calculates the average value of all recorded I / O port voltages. I / O ports with a large difference from the average voltage are determined to be abnormal, and I / O ports with a voltage close to the average voltage are determined to be normal.The average voltage is selected as the port voltage of the motherboard. Then, the IO10 terminal of the first controller U1 controls the conduction state of the first power transistor Q1, thereby adjusting the regulated voltage output of the first regulator U2. This regulated voltage is equal to the selected average voltage. Next, the first controller U1 communicates with the motherboard, controlling the motherboard to configure the IO port as an input state. The IO11, IO12, IO13, and IO14 terminals of the first controller U1 output high levels sequentially with the same duration. Specifically, when the IO11 terminal of the first controller U1 controls the third and fourth terminals of the third analog switch IC3 to conduct, the regulated voltage will be input to the first IO port of the motherboard connection interface. At this time, the third comparator A3 and the second reference source V... F2 will detect the voltage of the first I / O port of the motherboard connection interface. The second reference source VF2 provides a voltage threshold, which can be obtained by voltage regulation and voltage reduction through a resistor, with a reduction range of 0.1V to 0.5V. When the voltage is lower than the voltage threshold, the third comparator A3 outputs a high level, which is received by the IO15 terminal of the first controller U1, indicating that there is an abnormality in the input state of this I / O port. Similarly, when the IO12 terminal of the first controller U1 controls the eighth and ninth terminals of the third analog switch IC3 to conduct, the input state of the second I / O port of the motherboard connection interface is detected. The input states of the third and fourth I / O ports of the motherboard interface are then detected sequentially by the IO13 and IO14 terminals of the first controller U1, respectively.

[0075] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0076] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A motherboard operating electrical status test circuit, characterized in that, The circuit includes: The motherboard module is used to connect to the motherboard. The microcontroller module connects to the motherboard module, input test module, and output test module. It communicates with the motherboard and configures multiple I / O ports of the motherboard to output or input states. During the output state, it records the time from the start to the end of the rising edge of the I / O port detected by the output test module. After the second rising edge of the I / O port reaches the recorded time, it outputs the first switching signal. Based on the error comparison output signal of the output test module, it determines whether the I / O port has an output abnormality and records the signal voltage of the normal I / O port. During the input state, it controls the input test module to output a voltage equal to the recorded signal voltage based on the recorded signal voltage of the normal I / O port, and controls the input test module to switch the signal transmission path sequentially. Based on the voltage comparison output signal of the input detection module, it determines whether the I / O port has an input abnormality. The output test module connects to the motherboard module and is used to transmit signals output from multiple I / O ports of the motherboard. During the first rising edge of the transmitted signal from the motherboard's I / O port, real-time signal sampling is performed, and signal holding is performed after the rising edge ends. During the second rising edge of the transmitted signal from the I / O port, the real-time sampled signal and the held signal are differentially amplified and absolute value processed, and the signal after absolute value processing is compared with the set error threshold. When the first switching signal is received, the remaining I / O ports of the motherboard are selected to be transmitted in sequence, and error comparison and detection are performed. The input test module connects to the motherboard module and is used to regulate and limit the DC power input. It sequentially switches the signal transmission path to input the processed power into multiple I / O ports of the motherboard and compares the voltage of the motherboard I / O port receiving the power with the set voltage threshold.

2. The motherboard operating electrical status test circuit according to claim 1, characterized in that, The output test module includes an output gating unit and a signal self-test unit; The output gating unit is used to transmit signals output from multiple I / O ports of the motherboard, and when it receives the first switching signal, it will sequentially select and transmit signals output from the I / O ports of the motherboard. The signal self-test unit, connected to the output gating unit, is used to perform real-time signal sampling during the first rising edge of the signal output from the I / O port of the transmitting motherboard, and to perform signal holding processing after the rising edge ends. During the second rising edge of the signal output from the I / O port, the real-time sampled signal and the held signal are differentially amplified and absolute value processed, and the signal after absolute value processing is compared with the set error threshold.

3. The motherboard operating electrical status test circuit according to claim 2, characterized in that, The input testing module includes a detection source unit, an input gating unit, and a state detection unit; The detection source unit is used to regulate and limit the voltage of the incoming DC power. The input gating unit, connected to the detection source unit, is used to sequentially input the processed electrical energy into multiple I / O ports of the motherboard by switching the signal transmission path in sequence. The status detection unit, connected to the input gating unit, is used to compare the voltage of the motherboard I / O port in power receiving mode with a set voltage threshold.

4. The motherboard operating electrical status test circuit according to claim 3, characterized in that, The motherboard module includes a motherboard connection interface; the output selection unit includes a first analog switch, a first logic unit, a first diode, a second diode, a third diode, and a first counter; the microcontroller module includes a first controller; The first, second, third, and fourth IO ports of the motherboard connection interface are respectively connected to the third, eighth, tenth, and first terminals of the first analog switch. The fourth terminal of the first analog switch is connected to the IO4 terminal, the ninth, eleventh, and second terminals of the first controller. The fifth terminal of the first analog switch is connected to the output terminal of the first logic device. The first input terminal of the first logic device is connected to the IO1 terminal of the first controller. The second input terminal of the first logic device is connected to the cathodes of the first, second, and third diodes. The anode of the first diode is connected to the sixth terminal of the first analog switch and the Q0 terminal of the first counter. The anode of the second diode is connected to the twelfth terminal of the first analog switch and the Q1 terminal of the first counter. The anode of the third diode is connected to the thirteenth terminal of the first analog switch and the Q2 terminal of the first counter. The CP terminal of the first analog switch is connected to the IO8 terminal of the first controller. The first and second communication terminals of the motherboard connection interface are respectively connected to the SDA and SCL terminals of the first controller.

5. The motherboard operating electrical status test circuit according to claim 4, characterized in that, The signal self-test unit includes a first flip-flop, a second flip-flop, a first operational amplifier, a second operational amplifier, a first inverter, a first switching transistor, a first resistor, a first regulator, and a first capacitor; The CP terminal of the first flip-flop is connected to the input terminal of the first inverter, the non-inverting terminal of the first operational amplifier, and the fourth terminal of the first analog switch. The inverting terminal and output terminal of the first operational amplifier are connected to the drain of the first regulating transistor. The source of the first regulating transistor is connected to the non-inverting terminal of the second operational amplifier and is connected to the emitter and low-end of the first switching transistor through the first capacitor. The input terminal of the first inverter is connected to the base of the first switching transistor and the IO3 terminal of the first controller. The collector of the first switching transistor is connected to the gate of the first regulating transistor and is connected to the Q2 terminal of the first flip-flop, the CP terminal of the second flip-flop, and the IO2 terminal of the first controller through the first resistor. The D terminal of the first flip-flop is connected to the Q1 terminal of the first flip-flop. The D terminal of the second flip-flop is connected to the Q1 terminal of the second flip-flop. The inverting terminal of the second operational amplifier is connected to the output terminal of the second operational amplifier.

6. The motherboard operating electrical status test circuit according to claim 5, characterized in that, The signal self-test unit also includes a second analog switch, a second resistor, a third resistor, and a signal processing device; The third terminal of the second analog switch is connected to the output terminal of the second operational amplifier, the eighth terminal of the second analog switch is connected to the second terminal of the first analog switch, the fifth and sixth terminals of the second analog switch are connected to the Q2 terminal of the second flip-flop, the fourth terminal of the second analog switch is connected to the first input terminal of the signal processing device through the second resistor, and the ninth terminal of the second analog switch is connected to the second input terminal of the signal processing device through the third resistor.

7. The motherboard operating electrical status test circuit according to claim 6, characterized in that, The signal self-test unit includes a first comparator, a second comparator, and a first reference source; The non-inverting input of the first comparator is connected to the inverting input of the second comparator and the output of the signal processing device. The inverting input of the first comparator is connected to the non-inverting input of the second comparator and the first reference source. The outputs of the first and second comparators are respectively connected to the IO6 and IO7 terminals of the first controller.

8. The motherboard operating electrical status test circuit according to claim 7, characterized in that, The detection source unit includes a power interface, a first voltage regulator, a first power transistor, a fourth resistor, a fifth resistor, a sixth resistor, and a seventh resistor; The first end of the power interface is connected to the VIN end of the first voltage regulator. The OUT end of the first voltage regulator is connected to one end of the fifth resistor and is connected to the IO9 end of the first controller and one end of the seventh resistor through the sixth resistor. The other end of the fifth resistor is connected to the GND end of the first voltage regulator and the drain of the first power transistor. The source of the first power transistor is connected to the other end of the seventh resistor, the second end of the power interface, and the ground end through the fourth resistor.

9. A motherboard operating electrical status test circuit according to claim 8, characterized in that, The input gating unit includes an eighth resistor and a third analog switch; The first end of the eighth resistor is connected to the OUT terminal of the first voltage regulator. The second end of the eighth resistor is connected to the third, eighth, tenth and first terminals of the third analog switch. The fourth, ninth, eleventh and second terminals of the third analog switch are respectively connected to the first, second, third and fourth I / O ports of the motherboard connection interface. The fifth, sixth, twelfth and thirteenth terminals of the third analog switch are respectively connected to the I / O11, I / O12, I / O13 and I / O14 terminals of the first controller.

10. A motherboard operating electrical status test circuit according to claim 9, characterized in that, The state detection unit includes a third comparator and a second reference source; The inverting input of the third comparator is connected to the second terminal of the eighth resistor, the non-inverting input of the third comparator is connected to the second reference source, and the output terminal of the third comparator is connected to the IO15 terminal of the first controller.

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