Chip and method of manufacturing a chip
Patent Information
- Application Number
- CN202510401952.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-31
- Publication Date
- 2026-10-13
AI Technical Summary
[0003]本申请提供了一种芯片及芯片的制造方法，旨在解决现有技术中光波导表面粗糙问题
[0017]本申请实施例中，通过第一刻蚀工艺形成多个空隙和深沟槽后，在每次循环步骤中在深沟槽和多个空隙中形成填充材料，再进行第二刻蚀工艺。在进行第二刻蚀工艺时，刻蚀气体无法直接接触深沟槽的侧壁(即耦合端面)，仅能对深沟槽中的填充材料进行刻蚀，使得每次进行第二刻蚀工艺后，深沟槽中的填充材料至少留存部分。从而实现了对深沟槽的侧壁的保护，避免了导致靠近耦合端面的衬底受到侧向刻蚀形成过度凹陷区域。提升了边缘耦合器的可靠性。
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Figure CN122902009A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the semiconductor field, and more particularly to a chip and a method for manufacturing the chip. Background Technology
[0002] An edge coupler is an important device in integrated photonics, primarily used to efficiently couple optical signals from optical fibers (or external components) to waveguides. The coupling face of an edge coupler refers to the interface where the edge coupler couples with the optical signal. Summary of the Invention
[0003] This application provides a chip and a method for manufacturing the chip, aiming to solve the problem of rough surface of optical waveguides in the prior art.
[0004] According to a first aspect of this application, this application provides a method for manufacturing a chip, the chip including an edge coupler, the method comprising: processing a substrate by a first etching process to form a plurality of voids in the substrate, wherein the first etching process forms a deep trench on the coupling end face of the edge coupler; and performing at least one cycle step, the cycle step comprising: forming a filler material in the deep trench and the plurality of voids, and after forming the filler material, performing a second etching process, wherein after the second etching process, at least a portion of the filler material in the deep trench is retained.
[0005] In some embodiments, after the second etching process, the filling material in the voids is completely removed.
[0006] In some embodiments, after the at least one cycle step, the projected area of the void increases in a plane parallel to the substrate.
[0007] In some embodiments, an insulating layer is formed on the substrate, and the substrate is processed by a first etching process to form a plurality of voids in the substrate, including: forming an opening in the insulating layer by the first etching process, and forming a plurality of voids in the substrate, wherein the opening is in communication with the voids; after at least one cycle step, the projected area of the opening is smaller than the projected area of the voids on a plane parallel to the substrate.
[0008] In some embodiments, after the at least one cycle step, the projected area of the void increases in a plane parallel to the substrate.
[0009] In some implementations, all filler material is removed after the final cycle step.
[0010] In some embodiments, when the substrate is processed by a first etching process, the etching rate in a first direction is greater than the etching rate in a second direction, wherein the first direction is perpendicular to the substrate and the second direction is perpendicular to the first direction.
[0011] In some implementations, after the at least one cycle step, the plurality of voids are connected to form a cavity in the substrate.
[0012] In some embodiments, the filler material contains carbon and at least one of hydrogen and oxygen.
[0013] According to a second aspect of this application, this application provides a chip manufactured using the method described in any one of the first aspects above.
[0014] In some embodiments, the chip includes an edge coupler formed on a substrate; and an insulating layer disposed on the substrate, wherein a waveguide portion of the edge coupler is disposed in the insulating layer.
[0015] In some embodiments, the edge coupler includes a plurality of openings arranged on both sides of the waveguide portion of the edge coupler.
[0016] Through one or more embodiments of the above embodiments in this application, at least the following technical effects can be achieved:
[0017] In this embodiment, after forming multiple voids and deep trenches through a first etching process, a filling material is formed in the deep trenches and multiple voids in each cycle step before a second etching process is performed. During the second etching process, the etching gas cannot directly contact the sidewalls (i.e., coupling end faces) of the deep trenches; it can only etch the filling material in the deep trenches. This ensures that at least a portion of the filling material remains in the deep trenches after each second etching process. This protects the sidewalls of the deep trenches and prevents the substrate near the coupling end face from being laterally etched, forming an excessively recessed region. This improves the reliability of the edge coupler. Attached Figure Description
[0018] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.
[0019] Figure 1-2 The structure of an edge coupler is shown;
[0020] Figure 3-7 The steps involved in the inventor's discovery of problems during the manufacture of the edge coupler are shown.
[0021] Figure 8 A flowchart illustrating the steps of a chip manufacturing method according to an embodiment of this application is shown;
[0022] Figure 9 A schematic diagram of a substrate according to an embodiment of this application is shown;
[0023] Figure 10 This diagram illustrates a mask layer formed on a substrate according to an embodiment of the present application.
[0024] Figure 11 A schematic diagram is shown after a patterned mask layer is formed using a mask layer according to an embodiment of this application;
[0025] Figure 12 A schematic diagram is shown after the substrate has been processed by a first etching process according to an embodiment of this application;
[0026] Figure 13 A schematic diagram is shown after sub-step one, forming the filling material, is performed according to an embodiment of this application;
[0027] Figure 14 A schematic diagram is shown after the second etching process according to an embodiment of this application;
[0028] Figure 15 A schematic diagram is shown after the last loop step according to an embodiment of this application has ended;
[0029] Figure 16 The following is illustrated according to an embodiment of this application: Figure 2 Cross-sectional view in the DD' direction.
[0030] The meanings of the reference numerals in the attached figures are as follows:
[0031] 11 Substrate
[0032] 12 Insulation layer
[0033] 20 Waveguide section of the edge coupler
[0034] 31 Opening
[0035] 32 gaps
[0036] 40 mask layers
[0037] 41. Patterned Mask Layer
[0038] 50 Filler material
[0039] 60 deep trench
[0040] 70 Depressed area Detailed Implementation
[0041] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0042] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.
[0043] In the description of this application, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances. In this embodiment, the simulated display screen touch unit is connected to the head tracking unit to obtain the movement path of the sensing cursor in the display device.
[0044] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.
[0045] The following disclosure provides many different embodiments or examples for implementing different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.
[0046] Edge couplers are an important component in photonic integrated circuit chips. Figure 1-2 The structure of an edge coupler is shown, wherein Figure 1 For along Figure 2 Cross-sectional view in the BB' direction. Figure 2 For along Figure 1 A cross-sectional view along the AA' direction. The edge coupler is formed using a substrate 11, on which an insulating layer 12 is disposed. The insulating layer 12 may include multiple layers of insulating material (for convenience, it is shown as a single insulating layer in the figure). Exemplarily, the waveguide portion 20 of the edge coupler is first formed on a portion of the insulating material, and then insulating material is deposited again on the waveguide portion 20 of the edge coupler to form the insulating layer 12 that encloses the waveguide portion 20 of the edge coupler. Figure 1-16 The insulating layer 12, which is deposited multiple times, is represented by the same filling pattern. The edge coupler has a coupling end face C, at which the optical signal is coupled to the waveguide portion 20 of the edge coupler to input or output the optical signal to a photonic integrated circuit chip. Multiple openings 31 are also provided on both sides of the waveguide portion 20 of the edge coupler.
[0047] The inventors of this application have discovered that, during the manufacturing process of the edge coupler, multiple gaps 32 and deep trenches 60 on the coupling end face C are formed through an etching process (see [link to application]). Figure 6When this occurs, the substrate 11 near the coupling end face C will be subjected to excessive lateral etching (lateral etching), resulting in a recessed region 70 in the waveguide portion 20 of the edge coupler located below the coupling end face C (see...). Figure 7 The structure above the recessed area 70 has poor mechanical stability, which can easily lead to chipping defects in the edge coupler during subsequent chip packaging, seriously affecting the reliability of the edge coupler. Figure 3-7 The steps described illustrate the problems the inventors encountered while manufacturing the edge coupler. It should be noted that... Figure 3-7 For along Figure 2 A cross-sectional view along the CC' direction (the waveguide portion 20 of the edge coupler is not shown in the cross-sectional view along the CC' direction). The inventor's process for forming multiple gaps 32 and coupling end faces C is as follows: providing a substrate 11 (see...). Figure 3 A mask layer 40 is formed on the insulating layer 12 (see...). Figure 4 A patterned mask layer 41 is formed using mask layer 40 (see...). Figure 5 Using the patterned mask layer 41 as a mask, the insulating layer 12 is etched to form the opening 31, the gap 32, and the coupling end face C (see...). Figure 6 Then the patterned mask layer 41 is removed, and the substrate 11 is etched using the insulating layer 12 as a mask to enlarge the gap 32 (see...). Figure 7 During the process of expanding the gap 32, the substrate 11 near the coupling end face will be laterally etched (lateral etching), forming a recessed region 70 below the region of the edge coupler near the coupling end face, thereby affecting the mechanical reliability of the edge coupler.
[0048] This application provides a method for manufacturing a chip. Figure 8 A flowchart illustrating a method for manufacturing a chip according to an embodiment of this application is shown. The chip includes an edge coupler, and the manufacturing method includes steps 101 to 102.
[0049] Step 101: The substrate is processed by a first etching process to form multiple voids in the substrate, wherein the first etching process forms a deep trench on the coupling end face of the edge coupler.
[0050] Step 102: And, perform at least one of the following loop steps, which include:
[0051] A filling material is formed in the deep trenches and multiple voids, and
[0052] After the filling material is formed, a second etching process is performed, and after the second etching process, at least a portion of the filling material in the deep trench is retained.
[0053] Figures 9 to 15This is a schematic diagram of the structure of each step in the chip manufacturing method according to an embodiment of this application. The chip manufacturing method according to an embodiment of this application will be described in detail below with reference to the accompanying drawings. It should be noted that... Figures 9 to 15 For along Figure 2 A cross-sectional view in the CC' direction is shown, with the waveguide portion 20 of the edge coupler not shown.
[0054] Figure 9 A schematic diagram of a substrate according to an embodiment of this application is shown. The above method may include providing a substrate 11 for forming an edge coupler. The substrate may be the bottom silicon in an SOI substrate (SOI wafer), wherein the SOI substrate (SOI wafer) includes a bottom silicon layer, a buried oxide layer, and a top silicon layer disposed sequentially. If an SOI substrate is used, the bottom silicon of the SOI substrate is the substrate 11 in the embodiment of this application. The waveguide portion 20 of the edge coupler is formed using the top silicon of the SOI substrate, and an insulating material is deposited on the waveguide portion 20. When the edge coupler is manufactured using an SOI substrate, the insulating layer 12 includes a buried oxide layer and an insulating material deposited on the buried oxide layer. Various types of photonic devices can be formed in the chip, such as optical waveguides, edge couplers, optical modulators, directional couplers, multi-mode inferometers (MMIs), photodetectors, and optical beam splitters.
[0055] Figure 10 This diagram illustrates a mask layer 40 formed on a substrate 11 according to an embodiment of the present application. The mask layer 40 (photoresist) is a photosensitive photoresist, which can be a positive or negative photoresist, and can be formed using a spin-coating process.
[0056] Figure 11 This diagram illustrates the process after a patterned mask layer 41 is formed using a mask layer 40 according to an embodiment of this application. The patterned mask layer 41 is formed by performing processes such as exposure and development on the mask layer 40.
[0057] Figure 12 A schematic diagram is shown after a substrate 11 has been processed by a first etching process according to an embodiment of this application. A patterned mask layer 41 is formed on the substrate 11, and the substrate 11 is etched based on the patterned mask layer 41 to form a plurality of voids 32 in the substrate 11. The first etching process forms a deep trench 60 at the coupling end face C of the edge coupler. In some embodiments, when the substrate 11 is processed by the first etching process, the etching rate in a first direction is greater than the etching rate in a second direction, wherein the first direction is perpendicular to the substrate 11, and the second direction is perpendicular to the first direction.
[0058] After forming the voids 32 and the deep trenches 60, at least one cycle step is performed, the cycle step comprising sub-step one and sub-step two. Sub-step one involves forming a filling material 50 in the deep trenches 60 and the plurality of voids 32. Sub-step two involves performing a second etching process after forming the filling material 50, the second etching process further etching the filling material 50 in the voids 32 and the filling material 50 in the deep trenches 60, and after the second etching process, at least a portion of the filling material 50 in the deep trenches 60 remains. In some embodiments, after at least one cycle step, the projected area of the voids 32 increases on a plane parallel to the substrate.
[0059] Figure 13 The diagram illustrates the process after sub-step one, forming the filler material 50, according to an embodiment of this application. In some embodiments, the filler material 50 comprises carbon and at least one of hydrogen and oxygen.
[0060] After the filling material 50 is formed, a second etching process is performed, and after the second etching process, at least a portion of the filling material 50 in the deep trench 60 is retained.
[0061] Figure 14 A schematic diagram is shown after the second etching process according to an embodiment of this application. After the second etching process, the filling material 50 in the void 32 is removed; furthermore, the second etching process can enlarge the size of the void 32. The second etching process can be isotropic etching, which causes the void 32 to enlarge more uniformly in each direction. After at least one cycle step, the projected area of the void 32 increases on a plane parallel to the substrate, and the projected area of the aperture 31 is smaller than the projected area of the void 32.
[0062] After the second etching process, the filling material 50 in the deep trench 60 was partially removed, which shows that... Figure 14 The height of the 60 section of the medium-deep trench is greater than Figure 13 The height of the deep trench 60 portion. Due to the protection of the filling material 50 remaining in the deep trench 60, the sidewalls of the deep trench 60 are not laterally etched to form a depression 70.
[0063] Figure 15 A schematic diagram is shown after the final cycle step according to an embodiment of this application. After the final cycle step, all filler material 50 is removed. In some embodiments, the filler material 50 can be removed by washing.
[0064] In some embodiments, due to material deposition and etching processes, for example, because the filler material 50 does not completely fill the deep trench 60, and because a portion of the filler material 50 at the top of the deep trench 60 is etched during each second etching process, a certain amount of lateral etching still occurs at the top portion of the sidewall of the deep trench 60 near the insulating layer 12. After at least one cycle, this results in a slight concave morphology at the top portion of the sidewall of the deep trench 60 (e.g., ...). Figure 15 As shown in the figure, this situation still avoids a large depression area 70.
[0065] In this embodiment, the gap is formed through a cyclic process. In sub-step one of each cyclic process, the deep trench and gap on the coupling end face are filled with a filler material. During the second etching process, the etching gas cannot directly contact the sidewalls of the deep trench (i.e., the coupling end face), and can only etch the filler material in the deep trench. By adjusting the etching efficiency of the second etching process, after each second etching process in the cyclic process, the filler material in the gap is completely removed, the gap expands, while at least a portion of the filler material in the deep trench remains. This protects the sidewalls of the deep trench and prevents the substrate near the coupling end face from being laterally etched, forming a recessed area. This improves the mechanical reliability of the edge coupler.
[0066] This application also provides a chip manufactured using the chip manufacturing method described above.
[0067] The chip includes an edge coupler formed on a substrate 11. An insulating layer 12 is formed on the substrate 11, and the waveguide portion 20 of the edge coupler is disposed in the insulating layer 12. Exemplarily, the insulating layer 12 can be an insulating material disposed in multiple layers on the substrate 11.
[0068] An edge coupler includes multiple gaps arranged on both sides of the waveguide portion of the edge coupler. In some embodiments, multiple openings are arranged in pairs, with two openings in each pair distributed on both sides of the waveguide portion of the edge coupler (e.g., ...). Figure 2 (As shown). In some embodiments, the two gaps below each pair of openings are interconnected. Figure 16 The following is illustrated according to an embodiment of this application: Figure 2 Cross-sectional view along the DD' direction. The two openings 31 are spaced apart, with a gap 32 as shown. Figure 16 The interconnections are shown. In some embodiments, after the at least one cycle step, the plurality of gaps 32 are connected to form a cavity in the substrate, which can prevent light field leakage.
[0069] In the above steps, the specific steps for depositing each layer can be designed according to actual needs, and this application embodiment does not impose specific limitations on them. The specific steps for etching each layer can also be designed according to actual needs, and this application embodiment does not impose specific limitations on them. The specific steps for doping each layer can also be designed according to actual needs, wherein the number of doped regions and the doping concentration and dopant ions of each doped region can be determined according to actual needs.
[0070] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.
[0071] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. However, these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
Claims
1. A method for manufacturing a chip, characterized in that, The chip includes an edge coupler, and the method includes: The substrate is processed by a first etching process to form multiple voids in the substrate, wherein the first etching process forms a deep trench at the coupling end face of the edge coupler; and at least one cyclic step is performed, the cyclic step comprising: A filling material is formed in the deep trenches and the plurality of voids, and After the filling material is formed, a second etching process is performed, after which at least a portion of the filling material in the deep trench is retained.
2. The manufacturing method as described in claim 1, characterized in that, After the second etching process, the filling material in the voids is completely removed.
3. The manufacturing method as described in claim 1, characterized in that, After the at least one cycle step, the projected area of the void increases on a plane parallel to the substrate.
4. The manufacturing method as described in claim 1, characterized in that, An insulating layer is formed on the substrate. The substrate is processed by a first etching process to form multiple voids in the substrate, including: An opening is formed in an insulating layer and a plurality of voids are formed in a substrate by a first etching process, wherein the opening and the voids are in communication. After the at least one cycle step, the projected area of the opening is smaller than the projected area of the void on a plane parallel to the substrate.
5. The manufacturing method as described in claim 4, characterized in that, After the at least one cycle step, the projected area of the void increases on a plane parallel to the substrate.
6. The manufacturing method as described in claim 1, characterized in that, After the final cycle step, remove all filler material.
7. The manufacturing method as described in claim 1, characterized in that, When the substrate is processed by the first etching process, the etching rate in the first direction is greater than the etching rate in the second direction, wherein the first direction is perpendicular to the substrate and the second direction is perpendicular to the first direction.
8. The manufacturing method as described in claim 1, characterized in that, After the at least one cycle step, the plurality of voids connect to form a cavity in the substrate.
9. The manufacturing method as described in claim 1, characterized in that, The filler material contains carbon and at least one of hydrogen and oxygen.
10. A chip, characterized in that, It is manufactured using the method described in any one of claims 1 to 9.
11. The chip as described in claim 10, characterized in that, The chip includes an edge coupler formed on a substrate; An insulating layer is disposed on the substrate, wherein the waveguide portion of the edge coupler is disposed in the insulating layer.
12. The chip as described in claim 11, characterized in that, The edge coupler includes multiple openings arranged on both sides of the waveguide portion of the edge coupler.