Wafer level chip wavelength allocation method and optoelectronic co-packaging system

Abstract

The application discloses a wafer-level chip wavelength allocation method and an optoelectronic co-packaging system, and the method comprises the following steps: constructing a basic Latin square matrix based on a chip array; performing row permutation, column permutation or symbol permutation on the basic Latin square matrix to obtain a target Latin square matrix; numbering each chip in the chip array according to the target Latin square matrix; and allocating a corresponding target wavelength to each chip based on the corresponding chip number of each chip; wherein each chip number corresponds to a unique target wavelength. The application can realize conflict-free allocation of target wavelengths and global multiplexing of wavelength resources in wafer-level chip optical interconnection, thereby improving the wavelength resource utilization rate, optical signal transmission reliability and system scalability.

Description

Technical Field

[0001] This invention relates to the field of optical communication technology, and in particular to a wafer-level chip wavelength allocation method and an optoelectronic co-packaging system. Background Technology

[0002] In wafer-level optical interconnect systems, wavelength allocation strategies directly affect optical signal transmission efficiency, wavelength resource utilization, and system scalability. Therefore, how to design a reasonable wavelength allocation strategy for large-scale two-dimensional chip arrays has become a technical problem that urgently needs to be solved in the field of wafer-level optical interconnects.

[0003] Currently, wafer-level optical interconnect systems typically employ a fixed wavelength bonding method, which pre-establishes a fixed correspondence between wavelengths and optical chips, and arranges the chips in a preset order, using wavelength division multiplexing (WDM) technology to achieve parallel transmission of multiple optical signals. When the chip array size is small, this wavelength allocation method can meet the basic communication requirements of the system, and therefore it has been widely used in existing wafer-level optical interconnect systems.

[0004] However, as the scale of chip arrays continues to increase, existing wavelength allocation methods easily lead to multiple chips in the same horizontal signal waveguide using the same wavelength for transmission, resulting in signal crosstalk and affecting the reliability of optical signal transmission. Simultaneously, since different chips may compete for wavelength resources in the same vertical carrier waveguide, some wavelength resources are easily left idle while others are used in competition, reducing wavelength resource utilization. Furthermore, existing wavelength allocation methods are usually tightly coupled with the chip array scale. When the chip array scale changes, it is often necessary to redesign the waveguide network and wavelength allocation relationships, resulting in poor system scalability and difficulty in meeting the application requirements of large-scale wafer-level chip optical interconnect systems.

[0005] This section is intended to provide background or context for the embodiments of the invention set forth in the claims. The description herein is not an admission that it is prior art simply because it is included in this section. Summary of the Invention

[0006] This invention provides a wafer-level chip-based wavelength allocation method to achieve conflict-free allocation of target wavelengths and global reuse of wavelength resources in wafer-level chip optical interconnects, thereby improving wavelength resource utilization, optical signal transmission reliability, and system scalability.

[0007] This wafer-level chip-based wavelength allocation method includes: A basic Latin square matrix is ​​constructed based on the core array size and a preset arrangement rule; The target Latin square matrix is ​​obtained by performing a permutation operation on the basic Latin square matrix. Each core in the core array is numbered according to the target Latin square matrix; Based on the core number corresponding to each core, a corresponding target wavelength is assigned to each core; wherein, each core number corresponds to a unique target wavelength.

[0008] In some embodiments, the arrangement rule includes: a cyclic shift rule; the construction of the basic Latin square matrix based on the core array size and the preset arrangement rule includes: The core particles in each row of the core particle array are numbered according to a preset numbering order to obtain a numbering matrix; The numbers in each row of the numbering matrix are rearranged according to the cyclic shift rule to obtain the basic Latin square matrix.

[0009] In some embodiments, rearranging the numbers of each row in the numbering matrix according to a cyclic shift rule to obtain a basic Latin square matrix specifically includes: keeping the numbers of the first row in the numbering matrix unchanged, and cyclically shifting the numbers of the second row to the m-th row according to the row order of the numbering matrix to obtain a basic Latin square matrix; where m is the number of rows of the core array.

[0010] In some embodiments, the step of cyclically shifting the numbers from the second row to the m-th row according to the row order of the numbering matrix specifically includes: The numbers in any row of the numbering matrix are cyclically shifted by a preset number of positions relative to the numbers in the previous row.

[0011] In some embodiments, the cyclic shift includes a cyclic left shift or a cyclic right shift.

[0012] In some embodiments, the numbers in any row of the basic Latin square matrix are all different, and the numbers in any column are all different.

[0013] In some embodiments, the arrangement rules further include: block splicing construction rules and backtracking enumeration rules.

[0014] In some embodiments, the permutation operation includes: row permutation and column permutation; the permutation operation on the basic Latin square matrix includes: After performing row permutations on the basic Latin square matrix, column permutations are performed; or After performing column permutations on the basic Latin square matrix, row permutations are then performed.

[0015] In some embodiments, the permutation operation includes: row permutation; the permutation operation on the basic Latin square matrix includes: Select at least two rows from the basic Latin square matrix and perform positional permutations on the selected rows; wherein the numbering in each row remains unchanged.

[0016] In some embodiments, the permutation operation includes: column permutation; the permutation operation on the basic Latin square matrix includes: Select at least two columns from the basic Latin square matrix and perform positional permutations on the selected columns, wherein the column numbers remain unchanged.

[0017] In some embodiments, the number of rows and columns to be replaced is selected according to a preset rule or a random rule.

[0018] In some embodiments, the permutation operation includes: sign permutation; the permutation operation on the basic Latin square matrix includes: The permutation rules are determined based on the set of numbers of the basic Latin square, and the numbers in the basic Latin square are permuted based on the permutation rules.

[0019] This invention also provides a wafer-level chip-based optoelectronic co-packaging system to achieve conflict-free allocation of target wavelengths and global reuse of wavelength resources in wafer-level chip optical interconnects, thereby improving wavelength resource utilization, optical signal transmission reliability, and system scalability.

[0020] The wafer-level chip-based optoelectronic co-packaging system is used to implement the wavelength allocation method. The optoelectronic co-packaging system includes: a substrate, an orthogonal layered waveguide network, at least one set of lasers and multiple sets of fiber optic connectors. The substrate includes a substrate layer and a core bonding layer. A core array is provided at a predetermined position in the core bonding layer; Each laser and each fiber optic connector passes through the core bonding layer and is integrated on the substrate layer; each laser and each fiber optic connector are located on the periphery of the core array and are respectively connected to the orthogonal layered waveguide network; the laser is used to generate optical signals of the target wavelength corresponding to each core and transmit them to the orthogonal layered waveguide network; Each of the fiber optic connectors is used to receive modulated optical signals from the orthogonal layered waveguide network.

[0021] In some embodiments, the chip bonding layer includes a passive conductive layer and an active optical waveguide layer, wherein the active optical waveguide layer is located between the passive conductive layer and the wafer substrate layer; and the orthogonal layered waveguide network is disposed in the active optical waveguide layer.

[0022] In some embodiments, the orthogonal layered waveguide network includes: a carrier waveguide layer and a signal waveguide layer; the carrier waveguide layer and the signal waveguide layer are spaced apart in the thickness direction of the wafer; The carrier waveguide layer includes multiple carrier waveguides, each of which extends along a first direction; each carrier waveguide corresponds to a column of cores in the core array. The signal waveguide layer includes multiple signal waveguides, each extending along a second direction orthogonal to the first direction; each signal waveguide corresponds to a row of cores in the core array.

[0023] This invention provides a wafer-level chip wavelength allocation method and optoelectronic co-packaging system. It constructs a basic Latin square matrix based on a chip array, and generates a target Latin square matrix by performing row, column, or row-column permutations on the basic Latin square matrix. Then, based on the target Latin square matrix, chip numbers and target wavelengths are allocated, establishing a correspondence between each chip number and a unique target wavelength. This achieves ordered allocation of wavelength resources within the chip array, avoiding wavelength conflicts within the same signal waveguide and wavelength resource competition within the same carrier waveguide. This improves wavelength resource utilization and optical signal transmission reliability, while also enhancing the adaptability of the wavelength allocation scheme to chip arrays of different sizes and the system's scalability. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings: Figure 1 This is a schematic flowchart of a wafer-level chip wavelength allocation method according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of the chip array and the orthogonal hierarchical network in an embodiment of the present invention; Figure 3 This is a flowchart illustrating a wafer-level chip wavelength allocation method in another embodiment of the present invention. Figure 4 5 is an embodiment of the present invention. A flowchart illustrating the wavelength allocation method for a 5-core array; Figure 5 In another embodiment of the present invention, 5 A flowchart illustrating the wavelength allocation method for a 5-core array; Figure 6 This is a schematic diagram of the optoelectronic co-packaging system in an embodiment of the present invention; Figure 7 As shown in embodiment 4 of the present invention A flowchart illustrating the wavelength allocation method for a 5-core array; Figure 8 In another embodiment of the present invention, 4 A schematic diagram of the wavelength allocation method for a 5-core array. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. Here, the illustrative embodiments and their descriptions are used to explain the present invention, but are not intended to limit the present invention. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be arbitrarily combined with each other. The acquisition, storage, use, and processing of data in the technical solutions of this application all comply with relevant laws and regulations. The user information in the embodiments of this application is obtained through legal and compliant means, and the acquisition, storage, use, and processing of user information have been authorized and agreed upon by the customer.

[0026] To facilitate understanding of the technical solution provided in this application, the relevant content of the technical solution in this application will be explained below.

[0027] To address the problems of wavelength conflict, low wavelength resource utilization, and difficulty in adapting to large-scale chip array expansion in existing wafer-level chip optical interconnects, this application provides a wafer-level chip-based wavelength allocation method. This method constructs a basic Latin square matrix and generates a target Latin square matrix using row permutation, column permutation, or row-column permutation. Chips are numbered according to the target Latin square matrix, and a unique target wavelength is allocated based on the chip number. This achieves conflict-free wavelength allocation and full reuse of wavelength resources in the chip array, improving the transmission reliability, wavelength utilization, and system scalability of wafer-level chip optical interconnects.

[0028] like Figure 1 As shown, the present invention provides a wavelength allocation method based on wafer-level chips, the wavelength allocation method comprising: S101 to S104.

[0029] S101: Construct a basic Latin square matrix based on the core array size and preset arrangement rules.

[0030] S102: Perform a permutation operation on the basic Latin square matrix to obtain the target Latin square matrix.

[0031] S103: Number each core in the core array according to the target Latin square matrix.

[0032] S104: Assign a target wavelength to each core based on its corresponding core number. Each core number corresponds to a unique target wavelength.

[0033] According to the above embodiments, a basic Latin square matrix is ​​constructed based on the chip array, and a target Latin square matrix is ​​generated by performing row permutation, column permutation, or symbol permutation on the basic Latin square matrix. Then, the chip numbering and target wavelength allocation are completed according to the target Latin square matrix, so that each chip number is associated with a unique target wavelength. This achieves the orderly allocation of wavelength resources in the chip array, avoids wavelength conflicts in the same signal waveguide and wavelength resource competition in the same carrier waveguide, improves wavelength resource utilization and optical signal transmission reliability, and enhances the adaptability of the wavelength allocation scheme to chip arrays of different sizes and the system scalability.

[0034] In embodiments of the present invention, such as Figure 2 As shown, a two-dimensional m×k chip array is arranged in the central region of the wafer, where m represents the number of rows in the chip array and k represents the number of columns in the chip array. , where n is the larger of the number of rows and columns in the chip array. n represents the number of target wavelengths configured in each vertical carrier waveguide, that is, each carrier waveguide can carry n different target wavelengths.

[0035] Each core particle corresponds to a unique pair of target wavelengths, which includes a first target wavelength and a second target wavelength. The target wavelength pair corresponding to the t-th core particle number is... Where t = 1, 2, ..., n. The first target wavelength and the second target wavelength are used to transmit optical signals in different directions, enabling the same core particle to complete bidirectional optical communication in an orthogonal layered waveguide network.

[0036] The orthogonal layered waveguide network comprises multiple vertically extending carrier waveguides and multiple horizontally extending signal waveguides. Each vertical carrier waveguide corresponds to a column of cores in the core array, and each horizontal signal waveguide corresponds to a row of cores in the core array. Each vertical carrier waveguide is configured with 2n target wavelengths, i.e. and Since the core array comprises k columns, the entire orthogonal layered waveguide network is configured with 2×k×n target wavelengths to achieve wavelength multiplexing for the entire core array.

[0037] In some embodiments, such as Figure 3 As shown, S101 includes: S301 to S302.

[0038] S301: Number each core in each row of the core array according to the preset numbering order to obtain a numbering matrix.

[0039] S302: Rearrange the numbers in each row of the numbering matrix according to the preset cyclic shift rule to obtain the basic Latin square matrix.

[0040] In this embodiment of the invention, the basic Latin square matrix is ​​an n-order Latin square matrix that satisfies preset constraints. The matrix elements are taken from the element set. Furthermore, all elements in any row are distinct, and all elements in any column are distinct.

[0041] Furthermore, the basic Latin square matrix needs to satisfy the following condition: the elements in the first row are arranged according to... The elements are arranged in natural ascending order, and the elements in the first column are arranged in... The Latin square matrix is ​​arranged in natural ascending order. The Latin square matrix that satisfies the above conditions is used as the basic Latin square matrix for subsequent generation of the target Latin square matrix and completion of core numbering and target wavelength allocation.

[0042] In some embodiments, the basic Latin square matrix can be generated by cyclic shift construction, or by block splicing construction, backtracking enumeration construction, or other construction methods that can generate a matrix that satisfies the Latin square constraint. The present invention is not limited to the above construction methods.

[0043] This invention constructs the basic Latin square matrix using a row-by-row cyclic shift method. The following explanation uses this row-by-row cyclic shift method as an example.

[0044] Suppose that a two-dimensional m×k chip array is set in the central region of the wafer, where m represents the number of rows of the chip array and k represents the number of columns of the chip array.

[0045] First, the cores in each row of the core array are numbered according to a preset numbering order, forming a numbering matrix. Each row is numbered sequentially in the order 1, 2, 3, ..., k, meaning the initial numbers for rows 1 to m are all 1, 2, 3, ..., k, as shown in Table 1 below: Table 1

[0046] In some embodiments, S302 specifically includes: keeping the numbers in the first row of the numbering matrix unchanged, and cyclically shifting the numbers in the second to m rows according to the row order of the numbering matrix to obtain the basic Latin square matrix. Here, m is the number of rows in the core array.

[0047] In some embodiments, the step of cyclically shifting the numbers from the second row to the mth row according to the row order of the numbering matrix specifically includes: cyclically shifting the number of any row in the numbering matrix relative to the number of the previous row by a preset number of positions.

[0048] In this embodiment of the invention, a row-by-row cyclic shift operation is performed on the numbering matrix to generate a basic Latin square matrix. Specifically, the numbering of the first row remains unchanged. For the i-th row (2≤i≤m), the numbering of the i-th row is cyclically shifted i-1 positions relative to the entire first row.

[0049] In some embodiments, cyclic shifting includes cyclic left shifting or cyclic right shifting.

[0050] In some embodiments, when using a circular left shift method, the numbers in the i-th row of the numbering matrix are circularly shifted left by i-1 positions relative to the numbers in the first row. This embodiment is illustrated using a circular left shift method, as shown in Table 2 below: Table 2

[0051] In some embodiments, when a circular right shift is used, the number in the i-th row of the numbering matrix is ​​circularly shifted i-1 positions to the right relative to the number in the first row.

[0052] For example, such as Figure 4 As shown, when the core array is a 5×5 core array, each row of cores is first numbered in the order of 1, 2, 3, 4, 5, resulting in a 5×5 numbering matrix. The numbering of each row is shown in Table 3 below: Table 3

[0053] Then, the above numbered matrix is ​​rearranged according to the row-by-row cyclic left shift rule. Specifically, the first row remains unchanged; the second row is cyclically shifted left by 1 position; the third row is cyclically shifted left by 2 positions; the fourth row is cyclically shifted left by 3 positions; and the fifth row is cyclically shifted left by 4 positions. The final result is the basic Latin square matrix, and its row numbers are shown in Table 4 below: Table 4

[0054] The resulting basic Latin square matrix satisfies the Latin square constraint, meaning that all numbers in any row and all numbers in any column are distinct. Subsequently, row permutations, column permutations, or row-column permutations can be performed on this basic Latin square matrix to generate target Latin square matrices suitable for different chip array layouts, and chip numbering and target wavelength allocation can be performed based on the target Latin square matrix.

[0055] For example, when If each row still uses only k numbers from 1 to k, then the column direction cannot be completely unique within m rows.

[0056] Therefore, based on the number of rows m and columns k of the core array, the maximum value n between the number of rows and columns is determined, that is:

[0057] Where m represents the number of rows in the core array, and k represents the number of columns in the core array. When the core array is a square array structure, n is equal to the number of rows and columns in the core array.

[0058] Construct a basic Latin square matrix of order n. Since the basic Latin square matrix is ​​an n×n square matrix, when the core array is not a square matrix, select the corresponding m rows and k columns from the basic Latin square matrix based on the number of rows m and columns k of the core array to obtain the numbering matrix corresponding to the core array. When the core array is an n×n square matrix, this basic Latin square matrix is ​​the numbering matrix.

[0059] In conjunction with this application By definition, a 6×4 core array should have n=6, that is, use a numbering system from 1 to 6, and then select 4 columns from it to form a 6×4 basic Latin square matrix.

[0060] First, a 6×6 numbering matrix is ​​constructed according to the numbering order 1, 2, 3, 4, 5, 6. Then, the numbering matrix is ​​rearranged by cyclically shifting left row by row to generate a 6×6 basic Latin square matrix, as shown in Table 5 below: Table 5

[0061] Then, based on the number of columns in the 6×4 core array, four columns from the 6×6 basic Latin square matrix are selected to obtain the basic Latin square matrix suitable for the 6×4 core array, as shown in Table 6 below: Table 6

[0062] In the resulting basic Latin square matrix, each number in any row is unique, and each number in any column is unique, thus avoiding wavelength conflicts in the same row and carrier resource competition in the same column during subsequent wavelength allocation.

[0063] According to the above embodiments, a numbering matrix is ​​generated according to a preset numbering order, and then the numbering matrix is ​​rearranged according to a preset cyclic shift rule to construct a basic Latin square matrix, ensuring that the numbers in each row and column of the basic Latin square matrix satisfy the constraint that they are mutually exclusive. Meanwhile, the cyclic shift construction method is simple and easy to implement, and can quickly generate basic Latin square matrices suitable for different sizes of chip arrays without complex calculations. This not only improves the construction efficiency of the basic Latin square matrix but also enhances the scalability and versatility of the wavelength allocation scheme.

[0064] In some embodiments, such as Figure 4 As shown, the substitution operations include row substitution and column substitution. S102 includes S401 to S402.

[0065] S401: Perform row permutations followed by column permutations on the basic Latin square matrix. Alternatively, S402: Perform column permutations on the basic Latin square matrix, followed by row permutations.

[0066] In this embodiment of the invention, the target Latin square matrix is ​​constructed using an interleaved method of row and column permutations. Specifically, the basic Latin square matrix is ​​used as the initial matrix, and while keeping the indices unchanged, row, column, or symbol permutations are performed on the basic Latin square matrix to generate the target Latin square matrix.

[0067] Row permutation and column permutation are two independent permutation processes. Only row permutation can be performed, only column permutation can be performed, or row permutation and column permutation can be performed sequentially. The execution order can be either row permutation followed by column permutation, or column permutation followed by row permutation.

[0068] In some embodiments, the permutation operation includes row permutation. S102 specifically includes selecting at least two rows from the basic Latin square matrix and performing position permutation on each of the selected rows. The row numbers remain unchanged.

[0069] In some embodiments, the permutation operation includes: column permutation. S102 specifically includes: selecting at least two columns in the underlying Latin square matrix and performing position permutation on each of the selected columns, wherein the numbering in each column remains unchanged.

[0070] In this embodiment of the invention, a basic Latin square matrix is ​​first constructed using the aforementioned cyclic shift method. In this basic Latin square matrix, the numbers in any row are distinct, and the numbers in any column are also distinct.

[0071] According to a preset permutation rule, at least two rows are selected from the basic Latin square matrix for position permutation. The position permutation only changes the arrangement of each row in the matrix, while the internal numbering of each row remains unchanged, and the remaining rows that are not permuted retain their original positions.

[0072] For example, such as Figure 5 As shown, taking a 5×5 basic Latin square matrix as an example, we select the 1st row and the 5th row to perform a positional permutation, and simultaneously select the 2nd row and the 4th row to perform a positional permutation, while keeping the 3rd row unchanged. The resulting matrix is ​​shown in Table 7 below: Table 7

[0073] Based on the matrix after the row permutation described above, at least two columns are selected from the matrix for position permutation according to preset permutation rules. This column permutation only changes the arrangement of each column in the matrix, while the column numbers remain unchanged.

[0074] For example, such as Figure 5As shown, columns 1 and 4 are swapped, and columns 2 and 5 are also swapped, while column 3 remains unchanged. The resulting target Latin square matrix is ​​shown in Table 8 below. Table 8

[0075] In some embodiments, the number of rows and columns to be replaced is selected according to a preset rule or a random rule.

[0076] In this embodiment of the invention, the row and column permutations described above are merely examples, and the invention is not limited to the permutation methods described above. In practical applications, at least two rows and / or at least two columns can be selected for position permutation according to preset rules or random rules, or more than two rows and / or more than two columns can be permuted simultaneously. Throughout the permutation process, each number remains unchanged, that is, no new numbers are added or deleted, only the row position and / or column position corresponding to the number is changed. Therefore, the target Latin square matrix after permutation still satisfies the Latin square constraint that each number in any row is different and each number in any column is different.

[0077] According to the above embodiments, by performing row and column permutations on the basis of the basic Latin square matrix, flexible reconstruction of the chip numbering space is achieved while keeping the numerical values ​​and Latin square constraints unchanged. This allows the target Latin square matrix to adapt to different chip array layouts and wavelength allocation requirements. Since the row and column permutations are independent and support the selection of permutation objects according to preset or random rules, the flexibility and diversity of numbering matrix generation are improved, avoiding regular conflicts caused by fixed numbering patterns. At the same time, the adaptability of the wavelength allocation scheme to wafer-level chips of different sizes and topologies is enhanced, which is conducive to further improving wavelength resource utilization, reducing wavelength conflict risks, and improving the transmission reliability and scalability of wafer-level chip optical interconnect systems.

[0078] In some embodiments, the permutation operation includes: symbol permutation; S102 further includes: determining permutation rules based on the set of numbers of the basic Latin square, and permuting each number in the basic Latin square based on the permutation rules.

[0079] In this embodiment of the invention, the basic Latin square matrix can also be generated using a symbolic substitution method. Assuming the basic Latin square matrix is ​​an n-order Latin square matrix, its index set S is:

[0080] Define a permutation map on the set of indices S. :

[0081] Wherein, permutation mapping It is a bijection, meaning that each number in the set of numbers S is uniquely mapped to another number in the set of elements S, and there is a one-to-one correspondence between the numbers, with no duplicate or missing mappings.

[0082] According to the permutation map The target Latin square matrix is ​​obtained by uniformly replacing all the indices in the basic Latin square matrix. Specifically, the original positions of the indices in the basic Latin square matrix are preserved, and only the indices in the matrix are subjected to a permutation mapping. Replace it.

[0083] Due to permutation mapping Since it is bijective, the numbering remains in one-to-one correspondence before and after the substitution, and the resulting target Latin square matrix still satisfies the Latin square constraint, that is, each element in any row is distinct, and each element in any column is distinct. Therefore, the target Latin square matrix obtained through symbol substitution can be used for subsequent core numbering and target wavelength allocation.

[0084] The following example uses a 3rd-order Latin square matrix to illustrate the symbolic permutation construction method.

[0085] Assume the original fundamental Latin square matrix is ​​as shown in Table 9 below: Table 9

[0086] Define number set Permutation mapping on for:

[0087] Subsequently, all indices in the basic Latin square matrix are uniformly replaced according to the above permutation mapping, that is: all indices 1 in the basic Latin square matrix are replaced with indices 2, all indices 2 in the basic Latin square matrix are replaced with indices 3, and all indices 3 in the basic Latin square matrix are replaced with indices 1. After the replacement, the target Latin square matrix is ​​obtained, as shown in Table 10 below: Table 10

[0088] According to the above embodiment, the original position of each number in the basic Latin square matrix remains unchanged during the symbol permutation process. Only the number is uniformly replaced according to the permutation mapping. Therefore, the target Latin square matrix still satisfies the Latin square constraint condition, that is, each number in each row is different and each number in each column is different.

[0089] In some embodiments, each core in the core array is numbered according to a target Latin square matrix, and the number in the target Latin square matrix is ​​used as the basic core number. Specifically, each core in each row of the core array is identified according to the number at the corresponding position in the target Latin square matrix, and the basic core numbers include 1, 2, ..., n, where, m is the number of rows in the core array, and k is the number of columns in the core array.

[0090] For any basic core number t (t = 1, 2, ..., n), a unique target wavelength pair is pre-established, forming a one-to-one mapping relationship between the basic core number and the target wavelength pair. The target wavelength pair includes the target wavelength. and target wavelength Among them, the target wavelength Used for optical signal transmission in the vertical direction, target wavelength It is used for optical signal transmission in the horizontal transmission direction orthogonal to the vertical transmission direction, thereby forming a unique bidirectional target wavelength pair corresponding to the basic core number.

[0091] According to the above embodiments, each core in the core array is numbered according to the generated target Latin square matrix, and a one-to-one mapping relationship between the core and the target wavelength pair is established according to the corresponding number of each core. This makes each core fixedly bound to a unique bidirectional target wavelength pair, thereby realizing conflict-free wavelength allocation and full reuse of wavelength resources in the orthogonal layered waveguide network.

[0092] This application provides a wafer-level chip-based optoelectronic co-packaging system, applied to the aforementioned wafer-level chip-based optoelectronic co-packaging method. This wafer-level chip-based optoelectronic co-packaging system and the wafer-level chip-based optoelectronic co-packaging method in one embodiment of this application are based on the same inventive concept and have similar problem-solving principles. Therefore, the implementation of the wafer-level chip-based optoelectronic co-packaging system is the same as the implementation of the wafer-level chip-based optoelectronic co-packaging method in one embodiment of this application, and repeated details will not be elaborated further. As used below, the terms "unit" or "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the system described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0093] This invention also provides a wafer-level chip-based optoelectronic co-packaging system for implementing the aforementioned wavelength allocation method. The term "wafer-level" in this invention describes the integration scale of the optoelectronic co-packaging system, meaning the entire system is integrated on a substrate with dimensions comparable to a semiconductor wafer, rather than limiting the chip substrate to a silicon wafer.

[0094] like Figure 6As shown, the optoelectronic co-packaging system includes: a substrate, at least one set of lasers 101, multiple sets of fiber optic connectors 102, and an orthogonal layered waveguide network. The substrate includes a substrate layer and a core bonding layer.

[0095] A core array is set at a preset position in the core bonding layer.

[0096] Each laser 101 and each of the aforementioned fiber optic connectors 102 passes through the core bonding layer and is integrated onto the substrate layer. Each laser 101 and each of the aforementioned fiber optic connectors 102 is located on the periphery of the core array and is connected to the orthogonal layered waveguide network. The laser 101 is used to generate optical signals of the target wavelength corresponding to each core and transmit them to the orthogonal layered waveguide network. Each of the aforementioned fiber optic connectors 102 is used to receive modulated optical signals from the orthogonal layered waveguide network.

[0097] In some embodiments, the substrate can be any one of a silicon substrate, a glass substrate, or an organic substrate. For ease of explanation, the following embodiments of the present invention use a silicon wafer as the substrate. However, those skilled in the art should understand that the present invention is equally applicable when using a glass substrate or an organic substrate to implement the technical solution of the present invention, and the present invention is not limited thereto.

[0098] In this embodiment of the invention, the optoelectronic co-packaging system for wafer-level chips provided by the present invention adopts a wafer-level monolithic vertical integration architecture. The wafer, from bottom to top, comprises: a wafer substrate layer (WSL) and a chip bonding layer (CBL). The chip bonding layer includes: a passive electrical interconnect layer (PEIL) and an active optical waveguide layer (AOWL). The active optical waveguide layer is disposed between the passive electrical interconnect layer and the wafer substrate layer.

[0099] The active optical waveguide layer is fabricated integrally on a wafer-level platform using a silicon photonics integration process compatible with CMOS technology. An orthogonal layered waveguide network is integrated within the active optical waveguide layer to realize laser carrier transmission.

[0100] like Figure 2 As shown, the central region of the passive electrical interconnect layer is provided with a... A matrix-arranged chiplet array. Here, m represents the number of rows in the chiplet array, and k represents the number of columns.

[0101] In some embodiments, such as Figure 6 As shown, a set of lasers 101 are respectively arranged on the first and second sides of the core array.

[0102] Each first laser in a set of lasers 101 is disposed on the first side of the core array, and the output end of each first laser is coupled to the first end of the corresponding carrier waveguide, so as to inject a set of optical signals generated into the corresponding carrier waveguide.

[0103] In another set of lasers 101, each second laser is disposed on the second side of the core array. The output end of each second laser is coupled to the second end of the corresponding carrier waveguide, and is used to inject another set of optical signals generated into the corresponding carrier waveguide. The wavelengths of each optical signal are different.

[0104] In this embodiment of the invention, each group of lasers 101 is continuously arranged along the horizontal direction of the core array to provide a continuous optical carrier of a preset wavelength to the carrier waveguide in the active optical waveguide layer.

[0105] A set of lasers 101 is disposed on the first and second sides of the core array. For example, the first side may correspond to the upper edge of the core array, and the second side may correspond to the lower edge of the core array. Each set of lasers 101 is continuously disposed along the horizontal direction of the core array, and is used to provide a continuous optical carrier of a preset wavelength to the carrier waveguide in the active optical waveguide layer. The number of lasers 101 disposed on the upper edge of the core array is k, and the output end of each laser 101 is coupled to one end of the corresponding carrier waveguide. Each laser 101 generates a set of laser carriers composed of the same wavelength. Each laser 101 is used to inject this set of laser carriers into the carrier waveguide coupled to it. Each set of laser carriers includes wavelengths of... Multiple laser carriers, each with a wavelength that does not overlap.

[0106] A group of k lasers 101 are positioned at the lower edge of the core array, with the output of each laser 101 coupled to one end of a corresponding carrier waveguide. Each laser 101 generates a set of laser carriers composed of the same wavelength. Each laser 101 is used to inject this set of laser carriers into the carrier waveguide coupled to it. Each set of laser carriers includes wavelengths of... Multiple laser carriers, each with non-overlapping wavelengths. The wavelength set... With wavelength set Non-overlapping, meaning any wavelength (1≤i≤n) are all different from any wavelength (n+1≤j≤2n). Wherein, This represents the maximum value between the number of rows and columns in the core array.

[0107] The carrier waveguide is used to transmit the set of laser carriers. Since a set of lasers 101 are connected to each end of the same carrier waveguide, a dual-end injection optical carrier structure is formed. By providing optical carriers from both ends of the carrier waveguide simultaneously, the propagation distance of part of the optical carrier can be shortened, compensating for the propagation loss generated during long-distance waveguide transmission, thereby improving the uniformity of optical power obtained by the chips at various locations in the wafer-level optical interconnect system.

[0108] In some embodiments, such as Figure 6 As shown, a set of fiber optic connectors 102 are respectively provided on the third and fourth sides of the core array. The fiber optic connectors 102 include: a first fiber optic connector and a second fiber optic connector.

[0109] Each first fiber optic connector is located on the third side of the core array and is coupled to the first end of the corresponding signal waveguide.

[0110] Each second fiber optic connector is located on the fourth side of the core array and is coupled to the second end of the corresponding signal waveguide.

[0111] In this embodiment of the invention, a set of fiber optic connectors 102 are bonded and integrated on the third and fourth sides of the core array using a high-precision end-face coupling process. Each fiber optic connector 102 is used to uniformly output the modulated optical signal to an external fiber optic link to achieve off-chip communication. The sets of fiber optic connectors 102 are continuously arranged along the vertical direction of the core array. For example, the third side corresponds to the left edge of the core array, and the fourth side corresponds to the right edge of the core array. The number of fiber optic connectors 102 located on the left edge of the core array is m, and each fiber optic connector 102 is coupled to one end of the corresponding signal waveguide via an edge coupler or a grating coupler. The number of fiber optic connectors 102 located on the lower edge of the core array is m, and each fiber optic connector 102 is coupled to one end of the corresponding signal waveguide via an edge coupler or a grating coupler.

[0112] According to the above embodiments, by setting multiple sets of fiber optic connectors on both sides of the chip array, the optical signals generated by each chip can be converged inside the wafer and then output to external switches, servers, optical network devices or other wafer-level computing nodes through a unified interface, thereby constructing a high-bandwidth optical interconnect system for large-scale heterogeneous chip arrays.

[0113] In some embodiments, such as Figure 2 As shown, an orthogonal layered waveguide network is disposed in the active optical waveguide layer.

[0114] In some embodiments, such as Figure 2 and Figure 6 As shown, the orthogonal layered waveguide network includes a carrier waveguide layer and a signal waveguide layer. The carrier waveguide layer and the signal waveguide layer are spaced apart in the thickness direction of the substrate.

[0115] The carrier waveguide layer comprises multiple carrier waveguides, each extending along a first direction. Each carrier waveguide corresponds to a column of cores in the core array.

[0116] The signal waveguide layer comprises multiple signal waveguides, each extending along a second direction orthogonal to the second direction. Each signal waveguide corresponds to a row of cores in the core array.

[0117] In embodiments of the present invention, such as Figure 6 As shown, the orthogonal layered waveguide network consists of a carrier waveguide layer and a signal waveguide layer. These two waveguide layers are spaced apart along the wafer thickness within the active optical waveguide layer, and respectively handle optical carrier distribution and modulated optical signal transmission. By employing a layered transmission architecture for different types of optical signals, crosstalk between waveguide layers can be reduced, improving the quality of optical signal transmission.

[0118] The carrier waveguide layer comprises k parallel carrier waveguides, each extending vertically along the wafer and corresponding to a row of cores in the core array. Each carrier waveguide is a silicon-based optical waveguide that meets single-mode transmission requirements. One end of each carrier waveguide is coupled to a laser 101 located at the upper edge of the core array, and the other end is coupled to a laser 101 located at the lower edge of the core array. The carrier waveguides are used to transmit the unmodulated laser carrier generated by the laser 101. The carrier waveguide layer primarily carries the unmodulated laser carrier and does not carry the modulated optical signal, thus achieving physical isolation between the original laser carrier and the modulated optical signal.

[0119] The signal waveguide layer comprises m parallel signal waveguides, each extending in a horizontal direction orthogonal to the vertical direction and corresponding to a row of cores in the core array. Each signal waveguide is a silicon-based optical waveguide that meets the single-mode transmission requirements. One end of each signal waveguide is coupled to an optical fiber connector 102 located at the left edge of the core array, and the other end of each signal waveguide is coupled to an optical fiber connector 102 located at the right edge of the core array.

[0120] Signal waveguides are used to transmit modulated optical signals. Multiple modulated optical signals of different wavelengths can be carried simultaneously in the same signal waveguide and transmitted in parallel through wavelength division multiplexing. The modulated optical signals generated by each row of chips are converged through the corresponding signal waveguides and transmitted to the fiber optic connector 102 to achieve centralized output of optical signals inside the wafer.

[0121] According to the above embodiments, by spatially layering the carrier waveguide layer and the signal waveguide layer, with the carrier waveguide layer used for longitudinal optical carrier distribution and the signal waveguide layer used for transversely modulated optical signal transmission, the two waveguide layers are spatially separated and orthogonal to each other in their extension directions, thereby forming a two-dimensional optical interconnect network covering the entire chip array. By functionally decoupling the optical carrier transmission path from the modulated optical signal transmission path, mutual interference between different types of optical signals can be reduced, and the bandwidth density, transmission efficiency, and scalability of the wafer-level optical interconnect system can be improved.

[0122] In some embodiments, such as Figure 7 As shown, this embodiment uses a 4×5 chip array wafer-level optoelectronic co-packaging system applied to AI massive parallel computing as an example to illustrate the wavelength allocation method provided by the present invention.

[0123] In this embodiment, a circular substrate is used as the wafer, and a wafer-level optoelectronic co-packaging system is formed based on CMOS-compatible silicon photonics technology. A 4×5 chip array is set at the center of the wafer. The chip array includes 4 rows and 5 columns of chips. Therefore, according to It can be seen that, The entire orthogonal layered waveguide network is configured with 2×k×n=2×5×5=50 target wavelengths to achieve global wavelength resource reuse.

[0124] In this embodiment, the orthogonal layered waveguide network includes 5 vertical carrier waveguides and 4 horizontal signal waveguides. The 5 vertical carrier waveguides correspond to the 5 columns of cores in the core array, and the 4 horizontal signal waveguides correspond to the 4 rows of cores in the core array. This enables orthogonal transmission of unmodulated and modulated optical signals in different waveguide layers, avoiding cross-interference between optical signals in different directions.

[0125] First, the basic Latin square matrix is ​​constructed using a row-by-row cyclic shifting method.

[0126] The cores in each row of the 4×5 core array are numbered in the order of 1, 2, 3, 4, 5, resulting in a 4×5 numbering matrix. The numbering of each row is shown in Table 11 below. Table 11

[0127] Subsequently, the numbering matrix is ​​rearranged according to the rule of cyclic left shifting row by row. Specifically, the first row of numbers remains unchanged; the second row is cyclically shifted left by 1 position; the third row is cyclically shifted left by 2 positions; and the fourth row is cyclically shifted left by 3 positions, thus obtaining the basic Latin square matrix, the row numbers of which are shown in Table 12. Table 12

[0128] like Figure 8 As shown, the target Latin square matrix is ​​constructed by interleaving row and column permutations on the basis of the basic Latin square matrix.

[0129] First, row permutations are performed on the basic Latin square matrix according to preset permutation rules. In this embodiment, rows 1 and 3 are permuted, and rows 2 and 4 are permuted, resulting in the matrix after row permutations, as shown in Table 13 below: Table 13

[0130] Then, the matrix after row permutation is further permuted, and column permutations are performed. In this embodiment, columns 1 and 4 are permuted, columns 2 and 5 are permuted, and column 3 remains unchanged, thus obtaining the target Latin square matrix, as shown in Table 14 below: Table 14

[0131] Finally, each core in the 4×5 core array is numbered according to the target Latin square matrix shown in Table 12, and wavelength binding is completed according to the mapping relationship between the basic core number and the target wavelength pair.

[0132] Specifically, the core particles numbered t (t=1, 2, ..., 5) are fixedly bound to a unique target wavelength pair. Among them, the target wavelength For optical signal transmission in the first transmission direction, target wavelength It is used for optical signal transmission in the second transmission direction, which is opposite to the first transmission direction. In the entire core array, there is always a one-to-one correspondence between the basic core number and the target wavelength pair. Each target wavelength pair is unique and does not overlap or occupy each other, thereby realizing conflict-free wavelength allocation in the orthogonal layered waveguide network and full reuse of global wavelength resources.

[0133] It should be noted that the above-mentioned 4×5 core array, row permutation rule and column permutation rule are only an exemplary implementation of the present invention. Those skilled in the art can also adjust the permutation rule according to the actual core array size and system requirements. As long as the target Latin square matrix satisfies the Latin square constraint conditions, all such adjustments are within the protection scope of the present invention.

[0134] According to the above embodiments, by constructing a target Latin square matrix to complete the core numbering and combining it with a unique bidirectional target wavelength binding rule, parallel optical communication of 20 cores in an orthogonal hierarchical waveguide network is realized. In this embodiment, 50 target wavelengths are globally configured, realizing global reuse of target wavelength resources. This ensures that there are no wavelength conflicts within the same horizontal signal waveguide and the same vertical carrier waveguide, effectively avoiding wavelength competition and optical signal crosstalk, and improving the reliability of optical signal transmission. At the same time, the core numbering can be flexibly reconstructed through the target Latin square matrix, adapting to different core layouts and core arrays of different sizes while maintaining the wavelength binding relationship. This enhances the flexibility and scalability of the wavelength allocation scheme, meeting the application requirements of high-density core integration, high bandwidth, and low-collision optical interconnection in AI massive parallel computing scenarios.

[0135] In the description of this specification, the references to terms such as "an embodiment," "a specific embodiment," "some embodiments," "for example," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0136] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A wafer-level chip wavelength allocation method, characterized in that, include: A basic Latin square matrix is ​​constructed based on the core array size and a preset arrangement rule; The target Latin square matrix is ​​obtained by performing a permutation operation on the basic Latin square matrix. Each core in the core array is numbered according to the target Latin square matrix; Based on the core number corresponding to each core, a corresponding target wavelength is assigned to each core; wherein, each core number corresponds to a unique target wavelength.

2. The method according to claim 1, characterized in that, The arrangement rules include: cyclic shift rules; the construction of the basic Latin square matrix based on the core array size and the preset arrangement rules includes: The core particles in each row of the core particle array are numbered according to a preset numbering order to obtain a numbering matrix; The numbers in each row of the numbering matrix are rearranged according to the cyclic shift rule to obtain the basic Latin square matrix.

3. The method according to claim 2, characterized in that, The step of rearranging the numbers of each row in the numbering matrix according to the cyclic shift rule to obtain the basic Latin square matrix specifically includes: keeping the numbers of the first row in the numbering matrix unchanged, and cyclically shifting the numbers of the second row to the mth row according to the row order of the numbering matrix to obtain the basic Latin square matrix; where m is the number of rows of the core array.

4. The method according to claim 3, characterized in that, The step of cyclically shifting the numbers from the second row to the m-th row according to the row order of the numbering matrix specifically includes: The numbers in any row of the numbering matrix are cyclically shifted by a preset number of positions relative to the numbers in the previous row.

5. The method according to claim 4, characterized in that, The cyclic shift includes a cyclic left shift or a cyclic right shift.

6. The method according to claim 3, characterized in that, The numbers in any row of the basic Latin square matrix are all different, and the numbers in any column are all different.

7. The method according to claim 1, characterized in that, The arrangement rules also include: block splicing construction rules and backtracking enumeration rules.

8. The method according to claim 1, characterized in that, The permutation operation includes: row permutation and column permutation; the permutation operation on the basic Latin square matrix includes: After performing row permutations on the basic Latin square matrix, column permutations are performed; or After performing column permutations on the basic Latin square matrix, row permutations are then performed.

9. The method according to claim 1 or 8, characterized in that, The permutation operation includes: row permutation; the permutation operation on the basic Latin square matrix includes: Select at least two rows from the basic Latin square matrix and perform positional permutations on the selected rows; wherein the numbering in each row remains unchanged.

10. The method according to claim 1 or 8, characterized in that, The permutation operation includes: column permutation; the permutation operation on the basic Latin square matrix includes: Select at least two columns from the basic Latin square matrix and perform positional permutations on the selected columns, wherein the column numbers remain unchanged.

11. The method according to claim 10, characterized in that, The number of rows and columns to be replaced is selected according to preset rules or random rules.

12. The method according to claim 1, characterized in that, The permutation operation includes: sign permutation; the permutation operation on the basic Latin square matrix includes: The permutation rules are determined based on the set of numbers of the basic Latin square, and the numbers in the basic Latin square are permuted based on the permutation rules.

13. A wafer-level chip-based optoelectronic co-packaging system for implementing the wavelength allocation method according to any one of claims 1 to 12, characterized in that, include: The substrate comprises a substrate layer and an orthogonal layered waveguide network, at least one set of lasers and multiple sets of fiber optic connectors, wherein the substrate includes a substrate layer and a core bonding layer. A core array is provided at a predetermined position in the core bonding layer; Each laser and each fiber optic connector passes through the core bonding layer and is integrated on the substrate layer; each laser and each fiber optic connector are located on the periphery of the core array and are respectively connected to the orthogonal layered waveguide network; the laser is used to generate optical signals of the target wavelength corresponding to each core and transmit them to the orthogonal layered waveguide network; Each of the fiber optic connectors is used to receive modulated optical signals from the orthogonal layered waveguide network.

14. The system according to claim 13, characterized in that, The core bonding layer includes a passive conductive layer and an active optical waveguide layer, wherein the active optical waveguide layer is located between the passive conductive layer and the wafer substrate layer; and the orthogonal layered waveguide network is disposed in the active optical waveguide layer.

15. The system according to claim 14, characterized in that, The orthogonal layered waveguide network includes: a carrier waveguide layer and a signal waveguide layer; the carrier waveguide layer and the signal waveguide layer are spaced apart in the thickness direction of the wafer; The carrier waveguide layer includes multiple carrier waveguides, each of which extends along a first direction; each carrier waveguide corresponds to a column of cores in the core array. The signal waveguide layer includes multiple signal waveguides, each extending along a second direction orthogonal to the first direction; each signal waveguide corresponds to a row of cores in the core array.

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