Array substrate, display panel and display device

Abstract

Embodiments of the present disclosure provide an array substrate, a display panel and a display device, and relate to the technical field of display, and are used for relieving the problem of display unevenness. The array substrate comprises a first substrate, a first electrode and a first spacer. The first electrode is located on one side of the first substrate; the first electrode is provided with a flow guide groove penetrating through the first electrode; the first spacer is located on the side of the first electrode away from the first substrate; in the orthographic projection on the first substrate, the flow guide groove is located on the side of the first spacer, and the distance between the flow guide groove and the first spacer is less than or equal to a preset value; or, in the orthographic projection on the first substrate, the flow guide groove overlaps with the first spacer, and part of the flow guide groove extends to the outside of the first spacer. The array substrate is used for a display panel.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Technology

[0002] With the continuous development of technology, display technology has been widely applied to various electronic products, such as small electronic products like smart bracelets, smartwatches, smartphones, and tablets, as well as large electronic products like laptops, desktop computers, car accessories, navigation systems, and televisions.

[0003] Liquid crystal display (LCD) technology, with its advantages of high resolution, high brightness, and long lifespan, can cover a wide range of applications, from low-power portable devices to large-size, high-definition displays. It also boasts a long technology lifecycle and excellent reliability. Therefore, LCD technology remains one of the mainstream development directions in the field of display technology. Summary of the Invention

[0004] The purpose of this disclosure is to provide an array substrate, a display panel, and a display device to alleviate the problem of uneven display.

[0005] To achieve the above objectives, the embodiments of this disclosure provide the following technical solutions: On one hand, an array substrate is provided. The array substrate includes a first substrate, a first electrode, and a first spacer portion. The first electrode is located on one side of the first substrate; the first electrode has a channeling groove extending through the first electrode. The first spacer portion is located on the side of the first electrode away from the first substrate; in an orthographic projection on the first substrate, the channeling groove is located on the periphery of the first spacer portion, and the distance between the channeling groove and the first spacer portion is less than or equal to a preset value; or, in an orthographic projection on the first substrate, the channeling groove overlaps with the first spacer portion and partially extends to the outside of the first spacer portion.

[0006] In the aforementioned array substrate, by providing a through-flow channel on the first electrode and arranging the channel near the periphery of the first septum or partially overlapping it, additional flow channels can be provided for the alignment film solution during the leveling stage after coating. When the alignment film solution tends to accumulate at the root of the first septum due to surface tension, the channel can promptly guide and disperse excess solution, effectively reducing the solution accumulation height at the root of the first septum, thereby preventing local bulges on the alignment film surface and making the cured alignment film thickness more even. Simultaneously, the channel interrupts the continuity of the first electrode in the area surrounding the first septum, effectively increasing the heat conduction path length and thermal resistance in this area. This effectively slows down the heat conduction rate around the first septum during pre-baking and other heating processes, reducing the solvent evaporation rate of the alignment film solution in this area, delaying the curing process, and contributing to the flattening of the alignment film. Due to the improved flatness of the alignment film, the liquid crystal molecules in the liquid crystal layer can achieve a more consistent initial state on the surface of the alignment film, thus alleviating the problem of uneven display caused by uneven alignment film thickness.

[0007] In some embodiments, the preset value is half of the radial dimension of the first spacer portion projected onto the first substrate.

[0008] In some embodiments, in an orthographic projection onto the first substrate, the flow channels are located on the periphery of the first septum portion, and a plurality of the flow channels are spaced apart along the periphery of the first septum portion.

[0009] In some embodiments, the flow channel includes a first flow channel and a second flow channel, wherein the distance between the first flow channel and the first septum is less than or equal to the preset value, and the second flow channel is located on the side of the first flow channel away from the first septum.

[0010] In some embodiments, the distance between the first guide channel and the second guide channel is 3μm to 10μm.

[0011] In some embodiments, the guide groove is arc-shaped or elongated.

[0012] In some embodiments, in the orthographic projection on the first substrate, the flow channel overlaps with the first septum portion, and a portion of the flow channel is located on the periphery of the first septum portion; the flow channel includes a third flow channel and a fourth flow channel, and the extension directions of the third flow channel and the fourth flow channel intersect.

[0013] In some embodiments, the flow channel includes a plurality of third flow channels and a plurality of fourth flow channels, wherein the distance between two adjacent third flow channels is 3μm to 10μm, and / or the distance between two adjacent fourth flow channels is 3μm to 10μm.

[0014] In some embodiments, the array substrate further includes a conductive structure and an insulating layer. The conductive structure is disposed between the first substrate and the first electrode. The insulating layer is disposed between the conductive structure and the first electrode. The insulating layer has a through-hole that penetrates the insulating layer. The first electrode is electrically connected to the conductive structure through the through-hole. In the orthographic projection on the first substrate, the first spacer portion overlaps with the through-hole.

[0015] On the other hand, a display panel is provided. The display panel includes: an array substrate, a counter substrate, and a liquid crystal layer as described in any of the above embodiments. The counter substrate is disposed opposite to the array substrate, and the liquid crystal layer is located between the array substrate and the counter substrate.

[0016] In some embodiments, the opposing substrate includes a second substrate and a second spacer portion. The second spacer portion is located on the side of the second substrate closer to the liquid crystal layer; the second spacer portion abuts against the first spacer portion.

[0017] In some embodiments, the opposing substrate further includes a color resist portion, a light-shielding portion, and a planarization layer. The color resist portion is located on the side of the second substrate near the second spacer portion; the light-shielding portion is located on the side of the second substrate near the second spacer portion, and is at least partially located between adjacent color resist portions; the planarization layer covers the surface of the color resist portion and the light-shielding portion away from the second substrate; one end of the second spacer portion is connected to the color resist portion or the light-shielding portion, and the other end extends through the planarization layer to the side of the planarization layer away from the second substrate.

[0018] In another aspect, a display device is provided. The display device includes a display panel and a backlight module as described in any of the above embodiments. The backlight module is disposed on the backlight side of the display panel.

[0019] The above-described display panel and display device have the same structure and beneficial technical effects as the array substrate provided in some of the above embodiments, and will not be described again here. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0021] Figure 1 This is a structural diagram of a display device according to some embodiments; Figure 2 for Figure 1 Cross-sectional view of the display device at point A-A'; Figure 3 This is a connection structure diagram of a display panel and a circuit board according to some embodiments; Figure 4 This is a diagram showing the film layer structure of a display panel according to some embodiments; Figure 5 This is a diagram of the film structure of an array substrate in related technologies; Figure 6 This is a diagram of the film structure of an array substrate according to some embodiments; Figure 7 This is a top view of an array substrate according to some embodiments; Figure 8 and Figure 9 This is a schematic diagram of an orthographic projection onto a first substrate according to some embodiments; Figure 10 This is a diagram showing the film structure of a display panel according to some other embodiments; Figures 11-13 This is a schematic diagram of an orthographic projection onto a first substrate according to some other embodiments; Figure 14 This is a film layer structure diagram of an array substrate according to some other embodiments; Figures 15-17 This is a film layer structure diagram of an opposing substrate according to some embodiments; Figure 18 This is a film layer structure diagram of a display panel according to some other embodiments. Detailed Implementation

[0022] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0023] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0024] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0025] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. The term "connected" should be interpreted broadly; for example, a "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection via an intermediate medium. The term "coupled," for example, indicates that two or more components have direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0026] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0027] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0028] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable deviation range, which is determined by those skilled in the art taking into account the measurement under discussion and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable deviation range for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable deviation range for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable deviation range for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0029] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on another layer or substrate, or that there is an intermediate layer between the layer or element and another layer or substrate.

[0030] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0031] like Figure 1 As shown, some embodiments of this disclosure provide a display device 1, which can be any display device that displays text or images, whether in motion (e.g., video) or fixed (e.g., still images).

[0032] For example, the display device 1 can be any product or component with display functionality, such as a television, laptop, tablet, mobile phone (e.g., cell phone), personal digital assistant (PDA), camera, navigator, in-vehicle display, flight display, wearable device (e.g., watch), virtual reality (VR) device, augmented reality (AR) device, extended reality (XR) device, mixed reality (MR) device, projector, electronic billboard, or signage. For instance, the display device 1 can be... Figure 1 The television set shown is, of course, a tablet computer or other product or component with display function. This disclosure does not specifically limit the embodiments herein.

[0033] In some embodiments, the display device 1 may be a liquid crystal display (LCD) device. For example... Figure 2 As shown, the display device 1 includes a backlight module 10 and a display panel 20. The display panel 20 is an LCD panel, and is disposed on one side of the backlight module 10, which provides backlight to the display panel 20. For example, the display panel 20 includes a display side and a backlight side, with the backlight module 10 disposed on the backlight side of the display panel 20.

[0034] The display panel 20 can be an Advanced Super Dimension Switch (ADS) panel or a High Aperture Ratio Advanced-Super Dimensional Switching (HADS) panel; this embodiment does not specifically limit the type of panel.

[0035] Please continue reading. Figure 2 The display device 1 may further include a housing 30, with a backlight module 10 and a display panel 20 disposed within the housing 30. The housing 30 may include a frame 31, the longitudinal section of which may be U-shaped, for example, and the backlight module 10 and display panel 20 may be disposed within the frame 31. Furthermore, the housing 30 may also include a front frame (…). Figure 2 (not shown in the image), the front frame can be connected to the frame 31, and the backlight module 10 and the display panel 20 are disposed within the space enclosed by the front frame and the frame 31.

[0036] For example, such as Figure 2As shown, the housing 30 only includes the frame 31, that is, the display device 1 does not include the front frame. The width of the bezel of the display device 1 does not need to take into account the thickness of the front frame, which is beneficial to the narrow bezel design of the display device 1. However, the embodiments disclosed herein are not limited to this.

[0037] like Figure 2 As shown, the display device 1 may also include a circuit board 40 and a flip-chip film 50. Figure 2 (Not shown in the image) The circuit board 40 is disposed on the side of the backlight module 10 away from the display panel 20, and is connected to the display panel 20 through the flip film 50. That is, one end of the flip film 50 is connected to the bonding part of the display panel 20, and the other end bypasses the backlight module 10 and is connected to the circuit board 40.

[0038] For example, such as Figure 3 As shown, circuit board 40 includes at least one of a display driver board 410, a flexible circuit board 420, and a main board 430. For example, circuit board 40 includes a display driver board 410, a flexible circuit board 420, and a main board 430. Figure 3 The circuit board 40 includes four display driver boards 410, with one display driver board 410 electrically connected to three flip-chip films 50, as illustrated in this example. However, the number of display driver boards 410 and flip-chip films 50 is not limited to this. Of course, the circuit board 40 may also exclude the flexible circuit board 420 or other components, and this embodiment does not specifically limit this.

[0039] The motherboard 430 is responsible for signal conversion and processing, timing control, and voltage regulation and supply, while the display driver board 410 can handle core display-related functions (such as at least one of brightness adjustment, color calibration, and display signal conversion). For example, the motherboard 430 may include a timing controller (TCON) chip and a power management integrated circuit (PMIC). In addition, the motherboard 430 may also include other circuit structures such as a level shift integrated circuit (LS IC), which will not be listed here.

[0040] Furthermore, the flexible circuit board 420 can be used for electrical connections between multiple display driver boards 410, and the flip-chip film 50 can be used for electrical connections between the display driver board 410 and the display panel 20. The display driver board 410, flexible circuit board 420, and main board 430 can be bent to the backlight side of the display panel 20 along with the flip-chip film 50. At this time, the main board 430 can be electrically connected to the display driver board 410, multiple display driver boards 410 can be electrically connected to each other via the flexible circuit board 420, and each display driver board 410 can be electrically connected to the display panel 20 via the flip-chip film 50.

[0041] It should be noted that the flip-chip thin film 50 may be provided with an active electrode driving circuit 510, or the active electrode driving circuit 510 may be provided on the display panel 20. This embodiment does not specifically limit this.

[0042] As can be seen from the above, the display panel 20 and the circuit board 40 are respectively arranged on opposite sides of the backlight module 10, and the display panel 20 and the circuit board 40 are connected by the flip-chip film 50. There is no need to set an installation position for the circuit board 40 in the circumference of the display panel 20, which is beneficial to the narrow bezel of the display device 1.

[0043] In some embodiments, such as Figure 2 As shown, the display panel 20 may include an array substrate 23 and a counter substrate 24 disposed opposite to each other, and a liquid crystal layer 21 disposed between the array substrate 23 and the counter substrate 24. The array substrate 23 and the counter substrate 24 can be bonded together by an adhesive 22, thereby confining the liquid crystal layer 21 within the area enclosed by the adhesive 22 to form multiple pixel areas. The counter substrate 24 may also be referred to as a color filter substrate or an encapsulation substrate. For example, the counter substrate 24 may filter the incident light to emit multiple colors of light (such as red, green, or blue) to achieve color display. Alternatively, the array substrate 23 may filter the incident light to emit multiple colors of light (such as red, green, or blue) to achieve color display; this embodiment does not specifically limit the specific application of this method.

[0044] The working principle of the LCD panel is as follows: The backlight module 10 emits uniform light, which is converted into linearly polarized light by the lower polarizer on the side of the array substrate 23 away from the liquid crystal layer 21; the gate lines on the array substrate 23 transmit scanning signals line by line, controlling the thin film transistors (TFTs) connected to the gate lines to be turned on or off; at the same time, the data lines transmit voltage signals corresponding to the gray levels, which are written to the pixel electrodes through the turned-on TFTs, forming a driving electric field between the TFTs and the common electrode. The driving electric field drives the liquid crystal molecules in the liquid crystal layer 21 to deflect, changing the polarization direction of the linearly polarized light as it passes through the liquid crystal layer 21. This causes the polarized light emitted from the liquid crystal layer 21 to be partially absorbed, completely absorbed, or not absorbed when it is placed on the upper polarizer on the side of the opposing substrate 24 away from the liquid crystal layer 21, thus changing the gray levels of the emitted light; finally, the emitted light of different gray levels is combined to form a complete image.

[0045] The display effect of the display panel 20 is highly sensitive to the thickness of the liquid crystal layer 21. Even slight non-uniformity in the thickness of the liquid crystal layer 21 can cause deviation in the polarization direction of linearly polarized light as it passes through the liquid crystal layer 21, thereby reducing the uniformity of the display panel 20. Since the uniformity of the thickness of the liquid crystal layer 21 directly depends on the uniformity of the distance (i.e., cell thickness) between the array substrate 23 and the opposing substrate 24, a spacer 201 is usually placed between these two substrates to maintain a uniform cell thickness.

[0046] Furthermore, the display effect of the display panel 20 is also sensitive to the consistency of the initial state of the liquid crystal molecules 211 in the liquid crystal layer 21 (such as the alignment direction and pretilt angle of the liquid crystal molecules when no electric field is applied). If there is a local inconsistency in the initial state of the liquid crystal molecules 211, even if the cell thickness is completely uniform, it will change the phase retardation of the liquid crystal layer 21 for linearly polarized light, causing the polarization state of the emitted polarized light to deviate from the design value, ultimately resulting in display defects such as uneven brightness and reduced contrast. To ensure that the initial state of the liquid crystal molecules 211 remains consistent, such as... Figure 4 As shown, an alignment film 212 is typically disposed between the liquid crystal layer 21 and the array substrate 23. The oriented microgroove structure formed on the surface of the alignment film 212 by friction or photoalignment process applies a uniform anchoring effect to the liquid crystal molecules 211 in contact with it, so that the liquid crystal molecules 211 are neatly aligned in the same direction and obtain a consistent pretilt angle in the initial state without the application of an electric field, thereby avoiding the phase delay non-uniformity caused by the initial pointing deviation of the liquid crystal and ensuring display uniformity.

[0047] However, in the fabrication process of related technologies, during the leveling stage after the alignment film solution is coated, the spacers, as three-dimensional structures protruding from the surface of the array substrate, hinder the free diffusion and backflow of the alignment film solution around them. Under the influence of surface tension, the alignment film solution droplets accumulate at the base of the spacers. Simultaneously, the materials surrounding the spacers have better thermal conductivity. During heating processes such as pre-baking to form the dry alignment film, the alignment film solution around the spacers is more likely to evaporate and solidify, prematurely terminating the leveling process. This results in the alignment film thickness around the spacers being greater than in other areas, causing localized bulges on the surface, such as... Figure 5 As shown. Among them, Figure 5 Only the portion of the alignment film deposited on the surface and at the root of the spacer is shown. This uneven surface topography makes it difficult for the initial alignment and pretilt angle of the liquid crystal molecules to remain consistent when anchored to the alignment film surface, resulting in localized pretilt angle anomalies and alignment disorder. This inconsistency in initial orientation directly alters the phase retardation of the liquid crystal layer for linearly polarized light, causing the polarization state of the emitted polarized light in that region to deviate from the design value, ultimately manifesting as display unevenness problems such as brightness differences or decreased contrast.

[0048] In view of this, the present disclosure provides an array substrate 23 to alleviate the problem of uneven display in the display panel 20.

[0049] like Figure 6 and Figure 7 As shown, the array substrate 23 includes: a first substrate 231, a first electrode 232, and a first spacer portion 233. The first electrode 232 is located on one side of the first substrate 231, and the first electrode 232 has a channel 234 extending through it. Figure 7 (not shown in the image); such as Figure 6 As shown, the first spacer portion 233 is located on the side of the first electrode 232 away from the first substrate 231. For example... Figure 8 As shown, in the orthographic projection on the first substrate 231, the flow channel 234 is located on the periphery of the first septum portion 233, and the distance D1 between it and the first septum portion 233 is less than or equal to a preset value; or, as shown... Figure 9 As shown, in the orthographic projection on the first substrate 231, the flow channel 234 overlaps with the first septum portion 233 and extends partially to the outside of the first septum portion 233.

[0050] By providing a through-flow channel 234 on the first electrode 232 and arranging the channel 234 near the periphery of the first septum portion 233 or partially overlapping it, an additional flow channel can be provided for the alignment film solution during the leveling stage after coating. When the alignment film solution tends to accumulate at the root of the first septum portion 233 due to surface tension, the channel 234 can promptly guide and disperse excess solution, effectively reducing the solution accumulation height at the root of the first septum portion 233, thereby preventing local bulges on the surface of the alignment film 212 and making the thickness of the cured alignment film 212 tend to be flat. Meanwhile, the placement of the guide groove 234 interrupts the continuity of the first electrode 232 in the area surrounding the first septum 233, effectively increasing the heat conduction path length and thermal resistance in this area. This effectively slows down the heat conduction rate around the first septum 233 during pre-baking and other heating processes, reduces the solvent evaporation rate of the alignment film solution in this area, delays the curing process, and facilitates the planarization of the alignment film 212. Due to the improved planarity of the alignment film 212, the liquid crystal molecules 211 in the liquid crystal layer 21 can achieve a more consistent initial state on the surface of the alignment film 212, alleviating the display unevenness problem caused by the uneven thickness of the alignment film 212.

[0051] In some possible embodiments, the alignment film 212 is made of polyimide (PI), which has good film-forming properties and chemical stability; the first electrode 232 is made of indium tin oxide (ITO), which has both conductivity and light transmittance; and the first septum portion 233 is made of negative acrylic resin, which can form a stable support structure through a photocuring process.

[0052] In some embodiments, the process for forming the alignment film 212 may include an Asahi Kasei Photosensitive Resin (APR) coating process. Under certain pressure, the alignment film solution is uniformly coated onto the surface of the array substrate 23 in the form of tiny droplets with a volume of approximately 200 pL using an APR plate. After coating, the tiny droplets fuse together under the drive of surface tension, gradually spreading and flattening to form a wet film covering the surface of the array substrate 23. Subsequently, the wet film is subjected to heat treatment such as pre-baking to remove the solvent and cure it, ultimately forming a solid alignment film 212.

[0053] In some embodiments, the process for forming the alignment film 212 may also include an inkjet coating process, in which the alignment film solution is sprayed dropwise onto the surface of the array substrate 23 in the form of tiny droplets with a volume of approximately 100 pL through a nozzle. After each tiny droplet falls, it connects with each other to form a continuous wet film by relying on its own spreading ability on the surface of the array substrate 23 and the fusion effect between adjacent droplets. Subsequently, the solvent is removed and the film is cured by a heating process such as pre-baking to form a solid alignment film 212.

[0054] As an example, the display panel 20 includes a first electrode 232 and a second electrode 241.

[0055] like Figure 4 As shown, when the display panel 20 is a vertical alignment (VA) panel, its working principle is as follows: In the initial state, the liquid crystal molecules 211 in the liquid crystal layer 21 are in an orientation perpendicular to the substrate surface and are arranged in a direction parallel to the substrate surface. During operation, the pixel electrode receives the grayscale voltage signal and forms a longitudinal electric field perpendicular to the substrate direction between itself and the common electrode. Under the action of the electric field, the liquid crystal molecules tilt in a direction parallel to the substrate, and the tilting angle changes with the electric field, thereby changing the phase delay of the linearly polarized light passing through the liquid crystal layer 21 and realizing grayscale display. The pixel electrode is located on the surface of the array substrate 23, and the common electrode is located on the opposing substrate 24, with the two electrodes disposed on opposite sides of the liquid crystal layer 21. When the alignment film 212 is formed, it covers the pixel electrode on the surface of the array substrate 23. Therefore, in the VA panel, the first electrode 232 is the pixel electrode, and the second electrode 241 is the common electrode.

[0056] like Figure 10 As shown, when the display panel 20 is an in-plane switching (IPS) panel, its working principle is as follows: In the initial state, the liquid crystal molecules 211 in the liquid crystal layer 21 are parallel to the substrate surface and arranged in the same direction, parallel to the substrate surface. During operation, a transverse electric field parallel to the substrate surface is formed between the pixel electrode and the common electrode. Under the action of the electric field, the liquid crystal molecules 211 rotate in a plane parallel to the substrate. The rotation angle changes with the electric field, thereby changing the phase delay of the linearly polarized light passing through the liquid crystal layer 21, and realizing grayscale display. The pixel electrode and the common electrode are both located on the array substrate 23 and are spaced apart in the thickness direction of the array substrate 23. A passivation layer 230 is filled between them. The common electrode is located on the surface of the array substrate, and the pixel electrode is located on the side of the passivation layer 230 away from the common electrode and is covered by the passivation layer 230. When the alignment film 212 is formed, the alignment film 212 covers the common electrode on the surface of the array substrate 23. Therefore, in the IPS panel, the first electrode 232 is the common electrode and the second electrode 241 is the pixel electrode.

[0057] As an example, the material of the passivation layer 230 includes silicon nitride, silicon dioxide, or silicon oxynitride.

[0058] In some possible implementations, in the orthographic projection on the first substrate 231, the guide groove 234 is located on the periphery of the first septum portion 233, and the distance D1 between it and the first septum portion 233 is less than or equal to a preset value, which is half of the radial dimension K1 of the orthographic projection of the first septum portion 233 on the first substrate 231. Here, the radial dimension K1 of the orthographic projection of the first septum portion 233 on the first substrate 231 refers to the length of the longest line segment that passes through the geometric center of the orthographic projection of the first septum portion 233 on the first substrate 231 and intersects with the boundary of the orthographic projection of the first septum portion 233 on the first substrate 231. Taking a circular orthographic projection of the first septum portion 233 on the first substrate 231 as an example, the radial dimension of the orthographic projection of the first septum portion 233 on the first substrate 231 is its diameter.

[0059] The upper limit of the distance D1 between the flow channel 234 and the first septum 233 is set to half of the radial dimension K1 of the orthogonal projection of the first septum 233 on the first substrate 231. During the leveling stage of the alignment film solution, the size of the solution accumulation area formed at the root of the first septum 233 due to surface tension is limited. If the distance D1 between the flow channel 234 and the first septum 233 exceeds this upper limit, that is, the flow channel 234 is placed outside the solution accumulation area, and the alignment film solution cannot be guided and dispersed in time. Therefore, setting the distance D1 between the flow channel 234 and the first septum 233 to be less than or equal to half of the radial dimension K1 of the orthogonal projection of the first septum 233 on the first substrate 231 can ensure that the flow channel 234 is close enough to the solution accumulation area, so that the accumulated alignment film solution can be smoothly guided through the flow channel 234, which is beneficial to the leveling of the alignment film 212.

[0060] For some possible implementations, please refer to [link / reference]. Figure 8 In the orthographic projection on the first substrate 231, the flow channel 234 is located on the periphery of the first septum portion 233, and a plurality of flow channels 234 are arranged at intervals along the circumferential direction of the first septum portion 233.

[0061] Multiple guide channels 234 are arranged at intervals along the circumference of the first septum portion 233, which can create a multi-point distribution of drainage channels around the root of the first septum portion 233. During the leveling stage of the alignment membrane solution, excess solution accumulated in all directions around the root of the first septum portion 233 can be smoothly guided through the guide channels 234 in the corresponding positions, achieving uniform drainage in all circumferential areas, effectively reducing the overall solution accumulation height at the root of the first septum portion 233, thereby promoting the leveling of the alignment membrane 212.

[0062] In some possible implementations, the width H1 of the guide groove 234 is 3μm to 10μm.

[0063] Setting the width H1 of the guide channel 234 to 3μm~10μm provides a sufficient flow channel for the alignment membrane solution. During the alignment membrane solution leveling stage, this width range ensures that the guide channel 234 effectively receives and guides excess solution discharged from the root of the first septum 233, allowing the solution to diffuse smoothly along the guide channel 234, reducing the root accumulation height, and promoting the leveling of the alignment membrane 212.

[0064] As an example, when the flow guide groove 234 is spaced apart from the first septum 233, the length L1 of the flow guide groove 234 can be 10μm~50μm.

[0065] In some possible implementations, such as Figure 11 As shown, the flow channel 234 includes a first flow channel 2341 and a second flow channel 2342, with the second flow channel 2342 located on the side of the first flow channel 2341 away from the first septum portion 233.

[0066] During the alignment membrane solution leveling stage, the first guide channel 2341, closest to the root of the first septum 233, first receives and guides the most concentrated excess solution, while the second guide channel 2342, located on the outer side, further collects residual solution that has crossed the first guide channel 2341 or diffused in its peripheral area, forming a drainage path that gradually disperses from the inside out. The two-stage guide channels 234 work together to more fully guide the alignment membrane solution in different ranges at the root of the first septum 233, further reducing the solution accumulation height and improving the overall flatness of the alignment membrane 212.

[0067] In some possible implementations, the distance D2 between the first guide groove 2341 and the second guide groove 2342 is 3μm to 10μm.

[0068] Setting the distance D2 between the first flow guide channel 2341 and the second flow guide channel 2342 to 3μm~10μm ensures a reasonable interval between the two flow guide channels, forming a gradient-defined and coherent flow-guiding layout around the root of the first septum 233. This spacing range ensures that the second flow guide channel 2342 is within the effective overflow receiving area of ​​the first flow guide channel 2341. When the amount of solution guided by the first flow guide channel 2341 exceeds its capacity, or when some solution diffuses outward along the substrate surface, the second flow guide channel 2342 can collect and continue guiding the solution in a timely manner, reducing the risk of solution re-accumulating around the first flow guide channel 2341.

[0069] Furthermore, when the width H1 of the guide channel 234 and the distance D2 between the first guide channel 2341 and the second guide channel 2342 are both within the matching range of 3μm to 10μm, the capacity of the guide channel 234 and the solution conduction capacity of the inter-channel area are coordinated with each other, so that the alignment membrane solution around the root of the first septum 233 can be dispersed in an orderly manner through each level of the guide channel 234, avoiding local solution overflow or interruption of drainage due to mismatch between channel width and spacing, further reducing the overall stacking height of the alignment membrane solution and improving the flatness of the alignment membrane 212.

[0070] In some embodiments, a guide groove 234 may be formed on the side of the second guide groove 2342 away from the first guide groove 2341 to further improve the guiding and diffusion effect on the alignment membrane solution.

[0071] In some possible implementations, the shape of the guide channel 234 can be as follows: Figure 8 and Figure 11 The elongated shape shown, or the shape of the guide groove 234, can be as follows: Figure 12 The arc shape shown. Here, the arc shape or elongated shape means that the center line of the guide groove 234 in the extension direction is arc-shaped or straight.

[0072] In some possible implementations, such as Figure 9 As shown, in the orthographic projection on the first substrate 231, the flow channel 234 overlaps with the first septum portion 233, and a portion of the flow channel 234 is located on the periphery of the first septum portion 233; the flow channel 234 includes a third flow channel 2343 and a fourth flow channel 2344, and the extending directions of the third flow channel 2343 and the fourth flow channel 2344 intersect.

[0073] Thus, the third and fourth guide channels 2343 and 2344 can intersect the area covered by the first septum 233 and penetrate the solution accumulation area. During the alignment membrane solution leveling stage, the solution accumulated in all directions around the root of the first septum 233 can be received nearby through the guide channels extending to the periphery and orderly guided along the extension direction of the guide channels. The intersecting third and fourth guide channels 2343 and 2344 provide different flow paths, allowing solutions from different directions to be smoothly introduced into the guide channels, achieving uniform flow in multiple directions, reducing the solution accumulation height at the root of the first septum 233, and promoting the leveling of the alignment membrane 212.

[0074] As an example, when the flow guide groove 234 overlaps with the first septum portion 233, the length L1 of the flow guide groove 234 can be 30μm~100μm.

[0075] In some examples, the third guide channel 2343 and the fourth guide channel 2344 extend in perpendicular directions.

[0076] In some possible implementations, such as Figure 13 As shown, the flow guide 234 includes a plurality of third flow guides 2343 and fourth flow guides 2344, the distance D3 between two adjacent third flow guides 2343 is 3μm~10μm, and / or the distance D4 between two adjacent fourth flow guides 2344 is 3μm~10μm.

[0077] As an example, the number of the third guide channel 2343 and the fourth guide channel 2344 can each be 3.

[0078] Setting the spacing between adjacent, unidirectionally extending channeling grooves 234 to 3μm~10μm creates a channeling groove array 234 with appropriate density around the periphery of the first septum portion 233. This spacing range ensures effective coverage of the inter-groove area by adjacent channeling grooves 234, allowing the accumulated solution around the root of the first septum portion 233 to be received and channeled by the nearest channeling groove. Simultaneously, this spacing matches the width H1 of the channeling grooves 234, resulting in a balanced distribution of the width H1 of the channeling grooves and the partial width of the first electrode 232 between the grooves. This helps to improve the flatness of the alignment film 212 while maintaining the stability of the electrical performance of the first electrode 232.

[0079] In some possible implementations, such as Figure 6 and Figure 14 As shown, the array substrate 23 also includes a conductive structure 235 and an insulating layer 236. The conductive structure 235 is disposed between the first substrate 231 and the first electrode 232; the insulating layer 236 is disposed between the conductive structure 235 and the first electrode 232, and the insulating layer 236 has a connection via 2361 that penetrates the insulating layer 236. The first electrode 252 is electrically connected to the conductive structure 235 through the connection via 2361. In the orthographic projection on the first substrate 231, the first spacer portion 233 covers the connection via 2361.

[0080] The conductive structure 235 is used to provide the required potential signal to the first electrode 232. For example, as shown... Figure 6 In the array substrate 23 of the IPS panel shown, the conductive structure 235 includes a TFT. The source or drain of the TFT is electrically connected to a second electrode 241, which serves as a pixel electrode, through a connecting via 2361. When the gate scan signal controls the TFT to turn on, the grayscale voltage signal on the data line is written to the second electrode 241 to control the pixel electrode potential. The conductive structure 235 also includes a common voltage line (Vcom line). The Vcom line is electrically connected to a first electrode 232, which serves as a common electrode, through a connecting via 2361, providing a stable common voltage reference potential for the first electrode 232. Figure 14In the array substrate 23 of the VA panel shown, the conductive structure 235 includes a TFT. The source or drain of the TFT is electrically connected to the first electrode 232, which serves as a pixel electrode, through a connecting via 2361. When the gate scan signal controls the TFT to turn on, the grayscale voltage signal on the data line is written into the first electrode 232 to realize the control of the pixel electrode potential.

[0081] The insulating layer 236 is, for example, an organic film, used to reduce the coupling between different conductive structures 235 in the array substrate 23, for example, to reduce the coupling between the TFT source / drain electrodes and the common electrode and / or pixel electrode, so as to obtain the largest possible aperture ratio.

[0082] As an example, the cross-sectional shape of the connecting via 2361 is an inverted trapezoid with a depth of 2μm to 3μm. The diameter of the upper bottom on the side near the first electrode 232 is about 9μm, and the diameter of the lower bottom on the side near the conductive structure 235 is about 5μm. The material of the first septum 233 is embedded in the interior of the connecting via 2361 and forms a protrusion above the hole, together forming a mushroom-shaped support structure.

[0083] By positioning the first spacer portion 233 to cover the connection via 2361 in its orthogonal projection onto the first substrate 231, the first spacer portion 233 can provide shielding protection for the connection via 2361. During the fabrication and subsequent use of the display panel 20, the connection via 2361 is a weak point susceptible to moisture erosion and stress damage due to film layer breaks and significant step differences. The first spacer portion 233 covering the connection via 2361 isolates it from the external environment, reducing the risk of moisture intrusion along the via interface and causing electrode corrosion, thereby improving the reliability of the connection via 2361 and its surrounding structure.

[0084] In some possible implementations, such as Figure 15 , Figure 16 and Figure 17 As shown, the opposing substrate 24 includes a second substrate 242 and a second spacer portion 243. (As...) Figure 18 As shown, the second spacer portion 243 is located on the side of the second substrate 242 near the liquid crystal layer 21, and the second spacer portion 243 abuts against the first spacer portion 233.

[0085] This configuration allows the height of the first spacer portion 233 to be less than the thickness of the wet alignment film, ensuring that the coated wet alignment film completely covers the top surface of the first spacer portion 233. During the alignment film solution leveling stage, since the first spacer portion 233 is no longer higher than the wet film surface, the wet film can continuously spread above the first spacer portion 233, eliminating solution circumference and root accumulation caused by the spacer 201 protruding from the liquid surface. This reduces the thickness difference of the alignment film around the first spacer portion 233 and improves the overall flatness of the cured alignment film 212. Simultaneously, a second spacer portion 243 is provided at a corresponding position on the opposing substrate 24, so that the second spacer portion 243 abuts against the first spacer portion 233. Together, they form a complete spacer 201, and their total height meets the preset cell thickness requirement. While improving the flatness of the alignment film 212, it can still reliably maintain the uniformity of cell thickness between the array substrate 23 and the opposing substrate 24.

[0086] As an example, the thickness of the display panel 20 is 3.5μm, so the height H2 of the first spacer portion 233 can be less than 1μm, and correspondingly, the height H3 of the second spacer portion 243 is about 2.5μm.

[0087] In some possible implementations, such as Figure 16 and Figure 17 As shown, the opposing substrate 24 further includes a color resist portion 244, a light-shielding portion 245, and a planarization layer 246. The color resist portion 244 is located on the side of the second substrate 242 near the second spacer portion 243, and the light-shielding portion 245 is located on the side of the second substrate 242 near the second spacer portion 243 and is at least partially located between adjacent color resist portions 244; the planarization layer 246 covers the surface of the color resist portion 244 and the light-shielding portion 245 away from the second substrate 242; as shown... Figure 16 As shown, one end of the second spacer portion 243 is connected to the color resist portion 244, and the other end penetrates the planarization layer 246 and extends to the side of the planarization layer 246 away from the second substrate 242; or, as Figure 17 As shown, one end of the second spacer portion 243 is connected to the light-shielding portion 245, and the other end penetrates through the planarization layer 246 and extends to the side of the planarization layer 246 away from the second substrate 242.

[0088] The color resist section 244 includes color resist units of various colors, such as red, green, and blue color resist units, each corresponding to a different sub-pixel. After the light emitted from the backlight module 10 passes through the lower polarizer and the liquid crystal layer 21, it is incident on the color resist unit of the corresponding color. The color resist unit selectively transmits light of a specific wavelength, filtering the light into monochromatic light of the corresponding color.

[0089] The light-shielding part 245 is used to separate adjacent color resist units. It is usually a black matrix containing light-shielding pigments or dyes. It has a high absorption rate for visible light and can effectively absorb and block light leakage in the pixel gap area, thereby improving the display contrast. At the same time, it can also reduce the risk of external light shining on the TFTs, gate lines and data lines on the array substrate 23 and causing reflections that affect the display effect of the display panel 20.

[0090] With this configuration, the second spacer portion 243 is formed directly on the color resist portion 244 or the light-shielding portion 245 and penetrates the planarization layer 246. While the effective height H4 of the second spacer portion 243 remains unchanged, the actual height H5 increases significantly. For example, when one end of the second spacer portion 243 is connected to the color resist portion 244, the actual height H5 of the second spacer portion 243 can increase from approximately 2.5 μm to approximately 4.3 μm; or, when one end of the second spacer portion 243 is connected to the light-shielding portion 245, the actual height H5 of the second spacer portion 243 can increase from approximately 2.5 μm to approximately 6.5 μm.

[0091] Here, the actual height H5 refers to the total physical height of the second spacer portion 243 from its bottom surface in contact with the color resist portion 244 and the light-shielding portion 245 to its top surface; the effective height H4 refers to the portion of the second spacer portion 243 that extends beyond the surface of the planarization layer 246 and actually participates in supporting the box thickness. Since the bottom of the second spacer portion 243 is embedded below the planarization layer 246, compared to a solution where the second spacer portion is directly placed on the surface of the planarization layer, the actual height H5 of the second spacer portion 243 is greater when the effective height H4 is the same.

[0092] The second septum portion 243, which has a larger actual height H5, can provide better elastic recovery force. When the display panel 20 is subjected to external pressure, the higher second septum portion 243 can better absorb and buffer the external pressure, and fully restore its original shape after the external force is removed. This can effectively improve the dark non-uniformity (DNU) phenomenon of the display panel 20.

[0093] Meanwhile, the increase in the actual height H5 of the second spacer portion 243 reduces the percentage fluctuation of its actual height H5 under the same process precision. For example, when the actual height H5 of the second spacer portion 243 increases from 2.5μm to 4.3μm, its height fluctuation percentage can be reduced from 8% to 5%; when the actual height H5 of the second spacer portion 243 increases from 2.5μm to 6.5μm, its height fluctuation percentage can be reduced from 8% to below 3%. This further reduces the cell thickness fluctuation of the display panel 20, improves the display uniformity of the display panel 20, and reduces the DNU phenomenon.

[0094] Furthermore, with the amount of liquid crystal in the liquid crystal layer 21 fixed, the reduction in the height fluctuation of the spacer 201 reduces the friction between it and the opposite substrate. When the display panel 20 is subjected to external force locally, the smaller friction makes it easier for the deformation to recover, which can further improve the DNU phenomenon of the display panel 20.

[0095] Regarding the Liquid Crystal Margin (LC Margin), since the Liquid Crystal Margin is determined by both the amount of liquid crystal in the liquid crystal layer 21 and the height of the spacer 201, the reduction in the height fluctuation of the spacer 201 makes the control of LC Margin more precise, which can effectively reduce display defects caused by liquid crystal amount mismatch and improve product yield.

[0096] Although the spacer material 201, the light-shielding part 245, the color resist part 244, and the planarization layer 246 all belong to the acrylic resin system, they differ significantly in terms of elastic recovery rate. The crosslinking density of the spacer material 201 can be flexibly adjusted to regulate its elastic recovery rate, giving it excellent elastic deformation and recovery capabilities. In contrast, materials such as the planarization layer 246 typically require the addition of epoxy components to improve crosslinking density and shielding properties, with elasticity being merely a passive manifestation of its capabilities. In terms of morphology, the spacer material 201 exhibits a columnar structure, deforming under compression and recovering its shape after the external force is removed. The planarization layer 246, on the other hand, has a planar structure; under localized pressure, the polymer chains are prone to creep under stress, transforming from elastic deformation to plastic deformation, which is difficult to recover once it occurs. Therefore, setting the second spacer part 243 as a taller columnar structure can fully utilize its dual elastic advantages in both material and morphology, providing more reliable cell thickness support and deformation recovery capabilities for the display panel 20.

[0097] As an example, a color resist portion 244 and a light-shielding portion 245 are first formed on a second substrate 242. Then, a second spacer portion 243 is prepared on the surface of the color resist portion 244 or the light-shielding portion 245 away from the second substrate 242. After that, a planarization layer 246 is coated and covers the sidewalls of the color resist portion 244, the light-shielding portion 245 and the second spacer portion 243. The thickness of the planarization layer 246 is controlled so that the top of the second spacer portion 243 is exposed, thereby forming a structure in which the second spacer portion 243 penetrates the planarization layer 246.

[0098] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An array substrate, characterized in that, include: First substrate; The first electrode is located on one side of the first substrate; The first electrode is provided with a flow guide groove that penetrates the first electrode; The first septum portion is located on the side of the first electrode away from the first substrate; in the orthographic projection on the first substrate, the flow channel is located on the periphery of the first septum portion and the distance between it and the first septum portion is less than or equal to a preset value; or, in the orthographic projection on the first substrate, the flow channel overlaps with the first septum portion and partially extends to the outside of the first septum portion.

2. The array substrate according to claim 1, characterized in that, The preset value is half of the radial dimension of the first spacer portion projected onto the first substrate.

3. The array substrate according to claim 1 or 2, characterized in that, In the orthographic projection on the first substrate, the flow channel is located on the periphery of the first septum portion, and the plurality of flow channels are spaced apart along the circumferential direction of the first septum portion.

4. The array substrate according to claim 3, characterized in that, The flow channel includes a first flow channel and a second flow channel, with the second flow channel located on the side of the first flow channel away from the first septum portion.

5. The array substrate according to claim 4, characterized in that, The distance between the first guide channel and the second guide channel is 3μm~10μm.

6. The array substrate according to any one of claims 3 to 5, characterized in that, The guide channel is in the shape of an arc or a long strip.

7. The array substrate according to claim 1 or 2, characterized in that, In the orthographic projection on the first substrate, the flow channel overlaps with the first septum portion, and a portion of the flow channel is located on the periphery of the first septum portion; The flow channel includes a third flow channel and a fourth flow channel, and the extension directions of the third flow channel and the fourth flow channel intersect.

8. The array substrate according to claim 7, characterized in that, The flow channel includes a plurality of third flow channels and a plurality of fourth flow channels, wherein the distance between two adjacent third flow channels is 3μm to 10μm, and / or the distance between two adjacent fourth flow channels is 3μm to 10μm.

9. The array substrate according to any one of claims 1 to 8, characterized in that, The width of the guide groove is 3μm~10μm.

10. The array substrate according to any one of claims 1 to 9, characterized in that, Also includes: A conductive structure is disposed between the first substrate and the first electrode; An insulating layer is disposed between the conductive structure and the first electrode; The insulating layer is provided with a connection via that penetrates the insulating layer. The first electrode is electrically connected to the conductive structure through the connection via. In the orthographic projection on the first substrate, the first spacer portion covers the connection via.

11. A display panel, characterized in that, include: The array substrate as described in any one of claims 1 to 10; The opposing substrate is disposed opposite to the array substrate; A liquid crystal layer is located between the array substrate and the opposing substrate.

12. The display panel according to claim 11, characterized in that, The opposing substrate includes: Second substrate; The second spacer portion is located on the side of the second substrate closer to the liquid crystal layer; the second spacer portion abuts against the first spacer portion.

13. The display panel according to claim 12, characterized in that, The opposing substrate further includes: The color resist portion is located on the side of the second substrate near the second spacer portion; The light-shielding portion is located on the side of the second substrate near the second spacer portion, and is at least partially located between adjacent color resist portions; A planarization layer covers the surface of the color resist portion and the light-shielding portion away from the second substrate; one end of the second spacer portion is connected to the color resist portion or the light-shielding portion, and the other end penetrates the planarization layer and extends to the side of the planarization layer away from the second substrate.

14. A display device, characterized in that, include: The display panel as described in any one of claims 11 to 13; A backlight module is disposed on the backlight side of the display panel.

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