Display panel and display device

Abstract

The application provides a display panel and a display device; the display panel comprises a plurality of pixel groups, each pixel group comprises a first sub-pixel and a second sub-pixel arranged adjacent along a first direction, the first sub-pixel comprises a first transistor and a first pixel electrode, the second sub-pixel comprises a second transistor and a second pixel electrode, and the first transistor and the second transistor are both located in the first sub-pixel; the first transistor and the second transistor in one pixel group are arranged adjacent to the first transistor and the second transistor in another pixel group, so that the transistors in the two pixel groups are all gathered between the two pixel groups, and a sufficient non-light-transmitting area is reserved to arrange a support column, the area of the light-transmitting area of the sub-pixel occupied by the support column is avoided, and the aperture ratio of the sub-pixel is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] Liquid Crystal Display (LCD) panels are widely used in various electronic devices such as mobile phones, digital cameras, computer screens, and laptop screens. In current display panels, the support pillars have a relatively large area, which occupies part of the light-transmitting area of ​​the sub-pixels, reducing the aperture ratio of the sub-pixels and affecting the display effect of the panel. Summary of the Invention

[0003] This application provides a display panel and display device to improve the technical problem of small aperture ratio of sub-pixels in existing display panels.

[0004] To address the above issues, the technical solution provided in this application is as follows: This application discloses a display panel comprising a plurality of pixel groups, each pixel group comprising: The first sub-pixel includes a first transistor and a first pixel electrode; The second sub-pixel is disposed adjacent to the first sub-pixel along a first direction. The second sub-pixel includes a second transistor and a second pixel electrode. Both the first transistor and the second transistor are located within the first sub-pixel. In the two pixel groups arranged along the second direction, the first transistor and the second transistor in one pixel group are arranged adjacent to the first transistor and the second transistor in the other pixel group.

[0005] Optionally, the plurality of pixel groups include a plurality of repeating units, each of the repeating units including a first pixel group and a second pixel group arranged along the second direction; In one of the repeating units, the first transistor and the second transistor in the first pixel group, and the first transistor and the second transistor in the second pixel group, are both located between the first pixel electrode of the first pixel group and the first pixel electrode of the second pixel group.

[0006] Optionally, the area of ​​the first pixel electrode is less than or equal to the area of ​​the second pixel electrode.

[0007] Optionally, the first pixel electrode includes a first sub-part and a second sub-part disposed adjacent to each other, the first sub-part being disposed away from the second pixel electrode and the second sub-part being disposed close to the second pixel electrode; Wherein, the length of the first sub-part in the second direction is greater than or equal to the length of the second sub-part in the second direction.

[0008] Optionally, the first sub-part and the first transistor are arranged along the second direction, and the second sub-part and the second transistor are arranged along the second direction.

[0009] Optionally, the display panel further includes: First substrate; A common electrode line is disposed on one side of the first substrate, and the common electrode line is disposed between the two pixel groups arranged along the second direction, and the common electrode line is disposed on the side of the first pixel electrode away from the first transistor; Multiple common electrode blocks, one of the common electrode blocks corresponding to a pixel electrode in the pixel group; The common electrode line is located on the surface of the common electrode block away from the first substrate.

[0010] Optionally, the distance between the first pixel electrode and the common electrode line is less than or equal to the distance between the second pixel electrode and the common electrode line.

[0011] Optionally, the width of the first pixel electrode in the first pixel group is greater than the width of the second pixel electrode in the first pixel group, and the width of the second pixel electrode in the second pixel group is greater than the width of the first pixel electrode in the second pixel group.

[0012] Optionally, the width of the first pixel electrode in the first pixel group is equal to the width of the second pixel electrode in the second pixel group, and the width of the first pixel electrode in the second pixel group is equal to the width of the second pixel electrode in the first pixel group.

[0013] Optionally, the display panel further includes: The color filter layer includes multiple light-shielding units and multiple color-resisting units. The light-shielding units are disposed between two pixel groups arranged along the second direction, and one color-resisting unit corresponds to a pixel electrode in the pixel group. The light-shielding unit extends along the first direction and covers the first transistor and the second transistor in the pixel group.

[0014] Optionally, the light-shielding unit includes a first light-shielding part and a second light-shielding part arranged adjacent to each other. The first light-shielding part is located between the first pixel electrode of the first pixel group and the first pixel electrode of the second pixel group, and the second light-shielding part is located between the second pixel electrode of the first pixel group and the second pixel electrode of the second pixel group. Wherein, the width of the first light-shielding part in the second direction is greater than the width of the second light-shielding part in the second direction.

[0015] Optionally, the display panel further includes: An array layer, comprising the first transistor and the second transistor; A pixel electrode layer is disposed on one side of the array layer, the pixel electrode layer including a first pixel electrode and a second pixel electrode disposed adjacently; and A planarization layer is disposed between the array layer and the pixel electrode layer. A first via is formed on the planarization layer. The first pixel electrode passes through one of the first vias and is electrically connected to the first transistor. The second pixel electrode passes through another of the first vias and is electrically connected to the second transistor. In the top view, the first via in both the first pixel group and the second pixel group is located within the second light-shielding part.

[0016] Optionally, the display panel further includes a plurality of support pillars, and the second light-shielding portion covers the support pillars.

[0017] Optionally, the color of the color resist unit corresponding to the first pixel electrode of the first pixel group is the same as the color of the color resist unit corresponding to the first pixel electrode of the second pixel group; The color of the color resist unit corresponding to the second pixel electrode of the first pixel group is the same as or different from the color resist unit corresponding to the second pixel electrode of the second pixel group.

[0018] This application also proposes a display device that includes the aforementioned display panel.

[0019] This application arranges the first and second transistors in one pixel group adjacent to the first and second transistors in another pixel group, so that the transistors in the two pixel groups are converged between the two pixel groups, so as to reserve enough non-transparent area for the support pillar, avoid the support pillar occupying the area of ​​the light-transmitting area of ​​the sub-pixel, and improve the aperture ratio of the sub-pixel.

[0020] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0023] Figure 1 This is a simplified structural diagram of the display panel of this application; Figure 2 This is a diagram of the film structure of the display panel in this application; Figure 3 This is the first structural diagram of the pixel group in this application; Figure 4 This is a second structural diagram of the pixel group in this application; Figure 5 This is a third structural diagram of the pixel group in this application; Figure 6 This is the fourth structural diagram of the pixel group in this application. Detailed Implementation

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0025] Please see Figures 1 to 6 This application provides a display panel 100, which includes a plurality of pixel groups PL, each pixel group PL including a first sub-pixel 10a and a second sub-pixel 10b.

[0026] In this embodiment, the first sub-pixel 10a includes a first transistor T1 and a first pixel electrode PE1. The second sub-pixel 10b is disposed adjacent to the first sub-pixel 10a along the first direction X. The second sub-pixel 10b includes a second transistor T2 and a second pixel electrode PE2. The first transistor T1 and the second transistor T2 are both located within the first sub-pixel 10a.

[0027] In this embodiment, in two pixel groups PL arranged along the second direction Y, the first transistor T1 and the second transistor T2 in one pixel group PL are arranged adjacent to the first transistor T1 and the second transistor T2 in the other pixel group PL.

[0028] This application arranges the first transistor T1 and the second transistor T2 in one pixel group PL adjacent to the first transistor T1 and the second transistor T2 in another pixel group PL, so that the transistors in the two pixel groups PL are all converged between the two pixel groups PL, so as to reserve enough non-transparent area to set up the support pillar 130, avoid the support pillar 130 occupying the area of ​​the light-transmitting area of ​​the sub-pixel 10, and improve the aperture ratio of the sub-pixel 10.

[0029] In this embodiment, the display panel 100 is provided with a plurality of pixel groups PL, which are arranged along the first direction X and the second direction Y. Each pixel group PL includes at least two sub-pixels 10. For example, this application describes the case where each pixel group PL includes two sub-pixels 10. Each sub-pixel 10 includes a transistor and a pixel electrode PE electrically connected to the transistor. The pixel electrode PE in each pixel group PL is arranged along the first direction X.

[0030] In this embodiment, the display panel 100 is further provided with multiple scan lines Scan, multiple data lines Data, and a common electrode line CM. The multiple scan lines Scan are arranged at intervals along the second direction Y, and two scan lines Scan are provided between two adjacent rows of pixel groups PL. The multiple data lines Data are arranged at intervals along the first direction X, and one data line Data is provided between two adjacent columns of sub-pixels.

[0031] It should be noted that the scan lines extend along the first direction X, and the data lines extend along the second direction Y. The angle between the first direction X and the second direction Y in this application can be greater than 0 and less than or equal to 90 degrees. For example, the angle between the first direction X and the second direction Y in this application can be 90 degrees.

[0032] In this embodiment, the plurality of pixel groups PL include a plurality of repeating units RU, and each repeating unit RU includes a first pixel group PL1 and a second pixel group PL2 arranged along the second direction Y. For example, in Figure 3 In the middle, the two side edges of the first pixel group PL1 and the second pixel group PL2 are aligned in the first direction; in Figure 4 In the middle, the first pixel group PL1 and the second pixel group PL2 are staggered in the second direction, and staggered by 1 sub-pixel.

[0033] For example, please see Figure 3Each of the first pixel group PL1 and the second pixel group PL2 has a first sub-pixel 10a and a second sub-pixel 10b. In a repeating unit RU, the first sub-pixel 10a in the first pixel group PL1 and the first sub-pixel 10a in the second pixel group PL2 are arranged along the second direction Y, and the second sub-pixel 10b in the first pixel group PL1 and the second sub-pixel 10b in the second pixel group PL2 are arranged along the second direction Y. The first transistor T1 in the first pixel group PL1 and the first transistor T1 in the second pixel group PL2 are both connected to a data line Data, and the second transistor T2 in the first pixel group PL1 and the second transistor T2 in the second pixel group PL2 are both connected to another data line Data.

[0034] For example, please see Figure 4 Each pixel group PL1 and pixel group PL2 has a first sub-pixel 10a and a second sub-pixel 10b. In a repeating unit RU, the first sub-pixel 10a in the first pixel group PL1 and the first sub-pixel 10a in the second pixel group PL2 are arranged along the second direction Y. The second sub-pixel 10b in the first pixel group PL1 is located on the side of the first sub-pixel 10a in the first pixel group PL1 away from the second sub-pixel 10b in the second pixel group PL2 along the first direction X. The second sub-pixel 10b in the second pixel group PL2 is located on the side of the first sub-pixel 10a in the second pixel group PL2 away from the second sub-pixel 10b in the first pixel group PL1 along the first direction X. The first transistor T1 in the first pixel group PL1 and the second transistor T2 in the second pixel group PL2 are both connected to a data line Data. The second transistor T2 in the first pixel group PL1 and the first transistor T1 in the second pixel group PL2 are both connected to another data line Data.

[0035] For example, please see Figure 3 and Figure 4 In a repeating unit RU, a first scan line Scan1 and a second scan line Scan2 are provided between the first pixel group PL1 and the second pixel group PL2. The first scan line Scan1 is electrically connected to the first transistor T1 and the second transistor T2 in the first pixel group PL1. The second scan line Scan2 is electrically connected to the first transistor T1 and the second transistor T2 in the second pixel group PL2.

[0036] It should be noted that the arrangement of the sub-pixels 10 in this application can be a standard RGB arrangement, that is, the red sub-pixels 10, green sub-pixels 10 and blue sub-pixels 10 are arranged as a unit group and repeated along the first direction X, and the color of each column of sub-pixels 10 is the same.

[0037] The technical solution of this application will now be described in conjunction with specific embodiments.

[0038] Please see Figure 1 The display panel 100 includes a display area AA and a non-display area NA adjacent to the display area AA. The display area AA contains multiple rows of sub-pixels. Optionally, the non-display area NA surrounds the display area AA, so that the display area AA is surrounded by the non-display area NA. The display area AA is the area within the display panel 100 used for display functions, and it contains multiple display units that implement its display functions. The non-display area NA may be a border area of ​​the display panel 100, and it may contain functional components that assist the display units within the display area AA in displaying information.

[0039] Please see Figure 1 A bonding terminal 400 is provided on the lower side of the display area AA. The bonding terminal 400 can be connected to an external circuit and transmits the signal input from the external circuit to the data trace, thereby driving the display panel 100 to display the image. For example, the bonding terminal 400 can be bonded to a chip or a flip-chip film to provide power and drive signals to the display panel 100.

[0040] Please see Figure 2 , Figure 2 This is a diagram of the film structure of the display panel 100 of this application. The display panel 100 includes a first substrate 110, a second substrate 120 disposed opposite to the first substrate 110, and a liquid crystal layer LC located between the first substrate 110 and the second substrate 120. The first substrate 110 can be an array substrate, and the second substrate 120 can be a color filter substrate.

[0041] Please see Figure 2 The first substrate 110 may include a first substrate 111 and a plurality of transistors located on the first substrate 111. The transistors may be etch-block type, back-channel etch type, or classified into bottom-gate thin-film transistors, top-gate thin-film transistors, etc., depending on the position of the gate and the active layer 115. The display panel film structure of this application is described below using a high transmission fringe field switching (HFS) type display product as an example.

[0042] Please see Figure 2 The first substrate 110 may include a gate layer 113 on the first substrate 111, an inter-insulating layer 114 on the gate layer 113, an active layer 115 on the inter-insulating layer 114, a source-drain layer 116 on the active layer 115, a first passivation layer PV1 on the source-drain layer 116, a planarization layer 112 on the first passivation layer PV1, a first electrode layer 117 on the planarization layer 112, a second passivation layer PV2 on the first electrode layer 117, and a second electrode layer 118 on the passivation layer PV2.

[0043] In this embodiment, the materials of the first electrode layer 117 and the second electrode layer 118 can both be transparent conductive materials.

[0044] exist Figure 2 In the structure, the second electrode layer 118 is the pixel electrode layer, and the first electrode layer 117 is the common electrode layer.

[0045] Please see Figure 2 The second substrate 120 may include a second substrate 121 and a color filter layer 122 located on the second substrate 121. The color filter layer 122 includes a plurality of spaced color resist units CF and a light-shielding unit BM disposed between two adjacent color resist units CF. One color resist unit may correspond to one pixel electrode in a pixel group. The light-shielding unit BM may be in the form of a mesh structure or a strip structure.

[0046] Please see Figure 2 The display panel 100 also includes a support post 130 disposed between the first substrate 110 and the second substrate 120, the support post 130 corresponding to the area where the light-shielding unit BM and the thin film transistor are located.

[0047] Please see Figure 2 The display panel 100 also includes a second polarizer POL2 and a first polarizer POL1. The second polarizer POL2 is disposed on the surface of the second substrate 120 away from the first substrate 110, and the first polarizer POL1 is disposed on the surface of the first substrate 110 away from the second substrate 120. That is, the second polarizer POL2 is disposed on the surface of the second substrate 121 away from the first substrate 110, and the first polarizer POL1 is disposed on the surface of the first substrate 111 away from the second substrate 120.

[0048] It should be noted that, Figure 2 The film layer structure of the display panel 100 is merely an example of this application, and the film layer structure of this application is not limited to... Figure 2 The structure.

[0049] In this embodiment, the array layer 110a includes a first transistor T1 and a second transistor T2; the pixel electrode layer 118 includes a first pixel electrode PE1 and a second pixel electrode PE2 disposed adjacently; a first via HL1 is formed on the planarization layer 112, and a second via HL2 is formed on the second passivation layer PV2. In the top view, the second via HL2 is located inside the first via HL1, which is equivalent to the second via HL2 passing through the first via HL1.

[0050] In this embodiment, the first pixel electrode PE1 is electrically connected to the first transistor T1 through a second via HL2, and the second pixel electrode PE2 is electrically connected to the second transistor T2 through another second via HL2. At the same time, since the second via HL2 passes through the first via HL1, the first pixel electrode PE1 of this application is electrically connected to the first transistor T1 through a first via HL1, and the second pixel electrode PE2 is electrically connected to the second transistor T2 through another first via HL1.

[0051] It should be noted that in the prior art, a planarization layer 112 is usually not provided. However, due to the small spacing between the common electrode layer 117 and the gate layer 113, the coupling capacitance between the common electrode layer 117 and the gate layer 113 is too large. The planarization layer 112 in this application increases the spacing between the common electrode layer 117 and the gate layer 113, thereby reducing the coupling capacitance between them. However, since the planarization layer 112 is relatively thick, a larger first via HL1 is required. The larger first via HL1 occupies part of the space in the non-transparent area, resulting in a decrease in the aperture ratio of the sub-pixel 10.

[0052] This application enables four transistors in the first pixel group PL1 and the second pixel group PL2 to converge between the first pixel electrode PE1 of the first pixel group PL1 and the first pixel electrode PE1 of the second pixel group PL2, thereby creating a large non-transparent area between the first pixel electrode PE1 of the first pixel group PL1 and the first pixel electrode PE1 of the second pixel group PL2. This provides sufficient space in the non-transparent area to accommodate the first via HL1 without occupying the space of the transparent area of ​​the sub-pixel 10, thus improving the aperture ratio of the sub-pixel 10.

[0053] Please see Figure 2 The common electrode layer 117 includes multiple common electrode lines 117a and multiple common electrode blocks 117b. Each common electrode block 117b corresponds to a pixel electrode PE in a pixel group PL. The common electrode lines 117a are located between two pixel groups PL arranged along the second direction Y. Figure 3 In the attached drawings, the common electrode line 117a is disposed on the side of the first pixel electrode PE1 away from the first transistor T1, and in the thickness direction of the display panel 100, the common electrode line 117a is disposed on the surface of the common electrode block 117b away from the array layer 110a.

[0054] In this embodiment, the common electrode line 117a is made of a single layer of metal, and the surfaces of the common electrode line 117a and the plurality of common electrode blocks 117b arranged along the first direction X are in direct contact, so that the plurality of common electrode blocks 117b arranged at intervals along the first direction X are electrically connected.

[0055] The arrangement of the common electrode line 117a in this application avoids the common electrode block 117b from being connected to the signal source through the electrical connection hole, eliminates the contact resistance of the electrical connection hole, and improves the uniformity of the common signal on multiple common electrode blocks 117b.

[0056] exist Figure 3 and Figure 4 In the first pixel group PL1, the color of the color resist unit CF corresponding to the first pixel electrode PE1 is the same as the color resist unit CF corresponding to the first pixel electrode PE1 of the second pixel group PL2. exist Figure 3 In the first pixel group PL1, the color of the color resist unit CF corresponding to the second pixel electrode PE2 is the same as the color resist unit CF corresponding to the second pixel electrode PE2 of the second pixel group PL2; in Figure 4 In the first pixel group PL1, the color of the color resist unit CF corresponding to the second pixel electrode PE2 is different from the color of the color resist unit CF corresponding to the second pixel electrode PE2 of the second pixel group PL2.

[0057] In a repeating unit RU, the first transistor T1 and the second transistor T2 in the first pixel group PL1, and the first transistor T1 and the second transistor T2 in the second pixel group PL2 are all located between the first pixel electrode PE1 of the first pixel group PL1 and the first pixel electrode PE1 of the second pixel group PL2.

[0058] Please see Figure 3 In a repeating unit RU, the first transistor T1 of the first pixel group PL1 and the first transistor T1 of the second pixel group PL2 are arranged along the second direction Y, and the second transistor T2 of the first pixel group PL1 and the second transistor T2 of the second pixel group PL2 are arranged along the second direction Y.

[0059] Please see Figure 4 In a repeating unit RU, the first transistor T1 of the first pixel group PL1 and the second transistor T2 of the second pixel group PL2 are arranged along the second direction Y, and the second transistor T2 of the first pixel group PL1 and the first transistor T1 of the second pixel group PL2 are arranged along the second direction Y.

[0060] In this embodiment, the second transistor T2 can be electrically connected to the second pixel electrode PE2 via an extension line across the data line Data, and the first transistor T1 can be directly electrically connected to the first pixel electrode PE1.

[0061] In this embodiment, in a repeating unit RU, the second transistors T2 in the two second sub-pixels 10b are both located in the corresponding first sub-pixels 10a. This is equivalent to converging the four transistors in the first pixel group PL1 and the second pixel group PL2 between the first pixel electrode PE1 of the first pixel group PL1 and the first pixel electrode PE1 of the second pixel group PL2, so that there is a large non-transparent area between the first pixel electrode PE1 of the first pixel group PL1 and the first pixel electrode PE1 of the second pixel group PL2. Sufficient non-transparent area is reserved for setting up the support pillar 130. The support pillar 130 can simultaneously overlap with the four transistors and / or the four first vias HL1, avoiding the support pillar 130 occupying the area of ​​the transparent area of ​​the sub-pixel 10 and improving the aperture ratio of the sub-pixel 10.

[0062] It should be noted that, Figure 3 and Figure 4 The embodiments in the examples all take a pixel group PL with two sub-pixels 10 as an example. When the area of ​​the support pillar 130 is further increased, a pixel group PL can also include a third sub-pixel 10, and the transistor in the third sub-pixel 10 can also be located in the first sub-pixel 10a.

[0063] In this embodiment, the area of ​​the first pixel electrode PE1 is less than or equal to the area of ​​the second pixel electrode PE2. Since the first sub-pixel 10a requires the simultaneous placement of the first transistor T1 and the second transistor T2 of the second sub-pixel 10b, while the second sub-pixel 10b does not require the placement of the second transistor T2, the area of ​​the pixel electrode PE that can be placed in the first sub-pixel 10a is reduced, while the area of ​​the pixel electrode PE that can be placed in the second sub-pixel 10b is increased. This results in the area of ​​the first pixel electrode PE1 being smaller than the area of ​​the second pixel electrode PE2. For example... Figure 3 The structure.

[0064] Please see Figure 3 In a repeating unit RU, the first pixel electrode PE1 includes a first sub-part PE1a and a second sub-part PE1b disposed adjacent to each other. The first sub-part PE1a is disposed away from the second pixel electrode PE2, and the second sub-part PE1b is disposed close to the second pixel electrode PE2. The length of the first sub-part PE1a in the second direction Y is greater than or equal to the length of the second sub-part PE1b in the second direction Y.

[0065] exist Figure 3In the structure, since the first pixel electrode PE1 and the first transistor T1 are directly connected, the distance between the first pixel electrode PE1 and the first transistor T1 in the second direction Y is small; and since the second transistor T2 is disposed within the first sub-pixel 10a, in order to avoid the second transistor T2 and the first pixel electrode PE1 being short-circuited, this application needs to set a sufficient safety distance between the second transistor T2 and the first pixel electrode PE1, so that the distance between the first transistor T1 and the first pixel electrode PE1 in the second direction Y is smaller than the distance between the second transistor T2 and the first pixel electrode PE1.

[0066] Optionally, the first sub-part PE1a and the first transistor T1 are arranged along the second direction Y, and the second sub-part PE1b and the second transistor T2 are arranged along the second direction Y.

[0067] In one embodiment, the distance between the first transistor T1 and the first pixel electrode PE1 in the second direction Y can also be equal to the distance between the second transistor T2 and the first pixel electrode PE1; that is, it is equivalent to reducing the length of the first sub-part PE1a in the second direction Y, so that the length of the first sub-part PE1a in the second direction Y is equal to the length of the second sub-part PE1b in the second direction Y.

[0068] This application differentiates the areas of the first sub-part PE1a and the second sub-part PE1b by making the length of the first sub-part PE1a in the second direction Y greater than or equal to the length of the second sub-part PE1b in the second direction Y. This maximizes the area of ​​the first pixel electrode PE1 and minimizes the area difference between the first pixel electrode PE1 and the second pixel electrode PE2 while avoiding short circuit between the second transistor T2 and the first pixel electrode PE1.

[0069] Please see Figure 5 The width of the first pixel electrode PE1 in the first pixel group PL1 can be greater than the width of the second pixel electrode PE2 in the first pixel group PL1, and the width of the second pixel electrode PE2 in the second pixel group PL2 can be greater than the width of the first pixel electrode PE1 in the second pixel group PL2.

[0070] Because the areas of the first pixel electrode PE1 and the second pixel electrode PE2 are different, the light-emitting areas of different sub-pixels 10 may differ, leading to a display unevenness problem. This application addresses this issue by increasing the width of some sub-pixels 10 and decreasing the width of others, thereby balancing the areas of the first pixel electrode PE1 and the second pixel electrode PE2. Figure 5The width of the first pixel electrode PE1 in the first pixel group PL1 is increased, and the width of the second pixel electrode PE2 in the first pixel group PL1 is decreased, so that the area of ​​the first pixel electrode PE1 and the area of ​​the second pixel electrode PE2 in the first pixel group PL1 are close to or equal.

[0071] In this embodiment, since the light emission color in the entire column of sub-pixels 10 is the same, although the areas of two adjacent columns of sub-pixels 10 are similar, when the width of the entire column of sub-pixels 10 increases, it may cause a technical problem of color shift in the two adjacent columns of sub-pixels 10 under different viewing angles.

[0072] Therefore, this application increases the width of the first pixel electrode PE1 in the first pixel group PL1 and decreases the width of the second pixel electrode PE2 in the first pixel group PL1, while also increasing the width of the second pixel electrode PE2 in the second pixel group PL2 and decreasing the width of the first pixel electrode PE1 in the second pixel group PL2. This is equivalent to having sub-pixels 10 with both increased and decreased widths in a column of sub-pixels 10, making the average width of a column of sub-pixels 10 the same, thus solving the technical problem of color shift in two adjacent columns of sub-pixels 10 under different viewing angles.

[0073] In this embodiment, the width of the first pixel electrode PE1 in the first pixel group PL1 is equal to the width of the second pixel electrode PE2 in the second pixel group PL2, and the width of the first pixel electrode PE1 in the second pixel group PL2 is equal to the width of the second pixel electrode PE2 in the first pixel group PL1.

[0074] Please see Figure 3 The distance between the first pixel electrode PE1 and the common electrode line 117a is less than or equal to the distance between the second pixel electrode PE2 and the common electrode line 117a.

[0075] In this embodiment, since the areas of the first pixel electrode PE1 and the second pixel electrode PE2 are different, this application can increase the area of ​​the first pixel electrode PE1 by reducing the distance between the first pixel electrode PE1 and the common electrode line 117a, or / and increase the distance between the second pixel electrode PE2 and the common electrode line 117a to reduce the area of ​​the second pixel electrode PE2, thereby reducing the area difference between the first pixel electrode PE1 and the second pixel electrode PE2.

[0076] Please see Figure 6 The light-shielding unit BM can be in the form of a long strip structure, and a light-shielding unit BM can be disposed between two pixel groups PL arranged along the second direction Y; the light-shielding unit BM extends along the first direction X, and the light-shielding unit BM covers the first transistor T1 and the second transistor T2 in the pixel group PL.

[0077] In this embodiment, the light-shielding unit BM includes a first light-shielding part BM1 and a second light-shielding part BM2 arranged adjacent to each other. The first light-shielding part BM1 is located between the first pixel electrode PE1 of the first pixel group PL1 and the first pixel electrode PE1 of the second pixel group PL2, and the second light-shielding part BM2 is located between the second pixel electrode PE2 of the first pixel group PL1 and the second pixel electrode PE2 of the second pixel group PL2.

[0078] This application makes the width of the first light-shielding part BM1 in the second direction Y greater than the width of the second light-shielding part BM2 in the second direction Y.

[0079] In this embodiment, since the four transistors in the first pixel group PL1 and the second pixel group PL2 converge between the first pixel electrode PE1 of the first pixel group PL1 and the first pixel electrode PE1 of the second pixel group PL2, there is a large non-transparent area between the first pixel electrode PE1 of the first pixel group PL1 and the first pixel electrode PE1 of the second pixel group PL2. Therefore, this application needs to set a light-shielding structure with a larger width to block this area. However, no transistors are set between the second pixel electrode PE2 of the first pixel group PL1 and the second pixel electrode PE2 of the second pixel group PL2. Therefore, a light-shielding structure with a smaller width is needed to block this area.

[0080] In this embodiment, in the top view, the first via HL1 in the first pixel group PL1 and the second pixel group PL2 are both located inside the second light-shielding part BM2, and the second light-shielding part BM2 covers the support column 130. In other words, this application arranges four transistors in the first pixel group PL1 and the second pixel group PL2 to converge between the first pixel electrode PE1 of the first pixel group PL1 and the first pixel electrode PE1 of the second pixel group PL2, so as to reserve a sufficient non-transparent area for setting up the support post 130 and the first via HL1. This area is blocked by the second light-shielding part BM2, thus avoiding the technical problem of the support post 130 and the first via HL1 occupying the area of ​​the light-transmitting area of ​​the sub-pixel 10 and improving the aperture ratio of the sub-pixel 10.

[0081] This application also proposes a display device, which includes a terminal body and the aforementioned display panel, wherein the terminal body and the display panel are integrated into one unit. The terminal body may include components such as a circuit board bonded to the display panel, and a cover plate disposed on the display panel. Mobile terminals may include electronic devices such as vehicle-mounted screens, mobile phones, televisions, and laptops.

[0082] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0083] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0084] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0085] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized in that, It includes multiple pixel groups, each of which includes: The first sub-pixel includes a first transistor and a first pixel electrode; The second sub-pixel is disposed adjacent to the first sub-pixel along a first direction. The second sub-pixel includes a second transistor and a second pixel electrode. Both the first transistor and the second transistor are located within the first sub-pixel. In the two pixel groups arranged along the second direction, the first transistor and the second transistor in one pixel group are arranged adjacent to the first transistor and the second transistor in the other pixel group.

2. The display panel as described in claim 1, characterized in that, The plurality of pixel groups include a plurality of repeating units, each repeating unit including a first pixel group and a second pixel group arranged along the second direction; In one of the repeating units, the first transistor and the second transistor in the first pixel group, and the first transistor and the second transistor in the second pixel group, are both located between the first pixel electrode of the first pixel group and the first pixel electrode of the second pixel group.

3. The display panel as described in claim 2, characterized in that, The area of ​​the first pixel electrode is less than or equal to the area of ​​the second pixel electrode.

4. The display panel as described in claim 2, characterized in that, The first pixel electrode includes a first sub-part and a second sub-part disposed adjacent to each other, the first sub-part being disposed away from the second pixel electrode, and the second sub-part being disposed close to the second pixel electrode; Wherein, the length of the first sub-part in the second direction is greater than or equal to the length of the second sub-part in the second direction.

5. The display panel as described in claim 4, characterized in that, The first sub-part and the first transistor are arranged along the second direction, and the second sub-part and the second transistor are arranged along the second direction.

6. The display panel as described in claim 2, characterized in that, The display panel also includes: First substrate; A common electrode line is disposed on one side of the first substrate, and the common electrode line is disposed between the two pixel groups arranged along the second direction, and the common electrode line is disposed on the side of the first pixel electrode away from the first transistor; Multiple common electrode blocks, one of the common electrode blocks corresponding to a pixel electrode in the pixel group; The common electrode line is located on the surface of the common electrode block away from the first substrate.

7. The display panel as described in claim 6, characterized in that, The distance between the first pixel electrode and the common electrode line is less than or equal to the distance between the second pixel electrode and the common electrode line.

8. The display panel as described in claim 2, characterized in that, The width of the first pixel electrode in the first pixel group is greater than the width of the second pixel electrode in the first pixel group, and the width of the second pixel electrode in the second pixel group is greater than the width of the first pixel electrode in the second pixel group.

9. The display panel as described in claim 8, characterized in that, The width of the first pixel electrode in the first pixel group is equal to the width of the second pixel electrode in the second pixel group, and the width of the first pixel electrode in the second pixel group is equal to the width of the second pixel electrode in the first pixel group.

10. The display panel as claimed in any one of claims 2 to 9, characterized in that, The display panel also includes: The color filter layer includes multiple light-shielding units and multiple color-resisting units. The light-shielding units are disposed between two pixel groups arranged along the second direction, and one color-resisting unit corresponds to a pixel electrode in the pixel group. The light-shielding unit extends along the first direction and covers the first transistor and the second transistor in the pixel group.

11. The display panel as claimed in claim 10, characterized in that, The light-shielding unit includes a first light-shielding part and a second light-shielding part arranged adjacent to each other. The first light-shielding part is located between the first pixel electrode of the first pixel group and the first pixel electrode of the second pixel group, and the second light-shielding part is located between the second pixel electrode of the first pixel group and the second pixel electrode of the second pixel group. Wherein, the width of the first light-shielding part in the second direction is greater than the width of the second light-shielding part in the second direction.

12. The display panel as claimed in claim 11, characterized in that, The display panel also includes: An array layer, comprising the first transistor and the second transistor; A pixel electrode layer is disposed on one side of the array layer, the pixel electrode layer including a first pixel electrode and a second pixel electrode disposed adjacently; and A planarization layer is disposed between the array layer and the pixel electrode layer. A first via is formed on the planarization layer. The first pixel electrode passes through one of the first vias and is electrically connected to the first transistor. The second pixel electrode passes through another of the first vias and is electrically connected to the second transistor. In the top view, the first via in both the first pixel group and the second pixel group is located within the second light-shielding part.

13. The display panel as claimed in claim 11, characterized in that, The display panel also includes multiple support pillars, and the second light-shielding part covers the support pillars.

14. The display panel as claimed in claim 10, characterized in that, The color of the color resist unit corresponding to the first pixel electrode of the first pixel group is the same as the color resist unit corresponding to the first pixel electrode of the second pixel group; The color of the color resist unit corresponding to the second pixel electrode of the first pixel group is the same as or different from the color resist unit corresponding to the second pixel electrode of the second pixel group.

15. A display device, characterized in that, The display device includes a display panel as described in any one of claims 1 to 14.

Images