A clock time synchronization correction method and system based on time sequence alignment

Abstract

The application discloses a kind of clock time synchronization correction method and system based on timing alignment, specifically relates to electronic timing technical field, for solving the problem that existing slave clock cannot distinguish whether zero-crossing point displacement is caused by power grid transient distortion or time service master clock clock drift when receiving power line time service, and causes time running disorder caused by misjudgment of power grid disease as synchronous instruction change;Symmetrical center drift is extracted by constructing zero-crossing point triplet from the zero-crossing point time sequence of ac power line voltage waveform to form displacement sequence;The first-order difference of displacement sequence is calculated, the pair rate and direction purity of transient impact point are counted, and the power grid transient distortion and the time service master clock clock drift are distinguished;For power grid transient distortion, freeze correction compensation loop, for time service master clock clock drift, update correction compensation amount with trend component, and then adjust the oscillation frequency control word of local clock, realize the timing alignment correction of tracking compensation only under the premise of reference signal being reliable.

Description

Technical Field

[0001] This invention relates to the field of electronic timing technology, and more specifically, to a clock time synchronization correction method and system based on timing alignment. Background Technology

[0002] In existing technologies, localized electronic clock systems often rely on power supply networks for time synchronization. A typical approach involves the master clock coupling a timing indicator signal to the AC power line, while the slave clock extracts an alignment reference by detecting the zero-crossing points of the power frequency voltage and uses this reference to correct its local clock. This power line-based timekeeping method eliminates the need for additional signal cabling and is widely used in buildings, factories, and other similar locations. In such systems, slave clocks typically assume that the zero-crossing intervals of the mains voltage are uniform and their positions are stable, using this as the basis for judging timing deviations. The timing indicator pulses emitted by the master clock are associated with the zero-crossing points, and the slave clock calculates the time difference and performs second tracking or synchronization by comparing the phase relationship between the local clock edge and the captured zero-crossing point.

[0003] However, when a high-power single-phase rectifier load is connected to the power supply network, the AC sinusoidal waveform will undergo asymmetrical distortion, resulting in irregular relative displacement at the zero-crossing points of the positive and negative half-cycles. The existing correction circuits and algorithms inside the slave clock simply track the phase changes at the zero-crossing points and cannot distinguish whether this displacement originates from the physical defects of the power grid waveform itself or from the timing adjustment actively applied by the master clock due to the drift of the reference source. Once the transient distortion of the power grid is misjudged as a change in the master clock's synchronization command, the slave clock will make a large-scale erroneous modification to the already correct time. After the power grid returns to normal, it will compensate in reverse, thus causing timekeeping disorder. This defect is directly due to the fact that the zero-crossing alignment mechanism itself lacks the ability to distinguish the reliability of the reference signal, making the correction action the source of disturbance to the timekeeping accuracy. Summary of the Invention

[0004] In order to overcome the above-mentioned defects of the prior art, the present invention provides a clock time synchronization correction method and system based on time alignment to solve the problems mentioned in the background art.

[0005] To achieve the above objectives, the present invention provides the following technical solution: A clock time synchronization and correction method based on timing alignment includes the following steps: S1: Capture the voltage waveform of the AC power line, obtain the zero-crossing time, and map it to a time-stamped sequence; S2: Construct zero-crossing triplets from the time-scaled sequence, calculate the symmetry center time-scale of the zero-crossing triplets, and use the offset of the symmetry center time-scale from the symmetry center time-scale of the previous zero-crossing triplet as the symmetry center drift, thus forming a displacement sequence. S3: Calculate the first-order difference of the displacement sequence, calculate the pairing rate of positive and negative impacts at transient impact points in the first-order difference, and calculate the directional purity of the continuous length of adjacent signs with the same value in the first-order difference relative to the total length of the analysis window. S4: If the pairing rate exceeds the pairing rate threshold and the directional purity is lower than the purity threshold, it is determined to be a transient distortion of the power grid; otherwise, it is determined to be a time synchronization master clock drift. S5: When a transient distortion of the power grid is detected, the correction and compensation loop of the local clock is frozen; when a time master clock drift is detected, the correction and compensation amount of the local clock is updated with the trend component of the displacement sequence. S6: Adjust the local clock oscillation frequency control word with the updated or frozen correction compensation amount.

[0006] Furthermore, the voltage waveform of the AC power line is captured, the zero-crossing time is obtained and mapped to a time-stamped sequence, including: The voltage waveform of the AC power supply line is sampled at equal intervals to obtain a sequence of sampled values; Identify pairs of adjacent sample points with different signs in a sampled value sequence; Interpolate the sampling point pairs with different signs to find the zero-crossing time; Using the zero-crossing point as the time marker, the time markers are arranged in chronological order to form a time marker sequence.

[0007] Furthermore, zero-crossing triples are constructed from the time-scaled sequence, and the symmetry center time-scale of the zero-crossing triples is calculated. The offset between the symmetry center time-scale and the symmetry center time-scale of the previous zero-crossing triple is used as the symmetry center drift, forming a displacement sequence, including: Select three consecutive zero-crossing time markers from the time marker sequence. The first and third zero-crossing time markers correspond to the zero-crossing point of the positive half-cycle, and the second zero-crossing time marker corresponds to the zero-crossing point of the negative half-cycle, forming a zero-crossing triplet. For the zero-crossing triplet formed in this case, calculate the average of the first and second zero-crossing time scales, and use it as the symmetry center time scale; Calculate the difference between the current symmetry center timescale and the symmetry center timescale of the previous zero-crossing triplet, and use it as the symmetry center drift. The multiple consecutively obtained center of symmetry drift values ​​are arranged in the order of acquisition to form a displacement sequence.

[0008] Furthermore, based on the construction method of the zero-crossing triplet, before forming a zero-crossing triplet, the order of the three consecutive zero-crossing time markers is verified: if the voltage waveform slope of the first zero-crossing time marker is positive, the voltage waveform slope of the second zero-crossing time marker is negative, and the voltage waveform slope of the third zero-crossing time marker is positive, then the formation order is confirmed to be valid; if the formation order is invalid, then the three consecutive zero-crossing time markers selected this time are discarded, and the next zero-crossing time marker is selected sequentially from the time marker sequence to re-form the zero-crossing triplet.

[0009] Furthermore, the first-order difference of the displacement sequence is calculated, the pairing rate of positive and negative impacts at transient impact points in the first-order difference is statistically analyzed, and the directional purity of the continuous length of adjacent signs with the same value in the first-order difference relative to the total length of the analysis window is calculated, including: The difference between adjacent displacement values ​​is calculated for the displacement sequence to obtain a first-order difference sequence; The difference values ​​in the first-order difference sequence whose absolute values ​​exceed the impact threshold are marked as transient impact points, with positive values ​​marked as positive impacts and negative values ​​marked as negative impacts. The transient impact points are sorted by their occurrence time. When two adjacent transient impact points are positive and negative impacts respectively, they are recorded as a pair event. The number of pair events is counted, and the pairing rate is the number of pair events divided by the total number of transient impact points. Within the analysis window, the lengths of consecutive segments with the same sign in the first-order difference sequence are counted. The sum of all the lengths of consecutive segments is then divided by the total number of difference points within the analysis window to obtain the directional purity.

[0010] Furthermore, based on the marking method of the transient impact point, the impact threshold is determined in the following way: Within the initial segment of the displacement sequence, a calm displacement sequence is extracted that does not contain power grid transient distortion or timing master clock drift. Calculate the standard deviation of the first difference of the static displacement sequence; The impact threshold is set as a preset multiple of the standard deviation.

[0011] Furthermore, the pairing rate threshold and purity threshold are determined as follows: under the condition that there is no single-phase rectifier load in the power grid, the displacement sequence is measured multiple times and the pairing rate and directional purity are calculated. The minimum value of the pairing rate among the multiple measurements is taken as the pairing rate threshold, and the maximum value of the directional purity among the multiple measurements is taken as the purity threshold.

[0012] Furthermore, when a transient distortion in the power grid is detected, the correction and compensation loop of the local clock is frozen; when a drift in the master clock is detected, the correction and compensation amount of the local clock is updated with the trend component of the displacement sequence, including: When a transient distortion of the power grid is detected, the integral operation of the correction compensation loop is prohibited, and the correction compensation amount is kept constant. When the timing master clock is determined to be drifting, the displacement sequence is passed through a low-pass filter to extract the trend component; Multiply the trend component by a preset scaling factor to obtain the correction increment; Add the correction increment to the current correction compensation amount to obtain the updated correction compensation amount.

[0013] Furthermore, the oscillation frequency control word of the local clock is adjusted by the updated or frozen correction compensation amount, including: Map the correction compensation amount to a frequency correction value; Update the oscillation frequency control word according to the frequency correction value; Apply the updated oscillation frequency control word to the local clock.

[0014] On the other hand, the present invention provides a clock time synchronization and correction system based on time alignment, comprising the following modules: The zero-crossing capture module is used to capture the voltage waveform of the AC power line, obtain the zero-crossing time, and map it into a time-stamped sequence. The drift generation module is used to construct zero-crossing triplets from the time-scaled sequence, calculate the symmetry center time-scale of the zero-crossing triplet, and use the offset of the symmetry center time-scale from the symmetry center time-scale of the previous zero-crossing triplet as the symmetry center drift to form a displacement sequence. The feature quantity statistics module is used to calculate the first-order difference of the displacement sequence, calculate the pairing rate of positive and negative impacts at transient impact points in the first-order difference, and calculate the directional purity of the continuous length of adjacent signs with the same value in the first-order difference relative to the total length of the analysis window. The disturbance type discrimination module is used to determine that if the pairing rate exceeds the pairing rate threshold and the direction purity is lower than the purity threshold, it is a power grid transient distortion; otherwise, it is a timing master clock drift. The correction and compensation management module is used to freeze the correction and compensation loop of the local clock when it is determined to be a transient distortion of the power grid; and to update the correction and compensation amount of the local clock with the trend component of the displacement sequence when it is determined to be a drift of the master clock. The frequency word adjustment module is used to adjust the oscillation frequency control word of the local clock with the updated or frozen correction compensation amount.

[0015] Compared with the prior art, the present invention has the following beneficial effects: 1. By constructing zero-crossing triplets and extracting the symmetry center drift, the time symmetry breaking of the power grid zero-crossing point is transformed into a quantifiable displacement sequence. Based on this, the first-order difference is calculated on the displacement sequence. Using the pairing rate of transient impact points and the directional purity of the difference sign as two-dimensional statistical features, the distinction between power grid transient distortion and timing master clock drift is realized. The pairing rate captures the essence that the positive and negative impacts caused by distortion are closely followed in time. The directional purity describes the characteristic of the drift signal continuously accumulating in a single direction. The two features reflect the physical differences of the disturbance type from different dimensions, so that the determination of the disturbance source no longer depends on the single zero-crossing point position change, but is based on the structural characteristics of the disturbance for comprehensive inference.

[0016] 2. When a transient distortion of the power grid is detected, the correction and compensation loop is frozen to prevent the slave clock from mistaking the false zero-crossing offset caused by the power grid malfunction as a time synchronization error and performing incorrect correction. This blocks the transmission path of the timekeeping disorder described in the background technology from the source. When a drift of the master clock is detected, the trend component is extracted from the displacement sequence and converted into a correction increment. The correction compensation amount is updated in an accumulative manner, thereby adjusting the oscillation frequency control word of the local clock. This makes the tracking of the master clock drift smooth and continuous, without frequency abrupt changes due to fluctuations in a single determination. The entire correction process is adapted to the physical characteristics of power line timekeeping. Tracking compensation is only performed when the reference signal is confirmed to be reliable, which solves the defect of the zero-crossing alignment mechanism lacking the ability to identify the reliability of the reference signal. Attached Figure Description

[0017] Figure 1 This is a flowchart of a clock time synchronization correction method based on timing alignment according to the present invention; Figure 2 This is a schematic diagram of the structure of a clock time synchronization correction system based on timing alignment according to the present invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0019] Example 1: Figure 1 This invention presents a clock time synchronization correction method based on timing alignment, which includes the following steps: S1: Capture the voltage waveform of the AC power line, obtain the zero-crossing time, and map it to a time-stamped sequence; S2: Construct zero-crossing triplets from the time-scaled sequence, calculate the symmetry center time-scale of the zero-crossing triplets, and use the offset of the symmetry center time-scale from the symmetry center time-scale of the previous zero-crossing triplet as the symmetry center drift, thus forming a displacement sequence. S3: Calculate the first-order difference of the displacement sequence, calculate the pairing rate of positive and negative impacts at transient impact points in the first-order difference, and calculate the directional purity of the continuous length of adjacent signs with the same value in the first-order difference relative to the total length of the analysis window. S4: If the pairing rate exceeds the pairing rate threshold and the directional purity is lower than the purity threshold, it is determined to be a transient distortion of the power grid; otherwise, it is determined to be a time synchronization master clock drift. S5: When a transient distortion of the power grid is detected, the correction and compensation loop of the local clock is frozen; when a time master clock drift is detected, the correction and compensation amount of the local clock is updated with the trend component of the displacement sequence. S6: Adjust the local clock oscillation frequency control word with the updated or frozen correction compensation amount.

[0020] S1: Capture the voltage waveform of the AC power line, obtain the zero-crossing time, and map it to a time-stamped sequence, as follows: The voltage waveform of the AC power line is sampled at equal intervals to obtain a sequence of sampled values. An analog-to-digital converter (ADC) is installed inside the slave clock, continuously acquiring the instantaneous voltage values ​​of the AC power line at a fixed sampling frequency. The sampling frequency is selected to satisfy the Nyquist condition, meaning the sampling frequency is greater than twice the fundamental frequency of the AC power line. For example, when the fundamental frequency of the AC power line is 50 Hz, the sampling frequency can be selected as 2000 Hz. Each acquired instantaneous voltage value corresponds to a sampling point, and the sampling point carries attributes including the sampling time and the voltage amplitude at that time. Adjacent sampling points have the same equal time interval in the time domain. As continuous acquisition proceeds, the voltage amplitudes of each sampling point are sequentially stored into a circular buffer of a preset number of sampling points in chronological order. When the circular buffer is full, the earliest stored sampling point is overwritten by the newest sampling point to ensure that the circular buffer always retains the voltage waveform data within the most recent time period. The sequence of voltage amplitudes arranged in chronological order in the circular buffer is the sampled value sequence. Each voltage amplitude in the sampled value sequence carries its own sign information, that is, a positive value indicates that the voltage waveform is in the positive half cycle, and a negative value indicates that the voltage waveform is in the negative half cycle.

[0021] Identify sampling point pairs with different signs in a sampled value sequence. Read two adjacent voltage amplitudes from the sampled value sequence and compare their respective signs. If the sign of the preceding voltage amplitude is opposite to that of the following voltage amplitude (i.e., the preceding voltage amplitude is positive and the following voltage amplitude is negative, or vice versa), then the pair of adjacent sampling points is determined to be a pair of sampling point pairs with different signs. Different signs indicate that the voltage waveform must cross zero within the time interval between adjacent sampling points, i.e., there exists a zero-crossing point. When the length of the sampled value sequence is sufficient to cover multiple power frequency cycles, all pairs of sampling point pairs with different signs can be identified sequentially by sliding and comparing the signs of adjacent sampling points. After identifying each pair of sampling point pairs with different signs, record the sampling time and voltage amplitude corresponding to each adjacent sampling point. The sampling time is the cumulative time value calculated from the sampling start time, and the voltage amplitude is the instantaneous voltage value acquired synchronously with the sampling time.

[0022] Interpolate the zero-crossing times for sampling point pairs with different signs. For each identified pair of sampling point pairs with different signs, take the sampling time and voltage amplitude of the previous sampling point as the first interpolation point, and the sampling time and voltage amplitude of the next sampling point as the second interpolation point. Take the absolute value of the voltage amplitude of the first interpolation point and the absolute value of the voltage amplitude of the second interpolation point. Using the sampling times of the first and second interpolation points as the horizontal axis boundaries, and the absolute value of the voltage amplitude of the first interpolation point as the starting value of the vertical axis, and the absolute value of the voltage amplitude of the second interpolation point as the ending value of the vertical axis, construct a straight line segment connecting the first and second interpolation points. The time corresponding to the intersection of the straight line segment and the time axis is the zero-crossing time. The zero-crossing time is calculated as follows: multiply the time difference between the sampling time of the first interpolation point and the sampling time of the second interpolation point by a first ratio, and then add the resulting product to the sampling time of the first interpolation point. The first ratio is the absolute value of the voltage amplitude at the first interpolation point divided by the sum of the absolute values ​​of the voltage amplitudes at the first and second interpolation points. The zero-crossing time obtained in this way is an approximate estimate of the time position at which the voltage waveform crosses zero between adjacent sampling points. The accuracy of the zero-crossing time depends on the sampling frequency and the magnitude of the voltage amplitude quantization error. A zero-crossing time is calculated for each pair of sampling points with different signs.

[0023] Zero-crossing moments are used as time markers, arranged chronologically to form a time marker sequence. Each zero-crossing moment is directly recorded as a time marker. As the sampled value sequence is continuously processed, multiple time markers are obtained sequentially, each representing the position of a zero-crossing moment on the time axis. The obtained time markers are stored sequentially in a time marker storage queue according to their corresponding chronological order. The time marker storage queue uses a first-in, first-out (FIFO) data structure; newly obtained time markers are added from the rear of the queue, and time markers are retrieved from the front when needed. All time markers arranged chronologically in the time marker storage queue constitute the time marker sequence. The time interval between adjacent time markers in the time marker sequence corresponds to half a fundamental cycle of the AC power line. Under stable and distortion-free grid conditions, the time interval between adjacent time markers is approximately equal. Under transient distortion conditions in the grid, the time interval between some adjacent time markers will deviate from the stable value. The time marker sequence serves as the basic time data for timing alignment operations of the slave clock. Subsequent steps extract zero-crossing triples from the time marker sequence and calculate the symmetry center drift, thus forming a displacement sequence. The acquisition of the time stamp sequence continues after the slave clock is powered on and initialized. As long as the slave clock is in normal working condition and the AC power line is supplying power normally, the analog-to-digital converter will continuously acquire the voltage waveform, and the acquisition of the zero-crossing point and the mapping of the time stamp sequence will also be carried out continuously to ensure that the slave clock always holds the latest power grid zero-crossing point timing information for timing alignment correction.

[0024] S2: Construct zero-crossing triples from the time-scaled sequence, calculate the symmetry center timescale of the zero-crossing triples, and use the offset between the symmetry center timescale and the symmetry center timescale of the previous zero-crossing triple as the symmetry center drift, forming a displacement sequence, as follows: Three consecutive zero-crossing time markers are selected sequentially from the time marker sequence. The first and third zero-crossing time markers correspond to the zero-crossing points of the positive half-cycle, and the second zero-crossing time marker corresponds to the zero-crossing point of the negative half-cycle, forming a zero-crossing triplet. The slave clock reads the zero-crossing time markers from the time marker sequence generated in step S1. The zero-crossing time markers in the time marker sequence are arranged in chronological order, and each zero-crossing time marker represents the moment when the AC power line voltage waveform crosses zero. The slave clock maintains a read pointer, which points to the next zero-crossing time marker to be read in the time marker sequence. Each time a zero-crossing triplet is formed, the slave clock starts from the position pointed to by the read pointer and continuously retrieves three zero-crossing time markers, which are then recorded as the first zero-crossing time marker, the second zero-crossing time marker, and the third zero-crossing time marker in the order of retrieval. To confirm that the three selected zero-crossing time markers meet the requirements for forming a zero-crossing triplet, the slave clock verifies the order of the three consecutive zero-crossing time markers before forming the triplet. The verification method is as follows: obtain the voltage waveform slope corresponding to the first zero-crossing time marker, the voltage waveform slope corresponding to the second zero-crossing time marker, and the voltage waveform slope corresponding to the third zero-crossing time marker. The voltage waveform slope is obtained by: for each zero-crossing time marker, checking back the sampling point pairs with different signs associated with the zero-crossing time marker in step S1; taking the difference between the voltage amplitude of the previous sampling point and the voltage amplitude of the next sampling point in the pair of sampling points with different signs; if the difference is greater than zero, the voltage waveform slope corresponding to the zero-crossing time marker is positive; if the difference is less than zero, the voltage waveform slope corresponding to the zero-crossing time marker is negative. If the verification results satisfy the following conditions: the voltage waveform slope of the first zero-crossing time marker is positive, the voltage waveform slope of the second zero-crossing time marker is negative, and the voltage waveform slope of the third zero-crossing time marker is positive, then the formation sequence is confirmed to be valid. The first zero-crossing time marker is identified as the corresponding positive half-cycle zero-crossing, the second zero-crossing time marker is identified as the corresponding negative half-cycle zero-crossing, and the third zero-crossing time marker is identified as the corresponding positive half-cycle zero-crossing. The first, second, and third zero-crossing time markers together form a valid zero-crossing triplet. If the verification results do not meet the above conditions, i.e., the formation sequence is invalid, then the selected first zero-crossing time marker is discarded, the read pointer is shifted one position forward, and three zero-crossing time markers are continuously retrieved from the time marker sequence again for the formation sequence verification, until the verification passes and a valid zero-crossing triplet is formed. The sequence check ensures that the three zero-crossing time scales within the zero-crossing triplet completely cover the zero-crossing points of the positive half-cycle, the negative half-cycle, and the next positive half-cycle in a complete power frequency cycle, providing the correct time base unit for the calculation of the symmetry center time scale.

[0025] For the zero-crossing triplet formed this time, the average of the first and second zero-crossing time scales is calculated and used as the center of symmetry time scale. After forming a valid zero-crossing triplet, the slave clock extracts the first and second zero-crossing time scales from the triplet. The first zero-crossing time scale is the time value representing the zero-crossing point of the previous positive half-cycle in the triplet, and the second zero-crossing time scale is the time value representing the zero-crossing point of the negative half-cycle in the triplet. The time values ​​of the first and second zero-crossing time scales are added together, and the result is divided by 2. The quotient is the center of symmetry time scale of this zero-crossing triplet. The center of symmetry time scale represents the geometric center position on the time axis between the zero-crossing point of the previous positive half-cycle and the zero-crossing point of the negative half-cycle located in the middle. When the AC power line voltage waveform is strictly symmetrical in both the positive and negative half-cycles, the symmetry center time marker coincides with the zero-crossing time marker of the negative half-cycle, differing from the zero-crossing time marker of the positive half-cycle by half a power frequency cycle. When the AC power line voltage waveform undergoes asymmetrical distortion due to a single-phase rectifier load, the widths of the positive and negative half-cycles are no longer equal, and the zero-crossing point of the negative half-cycle deviates from the exact center between the two zero-crossing points of the positive half-cycles in time. Consequently, the symmetry center time marker deviates from the zero-crossing time marker of the negative half-cycle, and the degree of deviation reflects the strength of the waveform asymmetry. The slave clock stores the calculated symmetry center time marker in a symmetry center temporary register. The symmetry center temporary register only retains the most recently calculated symmetry center time marker value and is overwritten and updated after each symmetry center time marker calculation, providing a reference benchmark for the next calculation of the symmetry center drift.

[0026] The difference between the current symmetry center time marker and the symmetry center time marker of the previous zero-crossing triplet is calculated as the symmetry center drift. After each calculation of the symmetry center time marker for the current zero-crossing triplet, the slave clock reads the previously stored symmetry center time marker value from the symmetry center temporary register. The previously stored symmetry center time marker value is the symmetry center time marker corresponding to the immediately preceding zero-crossing triplet. Subtracting the previous symmetry center time marker from the current symmetry center time marker yields the current symmetry center drift. The sign of the symmetry center drift indicates the drift direction of the symmetry center on the time axis. If the current symmetry center time marker is later than the previous symmetry center time marker, the symmetry center drift is positive; otherwise, it is negative. The absolute value of the symmetry center drift indicates the offset amplitude of the symmetry center between two consecutive zero-crossing triplets. For operating conditions where the timing indicator signal is generated by the same master clock and the AC power line voltage waveform is undistorted, the symmetry center time markers of consecutive zero-crossing triplets remain stable, and the symmetry center drift approaches zero. When transient distortions occur in the AC power supply line, due to asymmetrical changes in the positive and negative half-cycle widths, the symmetry center time marker experiences instantaneous jumps between consecutive zero-crossing triplets. The symmetry center drift manifests as a pulse-type offset with a sudden increase in absolute value. When the reference clock of the master clock drifts, all zero-crossing time markers shift as a whole, and the symmetry center time marker also moves slowly in the same direction accordingly. The symmetry center drift manifests as a slowly varying offset with a continuously consistent sign and a small amplitude. After calculating the current symmetry center drift, the slave clock writes the current symmetry center time marker value into the symmetry center temporary register to overwrite the previously stored symmetry center time marker value for use in the next round of zero-crossing triplet processing.

[0027] Multiple consecutively obtained symmetry center drift values ​​are arranged in the order of acquisition to form a displacement sequence. Each time a symmetry center drift value is calculated, the slave clock appends it to a displacement sequence buffer. The displacement sequence buffer is a data set organized in chronological order, with newly generated symmetry center drift values ​​appended to the end of the displacement sequence. The length of the displacement sequence buffer is set to a fixed value, for example, storing the 512 most recently obtained symmetry center drift values. When the number of symmetry center drift values ​​in the displacement sequence buffer exceeds the preset length, the earliest stored symmetry center drift value is removed to maintain the fixed length. All symmetry center drift values ​​in the displacement sequence buffer are arranged in the order of their storage, forming the displacement sequence. The time interval between adjacent symmetry center drift values ​​in the displacement sequence is equal to half a fundamental period of the AC power line. The displacement sequence serves as the basic input data for subsequent steps. Step S3 calculates the first-order difference of the displacement sequence and extracts the pairing rate and directional purity of transient impact points from the first-order difference for step S4 to determine the disturbance type. The continuous updating of the displacement sequence ensures that the slave clock tracks the changes in the AC power line status and the timing master clock status in real time. When the disturbance type determination logic needs the latest data, it directly obtains the time-aligned symmetry center drift data from the displacement sequence buffer.

[0028] S3: Calculate the first-order difference of the displacement sequence, statistically analyze the pairing rate of positive and negative impacts at transient impact points in the first-order difference, and calculate the directional purity of the continuous length of adjacent signs with the same value relative to the total length of the analysis window in the first-order difference, as follows:

[0029] The difference between adjacent displacement values ​​is calculated in the displacement sequence to obtain a first-order difference sequence. The clock reads the center-of-symmetry drift from the displacement sequence generated in step S2; the drift values ​​of each center-of-symmetry in the displacement sequence are arranged in the order they were acquired. For two adjacent center-of-symmetry drift values ​​in the displacement sequence, the value of the latter drift value is subtracted from the value of the former drift value, and the difference is taken as a first-order difference value. This process is repeated sequentially, starting from the beginning of the displacement sequence, for each pair of adjacent center-of-symmetry drift values ​​until the end of the displacement sequence. The differences obtained from each calculation are arranged in the order of the operations, thus forming the first-order difference sequence. Each first-order difference value in the first-order difference sequence carries two pieces of information: the absolute value of the first-order difference value represents the magnitude of change between adjacent center-of-symmetry drift values, and the sign of the first-order difference value represents the direction of change between adjacent center-of-symmetry drift values; a positive value indicates that the latter drift value is greater than the former, and a negative value indicates that the latter drift value is less than the former. The length of the first-order difference sequence is one less than the length of the displacement sequence. The first-order difference sequence serves as the common data basis for transient impact point identification and directional purity calculation. The slave clock stores the first-order difference sequence in a first-order difference buffer for subsequent processing.

[0030] In the first-order difference sequence, difference values ​​whose absolute values ​​exceed the impact threshold are marked as transient impact points, with positive values ​​marked as positive impacts and negative values ​​as negative impacts. Before marking transient impact points, the slave clock determines the impact threshold. The impact threshold is determined as follows: within the initial segment of the displacement sequence, a calm displacement sequence without power grid transient distortion and without master clock drift is extracted. The standard deviation of the first-order difference of the calm displacement sequence is calculated, and the impact threshold is taken as a preset multiple of the standard deviation. Specifically, after the slave clock completes power-on initialization and begins continuously acquiring displacement sequences, the first 256 symmetry center drifts acquired in the displacement sequence are taken as candidate segments of the calm displacement sequence. The slave clock calculates the first-order difference of the candidate segments to obtain the calm first-order difference sequence. The slave clock calculates the standard deviation of the calm first-order difference sequence. The standard deviation is calculated as follows: first, the average of all first-order difference values ​​in the calm first-order difference sequence is calculated; then, the square of the difference between each first-order difference value and the average is calculated; all squares are summed and divided by the total number of first-order difference values ​​in the calm first-order difference sequence; finally, the square root is taken. The preset multiplier is set based on the ratio between the typical amplitude of power grid transient distortion and the background noise level. The preset multiplier avoids being too small, which could lead to misjudging normal fluctuations as transient impacts, and also avoids being too large, which could lead to missing true distortions. The slave clock sets the preset multiplier to, for example, 3 times, meaning the impact threshold is equal to 3 times the standard deviation. Once the calm displacement sequence is acquired, the impact threshold is determined and remains unchanged in subsequent processing until the slave clock is re-initialized by power-on or triggered for recalibration by an external command. After the impact threshold is determined, the slave clock iterates through each first-order difference value in the first-order difference sequence, comparing the absolute value of each first-order difference value with the impact threshold. If the absolute value of the first-order difference exceeds the impact threshold, the first-order difference is marked as a transient impact point. Simultaneously, the impact direction of the transient impact point is determined based on the sign of the first-order difference: if the first-order difference is positive, the transient impact point is marked as a positive impact; if the first-order difference is negative, the transient impact point is marked as a negative impact. If the absolute value of the first-order difference does not exceed the impact threshold, the first-order difference is not marked as a transient impact point and is considered a non-impact point. After traversal, the slave clock stores all marked transient impact points in a transient impact point list according to the order of their corresponding first-order difference values ​​in the first-order difference sequence.

[0031] Transient impact points are sorted by their occurrence time. When two adjacent transient impact points are positive and negative impact points respectively, they are recorded as a pair event. The number of pair events is counted, and the pairing rate is the number of pair events divided by the total number of transient impact points. The slave clock reads transient impact points from the list in storage order, which is consistent with the order of the first-order difference values ​​corresponding to the transient impact points in the first-order difference sequence, i.e., consistent with the occurrence time order of the transient impact points. The slave clock maintains a pair event counter, which is initialized to zero. Starting from the second transient impact point in the list, the slave clock pairs the currently read transient impact point with the previous transient impact point to form an adjacent transient impact point pair. The clock checks the impact direction of the preceding transient impact point in adjacent transient impact point pairs against the impact direction of the following transient impact point: if the preceding transient impact point is a negative impact and the following transient impact point is a positive impact, or the preceding transient impact point is a positive impact and the following transient impact point is a negative impact, i.e., the impact directions of adjacent transient impact point pairs are opposite, then a paired event is determined to have occurred, and the paired event counter is incremented by 1. If the impact directions of adjacent transient impact point pairs are the same, then it is not recorded as a paired event. The slave clock traverses all transient impact points in the transient impact point list in this manner, and after the traversal is completed, the final value of the paired event counter is read as the number of paired events. The slave clock calculates the pairing rate by dividing the number of paired events by the total number of transient impact points in the transient impact point list. When the total number of transient impact points is zero, the pairing rate is defined as zero. The pairing rate reflects the degree to which transient impact points appear in positive and negative pairs in time sequence. The symmetry center drift caused by transient distortion of the power grid exhibits a high pairing rate in the first-order difference domain, characterized by closely following positive and negative impacts. The symmetry center drift caused by the master clock drift exhibits sporadic or irregular impacts in the first-order difference domain, with a low pairing rate.

[0032] Within the analysis window, the lengths of consecutive segments with the same sign in the first-order difference sequence are counted. The sum of all consecutive segment lengths is divided by the total number of difference points within the analysis window to obtain the directional purity. The clock sub-clock defines an analysis window covering a continuous region in the first-order difference sequence. The length of the analysis window is set to a fixed value, for example, containing 512 first-order difference values. Starting from the beginning of the analysis window, the clock sub-clock iterates through the first-order difference values, identifying consecutive segments with the same sign. The identification method for consecutive segments is as follows: starting from the current first-order difference value, the sign of the current first-order difference value is compared with the sign of the next first-order difference value. If the signs are the same, the consecutive segment is extended to the next first-order difference value, and the comparison continues until a first-order difference value with a different sign is encountered or the end of the analysis window is reached. This segment of first-order difference values ​​with the same sign constitutes a consecutive segment. The number of first-order difference values ​​contained in each consecutive segment is recorded as the length of the consecutive segment. After identifying a continuous segment, the identification of the next continuous segment begins from the immediately following first-order difference value. This process is repeated until all first-order difference values ​​within the analysis window have been traversed. The slave clock sums the lengths of all identified continuous segments to obtain the total length of the continuous segments. The total length of the continuous segments is divided by the total number of first-order difference values ​​within the analysis window, which is the total number of difference points within the analysis window. The quotient is the directional purity. Directional purity characterizes the proportion of the first-order difference sequence where the sign remains unchanged. First-order difference sequences caused by transient distortions in the power grid alternate frequently between positive and negative signs, resulting in generally shorter continuous segment lengths and lower directional purity. First-order difference sequences caused by clock drift in the master clock tend to have a long-term bias in the same direction, resulting in longer continuous segments and higher directional purity. The analysis window advances along the first-order difference sequence in a sliding manner, advancing by, for example, 64 first-order difference values ​​each time. The directional purity is recalculated after each advance to maintain a timely response to changes in the power grid state.

[0033] S4: If the pairing rate exceeds the pairing rate threshold and the direction purity is lower than the purity threshold, it is determined to be a transient distortion of the power grid; otherwise, it is determined to be a time synchronization master clock drift, and the following measures are taken: The pairing rate threshold and purity threshold are predetermined through a calibration process, which is performed after the slave clock is installed and under conditions where the power grid is free of single-phase rectifier loads. During calibration, the slave clock continuously captures the voltage waveform of the AC power line. Step S1 acquires zero-crossing events and maps them to a time-scaled sequence. Step S2 constructs zero-crossing triplets from the time-scaled sequence and calculates the center-of-symmetry drift to form a displacement sequence. Step S3 calculates the first-order difference of the displacement sequence and extracts the pairing rate and directional purity. The calibration process is performed under conditions where the power grid is free of single-phase rectifier loads. This condition can be determined manually by confirming the load status or automatically by the slave clock when the power grid current waveform shows no obvious single-phase rectification characteristics. During calibration, the slave clock performs multiple measurements, each corresponding to a complete analysis window period. Each measurement outputs a pairing rate value and a directional purity value. The total number of measurements is preset, selected based on the short-term fluctuations of the power grid operating conditions; for example, the total number of measurements is set to 100 to cover natural fluctuations in the power grid at different times. After completing all measurements, the slave clock obtains a pairwise ratio numerical sequence and a directional purity numerical sequence. The slave clock selects the minimum value from the pairwise ratio numerical sequence and uses this minimum value as the pairwise ratio threshold. The slave clock also selects the maximum value from the directional purity numerical sequence and uses this maximum value as the purity threshold. The pairwise ratio threshold represents the lower bound of the pairwise ratio under the condition that no single-phase rectifier load is connected to the power grid, and the purity threshold represents the upper bound of the directional purity under the same condition. Once determined, the pairwise ratio threshold and purity threshold are stored in the slave clock's non-volatile storage medium and continuously invoked by the decision logic in step S4 during normal operation of the slave clock until the slave clock is recalibrated or restored to factory settings.

[0034] During normal operation of the slave clock, after step S3 completes the calculation of the pairing rate and directional purity of each analysis window, it compares the pairing rate of the current analysis window with the pairing rate threshold and the directional purity of the current analysis window with the purity threshold. If the pairing rate of the current analysis window exceeds the pairing rate threshold and the directional purity of the current analysis window is lower than the purity threshold, then the operating condition corresponding to the current analysis window is determined to be a power grid transient distortion. If the pairing rate of the current analysis window does not exceed the pairing rate threshold, or the directional purity of the current analysis window is not lower than the purity threshold, as long as at least one of the two conditions is not met, then the operating condition corresponding to the current analysis window is determined to be a timing master clock drift. The determination logic uses the pairing rate threshold and the purity threshold as boundary conditions to distinguish between power grid transient distortion and timing master clock drift. Power grid transient distortion is caused by voltage waveform asymmetry due to the connection or disconnection of single-phase rectifier loads. Its characteristics are that the symmetry center drift amount presents a transient impact of positive and negative pairs in the first-order differential domain and the first-order differential signs alternate frequently, thus the pairing rate is high and the directional purity is low. The timing master clock drift is caused by frequency offset or aging of the internal crystal oscillator. Its characteristics include a small amount of sporadic or no significant drift in the first-order difference domain, and the first-order difference symbols consistently biased in the same direction. Therefore, the pairing rate does not exhibit a high value, and the directional purity does not exhibit a low value. The decision logic possesses decision-making safety under power plant distortion conditions: the determination of transient distortion in the power grid is triggered only when both conditions are met simultaneously, avoiding misjudgments due to accidental fluctuations of a single indicator. The determination result serves as the basis for selecting the correction strategy in step S5. The slave clock transmits the current determination result along with the displacement sequence of the current analysis window to step S5.

[0035] S5: When a transient distortion in the power grid is detected, the local clock's correction and compensation loop is frozen; when a master clock drift is detected, the local clock's correction and compensation amount is updated with the trend component of the displacement sequence, as follows: When step S4 determines that the current analysis window corresponds to a power grid transient distortion, the integration operation of the correction compensation loop is prohibited, and the correction compensation amount remains unchanged. An internal correction compensation loop is maintained within the slave clock. During normal operation, this loop continuously receives the time deviation between the timing indicator signal from the master clock and the local clock feedback signal, and performs integration on the time deviation. The integration result forms the correction compensation amount, which is used to adjust the oscillation frequency control word of the local clock to eliminate the accumulated time deviation. The integration operation of the correction compensation loop is controlled by the integration enable signal. When the integration enable signal is valid, the integration operation proceeds normally; when the integration enable signal is invalid, the integration operation is prohibited. When the output of step S4 determines a power grid transient distortion, the slave clock sets the integration enable signal to invalid. After the integration enable signal is invalidated, the integrator of the correction compensation loop stops accumulating the time deviation, and the output value of the integrator remains unchanged at the stop time; that is, the correction compensation amount is frozen. Freezing the correction compensation amount means that the slave clock no longer dynamically adjusts the oscillation frequency of the local clock based on the currently detected zero-crossing phase deviation. The local clock continues to run according to the oscillation frequency control word before freezing. During power grid transient distortion, the zero-crossing time markers experience irregular shifts due to waveform asymmetry. If the zero-crossing phase deviation is continuously tracked and the correction compensation amount is updated at this time, false time deviations caused by power grid waveform distortion will be introduced into the local clock correction system, leading to timekeeping irregularities. Freezing the correction compensation loop prevents the slave clock from mistaking power grid abnormalities for time synchronization errors and making incorrect corrections. After the power grid transient distortion disappears and the operating condition is determined to be restored in step S4, the integration enable signal is reset to valid, and the correction compensation loop resumes normal integration operation.

[0036] When step S4 determines that the operating condition corresponding to the current analysis window is a master clock drift, the displacement sequence is passed through a low-pass filter to extract the trend component. The slave clock obtains the displacement sequence corresponding to the current analysis window from step S2. Each symmetry center drift in the displacement sequence carries the offset information of the master clock relative to the zero-crossing reference of the power grid. The low-pass filter is used to separate the slowly changing trend component from the displacement sequence, while suppressing high-frequency fluctuation components caused by short-term power grid fluctuations or measurement noise. The low-pass filter is implemented as a digital first-order infinite impulse response low-pass filter. The processing procedure of the digital first-order infinite impulse response low-pass filter is as follows: the symmetry center drift in the displacement sequence is used as the input value in sequence. For the current input value, the current output value is obtained by adding three parts: the first part is the current input value multiplied by the filter coefficient, the second part is the previous input value multiplied by the filter coefficient, and the third part is the previous output value multiplied by one minus twice the filter coefficient. The filter coefficient determines the cutoff frequency of the low-pass filter. A smaller filter coefficient results in a lower cutoff frequency and a smoother extracted trend component, but also a slower response to drift. The filter coefficient is set based on the typical drift rate of the master clock. The drift rate of the master clock is usually much lower than the rate of change of the AC power line's power frequency cycle. The filter coefficient is set, for example, to 1 / 64 or 1 / 128, ensuring that the cutoff frequency of the low-pass filter is much lower than the power frequency. The slave clock inputs the drift amounts of each symmetry center in the displacement sequence sequentially into the digital first-order infinite impulse response low-pass filter. The corresponding sequence output by the filter is the trend component. The trend component reflects the overall offset direction and rate of the master clock's reference clock over a period of time, eliminating pulse-like jumps and short-term random fluctuations caused by transient distortions in the power grid.

[0037] The correction increment is obtained by multiplying the trend component by a preset scaling factor. The trend component, in terms of time, represents the cumulative time drift of the master clock's reference clock between consecutive zero-crossing triplets. The correction increment is the input quantity used by the slave clock to adjust the local clock oscillation frequency. There is a dimensional and amplitude correspondence between the correction increment and the trend component. The scaling factor is a proportionality factor connecting the trend component and the correction increment. The scaling factor is set according to the adjustment sensitivity of the local clock oscillation frequency control word and the closed-loop gain of the correction compensation loop. The scaling factor is set as follows: before the slave clock leaves the factory or during the field debugging phase, a master clock drift test signal with a known amplitude is injected. The steady-state response amplitude of the correction compensation is measured. The steady-state response amplitude is divided by the amplitude of the injected drift signal to obtain the loop gain. The scaling factor is taken as the reciprocal of the loop gain or a value attenuated according to the loop stability requirements. The scaling factor should not be too large, as this will cause the correction compensation to over-respond to the trend component, resulting in overshoot and oscillation of the local clock output frequency. The scaling factor should not be too small, as this will result in slow tracking of the master clock's drift by the correction compensation, leaving the local clock with uncompensated residual biases for a long time. A typical value for the scaling factor is determined based on the parameters of the actual system and stored in the non-volatile storage medium of the slave clock. The slave clock uses the final value of the extracted trend component or the average value of the trend component sequence as the representative trend amplitude of the current analysis window. Multiplying this representative trend amplitude by the scaling factor yields the correction increment.

[0038] The correction increment is added to the current correction compensation amount to obtain the updated correction compensation amount. The slave clock maintains a correction compensation amount register, which stores the currently used correction compensation amount. This correction compensation amount is used in step S6 to adjust the oscillation frequency control word of the local clock. After the slave clock completes the calculation of the correction increment, it reads the current correction compensation amount from the correction compensation amount register, arithmetically adds the correction increment value to the current correction compensation amount value, and writes the sum to the correction compensation amount register, overwriting the original current correction compensation amount value, thus becoming the updated correction compensation amount. When the correction increment is positive, the updated correction compensation amount increases, indicating that the local clock needs to speed up its oscillation frequency to catch up with the reference clock of the master clock. When the correction increment is negative, the updated correction compensation amount decreases, indicating that the local clock needs to slow down its oscillation frequency to wait for the reference clock of the master clock. The correction compensation amount update process is performed once at the end of each analysis window period. The updated correction compensation amount is continuously used by step S6 in the next analysis window period until it is updated again at the end of the next analysis window period based on the new judgment result and the new correction increment. The correction compensation amount is updated using an incremental method rather than a direct assignment method, allowing the correction compensation amount to transition smoothly over multiple consecutive analysis window periods, avoiding sudden jumps in the local clock frequency caused by fluctuations in a single judgment. The slave clock simultaneously transmits the updated correction compensation amount to the oscillation frequency control word adjustment stage in step S6.

[0039] S6: Adjust the local clock oscillation frequency control word with the updated or frozen correction compensation amount, as follows: The correction compensation amount is mapped to a frequency correction value. The slave clock obtains the updated or frozen correction compensation amount from step S5. The correction compensation amount is in time dimension and represents the cumulative time deviation that the local clock needs to compensate for relative to the reference clock of the master clock. The slave clock maintains a local clock frequency source internally. The core of the local clock frequency source is a voltage-controlled oscillator (VCO). The output frequency of the VCO is determined by the voltage or digital control word applied to the control input terminal of the VCO. The frequency correction value is an input parameter that directly changes the output frequency of the VCO. There is a mapping relationship between the frequency correction value and the correction compensation amount. The mapping relationship is established based on the VCO's voltage control sensitivity or the step accuracy of the frequency control word. The voltage control sensitivity represents the output frequency change caused by a unit change in control voltage, and the unit of voltage control sensitivity is Hertz per volt. When the VCO uses a digital control interface, the step accuracy of the frequency control word represents the output frequency change corresponding to each change in the least significant bit of the control word. The mapping method is: multiply the time value of the correction compensation amount by the nominal oscillation frequency of the local clock to obtain the equivalent phase deviation conversion value of the correction compensation amount. The phase deviation value is then divided by the length of the target correction time window. The length of the target correction time window is the predetermined time interval for the slave clock to complete one full correction compensation. The length of the target correction time window is set according to the correction accuracy requirements and the drift rate of the master clock, for example, a target correction time window length of 60 seconds. The resulting quotient is the frequency offset that needs to be evenly distributed within the correction time window. Dividing the frequency offset by the voltage-controlled oscillator's voltage control sensitivity, or by the frequency offset by the step accuracy of the frequency control word, yields the frequency correction value. When the local clock uses digital direct frequency synthesis to generate the clock signal, the frequency correction value represents the phase increment adjustment of the phase accumulator in the direct frequency synthesizer. The slave clock stores the calculated frequency correction value in a frequency correction value register for use in subsequent steps.

[0040] The oscillation frequency control word is updated according to the frequency correction value. The slave clock maintains an oscillation frequency control word register, which stores the currently used oscillation frequency control word. This oscillation frequency control word directly drives the local clock's oscillation frequency generation circuit. The current oscillation frequency control word corresponds to the current running rate of the local clock. The slave clock reads the current oscillation frequency control word from the register, arithmetically adds it to the frequency correction value, and writes the result back to the register, overwriting the original value, thus creating the updated oscillation frequency control word. The bit width of the oscillation frequency control word determines the resolution of the frequency adjustment; a wider bit width results in finer granularity. When the frequency correction value is positive, the updated oscillation frequency control word increases, the local clock's oscillation frequency rises, and it runs faster to catch up with the master clock's reference clock. When the frequency correction value is negative, the updated oscillation frequency control word decreases, the local clock's oscillation frequency decreases, and it runs slower to wait for the master clock's reference clock. The update operation of the oscillation frequency control word is performed synchronously with the correction compensation update operation in step S5, and is performed once at the end of each analysis window period. The updated oscillation frequency control word remains constant throughout the entire analysis window period until the end of the next analysis window period, when it is updated again based on the new correction compensation amount and the new frequency correction value. The update of the oscillation frequency control word adopts an accumulation method rather than a direct assignment method to ensure that the oscillation frequency of the local clock does not undergo abrupt changes during continuous adjustment, and to avoid period jumps or phase breaks in the second pulse signal output by the local clock.

[0041] The updated oscillation frequency control word is applied to the local clock. The slave clock outputs the updated oscillation frequency control word from the oscillation frequency control word register to the oscillation frequency generation circuit of the local clock. After receiving the oscillation frequency control word, the oscillation frequency generation circuit generates a clock signal according to the frequency parameters specified in the oscillation frequency control word. The clock signal is divided by a frequency divider chain to generate a second pulse signal. The second pulse signal is the base clock edge for the slave clock to drive the timing pointer to step or update the digital display timing. After the oscillation frequency control word is changed, the oscillation frequency of the local clock will run at the new frequency value in the next oscillation cycle, and the period of the second pulse signal will be finely adjusted accordingly. After correction and compensation for several consecutive analysis window cycles, the time deviation between the rising edge of the second pulse signal of the local clock and the timing reference transmitted by the master clock through the zero-crossing point of the AC power line gradually decreases, and the display time of the slave clock tends to be consistent with the standard time of the master clock. When the correction compensation amount is frozen in step S5 due to the determination of transient distortion in the power grid, the frequency correction value is zero, the oscillation frequency control word remains unchanged, and the local clock continues to run at the oscillation frequency before freezing. The timekeeping accuracy is maintained only by the short-term stability of the local clock's own crystal oscillator. The reference clock for tracking the master clock is restored after the transient distortion in the power grid disappears and the correction compensation loop is unfrozen. After the oscillation frequency control word of the local clock is updated, the slave clock completes a complete timing alignment correction cycle. The slave clock returns to step S1 to continue capturing the voltage waveform of the AC power line and begins the next round of loop processing, including zero-crossing event acquisition, symmetry center drift calculation, disturbance type determination, correction compensation amount update, and oscillation frequency control word adjustment.

[0042] Example 2: Figure 2 A schematic diagram of a time synchronization and correction system for clocks based on time alignment is provided according to the present invention. The time synchronization and correction system for clocks based on time alignment includes the following modules: The zero-crossing capture module is used to capture the voltage waveform of the AC power line, obtain the zero-crossing time, and map it into a time-stamped sequence. The drift generation module is used to construct zero-crossing triplets from the time-scaled sequence, calculate the symmetry center time-scale of the zero-crossing triplet, and use the offset of the symmetry center time-scale from the symmetry center time-scale of the previous zero-crossing triplet as the symmetry center drift to form a displacement sequence. The feature quantity statistics module is used to calculate the first-order difference of the displacement sequence, calculate the pairing rate of positive and negative impacts at transient impact points in the first-order difference, and calculate the directional purity of the continuous length of adjacent signs with the same value in the first-order difference relative to the total length of the analysis window. The disturbance type discrimination module is used to determine that if the pairing rate exceeds the pairing rate threshold and the direction purity is lower than the purity threshold, it is a power grid transient distortion; otherwise, it is a timing master clock drift. The correction and compensation management module is used to freeze the correction and compensation loop of the local clock when it is determined to be a transient distortion of the power grid; and to update the correction and compensation amount of the local clock with the trend component of the displacement sequence when it is determined to be a drift of the master clock. The frequency word adjustment module is used to adjust the oscillation frequency control word of the local clock with the updated or frozen correction compensation amount.

[0043] All calculations involved in the embodiments are dimensionless numerical calculations, and the preset parameters and thresholds in the calculations are set by those skilled in the art according to the actual situation.

[0044] The above embodiments can be implemented, in whole or in part, by software, hardware, firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, in the form of a computer program product.

[0045] Those skilled in the art will recognize that the modules and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and inventive constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0046] In addition, the functional modules in the various embodiments of this application can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module.

[0047] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or modules may be electrical, mechanical, or other forms.

[0048] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0049] In conclusion, the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A clock time synchronization and correction method based on time alignment, characterized in that, Includes the following steps: S1: Capture the voltage waveform of the AC power line, obtain the zero-crossing time, and map it to a time-stamped sequence; S2: Construct zero-crossing triplets from the time-scaled sequence, calculate the symmetry center time-scale of the zero-crossing triplets, and use the offset of the symmetry center time-scale from the symmetry center time-scale of the previous zero-crossing triplet as the symmetry center drift, thus forming a displacement sequence. S3: Calculate the first-order difference of the displacement sequence, calculate the pairing rate of positive and negative impacts at transient impact points in the first-order difference, and calculate the directional purity of the continuous length of adjacent signs with the same value in the first-order difference relative to the total length of the analysis window. S4: If the pairing rate exceeds the pairing rate threshold and the directional purity is lower than the purity threshold, it is determined to be a transient distortion of the power grid; otherwise, it is determined to be a time synchronization master clock drift. S5: When a transient distortion of the power grid is detected, the correction and compensation loop of the local clock is frozen; when a time synchronization master clock drift is detected, the correction and compensation amount of the local clock is updated with the trend component of the displacement sequence. S6: Adjust the local clock oscillation frequency control word with the updated or frozen correction compensation amount.

2. The clock time synchronization correction method based on time alignment according to claim 1, characterized in that, Capture the voltage waveform of the AC power line, obtain the zero-crossing time, and map it to a time-stamped sequence, including: The voltage waveform of the AC power supply line is sampled at equal intervals to obtain a sequence of sampled values; Identify pairs of adjacent sample points with different signs in a sampled value sequence; Interpolate the sampling point pairs with different signs to find the zero-crossing time; Using the zero-crossing point as the time marker, the time markers are arranged in chronological order to form a time marker sequence.

3. The clock time synchronization correction method based on time alignment according to claim 1, characterized in that, Construct zero-crossing triples from the time-scaled sequence, calculate the symmetry center timescale of the zero-crossing triples, and use the offset of the symmetry center timescale from the symmetry center timescale of the previous zero-crossing triple as the symmetry center drift, forming a displacement sequence, including: Select three consecutive zero-crossing time markers from the time marker sequence. The first and third zero-crossing time markers correspond to the zero-crossing point of the positive half-cycle, and the second zero-crossing time marker corresponds to the zero-crossing point of the negative half-cycle, forming a zero-crossing triplet. For the zero-crossing triplet formed in this case, calculate the average of the first and second zero-crossing time scales, and use it as the symmetry center time scale; Calculate the difference between the current symmetry center timescale and the symmetry center timescale of the previous zero-crossing triplet, and use it as the symmetry center drift. The multiple consecutively obtained center of symmetry drift values ​​are arranged in the order of acquisition to form a displacement sequence.

4. The clock time synchronization correction method based on time alignment according to claim 3, characterized in that, According to the construction method of zero-crossing triplet, before forming a zero-crossing triplet, the formation order of three consecutive zero-crossing time markers is checked: if the voltage waveform slope of the first zero-crossing time marker is positive, the voltage waveform slope of the second zero-crossing time marker is negative, and the voltage waveform slope of the third zero-crossing time marker is positive, then the formation order is confirmed to be valid; if the formation order is invalid, the three consecutive zero-crossing time markers selected this time are discarded, and the next zero-crossing time marker is selected sequentially from the time marker sequence to re-form a zero-crossing triplet.

5. A clock time synchronization correction method based on time alignment according to claim 1, characterized in that, Calculate the first-order difference of the displacement sequence, statistically analyze the pairing rate of positive and negative impacts at transient impact points in the first-order difference, and calculate the directional purity of the continuous length of adjacent signs with the same value relative to the total length of the analysis window in the first-order difference, including: The difference between adjacent displacement values ​​is calculated for the displacement sequence to obtain a first-order difference sequence; The difference values ​​in the first-order difference sequence whose absolute values ​​exceed the impact threshold are marked as transient impact points, with positive values ​​marked as positive impacts and negative values ​​marked as negative impacts. The transient impact points are sorted by their occurrence time. When two adjacent transient impact points are positive and negative impacts respectively, they are recorded as a pair event. The number of pair events is counted, and the pairing rate is the number of pair events divided by the total number of transient impact points. Within the analysis window, the lengths of consecutive segments with the same sign in the first-order difference sequence are counted. The sum of all the lengths of consecutive segments is then divided by the total number of difference points within the analysis window to obtain the directional purity.

6. A clock time synchronization correction method based on time alignment according to claim 5, characterized in that, Based on the marking method of transient impact points, the impact threshold is determined in the following way: Within the initial segment of the displacement sequence, a calm displacement sequence is extracted that does not contain power grid transient distortion or timing master clock drift. Calculate the standard deviation of the first difference of the static displacement sequence; The impact threshold is set as a preset multiple of the standard deviation.

7. A clock time synchronization correction method based on time alignment according to claim 1, characterized in that, The pairing rate threshold and purity threshold are determined as follows: under the condition that there is no single-phase rectifier load in the power grid, the displacement sequence is measured multiple times and the pairing rate and directional purity are calculated. The minimum value of the pairing rate among the multiple measurements is taken as the pairing rate threshold, and the maximum value of the directional purity among the multiple measurements is taken as the purity threshold.

8. A clock time synchronization correction method based on time alignment according to claim 1, characterized in that, When a transient distortion in the power grid is detected, the local clock's correction and compensation loop is frozen; when a master clock drift is detected, the local clock's correction and compensation amount is updated with the trend component of the displacement sequence, including: When a transient distortion of the power grid is detected, the integral operation of the correction compensation loop is prohibited, and the correction compensation amount is kept constant. When the timing master clock is determined to be drifting, the displacement sequence is passed through a low-pass filter to extract the trend component; Multiply the trend component by a preset scaling factor to obtain the correction increment; Add the correction increment to the current correction compensation amount to obtain the updated correction compensation amount.

9. A clock time synchronization correction method based on time alignment according to claim 1, characterized in that, Adjust the local clock oscillation frequency control word with the updated or frozen correction compensation amount, including: Map the correction compensation amount to a frequency correction value; Update the oscillation frequency control word according to the frequency correction value; Apply the updated oscillation frequency control word to the local clock.

10. A clock time synchronization and correction system based on time alignment, used to implement the clock time synchronization and correction method based on time alignment as described in any one of claims 1-9, characterized in that, Includes the following modules: The zero-crossing capture module is used to capture the voltage waveform of the AC power line, obtain the zero-crossing time, and map it into a time-stamped sequence. The drift generation module is used to construct zero-crossing triplets from the time-scaled sequence, calculate the symmetry center time-scale of the zero-crossing triplet, and use the offset of the symmetry center time-scale from the symmetry center time-scale of the previous zero-crossing triplet as the symmetry center drift to form a displacement sequence. The feature quantity statistics module is used to calculate the first-order difference of the displacement sequence, calculate the pairing rate of positive and negative impacts at transient impact points in the first-order difference, and calculate the directional purity of the continuous length of adjacent signs with the same value in the first-order difference relative to the total length of the analysis window. The disturbance type discrimination module is used to determine that if the pairing rate exceeds the pairing rate threshold and the direction purity is lower than the purity threshold, it is a power grid transient distortion; otherwise, it is a timing master clock drift. The correction and compensation management module is used to freeze the correction and compensation loop of the local clock when it is determined to be a transient distortion of the power grid; and to update the correction and compensation amount of the local clock with the trend component of the displacement sequence when it is determined to be a drift of the master clock. The frequency word adjustment module is used to adjust the oscillation frequency control word of the local clock with the updated or frozen correction compensation amount.

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