General-purpose main processing sub-card of civil aircraft controller based on arm architecture mcu and control method

Abstract

The application provides a general main processing sub-card of a civil aircraft controller based on an ARM architecture MCU and a control method, which comprises an MCU circuit, a clock generation circuit, a JTAG debugging circuit, a power conversion circuit, a data storage circuit, a brightness control and level conversion circuit, an RS422 communication circuit, an RS232 communication circuit, a discrete quantity signal input collection circuit, a discrete quantity signal output circuit, an ARINC825 communication circuit and an external connector, so as to realize the unified type, generalization and low-cost design of the civil aircraft controller, and improve the safety and reliability of data transmission through the fault-tolerant control mechanism of hardware and software cooperation.

Description

Technical Field

[0001] This invention belongs to the field of avionics engineering and relates to a general main processing daughter card and control method for civil aircraft controllers based on ARM architecture MCU. Background Technology

[0002] Controllers are control products primarily used in various avionics subsystems and display control subsystems in aircraft cockpits, interacting with display control processors or displays. Controllers provide human-machine interfaces such as buttons, switches, and knobs. Pilot operations on the panels are reported via discrete signals or communication methods, while simultaneously responding to external commands. Typical controllers related to the display control subsystem in the aircraft cockpit include: Display Control Panel (DCP), Multi-functional Keyboard (MKB), Cursor Control Device (CCD), and Reversion Control Panel (RCP). A controller typically consists of a light guide panel, main processing daughter card, power module, chassis, and tailpiece accessories.

[0003] Civil aircraft controllers come in a wide variety of types, differing in function, performance, interfaces, and dimensions. Current technology typically employs a customized design approach for each type of controller, including separate complete units, hardware modules, and software. For example, a DCP requires analog signal acquisition interfaces, an MKB requires numerous button acquisition interfaces, and a CCD requires a trackball communication serial port. Using traditional design methods to customize each type of controller would significantly increase labor costs, component costs, manufacturing costs, and airworthiness costs.

[0004] Furthermore, high safety and high reliability are also key considerations in the design of civil aircraft controller products. In existing civil aircraft controller designs, the microcontroller units (MCUs) responsible for core processing mostly do not support error checking and correcting (ECC) and cyclic redundancy check (CRC) functions. They are unable to perform data verification and error correction on the chip's internal SRAM, register, and FLASH resources, making them susceptible to single-event upsets (SEUs) and multiple-bit upsets (MBUs). In avionics environments, high-energy particles incident on semiconductor devices can cause memory cell state flips, leading to data errors, program crashes, or even system failures. Existing solutions typically require mitigation through system architecture design (such as triple-modular redundancy and periodic refresh), which increases the burden on system architecture design and adds to software complexity and resource overhead.

[0005] In summary, existing civil aircraft controller designs have significant shortcomings in terms of standardization, cost, data reliability, and fault tolerance. Therefore, it is necessary to standardize and generalize the controller hardware platform, enabling it to perform data verification and error correction, and to establish a matching control methodology. This would allow for flexible adaptation to different types of controller products, reduce development costs, improve system reliability, and meet airworthiness certification requirements. Summary of the Invention

[0006] This invention provides a general-purpose main processing daughter card and control method for civil aircraft controllers based on ARM architecture MCUs, so as to realize the standardized, universal and low-cost design of civil aircraft controllers. Through a hardware and software collaborative fault-tolerant control mechanism, the security and reliability of data transmission are improved, and the effects of single-event upset (SEU) and multiple-bit upset (MBU) are effectively dealt with.

[0007] The first aspect of this invention provides a general-purpose main processing daughter card for a civil aircraft controller based on an ARM architecture MCU, comprising: an MCU circuit, a clock generation circuit, a JTAG debugging circuit, a power conversion circuit, a data storage circuit, a brightness control and level conversion circuit, an RS422 communication circuit, an RS232 communication circuit, a discrete signal input acquisition circuit, a discrete signal output circuit, an ARINC825 communication circuit, and an external connector; wherein, The MCU circuit includes an ARM architecture MCU chip with ECC and CRC check functions; a clock generation circuit to provide an 8MHz clock source for the MCU; and a JTAG debugging circuit to support MCU circuit code burning and debugging. The power conversion circuit is used to convert 5V power to 3.3V power input to the daughter card, which is used by the various functional circuits on the daughter card; The data storage circuit includes an MRAM memory chip that communicates with the MCU circuit via an SPI interface and is used to store critical data and fault codes during controller operation. The brightness control and level conversion circuit is used to convert the 3.3V level PWM dimming signal output by the MCU circuit into a 5V level PWM dimming signal, which is used for brightness control of the indicator lights and backlight on the controller's light guide panel; The RS422 and RS232 communication circuits are used to convert the two pairs of UART RX / TX signals, LPUART1 and LPUART2, of the MCU circuit into one RS422 transmit / receive signal and one RS232 transmit / receive signal, respectively. The ARINC825 communication circuit is used to convert the two sets of CAN TX / RX signals of the MCU circuit into two CAN_H / L signals that conform to the ARINC825 standard. The discrete signal input acquisition circuit is used to convert the 6 channels of 28VGND / OPEN discrete input signals from the external connector into 3.3V discrete signals for the MCU circuit to acquire. The discrete signal output circuit is used to convert the 8 discrete signals output by the MCU circuit into 28VGND / OPEN discrete output signals, and then send them to the external connector pins; The external connectors include three connectors, two of which are used to connect to the controller's light guide panel and one connector is used to connect to the controller's power module. The MCU circuit also connects to the signals of buttons, switches, and knobs via pull-up resistors for signal acquisition.

[0008] Optionally, the MCU chip model is FS32K144HAT0MLLT, with an Arm Cortex-M4F core, an operating frequency of 80MHz, an operating voltage of 3.3V, and memory including: 64kB SRAM, 512kB FLASH, and 4kB EEPROM; the MCU chip has peripheral interfaces: 89 x GPIO, 1 x I²C, 3 x SPI, 3 x UART, 3 x CAN, 4 x 16-bit Timer, and 2 x 12-bit ADC.

[0009] Optionally, the clock generation circuit includes an 8MHz passive crystal oscillator, a pair of load capacitors, and a feedback resistor; the two ends of the 8MHz passive crystal oscillator are grounded through the pair of load capacitors, and the feedback resistor is connected in parallel across the two ends of the 8MHz passive crystal oscillator.

[0010] Optionally, the power conversion circuit includes: an LDO chip, a MOSFET, a resistor, and a light-emitting diode (LED); the anode of the LED is connected to a 3.3V power supply, the cathode is connected to the first end of the resistor, the second end of the resistor is connected to the source of the MOSFET, and the drain of the MOSFET is grounded; the 3.3V power signal output by the LDO chip is connected to the gate of the MOSFET, and the power-on status of the daughter card is indicated by the on / off state of the LED.

[0011] Optionally, the JTAG debugging circuit is used for MCU circuit debugging and software programming via a connected emulator. Optionally, the data storage circuit is used to store and retrieve the MCU circuit's power-on count and BIT fault codes. Optionally, two external connectors connected to the light guide panel are located on the left and right sides of the front of the daughter card, and different models are used to prevent incorrect insertion; the external connector connecting to the power conversion module inside the controller is located on the back of the daughter card.

[0012] The second aspect of the present invention also provides a control method for a general-purpose main processing daughter card of a civil aircraft controller based on an ARM architecture MCU as described in any of the first aspects, comprising: Step 1: Power-on Reset and Boot Loading; After the daughter card is powered on, the MCU executes the boot load program, initializes the clock, GPIO, LPUART2, and SPI, enables the NVIC interrupt, and initializes the MRAM chip; Step 2: Mode selection; MCU reads the mode discrete pin level: if it is high, it enters debug mode and proceeds to step 3; if it is low, it enters master control mode and proceeds to step 6. Step 3: RS232 serial port command parsing: The MCU receives commands from the host computer via the RS232 serial port. If the command is 100, it enters the software programming mode and proceeds to Step 4; if the command is 210, it enters the fault data reading mode and proceeds to Step 5. Step 4: Software Programming; The MCU erases the main control software storage area in its internal FLASH memory, and receives data packets cyclically via the RS232 serial port. For each data packet, a CRC check is performed. If the check is successful, the data is written to the corresponding address in the FLASH memory, and a CRC check is performed again. If the second check is successful, the CRC check value is sent to the host computer via the RS232 serial port. If the current data packet is not the last data packet, the next data packet is received. If the CRC check fails, a failure code is sent to the host computer via the RS232 serial port, and the programming process is terminated. When all data packets have been received and the CRC check is successful, a programming success message is sent to the host computer via the RS232 serial port, and the process returns to Step 1. Step 5: MRAM fault data reading; The MCU reads the key operating data stored in the MRAM through the SPI interface and sends it to the host computer through the RS232 serial port. After the transmission is completed, return to Step 1. Step Six: Jump to the main control software; The MCU reads the stack pointer and reset vector at the starting address of the main control software, sets the main stack pointer and process stack pointer, redirects the interrupt vector table to the main control software area, and jumps to the main control software entry point through the function pointer; Step 7: Clock Configuration; The MCU initializes the external crystal oscillator and phase-locked loop sequentially, configures the core clock to 80MHz, the bus clock to 40MHz, and the Flash clock to 26.67MHz, and allocates clock sources to each peripheral module through the peripheral clock controller; Step 8: Configuration file parsing and dynamic port configuration; The MCU parses the pre-compiled binary configuration file, extracts input messages, output messages, signal mappings and hardware configuration information, and dynamically configures GPIO pin functions, matrix keyboard scanning parameters and communication interface enable based on the identified controller type information, so as to realize the standardization and generalization of the hardware platform design. Step Nine: Functional Module Initialization and Stack Overflow Monitoring Settings; The MCU performs the following initialization operations in sequence: a. Initialize the ADC module for RLS analog brightness acquisition; b. Initialize the LPSPI0 module to master mode and initialize the MRAM chip for critical data storage; c. Initialize the LPUART1 and LPUART2 modules, configure the baud rate to 115200, and enable transmit and receive interrupts; d. Initialize the LPIT0 module, set the timing period to 0.5ms, and enable channel 0 interrupt as the time base for system task scheduling; e. Initialize the FlexCAN0 and FlexCAN1 modules, configure the baud rate to 500kbps, allocate DMA channels for CAN0 and CAN1 respectively, and configure DMAMUX to realize automatic transmission of CAN received data. f. Initialize FTM0, FTM1, FTM2, and FTM3 modules, and configure the PWM output channel for brightness control of the backlight and indicator lights of the light guide panel; g. Fill the initial region of the stack with a preset magic number to create a stack overflow monitoring area for subsequent continuous self-check tasks to detect the stack.

[0013] Step 10: Power status check; The MCU reads the reset status register and records the number of power-on cycles to MRAM; Step 11: Power-on self-test; The MCU performs a power-on self-test, including: watchdog test, position discreteness test, internal SRAM data bus test, internal FLASH function test, MRAM test, ARINC825-A channel loopback test, and ARINC825-B channel loopback test; If PBIT passes, the CAN module is switched to normal mode, and the self-test mode is switched from PBIT to periodic self-test, then proceed to Step 12; If PBIT fails, the system enters fault mode and proceeds to Step 15; Step 12: Task Registration and Scheduler Startup; The MCU adds periodic tasks to the task scheduler, including pilot input message sending, signal acquisition, equipment configuration information sending, equipment status information sending, continuous self-testing, etc.; The scheduler updates the task delay count based on the time base generated by the hardware timer and sets the task running flag when the delay reaches zero. Step 13: Main Loop; The MCU enters the main loop, starts interrupt-based task scheduling, iterates through and executes all tasks in sequence, and executes the corresponding function for tasks with the running flag set; Each cycle calls the watchdog feed function to reset the watchdog counter; Step Fourteen: Continuous Self-Test; The MCU periodically performs continuous self-tests, including: button test, knob test, software task frame overflow test, software stack overflow test, SEE error check, MBU error monitoring, ARINC825 input status monitoring, 28V input power supply voltage detection, trackball status monitoring, etc.; A fault verification mechanism is adopted, and a fault is confirmed after the number of faults reaches a threshold, and then proceed to Step Fifteen. Step 15: Fault Recording and Safety Handling; When a fault is detected during power-on self-test or continuous self-test, the MCU writes the fault code and fault count into the MRAM and reports the system status through the ARINC825 interface; For unrecoverable faults, the MCU enters stop mode and waits for the system to reset.

[0014] The beneficial effects of this invention are as follows: This invention provides a general-purpose main processing daughter card and control method for civil aircraft controllers based on ARM architecture MCUs. It can support multiple functions such as button, switch, and knob signal acquisition, RS422 serial communication, RS232 serial communication, ARINC825 bus communication, discrete quantity acquisition and output, signal light and backlight brightness control, and key data storage. The same hardware platform can be adapted to various civil aircraft controller products, improving the standardization and universality of civil aircraft controller products, significantly reducing manpower, component, manufacturing, and airworthiness costs. Through a hardware and software collaborative fault-tolerant control mechanism, it improves the security and reliability of data transmission, effectively copes with the impact of SEU and MBU, and meets airworthiness certification requirements. Attached Figure Description

[0015] Figure 1This is a schematic diagram of the structure of a general-purpose main processing daughter card for a civil aircraft controller based on an ARM architecture MCU; Figure 2 This is a schematic diagram of a general-purpose main processing daughter card for a civil aircraft controller based on an ARM architecture MCU. Figure 3 For MCU circuits; Figure 4 For clock generation circuit; Figure 5 Debugging circuits for JTAG; Figure 6 It is a power conversion circuit; Figure 7 For data storage circuitry; Figure 8 For brightness control and level conversion circuitry; Figure 9 It is an RS422 communication circuit; Figure 10 It is an RS232 communication circuit; Figure 11 shows the ARINC825 communication circuit; Figure 12 This is a discrete input acquisition circuit for 28VGND / OPEN. Figure 13 This is a discrete output circuit with 28VGND / OPEN. Figure 14 This is a schematic diagram of the control method for a general-purpose main processing daughter card of a civil aircraft controller based on an ARM architecture MCU. Detailed Implementation

[0016] The present invention will be further described in detail below with reference to the embodiments and accompanying drawings, but the embodiments of the present invention are not limited thereto.

[0017] like Figure 1-13 As shown, the present invention provides a general-purpose main processing sub-card (hereinafter referred to as sub-card) for civil aircraft controller based on ARM architecture MCU and a control method based on the sub-card.

[0018] The daughter card includes: MCU circuit, clock generation circuit, JTAG debugging circuit, power conversion circuit, data storage circuit, level conversion circuit, RS422 interface circuit, RS232 interface circuit, discrete input acquisition circuit, discrete output circuit, ARINC825 interface circuit, external connectors, and several pull-up resistors, etc.

[0019] The external connectors include three connectors: two connectors for connecting to the controller's light guide panel and one connector for connecting to the controller's power module.

[0020] The MCU circuit includes an ARM architecture MCU chip and several decoupling and filtering capacitors, and its function is core processing.

[0021] The MCU chip model is FS32K144HAT0MLLT, with an Arm Cortex-M4F core, an operating frequency of 80MHz, and an operating voltage of 3.3V. Its memory includes 64kB SRAM, 512kB FLASH, and 4kB EEPROM. It has rich peripheral interfaces: 89 x GPIO (supporting pin multiplexing), 1 x I²C, 3 x SPI, 3 x UART, 3 x CAN (one of which is CANFD), 4 x 16-bit Timer, 2 x 12-bit ADC, etc. It has ECC and CRC verification functions, which can significantly improve the security and reliability of data transmission.

[0022] The crystal oscillator circuit includes an 8MHz passive crystal oscillator, a load capacitor, and several feedback resistors. Its function is to provide an 8MHz clock source for the MCU.

[0023] The JTAG debug circuit includes a 10-pin (2*5, 1.27mm pitch) connector and several pull-up resistors, and its function is to support MCU code burning and debugging.

[0024] The power conversion circuit includes a low dropout regulator (LDO) chip TPS74401RGWT and related peripheral circuits. Its function is to convert the 5V power input to the daughter card into a 3.3V power supply for use by various functional circuits on the daughter card.

[0025] The data storage circuit includes an MRAM memory chip MR25H40CDC and related peripheral circuits. The MCU communicates with the MRAM through the SPI interface for storing key data, fault codes, etc. during the operation of the controller.

[0026] The level conversion circuit includes a bus driver chip SN74LVC4245APW with level conversion function and related peripheral circuits. Its function is to convert the 6 channels of 3.3V level PWM dimming signals output by the MCU into 5V level PWM dimming signals for brightness control of the indicator lights and backlight on the controller's light guide panel.

[0027] The RS422 interface circuit includes an RS422 interface chip MAX3490ESA+ and related peripheral circuits. Its function is to convert a pair of UART RX / TX signals (LPUART1) of the MCU into one RS422 transmit / receive signal. The RS232 interface circuit includes an RS232 interface chip MAX3232EUE+ and related peripheral circuits. Its function is to convert a pair of UART RX / TX signals (LPUART2) of the MCU into one RS232 transmit / receive signal.

[0028] The discrete input acquisition circuit includes a discrete acquisition chip HI-8425PQI and related peripheral circuits. Its function is to convert the 6 channels of 28VGND / OPEN discrete input signals from the external connector (the connector connected to the controller power module) into 3.3V level discrete signals for the MCU to acquire.

[0029] The discrete output circuit includes two optocouplers TLP291-4GB and related peripheral circuits. Its function is to convert the eight discrete signals output by the MCU into 28VGND / OPEN and then send them to the pins of the external connector (the connector connected to the controller power module). Each optocoupler is responsible for the conversion / isolation of four discrete output signals.

[0030] The ARINC825 interface circuit includes two CAN interface chips (ADM3053BRWZ) and related peripheral circuitry. Its function is to convert the MCU's two sets of CAN TX / RX signals into two CAN_H / L signals conforming to the ARINC825 standard, and then send them to the connector pins connected to the controller's power module. Several pull-up resistors are used to pull up signals from buttons, switches, knobs, etc., to facilitate signal acquisition by the MCU.

[0031] The control method based on the above-mentioned sub-card includes the following steps: Step 1: Power-on Reset and Boot Loading; After the daughter card is powered on, the MCU executes the bootloader, initializes the clock, GPIO, LPUART2, and SPI, enables the NVIC interrupt (configured as LPUART2 receive interrupt), and initializes the MRAM chip; Step 2: Mode selection; MCU reads the mode discrete pin level: if it is high, it enters debug mode and proceeds to step 3; if it is low, it enters master control mode and proceeds to step 6. Step 3: RS232 serial port command parsing: The MCU receives commands from the host computer via the RS232 serial port. If the command is 100, it enters the software programming mode and proceeds to Step 4; if the command is 210, it enters the fault data reading mode and proceeds to Step 5. Step 4: Software Programming; The MCU erases the main control software storage area in its internal FLASH memory, and receives data packets cyclically via the RS232 serial port. For each data packet, a CRC check is performed. If the check is successful, the data is written to the corresponding address in the FLASH memory, and a CRC check is performed again. If the second check is successful, the CRC check value is sent to the host computer via the RS232 serial port. If the current data packet is not the last data packet, the next data packet is received. If the CRC check fails, a failure code is sent to the host computer via the RS232 serial port, and the programming process is terminated. When all data packets have been received and the CRC check is successful, a programming success message is sent to the host computer via the RS232 serial port, and the process returns to Step 1. Step 5: MRAM fault data reading; The MCU reads the key operating data stored in the MRAM through the SPI interface and sends it to the host computer through the RS232 serial port. After the transmission is completed, return to Step 1. Step Six: Jump to the main control software; The MCU reads the stack pointer and reset vector at the starting address of the main control software, sets the main stack pointer and process stack pointer, redirects the interrupt vector table to the main control software area, and jumps to the main control software entry point through the function pointer; Step 7: Clock Configuration; The MCU initializes the external crystal oscillator (SOSC) and phase-locked loop (SPLL) sequentially, configures the core clock to 80MHz, the bus clock to 40MHz, and the Flash clock to 26.67MHz, and allocates clock sources to each peripheral module (GPIO, LPUART, CAN, SPI, timer, ADC, etc.) through the peripheral clock controller (PCC); NVIC is an abbreviation for Nested Vectored Interrupt Controller.

[0032] Step 8: Configuration file parsing and dynamic port configuration; The MCU parses the pre-compiled binary configuration file, extracts input messages, output messages, signal mappings and hardware configuration information, and dynamically configures GPIO pin functions, matrix keyboard scanning parameters and communication interface enable based on the identified controller type information, so as to realize the standardization and generalization of the hardware platform design. Step Nine: Functional Module Initialization and Stack Overflow Monitoring Settings; The MCU performs the following initialization operations in sequence: a. Initialize the ADC module for RLS luminance analog signal acquisition (only enabled for DCP type). b. Initialize the LPSPI0 module to master mode and initialize the MRAM chip for critical data storage; c. Initialize the LPUART1 module (RS422) and LPUART2 module (RS232), configure the baud rate to 115200, and enable transmit and receive interrupts; d. Initialize the LPIT0 module, set the timing period to 0.5ms, and enable channel 0 interrupt as the time base for system task scheduling; e. Initialize the FlexCAN0 and FlexCAN1 modules, configure the baud rate to 500kbps, allocate DMA channels for CAN0 and CAN1 respectively, and configure DMAMUX to realize automatic transmission of CAN received data. f. Initialize FTM0, FTM1, FTM2, and FTM3 modules, and configure the PWM output channel for brightness control of the backlight and indicator lights of the light guide panel; g. Fill the stack start area with a preset magic number (0xCC) to create a stack overflow monitoring area for subsequent continuous self-check tasks to detect the stack.

[0033] Step 10: Power status check; The MCU reads the reset status register and records the number of power-on cycles to MRAM; Step 11: Power-on Self-Test; The MCU performs a Power-on Build-in-TEST (PBIT), including: watchdog test, position discreteness test, internal SRAM data bus test, internal FLASH function test, MRAM test, ARINC825-A channel loopback test, and ARINC825-B channel loopback test. If PBIT passes, the CAN module is switched to normal mode, and the self-test mode is switched from PBIT to Continuous Built-in Test (CBIT), and Step 12 is executed; if PBIT fails, the system enters fault mode and proceeds to Step 15. Step 12: Task Registration and Scheduler Startup; The MCU adds periodic tasks to the task scheduler, including pilot input message sending, signal acquisition, equipment configuration information sending, equipment status information sending, continuous self-testing, etc.; The scheduler updates the task delay count based on the time base generated by the hardware timer and sets the task running flag when the delay reaches zero. Step 13: Main Loop; The MCU enters the main loop, starts interrupt-based task scheduling, iterates through and executes all tasks in sequence, and executes the corresponding function for tasks with the running flag set; Each cycle calls the watchdog feed function to reset the watchdog counter; Step Fourteen: Continuous Self-Test; The MCU periodically performs continuous self-tests (triggered by timer interrupts), including: button test, knob test, software task frame overflow test, software stack overflow test, SEE error check, MBU error monitoring, ARINC825 input status monitoring, 28V input power supply voltage detection, trackball status monitoring, etc.; A fault verification mechanism is adopted, and a fault is confirmed after the number of faults reaches a threshold, and then proceed to Step Fifteen; Step 15: Fault Recording and Safety Handling; When a fault is detected during power-on self-test or continuous self-test, the MCU writes the fault code and fault count into the MRAM and reports the system status through the ARINC825 interface; For unrecoverable faults, the MCU enters stop mode and waits for the system to reset.

[0034] The schematic diagram of a general-purpose main processing daughter card for a civil aircraft controller based on an ARM architecture MCU shown in this embodiment is as follows: Figure 1 As shown, the dimensions are 110mm (length) x 45mm (width) x 2mm (thickness). Its small size allows it to fit into most controller chassis. The daughter card has 6 screw mounting holes for structural support and stress reduction. On the left and right sides of the front of the daughter card, there is a TFM-125-01-SD-WT connector and a TFM-120-01-SD-DS connector, respectively, for connecting to the light guide panel inside the controller. Different connector models are used to prevent incorrect insertion. On the back of the daughter card, there is an FLE-120-01-G-DV connector for connecting to the power conversion module inside the controller.

[0035] The principle block diagram of the daughter card shown in this embodiment is as follows: Figure 2 As shown, it includes: MCU circuit, clock generation circuit, JTAG debugging circuit, power conversion circuit, data storage circuit, level conversion circuit, RS422 interface circuit, RS232 interface circuit, discrete input acquisition circuit, discrete output circuit, ARINC825 interface circuit, external connectors and several pull-up resistors, etc.

[0036] The following is a detailed description of the components of a general-purpose main processing daughter card for a civil aircraft controller based on an ARM architecture MCU: The selected MCU chip is model FS32K144HAT0MLLT, belonging to NXP's S32K144 series MCU chips. It conforms to the automotive-grade ASIL-B standard, with an Arm Cortex-M4F core, an operating frequency of 80MHz, and an operating voltage of 3.3V. Its memory includes 64kB SRAM, 512kB FLASH, and 4kB EEPROM. It features rich peripheral interfaces: 89 x GPIO (supporting pin multiplexing for EIP3V3-X, DIP3V3-X, etc. signal acquisition), 1 x I²C, 3 x SPI (one SPI for communication with the MRAM chip, the other two unused), 3 x UART (one UART for RS232 serial debugging, one for RS422 communication), 3 x CAN (one CAN FD, two of which are used for ARINC825 communication), and 4 x 16-bit... Timer (all 4 timers are enabled to output PWM signals to control the brightness of indicator lights and backlight), 2 x 12 bits ADC (one of the 2 ADCs is used to acquire RLS brightness analog signals), etc., with ECC and CRC verification functions.

[0037] like Figure 3 The diagram shows the MCU circuit. The MCU is powered by a +3.3V power supply, and multiple decoupling capacitors are placed near the power-related pins. Additionally, filter capacitors are added to some receive signal pins. The communication signals between the MCU (U1) and other functional circuits on the daughter card include: a. Power interface: 1 +3.3V DC input, connected to the power conversion circuit for MCU operating power; b. Clock signal interface: 1 input, connected to the clock generation circuit, used for the clock signal required by the MCU; c. JTAG interface: 1 input / output, connected to the JTAG debugging circuit, used for MCU debugging and software programming; d. Reset signal interface: 1 input, connected to the reset circuit, used for MCU reset; e.SPI interface: 1 input / output, connected to the data storage circuit, used to communicate with the MRAM memory chip; f.PWM signal interface: 9 outputs, connected to the brightness control and level conversion circuit unit, of which 1 is used for the backlight brightness control of the light guide panel, and the other 8 are used for the brightness control of the indicator lights and alarm lights of the light guide panel. g. UART TX / RX interface: 2 input / output channels, one channel connects to the RS422 communication circuit for trackball communication; the other channel connects to the RS232 communication circuit for serial port debugging; h.CAN TX / RX interface: 2 inputs and outputs, connected to the main and backup ARINC825 communication circuits for ARINC825 communication; i. Analog interface: 1 input signal for RLS brightness analog signal acquisition; j. Discrete signal interface: A total of 32 signals are connected to the discrete signal acquisition circuit, including 12 inputs for encoder knob switch signal acquisition; 12 inputs for key and band switch signal acquisition; and 8 outputs for matrix keypad row and column scanning. k.28VGND / OPEN Discrete Signal Interface: 6 inputs, connected to the 28VGND / OPEN discrete signal input acquisition circuit for 28VGND / OPEN discrete signal input acquisition; 8 outputs, connected to the 28VGND / OPEN discrete signal output circuit for 28VGND / OPEN discrete signal output. l. Power status monitoring signal interface: 3 input signals, used to monitor the status of the three 28V power supplies of the power module.

[0038] like Figure 4 As shown, the clock generation circuit includes an 8MHz passive crystal oscillator, a pair of load capacitors, and a feedback resistor. Its function is to provide a pair of 8MHz differential clock signals to the MCU.

[0039] like Figure 5 The diagram shows a JTAG debugging circuit, which includes a 10-pin (2*5 1.27mm pitch) connector (model: FTSH-105-01-LD-RA) and several pull-up resistors. Its function is to connect to an emulator for MCU debugging and software programming.

[0040] like Figure 6 The circuit shown is a power conversion circuit, including an LDO chip TPS74401RGWT and external resistors and capacitors. Its function is to convert the +5V DC power input to the daughter card into a +3.3V DC power supply, which serves as the daughter card's operating power. In addition, this circuit also has a power status indication function. The PGOOD3V3 signal output from the LDO chip is connected to a MOSFET, and the on / off state of the daughter card is indicated by the illumination of an LED.

[0041] like Figure 7The diagram shows the data storage circuit, which includes an MRAM memory chip MR25H40CDC and several external pull-up / pull-down resistors and decoupling capacitors. The MCU communicates with the MRAM via an SPI interface to access critical operational data such as power-on counts and BIT fault codes. The MR25H40CDC chip has a storage capacity of 4 Mbit (512kbit*8), and its SPI interface supports a maximum clock frequency of 50MHz, which meets the storage requirements of critical data during daughter card operation.

[0042] like Figure 8 As shown, the brightness control and level conversion circuit includes a bus driver chip SN74LVC4245APW with level conversion function and several external pull-down resistors and decoupling capacitors. Its function is to convert the 6 channels of 3.3V level PWM dimming signals output by the MCU into 5V level for brightness control of the controller's light guide panel signal indicator lights, alarm lights and backlight.

[0043] like Figure 9 The diagram shows an RS422 communication circuit, including an RS422 interface chip MAX3490ESA+ and several external pull-up / pull-down resistors, matching resistors, and decoupling capacitors. Its function is to convert a pair of UART RX / TX signals (RS422-TXD, RS422-RXD) from the MCU into a set of RS422 differential transmit / receive signals (RS422-R+ / -, RS422-T+ / -). This RS422 communication circuit is used for acquiring trackball signals from the daughter card.

[0044] like Figure 10 The diagram shows an RS232 communication circuit, including an RS232 interface chip MAX3232EUE+ and several external capacitors. Its function is to convert a pair of UART RX / TX signals (RS232-TXD, RS232-RXD) from the MCU into a single RS232 transmit / receive signal (RS232-T, RS232-R). RS232 is used for serial port debugging and code programming of the daughter card MCU.

[0045] As shown in Figure 11, this is a primary and backup ARINC825 communication circuit, which includes two CAN interface chips (ADM3053BRWZ) and external resistors and capacitors. Its function is to convert the two sets of CAN data signals (CAN1_RX / TX, CAN2_RX / TX) of the MCU into two CAN signals conforming to the ARINC825 standard (primary channel is A825_A_H / L, backup channel is A825_B_H / L), which are used for communication between the controller and other products in the avionics system.

[0046] like Figure 12As shown, this is a 28VGND / OPEN discrete input acquisition circuit, which includes a discrete acquisition chip HI-8425PQI and several external resistors and capacitors. Its function is to convert 6 channels of 28VGND / OPEN discrete input signals into discrete signals at a +3.3V / GND level for the MCU to acquire.

[0047] like Figure 13 The diagram shows a 28VGND / OPEN discrete output circuit, comprising two TLP291-4GB optocouplers and several peripheral circuits including resistors, capacitors, and diodes. Its function is to convert eight discrete signals at +3.3V / GND level output from the MCU into 28VGND / OPEN level signals. Each optocoupler is responsible for the conversion / isolation of four discrete output signals.

[0048] like Figure 14 As shown, the control method based on the daughter card includes the following steps: Step 1: Power-on Reset and Boot Loading; After the daughter card is powered on, the MCU executes the bootloader, initializes the clock, GPIO, LPUART2, and SPI, enables the NVIC interrupt (configured as LPUART2 receive interrupt), and initializes the MRAM chip; Step 2: Mode selection; MCU reads the mode discrete pin level: if it is high, it enters debug mode and proceeds to step 3; if it is low, it enters master control mode and proceeds to step 6. Step 3: RS232 serial port command parsing: The MCU receives commands from the host computer via the RS232 serial port. If the command is 100, it enters the software programming mode and proceeds to Step 4; if the command is 210, it enters the fault data reading mode and proceeds to Step 5. Step 4: Software Programming; The MCU erases the main control software storage area in its internal FLASH memory, and receives data packets cyclically via the RS232 serial port. For each data packet, a CRC check is performed. If the check is successful, the data is written to the corresponding address in the FLASH memory, and a CRC check is performed again. If the second check is successful, the CRC check value is sent to the host computer via the RS232 serial port. If the current data packet is not the last data packet, the next data packet is received. If the CRC check fails, a failure code is sent to the host computer via the RS232 serial port, and the programming process is terminated. When all data packets have been received and the CRC check is successful, a programming success message is sent to the host computer via the RS232 serial port, and the process returns to Step 1. Step 5: MRAM fault data reading; The MCU reads the key operating data stored in the MRAM through the SPI interface and sends it to the host computer through the RS232 serial port. After the transmission is completed, return to Step 1. Step Six: Jump to the main control software; The MCU reads the stack pointer and reset vector at the starting address of the main control software, sets the main stack pointer and process stack pointer, redirects the interrupt vector table to the main control software area, and jumps to the main control software entry point through the function pointer; Step 7: Clock Configuration; The MCU initializes the external crystal oscillator (SOSC) and phase-locked loop (SPLL) sequentially, configures the core clock to 80MHz, the bus clock to 40MHz, and the Flash clock to 26.67MHz, and allocates clock sources to each peripheral module (GPIO, LPUART, CAN, SPI, timer, ADC, etc.) through the peripheral clock controller (PCC); Step 8: Configuration file parsing and dynamic port configuration; The MCU parses the pre-compiled binary configuration file, extracts input messages, output messages, signal mappings and hardware configuration information, and dynamically configures GPIO pin functions, matrix keyboard scanning parameters and communication interface enable based on the identified controller type information, so as to realize the standardization and generalization of the hardware platform design. Step Nine: Functional Module Initialization and Stack Overflow Monitoring Settings; The MCU performs the following initialization operations in sequence: a. Initialize the ADC module for RLS luminance analog signal acquisition (only enabled for DCP type). b. Initialize the LPSPI0 module to master mode and initialize the MRAM chip for critical data storage; c. Initialize the LPUART1 module (RS422) and LPUART2 module (RS232), configure the baud rate to 115200, and enable transmit and receive interrupts; d. Initialize the LPIT0 module, set the timing period to 0.5ms, and enable channel 0 interrupt as the time base for system task scheduling; e. Initialize the FlexCAN0 and FlexCAN1 modules, configure the baud rate to 500kbps, allocate DMA channels for CAN0 and CAN1 respectively, and configure DMAMUX to realize automatic transmission of CAN received data. f. Initialize FTM0, FTM1, FTM2, and FTM3 modules, and configure the PWM output channel for brightness control of the backlight and indicator lights of the light guide panel; g. Fill the stack start area with a preset magic number (0xCC) to create a stack overflow monitoring area for subsequent continuous self-check tasks to detect the stack.

[0049] As can be understood, LPSPI0, LPUART1, LPUART2, LPIT0, FLEXCAN0, FLEXCAN1, and FTM0-3 in the above steps are all names of peripheral modules within the MCU. The software will enable these modules to send / receive signals on the corresponding peripheral interfaces. For example, if the LPUART1 module is enabled first, a UART TX / RX signal will be generated on the corresponding MCU pin, and then converted into RS422 signals (RS422-T+, RS422-T-, RS422-R+, RS422-R-) by the interface chip.

[0050] Step 10: Power status check; The MCU reads the reset status register and records the number of power-on cycles to MRAM; Step 11: Power-on Self-Test; The MCU performs a Power-on Build-in-TEST (PBIT), including: watchdog test, position discreteness test, internal SRAM data bus test, internal FLASH function test, MRAM test, ARINC825-A channel loopback test, and ARINC825-B channel loopback test. If PBIT passes, the CAN module is switched to normal mode, and the self-test mode is switched from PBIT to Continuous Built-in Test (CBIT), and Step 12 is executed; if PBIT fails, the system enters fault mode and proceeds to Step 15. Step 12: Task Registration and Scheduler Startup; The MCU adds periodic tasks to the task scheduler, including pilot input message sending, signal acquisition, equipment configuration information sending, equipment status information sending, continuous self-testing, etc.; The scheduler updates the task delay count based on the time base generated by the hardware timer and sets the task running flag when the delay reaches zero. Step 13: Main Loop; The MCU enters the main loop, starts interrupt-based task scheduling, iterates through and executes all tasks in sequence, and executes the corresponding function for tasks with the running flag set; Each cycle calls the watchdog feed function to reset the watchdog counter; Step Fourteen: Continuous Self-Test; The MCU periodically performs continuous self-tests (triggered by timer interrupts), including: button test, knob test, software task frame overflow test, software stack overflow test, SEE error check, MBU error monitoring, ARINC825 input status monitoring, 28V input power supply voltage detection, trackball status monitoring, etc.; A fault verification mechanism is adopted, and a fault is confirmed after the number of faults reaches a threshold, and then proceed to Step Fifteen; Step 15: Fault Recording and Safety Handling; When a fault is detected during power-on self-test or continuous self-test, the MCU writes the fault code and fault count into the MRAM and reports the system status through the ARINC825 interface; For unrecoverable faults, the MCU enters stop mode and waits for the system to reset.

[0051] The above detailed embodiments are a description of the present invention. It should not be considered that the specific embodiments of the present invention are limited to these descriptions. For those skilled in the art, several simple deductions and substitutions can be made without departing from the concept of the present invention, and all of these should be considered to fall within the protection scope of the present invention.

Claims

1. A general-purpose main processing daughter card for civil aircraft controllers based on ARM architecture MCUs, characterized in that, include: The circuit includes an MCU circuit, clock generation circuit, JTAG debugging circuit, power conversion circuit, data storage circuit, brightness control and level conversion circuit, RS422 communication circuit, RS232 communication circuit, discrete signal input acquisition circuit, discrete signal output circuit, ARINC825 communication circuit, and external connectors. The MCU circuit includes an ARM architecture MCU chip, which has ECC and CRC check functions; The clock generation circuit is used to provide an 8MHz clock source for the MCU; The JTAG debugging circuit is used to support MCU circuit code burning and debugging; The power conversion circuit is used to convert 5V power to 3.3V power input to the daughter card, which is used by the various functional circuits on the daughter card; The data storage circuit includes an MRAM memory chip that communicates with the MCU circuit via an SPI interface and is used to store critical data and fault codes during controller operation. The brightness control and level conversion circuit is used to convert the 3.3V level PWM dimming signal output by the MCU circuit into a 5V level PWM dimming signal, which is used for brightness control of the indicator lights and backlight on the controller's light guide panel; The RS422 and RS232 communication circuits are used to convert the two pairs of UART RX / TX signals, LPUART1 and LPUART2, of the MCU circuit into one RS422 transmit / receive signal and one RS232 transmit / receive signal, respectively. The ARINC825 communication circuit is used to convert the two sets of CAN TX / RX signals of the MCU circuit into two CAN_H / L signals that conform to the ARINC825 standard. The discrete signal input acquisition circuit is used to convert the 6 channels of 28VGND / OPEN discrete input signals from the external connector into 3.3V discrete signals for the MCU circuit to acquire. The discrete signal output circuit is used to convert the 8 discrete signals output by the MCU circuit into 28VGND / OPEN discrete output signals, and then send them to the external connector pins; The external connectors include three connectors, two of which are used to connect to the controller's light guide panel and one connector is used to connect to the controller's power module. The MCU circuit also connects to the signals of buttons, switches, and knobs via pull-up resistors for signal acquisition.

2. The general-purpose main processing daughter card for civil aircraft controllers based on ARM architecture MCU according to claim 1, characterized in that, The MCU chip is model FS32K144HAT0MLLT, with an Arm Cortex-M4F core, an operating frequency of 80MHz, an operating voltage of 3.3V, and memory including: 64kB SRAM, 512kB FLASH, and 4kB EEPROM. The MCU chip has the following peripheral interfaces: 89 x GPIO, 1 x I²C, 3 x SPI, 3 x UART, 3 x CAN, 4 x 16-bit Timer, and 2 x 12-bit ADC.

3. The general-purpose main processing daughter card for civil aircraft controllers based on ARM architecture MCU according to claim 1, characterized in that, The clock generation circuit includes an 8MHz passive crystal oscillator, a pair of load capacitors, and a feedback resistor. The two ends of the 8MHz passive crystal oscillator are grounded through a pair of load capacitors. The feedback resistors are connected in parallel across the 8MHz passive crystal oscillator.

4. The general-purpose main processing daughter card for civil aircraft controllers based on ARM architecture MCU according to claim 1, characterized in that, The power conversion circuit includes: an LDO chip, a MOSFET, a resistor, and a light-emitting diode; The anode of the LED is connected to a 3.3V power supply, the cathode is connected to the first end of a resistor, the second end of the resistor is connected to the source of a MOSFET, and the drain of the MOSFET is grounded. The 3.3V power signal output by the LDO chip is connected to the gate of the MOSFET, and the power-on status of the daughter card is indicated by the on / off state of the LED.

5. The general-purpose main processing daughter card for civil aircraft controllers based on ARM architecture MCU according to claim 1, characterized in that, The JTAG debug circuit is used to debug MCU circuits and program software by connecting to an emulator.

6. The general-purpose main processing daughter card for civil aircraft controllers based on ARM architecture MCU according to claim 1, characterized in that, The data storage circuit is used to store and retrieve the number of power-on cycles and BIT fault codes of the MCU circuit.

7. The general-purpose main processing daughter card for civil aircraft controllers based on ARM architecture MCU according to claim 1, characterized in that, Two external connectors connected to the light guide panel are located on the left and right sides of the front of the sub-card, and different models are used to prevent incorrect insertion. The external connector that connects to the power conversion module inside the controller is located on the back of the daughter card.

8. A control method for a general-purpose main processing daughter card of a civil aircraft controller based on an ARM architecture MCU as described in any one of claims 1-7, characterized in that, include: Step 1: Power-on Reset and Boot Loading; After the daughter card is powered on, the MCU executes the boot load program, initializes the clock, GPIO, LPUART2, and SPI, enables the NVIC interrupt, and initializes the MRAM chip; Step 2: Mode selection; MCU reads the mode discrete pin level: if it is high, it enters debug mode and proceeds to step 3; if it is low, it enters master control mode and proceeds to step 6. Step 3: RS232 serial port command parsing: The MCU receives commands from the host computer via the RS232 serial port. If the command is 100, it enters the software programming mode and proceeds to Step 4; if the command is 210, it enters the fault data reading mode and proceeds to Step 5. Step 4: Software Programming; The MCU erases the main control software storage area in its internal FLASH memory, and receives data packets cyclically via the RS232 serial port. For each data packet, a CRC check is performed. If the check is successful, the data is written to the corresponding address in the FLASH memory, and a CRC check is performed again. If the second check is successful, the CRC check value is sent to the host computer via the RS232 serial port. If the current data packet is not the last data packet, the next data packet is received. If the CRC check fails, a failure code is sent to the host computer via the RS232 serial port, and the programming process is terminated. When all data packets have been received and the CRC check is successful, a programming success message is sent to the host computer via the RS232 serial port, and the process returns to Step 1. Step 5: MRAM fault data reading; The MCU reads the key operating data stored in the MRAM through the SPI interface and sends it to the host computer through the RS232 serial port. After the transmission is completed, return to Step 1. Step Six: Jump to the main control software; The MCU reads the stack pointer and reset vector at the starting address of the main control software, sets the main stack pointer and process stack pointer, redirects the interrupt vector table to the main control software area, and jumps to the main control software entry point through the function pointer; Step 7: Clock Configuration; The MCU initializes the external crystal oscillator and phase-locked loop sequentially, configures the core clock to 80MHz, the bus clock to 40MHz, and the Flash clock to 26.67MHz, and allocates clock sources to each peripheral module through the peripheral clock controller; Step 8: Configuration file parsing and dynamic port configuration; The MCU parses the pre-compiled binary configuration file, extracts input messages, output messages, signal mappings and hardware configuration information, and dynamically configures GPIO pin functions, matrix keyboard scanning parameters and communication interface enable based on the identified controller type information, so as to realize the standardization and generalization of the hardware platform design. Step Nine: Functional Module Initialization and Stack Overflow Monitoring Settings; The MCU performs the following initialization operations in sequence: a. Initialize the ADC module for RLS analog brightness acquisition; b. Initialize the LPSPI0 module to master mode and initialize the MRAM chip for critical data storage; c. Initialize the LPUART1 and LPUART2 modules, configure the baud rate to 115200, and enable transmit and receive interrupts; d. Initialize the LPIT0 module, set the timing period to 0.5ms, and enable channel 0 interrupt as the time base for system task scheduling; e. Initialize the FlexCAN0 and FlexCAN1 modules, configure the baud rate to 500kbps, allocate DMA channels for CAN0 and CAN1 respectively, and configure DMAMUX to realize automatic transmission of CAN received data. f. Initialize FTM0, FTM1, FTM2, and FTM3 modules, and configure the PWM output channel for brightness control of the backlight and indicator lights of the light guide panel; g. Fill the stack start area with a preset magic number to establish a stack overflow monitoring area for subsequent continuous self-check tasks to detect the stack; Step 10: Power status check; The MCU reads the reset status register and records the number of power-on cycles to MRAM; Step 11: Power-on self-test; The MCU performs a power-on self-test, including: watchdog test, position discreteness test, internal SRAM data bus test, internal FLASH function test, MRAM test, ARINC825-A channel loopback test, and ARINC825-B channel loopback test; If PBIT passes, the CAN module is switched to normal mode, and the self-test mode is switched from PBIT to periodic self-test, then proceed to Step 12; If PBIT fails, the system enters fault mode and proceeds to Step 15; Step 12: Task Registration and Scheduler Startup; The MCU adds periodic tasks to the task scheduler, including pilot input message sending, signal acquisition, equipment configuration information sending, equipment status information sending, continuous self-testing, etc.; The scheduler updates the task delay count based on the time base generated by the hardware timer and sets the task running flag when the delay reaches zero. Step 13: Main Loop; The MCU enters the main loop, starts interrupt-based task scheduling, iterates through and executes all tasks in sequence, and executes the corresponding function for tasks with the running flag set; Each cycle calls the watchdog feed function to reset the watchdog counter; Step Fourteen: Continuous Self-Test; The MCU periodically performs continuous self-tests, including: button test, knob test, software task frame overflow test, software stack overflow test, SEE error check, MBU error monitoring, ARINC825 input status monitoring, 28V input power supply voltage detection, trackball status monitoring, etc.; A fault verification mechanism is adopted, and a fault is confirmed after the number of faults reaches a threshold, and then proceed to Step Fifteen. Step 15: Fault Recording and Safety Handling; When a fault is detected during power-on self-test or continuous self-test, the MCU writes the fault code and fault count into the MRAM and reports the system status through the ARINC825 interface; For unrecoverable faults, the MCU enters stop mode and waits for the system to reset.

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