An LDO circuit that responds quickly to transient current surges

Abstract

The application relates to the technical field of integrated circuits, and discloses an LDO circuit capable of responding to a transient current mutation quickly, which comprises a differential error amplification module, an output feedback module, an overshoot suppression module, a dive suppression module and a compensation module, and constitutes a closed-loop voltage stabilization loop. The overshoot suppression module and the dive suppression module can be adapted to the conditions of sudden load current reduction and sudden load current increase respectively, bidirectionally suppress output voltage fluctuation, and improve the defects of transient overshoot and dive. In the application, the compensation Miller capacitor is set as an adjustable capacitor array, a working condition detection unit is used to identify the real-time working condition of the load, and a preset capacitor database is combined to adaptively adjust the compensation capacitance value and match the optimal loop compensation parameter. The application does not need an external large-capacity capacitor, effectively improves the transient response speed of load switching, and takes into account the loop stability and working condition adaptation capability in all working conditions.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to an LDO circuit that responds quickly to transient current surges. Background Technology

[0002] Low-dropout linear regulators (LDOs) are core functional modules in power management integrated circuits and are now widely used in various portable and automotive electronic devices, such as smartphones, IoT terminals, and in-vehicle autonomous driving control units. The transient response performance of the LDO output voltage is a key indicator for measuring the operational stability and overall reliability of the power system. Overshoot and undershoot phenomena in the output voltage caused by a step change in load current directly affect the power supply quality of downstream chips. Various high-precision, low-noise electronic systems impose strict constraints on the transient characteristics of LDOs.

[0003] With the rapid iteration of 5G mobile communication, artificial intelligence computing, and IoT terminal industries, the dynamic switching conditions of internal loads in various electronic devices are becoming increasingly complex. Scenarios such as instantaneous high-load computing of the central processing unit, flash memory read / write start / stop, and time-division switching of RF transceiver modules will generate drastic dynamic load jumps. Existing commercial LDOs struggle to simultaneously achieve multiple design specifications such as fast transient response, symmetrical response under light and heavy loads, integration without external capacitors, and low static power consumption. Conventional transient enhancement circuits often sacrifice loop phase margin, while architectures without external capacitors require additional compensation branches, which increases the circuit's static power consumption.

[0004] Existing LDO architectures are prone to large output voltage fluctuations when dealing with sudden changes in load current due to feedback loop propagation delays and limitations in the compensation network topology. Furthermore, voltage recovery is time-consuming, which can severely impact the operation of downstream load chips or even cause malfunctions. Current LDOs generally employ a single feedback loop architecture, which inherently limits the loop's DC gain and effective bandwidth. This results in significant lag in the regulation of the power regulator's gate drive voltage during load transients, leading to a prolonged output voltage recovery period. Summary of the Invention

[0005] To improve the response speed of LDO to transient currents, this application provides an LDO circuit that responds quickly to transient current changes, employing the following technical solution:

[0006] An LDO circuit that responds quickly to transient current surges includes a differential error amplification module, an output feedback module, an overshoot suppression module, a dive suppression module, and a compensation module.

[0007] The differential error amplification module includes a first NMOS transistor, a second NMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth PMOS transistor, and an eleventh NMOS transistor. The gate of the second NMOS transistor is connected to a reference voltage VREF, and the gate of the first NMOS transistor is connected to a feedback voltage VFB. The sources of the first and second NMOS transistors are both connected to the drain of the ninth NMOS transistor. The gate of the ninth NMOS transistor is connected to a bias voltage vb1, and the source of the ninth NMOS transistor is grounded. The gate and drain of the third PMOS transistor are shorted, and the gates of the third, fifth, and tenth PMOS transistors are all connected to the drain of the first NMOS transistor. The fourth PMOS transistor... The gates and drains are shorted; the gates of the fourth and sixth PMOS transistors are both connected to the drain of the second NMOS transistor; the sources of the third, fourth, fifth, and tenth PMOS transistors are all connected to the power supply VDDA; the drain of the sixth PMOS transistor is connected to the drain of the eighth NMOS transistor; the drains of the fifth and seventh NMOS transistors are both connected to the gate of the fourteenth NMOS transistor; the drains of the tenth and eleventh NMOS transistors are both connected to one end of the third resistor; the sources of the seventh, eighth, and eleventh NMOS transistors are all grounded; the gates of the seventh, eighth, eleventh, and seventeenth PMOS transistors are all connected to one end of the third capacitor; the gate and drain of the eighth NMOS transistor are connected.

[0008] The output feedback module includes a twelfth PMOS transistor, a first resistor, and a second resistor. The source of the twelfth PMOS transistor is connected to the power supply VDDA, and the gate of the twelfth PMOS transistor is connected to the drain of the tenth PMOS transistor. The drain of the twelfth PMOS transistor serves as the circuit output terminal VOUT. VOUT is connected to one end of the first resistor, one end of the first capacitor, and one end of the second capacitor. The other end of the first resistor is connected to one end of the second resistor to form a voltage divider feedback node. The voltage divider feedback node is connected to the gate of the second NMOS transistor, and the other end of the second resistor is grounded. The other end of the first capacitor is connected to the other end of the third resistor.

[0009] The overshoot suppression module includes a fourteenth NMOS transistor, a fifteenth NMOS transistor, a seventeenth PMOS transistor, a second capacitor, a third capacitor, and a fourth resistor. The source of the seventeenth PMOS transistor is connected to one end of the power supply VDDA, the drain of the seventeenth PMOS transistor is connected to one end of the third capacitor, the other end of the third capacitor is connected to the gate of the seventeenth PMOS transistor, and the gate of the seventeenth PMOS transistor is connected to the gate of the eleventh NMOS transistor. One end of the fourth resistor is connected to the bias voltage vb2, and the other end of the fourth resistor and one end of the second capacitor are both connected to the gate of the fifteenth NMOS transistor. The drain of the fifteenth NMOS transistor is connected to the source of the fourteenth NMOS transistor, and the drain of the fourteenth NMOS transistor and the other end of the second capacitor are both connected to VOUT. The sources of the fifteenth NMOS transistor and the thirteenth NMOS transistor are both grounded.

[0010] The dive suppression module includes a sixteenth PMOS transistor, a third capacitor, and a third resistor; the source of the sixteenth PMOS transistor is connected to the power supply VDDA, the gate of the sixteenth PMOS transistor is connected to the drain of the tenth PMOS transistor, and the drain of the sixteenth PMOS transistor is connected to the other end of the third capacitor.

[0011] The compensation module includes a first capacitor, one end of which is connected to VOUT, and the other end of which is connected to the end of a third resistor away from the drain of the eleventh NMOS transistor.

[0012] By adopting the above technical solution, independent overshoot suppression modules and undershoot suppression modules are set up to correspond to the conditions of decreasing and increasing transient current of the load, respectively. Together with the differential error amplification module, Miller structure compensation module and voltage divider output feedback module, a closed-loop voltage regulation loop is formed. The transient detection and acceleration path is built by relying on on-chip capacitors and resistors. The output voltage can be quickly adjusted when the load changes suddenly without the need for external large-capacity external capacitors. The transient response characteristics of light and heavy load switching are symmetrical. At the same time, the suppression branch does not work in steady state. While improving the transient response speed and suppressing the overshoot and undershoot of the output voltage, the loop stability and low static power consumption are also taken into account.

[0013] Optionally, the first compensation circuit is configured with an adjustable capacitor array. Based on a preset operating condition detection unit, it collects the current and voltage signals of the load in real time, performs calculations based on the current and voltage signals to generate operating condition characterization information, identifies the current operating condition type of the circuit based on the operating condition characterization information, obtains a pre-stored operating condition capacitor database containing compensation capacitance values ​​corresponding to each operating condition type, retrieves the matching target capacitance value from the operating condition capacitor database according to the identified operating condition type, and switches the conduction level of the adjustable capacitor array so that the equivalent capacitance value of the first capacitor is adjusted to the target capacitance value.

[0014] By adopting the above technical solution, the first compensation circuit adds an adjustable capacitor array. Based on the load current and voltage signals collected in real time by the operating condition detection unit, the operating condition characterization information is obtained to distinguish different operating conditions. Then, the operating condition capacitor database corresponding to the compensation capacitance value of each operating condition is retrieved to match the target capacitance value. The adjustable capacitor array is switched to dynamically adjust the equivalent capacitance value of the first capacitor. The total capacitance value of the compensation capacitor can be flexibly changed according to the actual load conditions of the circuit. When the equivalent capacitance value of the capacitor increases, the loop stability is improved, the circuit bandwidth is reduced, and the transient voltage spikes are reduced, so as to realize the adaptive matching of compensation parameters under different load conditions.

[0015] Optionally, the adjustable capacitor array is configured as an adjustable parallel capacitor matrix, which includes multiple parallel capacitor branches. Each capacitor branch contains a fixed compensating sub-capacitor and a switching transistor. The control terminal of each branch's switching transistor is connected to the range control signal output from the operating condition capacitor database. One end of all capacitor branches is connected to form a matrix input terminal, which is connected to the output terminal of the differential error amplifier module. The other end of all capacitor branches is connected to form a matrix output terminal, which is connected to the circuit output terminal VOUT. Each branch's switching transistor is turned on or off according to the range control signal, connecting or disconnecting the corresponding fixed compensating sub-capacitor, thereby changing the overall equivalent capacitance value of the adjustable capacitor array.

[0016] By adopting the above technical solution, an adjustable parallel capacitor matrix composed of multiple switching transistors and fixed sub-capacitors is used as an adjustable capacitor array. By controlling the on and off of each switching transistor to flexibly switch different sub-capacitors, the equivalent total capacitance value of the compensation network can be accurately changed. The optimal compensation parameters can be matched for different circuit conditions such as light load and heavy load. When the capacitance value is increased, the loop phase margin can be improved, the system stability can be enhanced, transient voltage spikes can be suppressed, and the loop bandwidth can be reduced, so as to achieve adaptive loop compensation across the entire load range.

[0017] Optionally, the second capacitor in the overshoot suppression module is configured as an adjustable capacitor array; the operating condition detection unit is used to collect the load current signal and output voltage signal at the LDO output terminal in real time, perform logical operations on the collected load current signal and output voltage signal to generate operating condition discrimination feature quantities, and distinguish the current operating condition of the circuit based on the operating condition discrimination feature quantities; the capacitor matching storage unit pre-stores the target capacitance values ​​of the second capacitor corresponding to various operating conditions; the operating condition detection unit outputs an operating condition identification signal to the adjustable capacitor array, and the adjustable capacitor array responds to the operating condition identification signal by switching the conduction level, adjusting the equivalent capacitance value of the second capacitor to the target capacitance value that matches the current operating condition.

[0018] By adopting the above technical solution, the second capacitor of the overshoot suppression module is set as an adjustable capacitor array. In conjunction with the operating condition detection unit, the output load current and voltage signals are collected in real time and the operating condition discrimination feature quantity is generated to identify the current operating condition. Then, the target capacitance value of the second capacitor under the corresponding operating condition is retrieved through the capacitor matching storage unit. The operating condition identification signal controls the adjustable capacitor array to switch the range and adaptively change the equivalent capacitance value of the second capacitor. This can match the optimal transient detection coupling capacitance value for different load operating conditions and optimize the transient response speed and voltage overshoot suppression capability of the overshoot suppression branch.

[0019] Optionally, the third resistor in the dive suppression module is an adjustable resistor. The operating condition detection unit is used to collect the load current signal and output voltage signal of the LDO output terminal in real time, and can also collect the chip temperature signal. The collected signals are processed to generate operating condition discrimination feature quantities, and the current operating condition of the circuit is identified based on the operating condition discrimination feature quantities. The target resistance value of the third resistor corresponding to each operating condition is pre-stored in the resistance value matching storage unit. The operating condition detection unit outputs the operating condition identification signal to the third resistor. The third resistor responds to the operating condition identification signal to switch the conduction level and adjust its own equivalent resistance value to the target resistance value matching the current operating condition.

[0020] By adopting the above technical solution, the real-time operating conditions of the circuit are identified based on the load current, output voltage and chip temperature signals collected by the operating condition detection unit. Combined with the resistance matching storage unit that pre-stores the resistance values ​​corresponding to multiple operating conditions, the equivalent resistance value of the third resistor is automatically switched to adapt to the current working state. This can dynamically adjust the RC time constant and positive feedback strength of the voltage dip suppression branch, and balance the voltage dip suppression speed and loop stability under different operating conditions such as sudden load increase, light load steady state, high and low temperature.

[0021] Optionally, the fourth resistor in the overshoot suppression module is an adjustable resistor. The operating condition detection unit is used to collect the load current signal, output voltage signal, and chip temperature signal at the LDO output terminal in real time. It calculates and generates operating condition discrimination features from the collected signals and identifies the current operating condition of the circuit based on these features. The resistance matching storage unit pre-stores target resistance values ​​for the fourth resistor corresponding to various operating conditions. The operating condition detection unit outputs an operating condition identification signal to the fourth resistor, and the fourth resistor responds to the signal by switching its conduction level, adjusting its equivalent resistance to the target resistance value that matches the current operating condition.

[0022] By adopting the above technical solution, the circuit operation signal is collected from multiple dimensions by the working condition detection unit to determine the working condition. The fourth resistor of the overshoot suppression module is dynamically adjusted by retrieving the matching resistance value in the resistance matching storage unit. The response rate of the transient coupling RC path is flexibly changed, which accelerates overshoot suppression under heavy load sudden drop transient and reduces the static power consumption of the branch under light load steady state.

[0023] Optionally, the adjustable resistor is an adjustable parallel resistor matrix; the adjustable parallel resistor matrix contains multiple parallel resistor branches, each resistor branch consisting of a fixed resistor unit connected in series with a control switch; one end of all resistor branches is connected to form the first port of the matrix, and the other end of all resistor branches is connected to form the second port of the matrix; each control switch receives a gear control signal and is controlled to turn on or off. Turning on the corresponding resistor branch adds the fixed resistor unit of that branch to the matrix, and turning off the corresponding resistor branch removes the fixed resistor unit of that branch. By switching different numbers of resistor branches, the equivalent total resistance of the adjustable resistor is changed.

[0024] By adopting the above technical solution, an adjustable parallel resistor matrix is ​​formed by connecting multiple resistor branches in parallel and using independent control switches. By switching the parallel branches to connect or disconnect the resistor units, the equivalent resistance value can be coarsely adjusted over a wide range. The resistance value adjustment range is wide and the range switching response is rapid.

[0025] Optionally, the adjustable resistor is an adjustable series resistor matrix; the adjustable series resistor matrix is ​​composed of multiple groups of fixed resistor units connected in series end to end, and each group of fixed resistor units has a bypass control switch connected in parallel at both ends; the first end of all series resistor units is the first port of the matrix, and the last end is the second port of the matrix; each bypass control switch receives a gear control signal and is controlled to be turned on or off. When the bypass control switch is on, the corresponding fixed resistor unit is short-circuited; when the bypass control switch is off, the corresponding fixed resistor unit is connected to the circuit. The equivalent total resistance of the adjustable resistor is adjusted by bypassing different resistor units.

[0026] By adopting the above technical solution, a series resistor matrix structure with fixed resistor units connected in series and bypass switches connected in parallel for each unit is used. By relying on the precise switching / bypassing of a single group of resistors by the bypass switches, small resistance values ​​can be finely adjusted with high adjustment resolution. This allows for fine calibration of the overshoot and dive suppression branch impedance.

[0027] Optionally, the LDO circuit further includes a response speed evaluation unit; the response speed evaluation unit is used to calculate the transient response speed of the circuit in real time and compare the calculated response speed with a preset standard speed threshold; when it is determined that the current response speed does not meet the preset requirements, the response speed evaluation unit outputs a shutdown control signal to control all control switches of the adjustable capacitor array, the adjustable parallel resistor matrix, and the adjustable series resistor matrix to be turned off, and to disconnect all adjustable branches.

[0028] By adopting the above technical solution, a response speed evaluation unit is added to measure the transient response speed of the circuit in real time. Once the response performance fails to meet the standard, a control signal can be output to cut off all adjustable branches, eliminate the influence of additional branches caused by adjustable capacitors and adjustable resistors, and allow the circuit to return to the basic fixed parameter working mode.

[0029] Optionally, the threshold adjustment storage unit is also connected to the operating condition detection unit; the operating condition detection unit outputs operating condition parameters such as chip temperature, steady-state load current, output voltage level, and load current change slope to the threshold adjustment storage unit; the threshold adjustment storage unit pre-stores the mapping relationship between each operating condition parameter and the response speed judgment threshold, and adaptively updates the judgment threshold of the response speed evaluation unit according to the real-time operating condition parameters; wherein the response speed judgment threshold increases positively with the increase of steady-state load current, output voltage level, and load current change slope, and decreases negatively with the increase of chip temperature.

[0030] By adopting the above technical solution, the response speed judgment threshold is adaptively adjusted based on the multi-dimensional operating parameters collected by the operating condition detection unit. The threshold is established with the key operating condition parameters in a positive and negative matching relationship. The judgment criteria are automatically relaxed in scenarios with low transient requirements such as high temperature and light load, while the judgment criteria are automatically tightened in scenarios with heavy load, high output voltage, and large current jump. The threshold judgment rules are in line with the actual operating characteristics of the circuit, reducing unnecessary adjustable branch shutdown operations.

[0031] In summary, this application includes at least one of the following beneficial technical effects: This application independently configures overshoot suppression and dive suppression modules to adapt to transient conditions of sudden drops and increases in load current, respectively. Combined with differential amplification, feedback, and Miller compensation modules, it forms a voltage regulation closed loop, achieving symmetrical and excellent transient response without the need for external large-capacity capacitors, while maintaining low static power consumption and loop stability. Simultaneously, this application configures the compensation capacitor, overshoot suppression capacitor, and the resistors of the dive and overshoot suppression branches as adjustable capacitor matrices and adjustable resistor matrices, respectively. Relying on the operating condition detection unit to identify the operating condition using current, voltage, and temperature signals, it retrieves pre-stored parameters to adaptively adjust the capacitance and resistance values, achieving dynamic matching of parameters across all operating conditions and optimizing transient suppression and loop compensation performance. Furthermore, this application adds a response speed evaluation mechanism, which can disconnect the adjustable branch when circuit performance is substandard, and can adaptively adjust the evaluation threshold based on operating condition parameters, effectively avoiding parameter mismatch problems and significantly improving the voltage regulation reliability and adaptability of the LDO circuit under all temperature ranges and load conditions. Attached Figure Description

[0032] Figure 1 This is a system framework diagram of a fast transient response LDO circuit according to the present invention.

[0033] Figure 2 This is a complete transistor-level schematic diagram of the differential error amplifier, push-pull driver stage, and overshoot suppression circuit of this invention.

[0034] Figure 3 This is a schematic diagram illustrating the independent refinement principle of the overshoot suppression structure of this invention. Detailed Implementation

[0035] The embodiments of this application are described in detail below, and examples of the embodiments are shown in the accompanying drawings.

[0036] This embodiment provides a fast transient response LDO circuit to address the shortcomings of traditional LDOs, such as large output voltage fluctuations, long recovery times, asymmetrical transient responses under light and heavy loads, reliance on large-capacity off-chip capacitors, and high steady-state power consumption during rapid load switching. The overall circuit architecture is as follows: Figure 1 As shown, the main circuit consists of five core functional units: the first differential error amplification module, the output feedback module, the overshoot suppression module, the dive suppression module, and the compensation module; the circuit is externally equipped with a first load resistor RL and a first load capacitor CL to simulate the dynamic load conditions of the back end.

[0037] Reference Figure 2 The first differential error amplifier module includes a first NMOS transistor M1, a second NMOS transistor M2, a third PMOS transistor M3, a fourth PMOS transistor M4, a fifth PMOS transistor M5, a sixth PMOS transistor M6, a seventh NMOS transistor M7, an eighth NMOS transistor M8, a ninth NMOS transistor M9, a tenth PMOS transistor M10, and an eleventh NMOS transistor M11, which provide differential amplification and two-stage push-pull drive output functions for the circuit.

[0038] Differential input tail current source: The ninth NMOS transistor M9 is the constant tail current source of the differential pair. The gate of M9 is connected to a fixed bias voltage vb1, the source of M9 is grounded, and the drain of M9 is connected to the source of the first NMOS transistor M1 and the source of the second NMOS transistor M2, providing a stable bias current for the differential input pair composed of M1 and M2.

[0039] Differential input pair: The gate of the second NMOS transistor M2 is connected to the system reference voltage VREF, serving as the positive input terminal of the differential amplifier; the gate of the first NMOS transistor M1 is connected to the feedback voltage VFB, serving as the negative input terminal of the differential amplifier, used to compare the reference voltage with the output voltage divider feedback voltage to generate an error signal.

[0040] The first stage of active load: The gate and drain of the third PMOS transistor M3 are shorted to form a diode connection structure. The gates of M3, M5, and M10 are all connected to the drain of the first NMOS transistor M1. The gate and drain of the fourth PMOS transistor M4 are shorted. The gates of M4 and M6 are all connected to the drain of the second NMOS transistor M2. The sources of all four PMOS transistors M3, M4, M5, and M10 are connected to the power supply VDDA, providing an active load for the differential input stage and improving the low-frequency gain of the amplifier.

[0041] The first secondary push-pull drive branch (driving overshoot suppression module): The drain of the sixth PMOS transistor M6 is interconnected with the drain of the eighth NMOS transistor M8; the drains of the fifth PMOS transistor M5 and the seventh NMOS transistor M7 are connected to the gate of the fourteenth NMOS transistor M14, serving as the control drive signal for the overshoot suppression module. The sources of the seventh NMOS transistor M7 and the eighth NMOS transistor M8 are grounded, and the gates of M7, M8, the eleventh NMOS transistor M11, and the drain of the seventeenth PMOS transistor M17 are all connected to one end of the third capacitor C3; the gate and drain of the eighth NMOS transistor M8 are interconnected.

[0042] The second-stage push-pull drive branch (driving the power transistors and the dive suppression module): The drains of the tenth PMOS transistor M10 and the eleventh NMOS transistor M11 are connected to one end of the third resistor R3. This node serves as the total output of the differential error amplifier module, synchronously outputting to the gates of the twelfth PMOS transistor M12 and the sixteenth PMOS transistor M16, thus achieving synchronous driving of the power adjustment transistor and the dive suppression circuit. The source of the eleventh NMOS transistor M11 is grounded, forming a push-pull structure with the tenth PMOS transistor M10 to quickly adjust the gate potential of the power transistor.

[0043] Reference Figure 1 and Figure 2 The output feedback module includes a twelfth PMOS transistor M12, a first resistor R1, and a second resistor R2 to realize power regulated output and output voltage divider sampling feedback.

[0044] Power regulation transistor: The twelfth PMOS transistor M12 is the main power transistor of this LDO. The source of M12 is connected to the power supply VDDA, and the gate of M12 receives the error control voltage output by the differential error amplifier module. The drain of M12 leads to the total output terminal VOUT of the circuit. The potential of VOUT is stabilized by adjusting the on-resistance of M12.

[0045] Voltage divider feedback branch: The output terminal VOUT is simultaneously connected to one end of the first capacitor C1, one end of the second capacitor C2, and the upper end of the first resistor R1; the lower end of the first resistor R1 is connected to the upper end of the second resistor R2 to form a voltage divider feedback node, and the output feedback voltage VFB of the voltage divider node is connected to the gate of the first NMOS transistor M1; the lower end of the second resistor R2 is grounded. Through voltage division by resistors R1 and R2, VOUT is proportionally reduced to VFB and sent back to the input of the differential amplifier, forming a complete negative feedback closed loop.

[0046] Ignoring amplifier offset in steady state, the output voltage satisfies the formula: ;

[0047] External load: The first load resistor RL and the first load capacitor CL are connected in parallel to ground at the output terminal VOUT to simulate dynamic loads such as CPU, RF, and memory chips, and to reproduce transient conditions of sudden increase and decrease in load current.

[0048] Reference Figure 2 and Figure 3 The overshoot suppression module is used to deal with the overshoot caused by a sudden decrease in load current and a rise in VOUT voltage. It includes the fourteenth NMOS transistor M14, the fifteenth NMOS transistor M15, the seventeenth PMOS transistor M17, the second capacitor C2, the third capacitor C3, and the fourth resistor R4.

[0049] Bias and transient detection branch: One end of the fourth resistor R4 is connected to a fixed bias voltage vb2, and the other end of R4 is interconnected with one end of the second capacitor C2 and the gate of the fifteenth NMOS transistor M15; the other end of the second capacitor C2 and the drain of the fourteenth NMOS transistor M14 are connected to the output terminal VOUT. C2 acts as an AC coupling capacitor to capture the transient rise signal of VOUT.

[0050] The drain of the fifteenth NMOS transistor M15 is connected to the source of the fourteenth NMOS transistor M14, and the source of the fifteenth NMOS transistor M15 is grounded. The gate of M14 receives the pre-drive signal output from the differential amplifier. When the load suddenly drops and VOUT rises instantaneously, the second capacitor C2 couples a positive jump voltage to the gate of M15, causing M15 to quickly turn on. Together with M14, it forms a current-to-ground leakage path, quickly dissipating excess charge at the VOUT node and lowering the drain potential of M14, accelerating its turn-off and reducing redundant current injected into the output. This dual action suppresses the output voltage overshoot amplitude and shortens the transient recovery time. When the load suddenly increases and VOUT drops instantaneously, C2 couples a negative jump signal to the gate of M15, causing the gate potential of M15 to drop synchronously and significantly weakening its conduction. The drain potential of M14 rises again, and M14 remains normally on to supplement the output current, effectively suppressing the output voltage dip. Under steady-state conditions, VOUT has no AC jump, the potential across C2 remains constant, the gate potential of M15 is fixed by R4, the branches of M14 and M15 are almost off, there is no additional static power consumption, and it will not interfere with the original DC operating point and steady-state stability of the loop.

[0051] Coupled energy storage branch: The source of the seventeenth PMOS transistor M17 is connected to the power supply VDDA, and the drain of M17 is connected to the other end of the third capacitor C3. C3 is connected across the differential amplifier's second-stage drive node and the overshoot suppression circuit to achieve signal linkage coupling between the overshoot and overshoot suppression circuits.

[0052] Under steady-state conditions, VOUT has no AC jump, the potential across the second capacitor C2 is stable, the gate potential of the fifteenth NMOS transistor M15 is fixed by vb2 through R4, the branches of M14 and M15 are almost off, there is no additional static power consumption, and it does not affect the steady-state operating point of the loop.

[0053] Reference Figure 2 and Figure 3The undershoot suppression module is used to handle situations where the load current suddenly increases and the VOUT voltage drops, causing an undershoot. It includes the sixteenth PMOS transistor M16, the third capacitor C3, and the third resistor R3. The source of the sixteenth PMOS transistor M16 is connected to the power supply VDDA, the gate of M16 is connected to the end of the third resistor R3 away from the differential amplifier, and the drain of M16 is connected to the other end of the third capacitor C3. The third resistor R3 is connected in series between the output node of the differential amplifier and the gate of M16. R3 and C3 form an RC transient signal path. Working principle: When the load current increases sharply, VOUT drops rapidly. Loop feedback pulls down the output node potential of the differential amplifier synchronously, pulling down the gate potential of the sixteenth PMOS transistor M16, which then quickly turns on. The power supply VDDA rapidly charges the third capacitor C3 through the conducting M16. C3 couples the potential jump signal to the gate of the eleventh NMOS transistor M11, accelerating the conduction of M11 and pulling down the gate potential of the power transistor M12, forming a positive feedback mechanism. This rapidly increases the output drive current of M12, suppressing the output voltage dip. When the circuit is in a voltage overshoot condition, the second capacitor C2 couples a high potential to the gate of M15. M14 and M15 turn on, clamping the gate potential of M16. The dip suppression circuit automatically turns off, avoiding mutual interference between the two suppression circuits.

[0054] Reference Figure 1 and Figure 2 The compensation module adopts a Miller compensation architecture and only includes a first capacitor C1. One end of the first capacitor C1 is connected to the output terminal VOUT, and the other end is connected to the other end of the third resistor R3. The second stage of the differential amplifier has a high output impedance, which will introduce a low-frequency pole within the loop bandwidth, easily causing loop oscillation. This embodiment utilizes the multiplication effect of the Miller capacitor C1 to shift the dominant pole to a lower frequency and the secondary pole to a higher frequency, improving the loop phase margin and ensuring loop stability under both light and heavy load conditions. At the same time, this structure does not require a large-capacity external compensation capacitor, which is beneficial for chip miniaturization and integration.

[0055] In this embodiment, all transistors are uniformly labeled with their transistor numbers, and resistors and capacitors are labeled with their corresponding numbers (such as first resistor R1 and first capacitor C1). The sources of all PMOS transistors are uniformly connected to the power supply voltage VDDA, and the sources of all NMOS transistors are uniformly grounded.

[0056] The overall steady-state operation of the circuit is as follows: When the load current is stable without any jumps, the output voltage VOUT is divided by R1 and R2 to obtain VFB. The differential amplifier compares VREF with VFB and outputs a stable control voltage to the gate of M12, maintaining VOUT constant. At this time, there are no AC voltage jumps across C2 and C3, and the overshoot suppression and dive suppression transistors are both in the off state. Only the differential amplifier has a very small quiescent current, resulting in low overall circuit power consumption. The low-frequency gain expression for the differential amplifier is: In the formula For differential input to transconductance, The equivalent impedance of the first-stage load. , , These represent the output impedances of the corresponding transistors, and the high-gain characteristics ensure the accuracy of output voltage regulation.

[0057] Load current sudden drop (voltage overshoot condition): The load current decreases instantaneously, and VOUT rises instantaneously; the second capacitor C2 couples the positive voltage to the gate of M15, and M14 and M15 quickly turn on, draining current to ground at the VOUT node, quickly consuming excess charge and suppressing voltage overshoot; at the same time, the overshoot suppression circuit is synchronously turned off, there is no reverse interference, and the output voltage quickly drops back to the rated value.

[0058] Sudden increase in load current (voltage dip condition): The load current increases instantaneously, and VOUT drops momentarily; the output potential of the differential amplifier is pulled down, the sixteenth PMOS transistor M16 is turned on, and together with the third capacitor C3, a positive feedback is formed to accelerate the pull-down of the gate potential of M12. The conduction level of M12 increases rapidly, the output current increases, and the dropped VOUT is quickly raised, shortening the voltage dip recovery time.

[0059] In other embodiments, the first capacitor C1 of the compensation module can be adaptively adjustable. By adding a working condition detection unit, a working condition capacitor database, and an adjustable parallel capacitor matrix, the equivalent capacitance value of the Miller compensation capacitor can be dynamically adjusted in real time according to the working condition of the circuit. This solves the technical contradiction that traditional fixed Miller compensation capacitors cannot simultaneously take into account the loop stability and transient response speed in multiple scenarios such as light load, heavy load, load transient jump, and high and low temperature. The following section fully describes this solution in conjunction with the circuit structure, signal interaction logic, and hardware topology.

[0060] This improved scheme adds three types of collaborative working units: a working condition detection unit, a working condition capacitor database, and an adjustable parallel capacitor matrix (i.e., an adjustable capacitor array). These three units are electrically interconnected with the original LDO main circuit, the output terminal VOUT, and the output terminal of the differential error amplifier module. The complete adaptive control logic is as follows: The working condition detection unit samples the load electrical signal in real time and calculates and identifies the working condition → the working condition capacitor database matches the optimal compensation capacitance value for the corresponding working condition → the output range control signal drives the switching branch of the internal switching transistor of the adjustable parallel capacitor matrix, and modifies the overall equivalent capacitance value of the first capacitor C1 in real time, dynamically optimizing the loop phase margin and transient response performance.

[0061] The operating condition detection unit is an on-chip integrated analog sampling and digital processing composite circuit with two independent sampling channels, capable of continuously acquiring the load current signal at the LDO output terminal VOUT in real time. With output voltage signal The specific signal processing steps are as follows:

[0062] Synchronous signal acquisition: The operating condition detection unit has a built-in on-chip current sampling resistor and voltage divider sampling branch. The sampling resistor is connected in series between the power transistor M12 and the output terminal VOUT to acquire the instantaneous load current. The voltage sampling branch is directly connected in parallel with VOUT and ground to collect the real-time output voltage. The sampling period is set to 100ns to meet the real-time capture requirements in high-speed load transient scenarios.

[0063] The unit's internal digital computing module performs differential, mean, and slope calculations on multiple sets of current and voltage raw signals to generate multi-dimensional operating condition characterization information. The characterization information includes four core parameters: (1) steady-state average load current. Used to distinguish between light-load steady-state and heavy-load steady-state operating conditions; sets the current threshold. , , Determined to be lightly loaded, (2) The load current change slope is determined to be heavy load; Used to identify transient jump conditions, when The load is determined to be in a high-speed step switching condition; (3) the steady-state amplitude of the output voltage : Used to identify multi-level output voltage regulation conditions; (4) Peak-to-peak voltage fluctuation This helps determine the intensity of transient disturbances in the current loop. The combination of the above multi-dimensional parameters constitutes complete operating condition characterization information, uniquely corresponding to a type of circuit operating condition.

[0064] Operating condition type identification output:

[0065] The operating condition detection unit has preset operating condition judgment logic thresholds. It compares the operating condition characterization information with the built-in thresholds to complete the operating condition classification and identification, and outputs a unique operating condition identification code to the operating condition capacitance database. This solution divides five typical operating conditions: light load steady-state operating condition, heavy load steady-state operating condition, load surge transient operating condition, load drop transient operating condition, and multi-level high voltage output steady-state operating condition. Each type of operating condition is independently assigned a unique identification code.

[0066] The operating condition capacitance database is an on-chip non-volatile storage unit. Data is written to it through simulation and actual measurement calibration before leaving the factory. The database establishes a one-to-one mapping data table between operating condition identification code and target compensation capacitance value. It pre-stores the optimal first capacitor C1 target equivalent capacitance value for all operating condition types. The data calibration rules meet the circuit stability design requirements.

[0067] Light load steady-state condition: High loop gain, prone to high frequency oscillation, match large capacitance target capacitor, the equivalent total capacitance is set to 8pF to increase Miller compensation strength and improve phase margin;

[0068] Heavy load steady-state conditions: low load equivalent impedance, loop poles shift to high frequency, matched with medium capacitance of 4pF, to balance bandwidth and stability.

[0069] Transient conditions with sudden load increases / decreases: Prioritize ensuring transient response speed, match a small capacitance value of 1pF, widen the loop bandwidth, and shorten the voltage recovery time;

[0070] High voltage output steady-state operation: The loop DC gain is improved, and a medium-to-large capacitance of 6pF is matched to suppress small steady-state voltage fluctuations.

[0071] When the operating condition capacitor database receives the operating condition identification code transmitted by the operating condition detection unit, it automatically retrieves the mapping data table, retrieves the target capacitance value corresponding to the code, and synchronously converts it into multiple binary range control signals, which are then output in parallel to the control terminals of all switching transistors inside the adjustable parallel capacitor matrix.

[0072] In this scheme, the adjustable capacitor array of the first compensation circuit adopts a multi-parallel capacitor matrix topology to replace the original single fixed first capacitor C1. The two ends of the matrix are respectively connected to the output terminal of the differential error amplifier module and the output terminal VOUT of the circuit. The complete topology is as follows:

[0073] The adjustable parallel capacitor matrix contains N parallel capacitor branches. In this embodiment, N=4 branches are preferred to cover four target capacitance values: 1pF, 4pF, 6pF, and 8pF. Each capacitor branch consists of one fixed compensation sub-capacitor connected in series with one MOS switch. The capacitance values ​​of the four fixed sub-capacitors are set as follows: C11=1pF, C12=3pF, C13=2pF, and C14=2pF. By combining different branch switching, multiple equivalent total capacitance values ​​of 1pF, 3pF, 4pF, 6pF, and 8pF can be obtained, perfectly matching all preset target compensation capacitance values ​​in the operating condition capacitance database. All capacitor branches converge on the same side to form a matrix input terminal; the matrix input terminal is electrically connected to the output terminal of the differential error amplifier module (gate node of the twelfth PMOS transistor M12); the other side of all capacitor branches converge to form a matrix output terminal; the matrix output terminal is electrically connected to the circuit output terminal VOUT; the original single Miller compensation capacitor C1 is completely replaced by this parallel capacitor matrix to realize the integrated adjustable design of the compensation network. The gate of the MOS switch in series in each branch is used as the control terminal, and all control terminals are connected in parallel to the gear control signal output by the working condition capacitor database; the gear control signal is a high and low level digital signal: (1) High level: the switch is turned on, the fixed compensation sub-capacitor of the corresponding branch is connected to the matrix circuit and participates in the equivalent capacitance value superposition; (2) Low level: the switch is turned off, the sub-capacitor of the corresponding branch is disconnected from the main circuit and does not participate in the capacitance value calculation.

[0074] The complete adaptive adjustment process is as follows:

[0075] Steady-state operating condition sampling and identification: The circuit operates stably under light load for an extended period of time, and the operating condition detection unit collects the average load current. When the current change slope is close to 0, the identification code is transmitted to the working condition capacitance database, the target capacitance value of 8pF is retrieved, and the corresponding gear control signal is output to conduct all four branches of C11, C12, C13, and C14. The matrix equivalent total capacitance value is superimposed to 8pF, which strengthens Miller compensation and improves the stability of the light load loop.

[0076] Transient load change condition: The load current rises and falls sharply in an instant. The condition detection unit detects that the slope of the current change exceeds the threshold and identifies it as a transient condition. The target capacitance value of 1pF is retrieved, and only the C11 branch is turned on while all other branch switches are turned off. The matrix equivalent capacitance value is reduced to 1pF, which widens the loop bandwidth, accelerates the gate regulation speed of the power transistor, and reduces the overshoot and undershoot of the output voltage.

[0077] Heavy load steady-state condition: average load current is greater than 50mA, database matching target capacitance of 4pF, C11 and C12 branches are turned on, equivalent capacitance of 4pF, taking into account both loop stability and transient response speed.

[0078] During dynamic switching of operating conditions, the operating condition detection unit updates the operating condition code in real time, the operating condition capacitance database is refreshed synchronously with the gear control signal, the switching transistor quickly switches between on and off states, and the matrix equivalent capacitance value follows the operating condition to complete adaptive adjustment without delay. No external intervention is required throughout the process, achieving automatic optimal loop compensation across the entire load range.

[0079] Traditional fixed Miller compensation capacitors can only adapt to a single operating condition, exhibiting oscillations under light loads and slow transient recovery under heavy loads. This implementation uses a condition detection unit to sense the circuit load status in real time, matching the optimal compensation capacitance value based on a pre-calibrated condition capacitance database. A parallel capacitor matrix topology allows for flexible switching of capacitors, achieving a wide range of continuously adjustable equivalent capacitance values. Under light load conditions, the compensation capacitance value is automatically increased to improve loop phase margin; under transient load changes, the capacitance value is automatically decreased to widen loop bandwidth, balancing steady-state stability and transient response speed. The parallel capacitor matrix topology is simple, has fast switching speed, and is easy to integrate on-chip, requiring no external compensation components. It adapts to the needs of miniaturized LDO designs without external capacitors, significantly expanding the circuit's applicable load and temperature range.

[0080] In other embodiments, the present invention also includes another adaptive optimization implementation method, which dynamically adapts and improves the transient detection coupling parameters of the overshoot suppression module. Specifically, the second capacitor C2 in the overshoot suppression module is configured as an adjustable capacitor array structure, replacing the traditional fixed-value capacitor. Relying on the on-chip integrated operating condition detection unit and capacitor matching storage unit to form a closed-loop adaptive adjustment system, the equivalent capacitance value of the second capacitor C2 can be dynamically switched according to the real-time operating conditions of the LDO circuit. This solves the technical problem that the traditional fixed-value second capacitor C2 cannot simultaneously adapt to complex operating conditions such as light and heavy load steady state, load transient jumps, and multiple voltage output levels, resulting in insufficient overshoot suppression capability or over-suppression causing small loop oscillations. This achieves the optimal balance between voltage overshoot suppression effect and circuit stability under all operating conditions.

[0081] The core adjustment logic of this implementation is as follows: The load current signal and output voltage signal of the LDO output terminal are collected in real time by the operating condition detection unit. Logical operations and data processing are performed on the collected raw electrical signals to generate operating condition discrimination feature quantities for distinguishing the circuit operating state. The specific operating condition of the circuit is determined based on the operating condition discrimination feature quantities. Then, the operating condition-capacity value mapping parameters pre-stored in the capacitor matching storage unit are retrieved to obtain the target capacitance value of the second capacitor C2 corresponding to the current operating condition. Finally, the adjustable capacitor array is controlled to switch the conduction working level through the operating condition identification signal to complete the adaptive matching adjustment of the equivalent capacitance value of the second capacitor C2.

[0082] Specifically, the operating condition detection unit is an on-chip integrated high-speed signal acquisition and logic operation circuit with uninterrupted real-time sampling capability. The sampling frequency is set to 10MHz, which can capture slight load fluctuations and high-speed step transition signals. The operating condition detection unit acquires the instantaneous load current signal and instantaneous output voltage signal at the LDO output terminal VOUT in real time. It performs logic processing such as mean filtering, differential operation, slope calculation, and threshold comparison on multiple sets of continuously acquired signal data to generate multi-dimensional operating condition discrimination features including steady-state load current amplitude, load current change slope, steady-state output voltage level, and output voltage fluctuation amplitude.

[0083] Based on the aforementioned multi-dimensional operating condition discrimination features, the operating condition detection unit can identify five typical operating conditions. The specific operating condition judgment thresholds have been calibrated through chip testing, and the parameters are reasonable and suitable for the circuit's operating characteristics: First, light load steady-state operating condition, where the average load current is less than 2mA and the current change slope is close to 0; Second, heavy load steady-state operating condition, where the average load current is greater than 40mA and the current change slope is close to 0; Third, heavy load sudden drop transient operating condition, where the absolute value of the negative change slope of the load current is greater than 2mA / μs; Fourth, high and low temperature extreme operating conditions, with on-chip temperature sampling signals used for auxiliary judgment; Fifth, multi-level high-voltage output steady-state operating condition, where the output voltage is in the high-gain regulated range. After completing the operating condition identification, the operating condition detection unit outputs a unique corresponding digital operating condition identification signal and transmits it to the adjustable capacitor array and capacitor matching storage unit.

[0084] The capacitor matching memory unit is an on-chip non-volatile memory unit. Before leaving the factory, it undergoes simulation calibration and actual system testing. It internally stores a one-to-one mapping relationship between all operating conditions and the target capacitance value of the second capacitor C2. The matching capacitance value for each operating condition is adapted to the working characteristics of the RC transient coupling path of the overshoot suppression module. Specific matching parameters are as follows: For light-load steady-state conditions, a small capacitance value of 0.8pF is matched to reduce the RC time constant, avoid micro-oscillations caused by capacitor coupling interference under steady-state conditions, and reduce static power consumption; for heavy-load steady-state conditions, a matching capacitance value of 0.8pF is matched to reduce the RC time constant, avoid micro-oscillations caused by capacitor coupling interference under steady-state conditions, and reduce static power consumption. A medium capacitance of 1.5pF ensures basic transient detection sensitivity; for heavy load and sudden load drops, a large capacitance of 2.5pF is matched to increase RC coupling capability, quickly capture positive voltage jump signals, enhance overshoot discharge suppression, and significantly reduce voltage overshoot amplitude; for multi-level high-voltage output conditions, a capacitance of 2.0pF is matched to adapt to high loop gain characteristics and balance transient response and loop stability; for extreme high and low temperature conditions, a temperature-compensated capacitance parameter is matched to offset the RC characteristic shift caused by device temperature drift.

[0085] Furthermore, in this embodiment, the adjustable capacitor array adapted to the second capacitor C2 is preferably an adjustable parallel capacitor matrix structure, which is integrated entirely within the chip, requiring no external components, resulting in high integration and fast response speed. The adjustable parallel capacitor matrix consists of multiple parallel capacitor branches. Each capacitor branch includes a set of fixed sub-capacitors connected in series with a MOS switch. One end of all capacitor branches is connected to form the matrix input terminal, which is connected to the output voltage sampling terminal VOUT of the overshoot suppression module. The other end of all capacitor branches is connected to form the matrix output terminal, which is connected to the signal coupling node of the gate of the fifteenth NMOS transistor M15. The control terminal of each MOS switch is connected to the operating condition identification signal output by the operating condition detection unit, and is controlled to turn on or off according to the high or low level of the identification signal.

[0086] When the MOS switch of a certain capacitor branch is turned on, the fixed sub-capacitor of that branch is connected to the circuit loop and participates in the superposition of the equivalent capacitance value of the second capacitor C2; when the MOS switch is turned off, the corresponding sub-capacitor branch is disconnected and does not participate in the capacitance superposition. By combining and switching different branches, seamless switching of multiple capacitance values ​​of 0.8pF, 1.5pF, 2.0pF, and 2.5pF can be achieved to match the preset target capacitance value for various operating conditions.

[0087] The complete adaptive adjustment process of this embodiment is as follows: When the circuit is working normally, the operating condition detection unit continuously collects the output voltage and load current signals, updates the operating condition discrimination characteristic quantities in real time, and completes the operating condition judgment; the capacitor matching storage unit responds to the operating condition identification signal in real time, retrieves the corresponding target capacitance value parameter, drives the adjustable capacitor array to switch the corresponding conduction level, and dynamically updates the equivalent capacitance value of the second capacitor C2. In scenarios where the load experiences a sudden heavy load drop and the output voltage is prone to large overshoot, the equivalent capacitance value of the second capacitor C2 is automatically increased to improve the transient signal coupling efficiency, quickly open the overshoot discharge branch, and suppress voltage overshoot; in light load steady-state scenarios, the equivalent capacitance value of the second capacitor C2 is automatically decreased to weaken useless transient coupling effects, avoid steady-state oscillations, and reduce static power consumption; in high and low temperature and multi-voltage level operating scenarios, the adaptive matching compensation capacitance value is used to offset the device parameter offset defects and ensure the stable performance of the overshoot suppression module under all temperature ranges and operating conditions.

[0088] The structural design of this embodiment solves the problem of poor adaptability of traditional fixed-parameter overshoot suppression circuits. It enables the transient response speed and voltage suppression strength of the overshoot suppression module to be dynamically and adaptively adjusted according to the load conditions. While improving the voltage overshoot suppression capability during load transient switching, it effectively ensures the stability of LDO steady-state operation, taking into account multiple performance requirements such as fast transient response, low power consumption, and high stability.

[0089] In other embodiments, the present invention further provides multiple sets of adaptive parameter adjustment implementation methods, and designs adjustable structures for the third resistor R3 of the dive suppression module and the fourth resistor R4 of the overshoot suppression module, and sets up two resistor matrix hardware topologies that can achieve high-precision resistance value switching. This allows the LDO circuit to adaptively match the optimal branch impedance according to the real-time load state, electrical parameters and chip temperature conditions, and solves the technical defects of traditional fixed resistor structures that cannot take into account the transient response speed, voltage suppression accuracy and loop stability under all operating conditions.

[0090] In this embodiment, the third resistor R3 in the dive suppression module is configured as an adjustable resistor, replacing the traditional fixed-value resistor. This circuit integrates a condition detection unit and a resistance matching storage unit to jointly achieve adaptive resistance adjustment of the third resistor R3 under all operating conditions. The condition detection unit has multi-dimensional signal acquisition capabilities, capable of real-time acquisition of the LDO output load current signal, output voltage signal, and internal chip temperature signal, comprehensively covering both load electrical conditions and chip environmental conditions.

[0091] The operating condition detection unit performs digital filtering, differential calculation, mean calculation, and threshold discrimination on the acquired raw signals of load current, output voltage, and chip temperature to generate quantified operating condition discrimination features. These features include core parameters such as load current amplitude, load current change slope, steady-state output voltage level, and chip operating temperature. Based on these features, the operating condition detection unit identifies the current operating condition of the circuit, specifically including light-load steady-state condition, heavy-load steady-state condition, sudden load surge transient condition, high-temperature operating condition, low-temperature operating condition, and multi-level output voltage steady-state condition.

[0092] The resistance matching memory unit is an on-chip non-volatile memory unit, calibrated through whole-system simulation and high and low temperature tests before leaving the factory. It pre-stores the target resistance value mapping relationship of the third resistor R3 corresponding to all operating conditions. The resistance parameters are configured differently for different operating conditions: under transient conditions where the load suddenly increases and the output voltage is prone to sag, a small resistance value is matched to reduce the RC charging and discharging time constant, accelerate the positive feedback response speed of the sag suppression branch, quickly increase the power tube drive current, and suppress voltage sag; under light load steady-state conditions, a large resistance value is matched to weaken the parasitic disturbance of the steady-state branch, reduce the static leakage current, improve the loop phase margin, and avoid steady-state high-frequency oscillation; under extreme high and low temperature conditions, a temperature-compensated resistance value is matched to offset the parameter offset caused by the temperature drift of MOS device mobility and capacitance value, ensuring consistent transient suppression performance across the entire temperature range; under different output voltage levels, a corresponding resistance value is matched to adapt to loop gain changes, avoiding the problems of oscillation under high gain conditions and insufficient response under low gain conditions.

[0093] After completing the current operating condition identification, the operating condition detection unit outputs the corresponding digital operating condition identification signal and transmits it to the adjustable structure of the third resistor R3. The adjustable third resistor R3 responds to the operating condition identification signal by switching its internal conduction level and dynamically adjusting its equivalent resistance value so that the final equivalent resistance value connected to the dive suppression circuit is completely matched with the preset target resistance value of the current real-time operating condition, thereby achieving a dynamic balance between dive suppression strength, response speed, and loop stability.

[0094] In this embodiment, the fourth resistor R4 in the overshoot suppression module is also configured as an adjustable resistor structure, which, together with the operating condition detection unit and the resistance value matching storage unit, achieves adaptive resistance value optimization adjustment. The fourth resistor R4 is the core impedance device of the RC transient coupling network of the overshoot suppression branch, which directly determines the suppression speed and steady-state power consumption level of voltage overshoot under load sag conditions, and has extremely high requirements for operating condition adaptability.

[0095] The operating condition monitoring unit acquires the load current signal, output voltage signal, and chip temperature signal at the LDO output terminal in real time. It performs comprehensive logical operations on the multi-dimensional acquired signals to generate operating condition discrimination feature quantities that can characterize the current circuit operating state, accurately distinguishing various operating conditions such as light load steady state, heavy load steady state, load drop overshoot transient, high and low temperature extremes, and multiple voltage levels. The resistance matching storage unit pre-stores the optimal target resistance value of the fourth resistor R4 corresponding to various operating conditions, forming a standardized operating condition-resistance value mapping database.

[0096] The specific resistance matching logic is as follows: When the circuit is under heavy load and sudden drop transient conditions, the fourth resistor R4 with a small resistance value is automatically matched, which greatly accelerates the AC signal coupling speed of the second capacitor C2, so that the overshoot suppression branch opens quickly, timely discharges excess charge at the output terminal, effectively suppresses the overshoot amplitude of the output voltage and shortens the voltage recovery time; when the circuit is under long-term light load steady-state conditions, the fourth resistor R4 with a large resistance value is automatically matched, which effectively reduces the steady-state leakage current of the overshoot branch, reduces the static power consumption of the circuit, and at the same time weakens the interference of the transient branch on the main voltage regulation loop, improving the steady-state stability of the entire system; when the circuit operates in extreme high and low temperature environments and different output voltage levels, the compensation resistance value is adaptively matched to compensate for the temperature drift of device parameters and the difference in loop gain, ensuring uniform and stable overshoot suppression performance across all operating conditions and temperature ranges.

[0097] The operating condition detection unit outputs an operating condition identification signal to the adjustable structure of the fourth resistor R4. The fourth resistor R4 switches its conduction level according to the operating condition identification signal and updates its equivalent input resistance in real time, so that the overshoot suppression module always works in the optimal operating state under the current operating condition.

[0098] In one specific embodiment of the present invention, the adjustable structures of the third resistor R3 and the fourth resistor R4 can both adopt an adjustable parallel resistor matrix topology, which is suitable for achieving coarse adjustment of resistance values ​​over a wide range and adapting to the adjustment requirements of large operating conditions and high impedance variation.

[0099] The adjustable parallel resistor matrix consists of multiple independent and parallel resistor branches. Each resistor branch is composed of a set of fixed resistor units connected in series with a switching control transistor. Each branch has a consistent structure and is independently controlled. One end of all resistor branches is connected to form the first port of the matrix, and the other end of all resistor branches is connected to form the second port of the matrix. The first and second ports of the matrix are directly connected in series to the circuit access node of the original third resistor R3 or fourth resistor R4, completely replacing the traditional fixed resistor.

[0100] The control terminals of the switching control transistors of each resistor branch are uniformly connected to the range control signal output by the resistance matching storage unit. Each switching control transistor can be independently controlled to turn on or off according to the range control signal. When the switching control transistor of any resistor branch is turned on, the fixed resistor unit of that branch is added to the matrix circuit and participates in the parallel superposition of equivalent resistance values. When the switching control transistor of any resistor branch is turned off, the corresponding resistor branch is completely cut off and does not participate in the calculation of equivalent resistance values. By controlling the switching combination of different numbers and resistance values ​​of resistor branches, a wide range of stepped adjustment of the equivalent total resistance of the adjustable resistor matrix can be achieved, meeting the large impedance switching requirements of the overshoot suppression and overshoot suppression branches under different operating conditions. The structure is simple, highly integrated, and has a fast switching response speed.

[0101] In another specific embodiment of the present invention, the adjustable structure of the third resistor R3 and the fourth resistor R4 can also adopt an adjustable series resistor matrix topology, which is suitable for realizing small resistance value and high precision fine adjustment, and is suitable for small impedance optimization scenarios such as high and low temperature compensation and voltage level fine adjustment.

[0102] The adjustable series resistor matrix is ​​composed of multiple sets of fixed resistor units with matched resistance values ​​connected in series end to end. Each set of fixed resistor units has a bypass control switch connected in parallel at both ends. The first and second ends of all series resistor units form the first port of the matrix, and the last end of all series resistor units forms the second port of the matrix. The entire matrix is ​​connected in series to the existing circuit path of the third resistor R3 or the fourth resistor R4.

[0103] Each bypass control switch's control terminal is connected to the gear control signal output by the resistance matching storage unit, and is turned on or off according to the gear control signal. When any bypass control switch is on, the corresponding fixed resistor unit is short-circuited and not connected to the circuit loop; when any bypass control switch is off, the corresponding fixed resistor unit is connected in series to the loop and participates in the overall equivalent resistance superposition. By selectively bypassing or connecting resistor units at different positions, high-precision, small-step fine-tuning of the equivalent resistance value of the resistance matrix can be achieved, compensating for performance deviations caused by temperature drift and subtle changes in loop gain, and realizing fine calibration of transient suppression strength.

[0104] In this invention, parallel resistor matrix and series resistor matrix topologies can be flexibly combined according to the different adjustment requirements of the third resistor R3 and the fourth resistor R4. Preferably, the third resistor R3 focuses on the adjustment of the large operating range and can be used as a parallel resistor matrix; the fourth resistor R4 focuses on impedance compensation and can be used as a series resistor matrix. The two work together to achieve full-range, high-precision adaptive adjustment of the LDO overshoot and undershoot suppression branch impedance, which significantly improves the circuit's adaptability to all operating conditions and voltage regulation performance.

[0105] In other embodiments, the present invention further adds a circuit performance self-test and adaptive threshold optimization scheme. By integrating a response speed evaluation unit and a threshold adjustment storage unit, it realizes real-time monitoring, fault determination and threshold adaptive calibration of LDO transient response performance. This solves the technical problems of poor adaptability of fixed evaluation thresholds, parameter adjustment mismatch under extreme conditions, erroneous triggering of adjustable branches and deterioration of circuit stability in traditional adaptive parameter adjustment circuits, and further improves the reliability and adaptive accuracy of LDO under all operating conditions.

[0106] In this embodiment, the LDO circuit also integrates a response speed evaluation unit, which is used to perform online detection and closed-loop judgment of the circuit's real-time transient response performance, realizing safe fallback control of the operating status of the adjustable capacitor array and adjustable resistor matrix. The response speed evaluation unit is an on-chip integrated high-speed timing detection and logic comparison circuit that monitors the voltage recovery timing parameters during the LDO load transient switching process in real time throughout the entire process, and continuously calculates the current transient response speed of the circuit.

[0107] The specific detection and calculation method is as follows: The response speed evaluation unit captures the start moment of the load step change and the stable moment when the output voltage returns to its steady-state rated value in real time, times the transient recovery time, and combines it with the output voltage fluctuation amplitude to quantify the transient response speed index of the current circuit. The response speed evaluation unit has a preset standard speed threshold range, which serves as the performance benchmark for normal circuit operation, and a reasonable qualified response speed range is preset for different load change amplitudes.

[0108] The response speed evaluation unit compares the real-time calculated transient response speed with the preset standard speed threshold in real time. When the transient response speed of the current circuit is detected to be within the preset standard threshold range, it is determined that the adaptive parameters of the circuit are matched normally, and each adjustable branch continues to work at the current conduction level. When the transient response speed of the current circuit is detected to be lower than the preset standard threshold and cannot meet the transient voltage regulation performance requirements, it is determined that the matching parameters of the current adjustable capacitor array and adjustable resistor matrix have a mismatch problem, which may cause loop oscillation, transient suppression failure, and reduced voltage regulation accuracy.

[0109] At this moment, the response speed evaluation unit immediately outputs a valid shutdown control signal, which synchronously acts on all the switch control transistors of the adjustable capacitor array, adjustable parallel resistor matrix, and adjustable series resistor matrix, uniformly shutting down all branch control switches and completely disconnecting all adaptive adjustable branches. The circuit immediately exits the parameter adaptive adjustment mode and switches back to the original fixed parameter operating mode, relying on the basic circuit structure to achieve stable voltage regulation output, avoiding circuit performance degradation and abnormal operation caused by parameter adaptive mismatch, and providing a hardware fallback protection mechanism for the stable operation of the LDO under all operating conditions.

[0110] This invention further optimizes the evaluation mechanism by incorporating a threshold adjustment and storage unit. This enables adaptive dynamic updating of the response speed evaluation threshold across all operating conditions, addressing the shortcomings of traditional fixed evaluation thresholds that cannot adapt to high and low temperatures, light and heavy loads, different voltage levels, and varying load fluctuation intensities, leading to overly strict or lenient evaluation standards and frequent misjudgments. The threshold adjustment and storage unit is electrically connected to the aforementioned operating condition detection unit, receiving multi-dimensional operating condition parameters output in real time by the unit.

[0111] The operating condition parameters collected and output in real time by the operating condition detection unit include four core parameters: real-time chip operating temperature, steady-state load current amplitude, LDO output voltage regulation level, and load current change slope. These four parameters fully cover the electrical operating status of the circuit and the environmental operating status.

[0112] The threshold adjustment storage unit has a complete one-to-one mapping relationship between the operating parameters and the response speed judgment threshold. This mapping relationship has been calibrated by simulation and high and low temperature whole machine test and has a rigorous linear correlation law. The specific adaptive adjustment logic is as follows: the response speed judgment threshold increases positively with the increase of steady-state load current, increases positively with the increase of output voltage level, increases positively with the increase of load current change slope, and decreases negatively with the increase of chip operating temperature.

[0113] In this embodiment, the transient response qualification index of the LDO circuit is uniformly defined as: the recovery time of the output voltage to return to steady state after a load step change, in ns.

[0114] This solution sets the following baseline thresholds: 25℃ ambient temperature, 20mA medium load, 5mA / μs current jump slope under normal conditions, and standard output voltage range; the preset baseline response speed threshold is 800ns. Based on these, the quantitative adjustment rules for the evaluation thresholds for each operating condition parameter are as follows:

[0115] First, steady-state load current positive regulation: When the steady-state load current increases in the range of 0 to 60 mA, the response speed threshold increases linearly and positively. For every 10 mA increase in load current, the threshold increases by 80 ns; under heavy load conditions with a load current of 60 mA, the evaluation threshold increases to 1280 ns. Heavy load conditions have more stringent requirements for transient recovery speed, which can effectively screen out abnormal conditions such as compensation failure and slow response under heavy load.

[0116] Second, positive adjustment of output voltage level: When the output voltage level increases within the 1.2V to 3.3V operating range, the loop DC gain gradually increases, the transient fluctuation amplitude increases, and the threshold increases synchronously in a positive direction. For every 0.5V increase in output voltage, the threshold increases by 60ns, and at the 3.3V high voltage level, the threshold increases to 1040ns, tightening the performance judgment standard for high voltage and high gain operating conditions.

[0117] Third, positive adjustment of load current change slope: as the load current jump slope increases in the range of 1 to 10 mA / μs, the transient impact intensity increases step by step. For every 1 mA / μs increase in current slope, the threshold increases by 50 ns, and the threshold can reach 1250 ns under the maximum impact condition, ensuring that the circuit has a fast compensation capability under strong transient disturbance conditions.

[0118] Fourth, reverse chip temperature regulation: When the chip temperature increases across the entire temperature range of -40℃ to 125℃, the carrier mobility of the MOS transistor increases, naturally accelerating the inherent response speed of the circuit. For every 20℃ increase in temperature, the response speed threshold decreases by 60ns in the reverse direction; at a high temperature of 125℃, the threshold drops to 440ns. This appropriately relaxes the judgment criteria, avoiding misjudgments caused by the inherent speed increase of the device, eliminating unnecessary shutdown actions of the adjustable branch, and ensuring the effective operation of the adaptive adjustment branch throughout its operation.

[0119] The threshold adjustment storage unit calculates and updates the current optimal evaluation threshold in real time based on the four types of parameters output by the operating condition detection unit, so that the response speed judgment standard always matches the real-time electrical operating conditions and temperature environment conditions of the circuit, and realizes performance self-testing without dead angles under the full temperature range, full load and full voltage range.

[0120] The specific operating condition adaptation principle is as follows: The larger the steady-state load current, the higher the output voltage level, the greater the load current jump slope, and the higher the load transient impact intensity, the more stringent the requirements for the circuit's transient response capability. Therefore, the response speed evaluation threshold is adaptively raised and the performance judgment standard is tightened to ensure that the circuit has a sufficiently fast compensation speed and suppression capability under strong transient operating conditions. When the chip operating temperature rises, the carrier mobility of the on-chip MOS device increases, the device switching speed naturally accelerates, and the inherent response speed of the circuit increases. Therefore, the evaluation threshold is adaptively lowered and the judgment standard is relaxed to avoid a large number of invalid false shutdown operations at high temperatures and ensure the continuous normal operation of the adjustable branch.

[0121] During operation, the threshold adjustment storage unit retrieves internal mapping data in real time based on the operating condition parameters output by the operating condition detection unit, dynamically updates and overwrites the current judgment threshold of the response speed evaluation unit, ensuring that the evaluation criteria always align with the real-time operating characteristics of the circuit. Compared to traditional fixed threshold evaluation methods, this adaptive threshold mechanism can achieve accurate performance judgment across the entire temperature range and load range, significantly reducing erroneous start / stop and shutdown of adjustable branches. While ensuring the rigor of the circuit's transient performance compliance judgment, it maximizes the optimization advantages of adaptive parameter adjustment, balancing transient performance, steady-state stability, and operational reliability.

[0122] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. An LDO circuit that responds quickly to transient current surges, characterized in that, It includes a differential error amplification module, an output feedback module, an overshoot suppression module, a dive suppression module, and a compensation module; The differential error amplification module includes a first NMOS transistor, a second NMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth PMOS transistor, and an eleventh NMOS transistor. The gate of the second NMOS transistor is connected to a reference voltage VREF, and the gate of the first NMOS transistor is connected to a feedback voltage VFB. The sources of the first and second NMOS transistors are both connected to the drain of the ninth NMOS transistor. The gate of the ninth NMOS transistor is connected to a bias voltage vb1, and the source of the ninth NMOS transistor is grounded. The gate and drain of the third PMOS transistor are shorted, and the gates of the third, fifth, and tenth PMOS transistors are all connected to the drain of the first NMOS transistor. The fourth PMOS transistor... The gates and drains are shorted; the gates of the fourth and sixth PMOS transistors are both connected to the drain of the second NMOS transistor; the sources of the third, fourth, fifth, and tenth PMOS transistors are all connected to the power supply VDDA; the drain of the sixth PMOS transistor is connected to the drain of the eighth NMOS transistor; the drains of the fifth and seventh NMOS transistors are both connected to the gate of the fourteenth NMOS transistor; the drains of the tenth and eleventh NMOS transistors are both connected to one end of the third resistor; the sources of the seventh, eighth, and eleventh NMOS transistors are all grounded; the gates of the seventh, eighth, eleventh, and seventeenth PMOS transistors are all connected to one end of the third capacitor; the gate and drain of the eighth NMOS transistor are connected. The output feedback module includes a twelfth PMOS transistor, a first resistor, and a second resistor. The source of the twelfth PMOS transistor is connected to the power supply VDDA, and the gate of the twelfth PMOS transistor is connected to the drain of the tenth PMOS transistor. The drain of the twelfth PMOS transistor serves as the circuit output terminal VOUT. VOUT is connected to one end of the first resistor, one end of the first capacitor, and one end of the second capacitor. The other end of the first resistor is connected to one end of the second resistor to form a voltage divider feedback node. The voltage divider feedback node is connected to the gate of the second NMOS transistor, and the other end of the second resistor is grounded. The other end of the first capacitor is connected to the other end of the third resistor. The overshoot suppression module includes a fourteenth NMOS transistor, a fifteenth NMOS transistor, a seventeenth PMOS transistor, a second capacitor, a third capacitor, and a fourth resistor. The source of the seventeenth PMOS transistor is connected to one end of the power supply VDDA, the drain of the seventeenth PMOS transistor is connected to one end of the third capacitor, the other end of the third capacitor is connected to the gate of the seventeenth PMOS transistor, and the gate of the seventeenth PMOS transistor is connected to the gate of the eleventh NMOS transistor. One end of the fourth resistor is connected to the bias voltage vb2, and the other end of the fourth resistor and one end of the second capacitor are both connected to the gate of the fifteenth NMOS transistor. The drain of the fifteenth NMOS transistor is connected to the source of the fourteenth NMOS transistor, and the drain of the fourteenth NMOS transistor and the other end of the second capacitor are both connected to VOUT. The sources of the fifteenth NMOS transistor and the thirteenth NMOS transistor are both grounded. The dive suppression module includes a sixteenth PMOS transistor, a third capacitor, and a third resistor; the source of the sixteenth PMOS transistor is connected to the power supply VDDA, the gate of the sixteenth PMOS transistor is connected to the drain of the tenth PMOS transistor, and the drain of the sixteenth PMOS transistor is connected to the other end of the third capacitor. The compensation module includes a first capacitor, one end of which is connected to VOUT, and the other end of which is connected to the end of a third resistor away from the drain of the eleventh NMOS transistor.

2. The LDO circuit with fast response to transient current surges according to claim 1, characterized in that, The first compensation circuit is equipped with an adjustable capacitor array. Based on a preset operating condition detection unit, it collects the current and voltage signals of the load in real time, performs calculations based on the current and voltage signals to generate operating condition characterization information, identifies the current operating condition type of the circuit based on the operating condition characterization information, obtains a pre-stored operating condition capacitor database containing the compensation capacitance values ​​corresponding to each operating condition type, retrieves the matching target capacitance value from the operating condition capacitor database according to the identified operating condition type, and switches the conduction level of the adjustable capacitor array to adjust the equivalent capacitance value of the first capacitor to the target capacitance value.

3. The LDO circuit with fast response to transient current surges according to claim 2, characterized in that, The adjustable capacitor array is configured as an adjustable parallel capacitor matrix, which includes multiple parallel capacitor branches. Each capacitor branch contains a fixed compensating sub-capacitor and a switching transistor. The control terminal of each branch's switching transistor is connected to the range control signal output from the operating condition capacitor database. One end of all capacitor branches is connected to form the matrix input terminal, which is connected to the output terminal of the differential error amplifier module. The other end of all capacitor branches is connected to form the matrix output terminal, which is connected to the circuit output terminal VOUT. Each branch's switching transistor is turned on or off according to the range control signal, connecting or disconnecting the corresponding fixed compensating sub-capacitor, thereby changing the overall equivalent capacitance value of the adjustable capacitor array.

4. The LDO circuit with fast response to transient current surges according to claim 3, characterized in that, The second capacitor in the overshoot suppression module is configured as an adjustable capacitor array; the operating condition detection unit is used to collect the load current signal and output voltage signal at the LDO output terminal in real time, perform logical operations on the collected load current signal and output voltage signal to generate operating condition discrimination feature quantity, and distinguish the current operating condition of the circuit based on the operating condition discrimination feature quantity. The capacitor matching storage unit pre-stores the target capacitance values ​​of the second capacitor corresponding to various operating conditions. The operating condition detection unit outputs an operating condition identification signal to the adjustable capacitor array. The adjustable capacitor array responds to the operating condition identification signal by switching the conduction level, adjusting the equivalent capacitance value of the second capacitor to the target capacitance value that matches the current operating condition.

5. The LDO circuit with fast response to transient current surges according to claim 1, characterized in that, The third resistor in the dive suppression module is an adjustable resistor. The operating condition detection unit is used to collect the load current signal and output voltage signal of the LDO output terminal in real time, and can also collect the chip temperature signal. The collected signals are processed to generate operating condition discrimination feature quantities, and the current operating condition of the circuit is identified based on the operating condition discrimination feature quantities. The resistance matching storage unit pre-stores the target resistance values ​​of the third resistor corresponding to each operating condition; the operating condition detection unit outputs an operating condition identification signal to the third resistor, and the third resistor responds to the operating condition identification signal by switching its conduction level and adjusting its equivalent resistance value to the target resistance value that matches the current operating condition.

6. The LDO circuit with fast response to transient current surges according to claim 1, characterized in that, The fourth resistor in the overshoot suppression module is an adjustable resistor. The operating condition detection unit is used to collect the load current signal, output voltage signal and chip temperature signal of the LDO output terminal in real time. It calculates the operating condition discrimination feature quantity of the collected signals and identifies the current operating condition of the circuit based on the operating condition discrimination feature quantity. The target resistance values ​​of the fourth resistor corresponding to various operating conditions are pre-stored in the resistance matching storage unit; the operating condition detection unit outputs an operating condition identification signal to the fourth resistor, and the fourth resistor responds to the operating condition identification signal to switch the conduction level and adjust its own equivalent resistance value to the target resistance value that matches the current operating condition.

7. The LDO circuit with fast response to transient current surges according to claim 5 or 6, characterized in that, The adjustable resistor employs an adjustable parallel resistor matrix; the adjustable parallel resistor matrix contains multiple parallel resistor branches, each resistor branch consisting of a fixed resistor unit connected in series with a control switch; one end of all resistor branches is connected to form the first port of the matrix, and the other end of all resistor branches is connected to form the second port of the matrix; each control switch receives a gear control signal and is controlled to turn on or off. Turning on the corresponding resistor branch adds the fixed resistor unit of that branch to the matrix, and turning off the corresponding resistor branch disconnects the fixed resistor unit of that branch. By switching different numbers of resistor branches, the equivalent total resistance of the adjustable resistor is changed.

8. The LDO circuit with fast response to transient current surges according to claim 5 or 6, characterized in that, The adjustable resistor adopts an adjustable series resistor matrix; the adjustable series resistor matrix is ​​composed of multiple groups of fixed resistor units connected in series end to end, and each group of fixed resistor units has a bypass control switch connected in parallel at both ends; the first end of all series resistor units is the first port of the matrix, and the last end is the second port of the matrix; each bypass control switch receives the gear control signal and is controlled to be turned on or off. When the bypass control switch is turned on, the corresponding fixed resistor unit is short-circuited; when the bypass control switch is turned off, the corresponding fixed resistor unit is connected to the circuit. The equivalent total resistance of the adjustable resistor is adjusted by bypassing different resistor units.

9. The LDO circuit with fast response to transient current surges according to claim 1, characterized in that, The LDO circuit also includes a response speed evaluation unit; the response speed evaluation unit is used to calculate the transient response speed of the circuit in real time and compare the calculated response speed with a preset standard speed threshold; when it is determined that the current response speed does not meet the preset requirements, the response speed evaluation unit outputs a shutdown control signal to control all control switches of the adjustable capacitor array, adjustable parallel resistor matrix, and adjustable series resistor matrix to turn off and disconnect all adjustable branches.

10. The LDO circuit with fast response to transient current surges according to claim 9, characterized in that, The threshold adjustment storage unit is also connected to the operating condition detection unit; the operating condition detection unit outputs operating condition parameters such as chip temperature, steady-state load current, output voltage level, and load current change slope to the threshold adjustment storage unit; the threshold adjustment storage unit pre-stores the mapping relationship between each operating condition parameter and the response speed judgment threshold, and adaptively updates the judgment threshold of the response speed evaluation unit according to the real-time operating condition parameters; wherein the response speed judgment threshold increases positively with the increase of steady-state load current, output voltage level, and load current change slope, and decreases negatively with the increase of chip temperature.

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