Low power mcu with cortex-m33 core deep sleep fast wake up system

Abstract

The application discloses a Cortex-M33 kernel-oriented low-power MCU deep sleep fast wake-up system and relates to the field of embedded microcontrollers, and comprises a partition module, a power supply mapping module and the like, wherein the partition module is used for dividing on-chip RAM into mutually independent key data storage areas and non-key data storage areas according to a preset address mapping rule; the power supply mapping module is used for establishing a one-to-one mapping relationship between the key data storage areas, the non-key data storage areas and corresponding power supply branches in a power supply circuit, and storing on-off control parameters of each power supply branch; the application can differentially allocate power supply according to data importance, provide a minimum threshold power supply for key data and suppress leakage current during sleep, and completely power off non-key data, thereby effectively reducing sleep power consumption, quickly filtering and shaping a wake-up signal during wake-up, skipping clock full-process calibration, and greatly shortening wake-up response time.

Description

Technical Field

[0001] This invention relates to the field of embedded microcontroller technology, specifically to a low-power MCU deep sleep and fast wake-up system for Cortex-M33 cores. Background Technology

[0002] With the widespread application of IoT terminals and portable low-power sensing devices, microcontrollers equipped with Cortex-M33 cores have become the core control carriers for these devices. These devices often operate in intermittent modes, remaining in deep sleep mode most of the time. Therefore, sleep power consumption control and wake-up response efficiency after external triggering are crucial indicators for evaluating battery life and real-time performance. Existing conventional architectures mostly employ a general design with unified power supply and complete clock calibration for the entire RAM, suitable for basic low-power applications.

[0003] The invention patent application with application number 202111466688.9 discloses a method, apparatus, device and storage medium for deep hibernation. The application aims to solve the problem that "in the prior art, manufacturers extend the power supply time of mobile phones by increasing the battery capacity of electronic products, but this cannot solve the problem of high power consumption from the perspective of hardware and software integration, and does not achieve the power saving effect from the perspective of daily use of mobile phones".

[0004] However, current technologies cannot achieve RAM partitioned sleep power management, making it difficult to further reduce sleep power consumption. At the same time, redundant steps in the wake-up process cannot be simplified, making it difficult to meet the dual requirements of ultra-low sleep power consumption and fast wake-up response.

[0005] To address this, we propose a low-power MCU deep sleep fast wake-up system for Cortex-M33 cores. Summary of the Invention

[0006] In view of the above-mentioned shortcomings of the existing technology, the present invention provides a low-power MCU deep sleep fast wake-up system for Cortex-M33 core, which can effectively solve the problems of the existing technology.

[0007] To achieve the above objectives, the present invention is implemented through the following technical solutions; This invention discloses a low-power MCU deep sleep fast wake-up system for Cortex-M33 cores, including a Cortex-M33 core, on-chip RAM, power supply circuitry, and external interrupt input pins, and further includes: The system comprises the following modules: a partitioning module, which divides the on-chip RAM into independent critical and non-critical data storage areas according to preset address mapping rules; a power supply mapping module, which establishes a one-to-one mapping relationship between critical and non-critical data storage areas and corresponding power supply branches in the power supply circuit, and stores the on / off control parameters of each power supply branch; a sleep power supply module, which, when the system enters deep sleep mode, cuts off all power to the non-critical data storage areas based on the mapping relationship and control parameters stored in the power supply mapping module, and simultaneously turns on the hold power supply branch of the critical data storage area; an adjustment module, which dynamically adjusts the output voltage of the hold power supply branch of the critical data storage area to the minimum threshold required for data hold and suppresses leakage current of the branch during the conduction of the hold power supply branch; a preprocessing module, which continuously monitors the external interrupt input pin, performs level shaping and noise filtering on the input signal, and outputs a valid wake-up trigger signal that meets the trigger conditions; and a clock bypass module, which, upon receiving a valid wake-up trigger signal from the preprocessing module, directly outputs a core clock start command to the Cortex-M33 core, skipping the full-process calibration steps of the system clock. The output signal of the partitioning module is connected to the input signal of the power supply mapping module. The output signal of the power supply mapping module is connected to the input signal of the sleep power supply module. The control output of the sleep power supply module is electrically connected to the power supply branch of the non-critical data storage area, the hold power supply branch of the critical data storage area, and the enable terminal of the adjustment module. The output of the adjustment module is electrically connected to the hold power supply branch of the critical data storage area. The first output signal of the preprocessing module is connected to the trigger input of the clock bypass module. The second output signal of the preprocessing module is connected to the reset terminal of the adjustment module. The output signal of the clock bypass module is connected to the clock control terminal of the Cortex-M33 core.

[0008] Furthermore, the preset address mapping rule in the partitioning module is as follows: The partitioning module divides the on-chip RAM into data blocks of fixed granularity, calculates the energy gain coefficient K for each data block, and then completes the region partitioning based on the comparison result of the energy gain coefficient K and the preset energy gain threshold. ; In the formula: This represents the total energy required for the system to return to normal operation after a power outage and loss of data blocks. The power consumption for maintaining power supply to this data block throughout the entire sleep cycle; When K is greater than the preset energy gain threshold, the continuous address range corresponding to the data block is assigned to the critical data storage area; otherwise, it is assigned to the non-critical data storage area.

[0009] Furthermore, the aforementioned ; In the formula: The number of kernel clock cycles consumed during the recovery process; This is the core operating voltage; This refers to the kernel's operating frequency. The duration of a single kernel clock cycle; Power is used for bus transfer of data from external non-volatile memory to on-chip RAM; The ; In the formula: Maintain power consumption per unit for a single data block; This represents the number of storage units contained in the data block. The preset duration for this hibernation.

[0010] Furthermore, after establishing the mapping relationship, the power supply mapping module automatically generates the on / off control parameters corresponding to each power supply branch. The on / off control parameters include branch conduction delay, branch cut-off delay, and holding current reference value. The power supply mapping module simultaneously performs mutual exclusion and integrity checks on the generated mapping relationship, ensuring that any address range of the on-chip RAM uniquely corresponds to only one power supply branch and that all address ranges are covered. After the check passes, the mapping relationship and on / off control parameters are written into the on-chip non-volatile control register.

[0011] Furthermore, when the sleep power supply module performs a power switching operation, it adopts an adaptive S-shaped voltage switching curve, and its instantaneous switching slope S(t) satisfies: ; In the formula: The maximum safe switching slope allowed by the power bus; The target output voltage for the power supply branch; The real-time output voltage of the power supply branch at time t; This is the preset voltage reference value; This is the inherent time constant of the power bus; The power supply cut-off curve of the non-critical data storage area and the power supply conduction curve of the critical data storage area adopt a phase-complementary S-shaped curve, so that the total current of the power bus remains within the preset current fluctuation range during the switching process.

[0012] Furthermore, the adjustment module collects the ambient temperature in real time while dynamically adjusting the output voltage of the power supply branch for the critical data storage area. Real-time leakage current of storage unit The time interval between the last time data was written and the current time. The minimum reliable holding voltage under the current operating conditions is calculated. ; In the formula: Standard temperature The reference holding voltage for newly written data; The voltage temperature coefficient of the storage cell; This is the charge decay compensation coefficient; The charge retention time constant of the storage cell; This is the leakage current compensation coefficient; This is the reference leakage current value at standard temperature; The adjustment module maintains a stable output voltage of the power supply branch through closed-loop negative feedback. And limit the leakage current of the branch to within the preset leakage current threshold.

[0013] Furthermore, the preprocessing module uses a sliding window level detection mechanism to filter noise. Only when the input signal maintains a stable level within a preset number of consecutive detection windows and the duration exceeds a preset effective trigger duration is it determined to be a valid wake-up trigger signal. During the operation of the preprocessing module, edge shaping processing is performed on the input signal synchronously, converting non-rectangular edges into standard digital edge signals whose rising and falling edge slopes meet the interrupt triggering requirements of the Cortex-M33 core.

[0014] Furthermore, the clock bypass module integrates a pre-calibration parameter storage unit, which is used to store the kernel clock frequency calibration value collected and locked before the end of the last normal operation of the system. When the clock bypass module receives a valid wake-up trigger signal, it directly loads the calibration value from the pre-calibration parameter storage unit and starts the kernel clock, skipping the full-process frequency calibration and stability detection steps of the system master clock phase-locked loop.

[0015] Furthermore, after outputting the kernel clock start command to the Cortex-M33 core, the clock bypass module is also used to trigger a cyclic redundancy check on all data in the critical data storage area when the Cortex-M33 core completes startup and enters the initialization state; if the check passes, a data valid signal is sent to the kernel and the system enters normal operation; if the check fails, a preset data recovery process is triggered to load the pre-backed-up critical data from the external non-volatile memory. The hibernation power supply module is also used to collect the on / off status of each power supply branch and the power supply voltage status of the key data storage area in real time, and to obtain the operating status of the kernel clock from the clock bypass module; the above status information is encoded into a serial feedback signal of a preset format and output to the external device interface, so that the external device can determine the current hibernation depth or wake-up ready state based on the serial feedback signal.

[0016] Compared with the known prior art, the technical solution provided by this invention has the following beneficial effects: This invention implements differentiated partitioned power supply management for on-chip RAM. During deep sleep, it cuts off power supply to non-critical storage areas and provides maintenance power to critical storage areas, effectively reducing the overall power consumption during system sleep. It also dynamically adjusts the power supply to critical storage areas to the minimum threshold required for data retention and suppresses branch leakage current, further compressing sleep energy consumption. It performs level shaping and noise filtering on external wake-up input signals to improve the effectiveness and stability of wake-up trigger signals. During the wake-up phase, it directly starts the kernel clock and skips the full system clock calibration process, further shortening the system wake-up response time. It adopts a phase-complementary power supply switching curve to keep the power bus current within a stable fluctuation range, avoiding voltage anomalies caused by power supply switching. After wake-up, it completes critical data verification to ensure data integrity and reliability, achieving an overall balance between low power consumption and fast wake-up performance. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0018] Figure 1 This is a schematic diagram of a low-power MCU deep sleep fast wake-up system for Cortex-M33 cores. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0020] The present invention will be further described below with reference to embodiments. Example

[0021] This embodiment presents a low-power MCU deep sleep and fast wake-up system for Cortex-M33 cores, such as... Figure 1 As shown, it includes a Cortex-M33 core, on-chip RAM, power supply circuitry, and external interrupt input pins, and also includes: The partitioning module is used to divide the on-chip RAM into independent critical data storage areas and non-critical data storage areas according to preset address mapping rules. The default address mapping rules in the partitioning module are as follows: The partitioning module divides the on-chip RAM into data blocks of fixed granularity, calculates the energy gain coefficient K for each data block, and then completes the region partitioning based on the comparison result of the energy gain coefficient K and the preset energy gain threshold. ; In the formula: This represents the total energy required for the system to return to normal operation after a power outage and loss of data blocks. The power consumption for maintaining power supply to this data block throughout the entire sleep cycle; The above formula quantifies the energy-saving benefit of a single data block by the ratio of the difference between the total energy consumed during power-off recovery of the data block and the energy consumed during hibernation. It can accurately distinguish between critical and non-critical data storage areas, allowing RAM partitioning to fully meet the actual needs of low-power hibernation, and achieving two-way optimization of data retention and energy consumption reduction. When K is greater than the preset energy gain threshold, the continuous address range corresponding to the data block is assigned to the critical data storage area; otherwise, it is assigned to the non-critical data storage area. The preset energy gain threshold is determined during the chip design phase based on the target sleep power consumption, expected sleep duration, and RAM process characteristics. The typical value range is 0.3~0.6. For low-power IoT terminal applications, the preferred threshold is 0.45. This threshold can balance the data retention gain and the sleep power reduction effect, and is suitable for the normal low-power operation of Cortex-M33 core MCU. ; In the formula: The number of kernel clock cycles consumed during the recovery process; This is the core operating voltage; This refers to the kernel's operating frequency. The duration of a single kernel clock cycle; Power is used for bus transfer of data from external non-volatile memory to on-chip RAM; The above formula combines the energy consumption of kernel clock recovery with the energy consumption of external non-volatile memory data transmission bus, and fully calculates the total energy consumption for system recovery after data block power failure. This provides an accurate recovery energy consumption benchmark for energy gain calculation and ensures the accuracy of RAM partition judgment. ; In the formula: Maintain power consumption per unit for a single data block; This represents the number of storage units contained in the data block. The preset duration for this hibernation; This formula combines the power consumption of a single data block, the number of storage units, and the preset sleep duration to accurately calculate the power consumption of the data block throughout the entire sleep cycle, providing a reliable power consumption value for energy benefit comparison and making the storage area division more in line with actual power consumption needs. The power supply mapping module is used to establish a one-to-one mapping relationship between critical data storage areas, non-critical data storage areas and corresponding power supply branches in the power supply circuit, and to store the on / off control parameters of each power supply branch. After establishing the mapping relationship, the power supply mapping module automatically generates the on / off control parameters corresponding to each power supply branch. The on / off control parameters include branch conduction delay, branch cut-off delay, and holding current reference value. The power supply mapping module performs mutual exclusion and integrity checks on the generated mapping relationship, ensuring that any address range of the on-chip RAM uniquely corresponds to only one power supply branch and that all address ranges are covered. After the check passes, the mapping relationship and on / off control parameters are written into the on-chip non-volatile control register. Among them, the branch turn-on delay is calculated based on the load capacitance of the corresponding power supply branch and the preset maximum allowable voltage rise rate, the branch turn-off delay is calculated based on the load capacitance of the corresponding power supply branch and the preset maximum allowable voltage drop rate, and the holding current reference value is calculated based on the total number of memory cells covered by the corresponding power supply branch and the reference holding current of a single memory cell. The mutual exclusion check follows this procedure: Iterate through the address ranges corresponding to all power supply branches, compare the start and end addresses of any two address ranges one by one, and determine whether there are overlapping address intervals. If there are, the mutual exclusion check fails and the process of regenerating the partition and mapping relationship is triggered. Integrity verification follows this procedure: continuously merge the address ranges corresponding to all power supply branches to obtain the merged total address range. Compare this total address range bit by bit with the complete physical address range of the on-chip RAM. If there are missing or out-of-range addresses, the integrity verification is deemed to have failed and the process of regenerating partitions and mapping relationships is triggered. After a verification fails, the system automatically marks data blocks with overlapping or missing addresses as blocks to be adjusted, prioritizes expanding the address range of critical data storage areas to eliminate overlaps, or supplements addresses of non-critical data storage areas to cover missing segments, and re-executes partition calculation and mapping relationship establishment until all mutual exclusion and integrity checks pass. The hibernation power supply module is used to cut off all power supply to non-critical data storage areas and simultaneously turn on the power supply branch for critical data storage areas when the system enters deep hibernation state, based on the mapping relationship and control parameters stored in the power supply mapping module. When the sleep power supply module performs a power switching operation, it adopts an adaptive S-shaped voltage switching curve, and its instantaneous switching slope S(t) satisfies: ; In the formula: The maximum safe switching slope allowed by the power bus; The target output voltage for the power supply branch; The real-time output voltage of the power supply branch at time t; This is the preset voltage reference value; This is the inherent time constant of the power bus; The above formula combines the power bus safety slope, the difference between the target and real-time voltage, and the inherent time constant of the bus to construct an adaptive S-shaped switching slope model, which makes the voltage switching of the power supply branch smooth and orderly, controls the total current fluctuation of the power bus within a safe range, and avoids the power supply switching from affecting the system stability. The power supply cut-off curve for non-critical data storage areas and the power supply turn-on curve for critical data storage areas adopt a phase-complementary S-shaped curve to keep the total current of the power bus within a preset current fluctuation range during the switching process. The maximum safe switching slope of the power bus is typically 0.5V / μs, and the preset voltage reference value is 0.1V; the inherent time constant of the power bus is calculated by multiplying the equivalent resistance (typically 5Ω) and the equivalent capacitance (typically 100pF), and the typical value is 0.5ns; the preset current fluctuation range is ±0.1μA to ensure that there are no voltage spikes and current surges during power supply switching. in, , This represents the equivalent resistance of the power bus. Indicates the equivalent capacitance of the power bus; The regulation module is used to dynamically adjust the output voltage of the power supply branch to the minimum threshold required for data retention during the period when the power supply branch in the critical data storage area is on, and to suppress the leakage current of the branch. While dynamically adjusting the output voltage of the power supply branch for the critical data storage area, the adjustment module collects the ambient temperature in real time. Real-time leakage current of storage unit The time interval between the last time data was written and the current time. The minimum reliable holding voltage under the current operating conditions is calculated. ; In the formula: Standard temperature The reference holding voltage for newly written data; The voltage temperature coefficient of the storage cell; This is the charge decay compensation coefficient; The charge retention time constant of the storage cell; This is the leakage current compensation coefficient; This is the reference leakage current value at standard temperature; The above formula integrates three major compensation parameters—temperature, data writing time, and leakage current—with the reference voltage to dynamically calculate the minimum voltage for reliable data retention. Combined with closed-loop control, it achieves voltage regulation and leakage current suppression, minimizing power consumption for data retention while ensuring no data loss. The regulating module maintains the output voltage of the power supply branch stable at a certain level through closed-loop negative feedback. And limit the branch leakage current to within a preset leakage current threshold; Among them, the voltage temperature coefficient α, charge decay compensation coefficient β, and leakage current compensation coefficient γ of the memory cell are all quantitatively determined through the chip factory calibration process: the voltage temperature coefficient α is obtained by measuring the reference holding voltage of the memory cell at at least three preset temperature points under standard test conditions, and the slope of the voltage change with temperature is obtained by linear fitting; the charge decay compensation coefficient β is obtained by measuring the change of the minimum holding voltage of the memory cell under different write time intervals through high temperature accelerated aging test, and is obtained by fitting based on the exponential decay model of charge leakage; the leakage current compensation coefficient γ is obtained by measuring the leakage current value of the memory cell under different bias voltages at standard temperature, and the correlation coefficient between voltage and leakage current is obtained by logarithmic fitting. Charge retention time constant of memory cell Wafer-level reliability testing determined the longest time a memory cell could correctly retain standard data after being written, under standard temperature and supply voltage. This time constant was obtained by fitting an exponential decay curve, and all memory cells on the same wafer used a uniform time constant. Nominal value; Among them, standard temperature Use 25℃ as the reference holding voltage. Typical value is 0.65V, reference leakage current Typical value is 0.04 μA; typical value of voltage temperature coefficient α after linear fitting is 0.002 / ℃; typical value of charge decay compensation coefficient β is 0.12; typical value of leakage current compensation coefficient γ is 0.08; charge retention time constant. After wafer testing, the uniform nominal value is 1000h. All the above parameters are written into the chip's factory calibration OTP register and are automatically loaded after power-on. The regulating module's operation of limiting branch leakage current to within a preset leakage current threshold follows the following rules: The adjustment module integrates a high-precision leakage current detection resistor connected in series with the power supply branch. It collects the voltage difference across the detection resistor in real time and converts it into a real-time leakage current value. The real-time leakage current value is compared with a preset leakage current threshold. If the real-time leakage current value exceeds the preset leakage current threshold, the gate bias voltage of the power transistor in the power supply branch is dynamically adjusted to reduce the conduction current of the power transistor until the real-time leakage current value falls back to within the preset leakage current threshold, thus forming a closed-loop negative feedback control. The preprocessing module is used to continuously monitor the external interrupt input pin, perform level shaping and noise filtering on the input signal, and output a valid wake-up trigger signal that meets the trigger conditions. The preprocessing module uses a sliding window level detection mechanism to filter noise. It determines a valid wake-up trigger signal only when the input signal maintains a stable level within a preset number of consecutive detection windows and the duration exceeds the preset effective trigger duration. During the preprocessing module's operation, edge shaping processing is performed on the input signal synchronously, converting non-rectangular edges into standard digital edge signals whose rising and falling edge slopes meet the interrupt triggering requirements of the Cortex-M33 core. In the sliding window level detection mechanism, the size of the sliding window is determined by the preprocessing module based on the kernel clock frequency in the system sleep state and the preset maximum noise duration. Each sliding window corresponds to a fixed number of kernel clock cycles. The formula for calculating the size of the sliding window is: ,in This is the clock frequency for the hibernation core (typically 32kHz). The maximum noise duration (typically 1μs) is set, and a single window corresponds to 2 core clock cycles; the preset number of continuous stable detection windows is 3, and the preset effective trigger duration is typically 3μs, which meets the minimum level stability requirement for Cortex-M33 core interrupt triggering; In the edge shaping stage, the input signal is first sampled synchronously for multiple cycles. The sampling result is input to the Schmitt trigger for high and low level threshold comparison to eliminate glitches and jitter in the input signal. Then, the level signal output by the comparison is aligned to the interrupt clock domain of the Cortex-M33 core through the edge synchronization circuit, and finally a standard digital edge signal with rising and falling edge slopes that conform to the core interrupt triggering specification is generated. The clock bypass module is used to directly output the kernel clock start instruction to the Cortex-M33 core when a valid wake-up trigger signal is received from the preprocessing module, skipping the entire system clock calibration process. The clock bypass module integrates a pre-calibration parameter storage unit, which is used to save the kernel clock frequency calibration value collected and locked before the end of the last normal operation. When the clock bypass module receives a valid wake-up trigger signal, it directly loads the calibration value from the pre-calibration parameter storage unit and starts the kernel clock, skipping the full-process frequency calibration and stability detection steps of the system main clock phase-locked loop. The pre-calibration parameter storage unit is implemented using an on-chip one-time programmable (OTP) non-volatile register. The kernel clock frequency calibration value is acquired and locked one kernel clock cycle before the system executes the deep sleep instruction, ensuring that the calibration value is the latest valid parameter before sleep. After outputting the kernel clock start command to the Cortex-M33 core, the clock bypass module is also used to trigger cyclic redundancy check of all data in the critical data storage area when the Cortex-M33 core completes startup and enters the initialization state. If the check passes, a data validity signal is sent to the kernel and the system enters normal operation. If the check fails, a preset data recovery process is triggered to load the pre-backed critical data from the external non-volatile memory. The hibernation power supply module is also used to collect the on / off status of each power supply branch and the power supply voltage status of the key data storage area in real time, and to obtain the running status of the kernel clock from the clock bypass module; the above status information is encoded into a serial feedback signal of a preset format and output to the external device interface, so that the external device can determine the current hibernation depth or wake-up ready state based on the serial feedback signal. The steps involved in cyclic redundancy check include: The clock bypass module first reads the verification configuration parameters pre-stored at the starting address of the critical data storage area to obtain the start address, end address, and preset generator polynomial of the data to be verified; The default generator polynomial uses the CRC-16-IBM polynomial (X¹). 6 +X¹ 5 +X²+1), adapting to the short frame verification requirements of critical data; the preset data block granularity is 4 bytes, matching the 32-bit data bus width of the Cortex-M33 core, improving verification efficiency; Then, according to the preset data block granularity, all valid data in the key data storage area is read block by block starting from the starting address. For each data block, a modulo 2 division operation based on the preset generator polynomial is performed bit by bit to generate the intermediate check value of the corresponding data block. Perform a concatenated XOR operation on the intermediate check values ​​of all data blocks in sequence to obtain the real-time total check value for this check. The real-time total check value is compared bit by bit with the baseline total check value that was pre-written to the specified address at the end of the critical data storage area before the system enters deep hibernation. If the two are completely consistent, the verification is deemed successful, and a high-level data valid signal is sent to the Cortex-M33 core. If there is any difference between the two, the verification is deemed to have failed, and a low-level data invalidation interrupt signal is immediately sent to the kernel, while triggering the preset data recovery process. The output signal of the partitioning module is connected to the input of the power supply mapping module. The output signal of the power supply mapping module is connected to the input of the sleep power supply module. The control output of the sleep power supply module is electrically connected to the power supply branch of the non-critical data storage area, the hold power supply branch of the critical data storage area, and the enable terminal of the adjustment module. The output of the adjustment module is electrically connected to the hold power supply branch of the critical data storage area. The first output signal of the preprocessing module is connected to the trigger input of the clock bypass module. The second output signal of the preprocessing module is connected to the reset terminal of the adjustment module. The output signal of the clock bypass module is connected to the clock control terminal of the Cortex-M33 core.

[0022] In this embodiment, the partitioning module divides the on-chip RAM into independent critical data storage areas and non-critical data storage areas according to preset address mapping rules. The power supply mapping module synchronously establishes a one-to-one mapping relationship between the critical data storage areas, non-critical data storage areas and corresponding power supply branches in the power supply circuit, and stores the on / off control parameters of each power supply branch. When the system enters deep sleep mode, the hibernation power supply module, based on the mapping relationship and control parameters stored in the power supply mapping module, cuts off all power supply to the non-critical data storage areas and synchronously turns on the holding power supply branch of the critical data storage area. Then, during the conduction of the holding power supply branch of the critical data storage area, the adjustment module dynamically adjusts the output voltage of the branch to the minimum threshold required for data retention and suppresses the leakage current of the branch. The preprocessing module further continuously monitors the external interrupt input pin, performs level shaping and noise filtering on the input signal, and outputs a valid wake-up trigger signal that meets the trigger conditions. Finally, when the clock bypass module receives the valid wake-up trigger signal output by the preprocessing module, it directly outputs the core clock start command to the Cortex-M33 core, skipping the full process calibration steps of the system clock.

[0023] In the above embodiments, when the system is applied to the deep sleep and wake-up scenario of a low-power MCU with a Cortex-M33 core, power supply can be allocated differently according to the importance of data. During sleep, only critical data is provided with the minimum threshold of power supply and leakage current is suppressed, while non-critical data is completely powered off, effectively reducing sleep power consumption. During wake-up, the system quickly filters and shapes the wake-up signal and skips the entire clock calibration process, greatly shortening the wake-up response time. At the same time, it ensures that critical data is stable and not lost and avoids false triggering, allowing the MCU to achieve an efficient balance between low power consumption and fast wake-up. This makes it suitable for demanding application scenarios such as battery-powered devices and IoT terminals, thereby effectively improving the device's battery life and operational stability.

[0024] Application example: The system is applied to the development of a portable intelligent Bluetooth temperature and humidity acquisition terminal product. This terminal uses a low-power MCU with a Cortex-M33 core as its main control core, integrating on-chip RAM, an independent power supply circuit, and external interrupt input pins. These interrupt pins are connected to the temperature and humidity sensor trigger port and the Bluetooth module wake-up port, respectively. The entire device is independently powered by a button battery. The design requirements are: continuous operation time on a single power supply of no less than 12 months, power consumption in deep sleep mode ≤1μA, and wake-up response time ≤5μs. The specific implementation process is as follows: After the terminal powers on and initializes, the system partitioning module divides the on-chip RAM into data blocks of fixed granularity according to preset address mapping rules. It calculates the energy gain coefficient for each data block and compares the results with preset energy gain thresholds to complete the region partitioning. Data blocks storing Bluetooth communication configuration parameters, temperature and humidity sampling reference values, interrupt trigger thresholds, and kernel clock calibration parameters all have energy gain coefficients greater than the preset thresholds and are therefore assigned to the critical data storage area. Data blocks storing temporary sampling caches and unused free space have energy gain coefficients less than the preset thresholds and are therefore assigned to the non-critical data storage area.

[0025] Based on the partitioning results, the power supply mapping module establishes a one-to-one correspondence between critical data storage areas, non-critical data storage areas, and each power supply branch in the power supply circuit. It automatically generates the on-delay, off-delay, and holding current reference values ​​for each branch. Subsequently, it performs mutual exclusion and integrity checks on the mapping relationships. The checks show that all addresses in the on-chip RAM have no overlap or missing values, and all checks pass. Finally, the mapping relationships and on / off control parameters are written to the on-chip non-volatile control register. In this application, three power supply branches for critical data storage areas and two power supply branches for non-critical data storage areas are generated. The on-delays for each branch are 1.2 microseconds, 1.5 microseconds, and 1.3 microseconds, respectively; the off-delays are 0.9 microseconds and 1.1 microseconds, respectively; and the holding current reference values ​​are 0.2 microamps, 0.25 microamps, and 0.22 microamps, respectively.

[0026] After the terminal completes a single temperature and humidity data acquisition and Bluetooth upload, it triggers a deep sleep command. The sleep power supply module performs power switching according to the mapping relationship and control parameters, cutting off all power supply to non-critical data storage areas and simultaneously turning on the power supply branch for critical data storage areas. The switching process adopts an adaptive S-shaped voltage switching curve. The curves of power outage in non-critical areas and power supply in critical areas are complementary in phase. The total current fluctuation of the power bus is controlled within the preset safety range, with no voltage spikes or current surges.

[0027] During the period when the critical data storage area is kept powered, the adjustment module collects ambient temperature, storage unit leakage current, and the last data write interval in real time. It then calculates the minimum reliable voltage required for data retention under the current operating conditions and stabilizes the output voltage of the power supply branch at this threshold through closed-loop negative feedback, while simultaneously suppressing the branch leakage current within a preset threshold. Under normal temperature conditions, the voltage in the critical data storage area remains stable at 0.7V, and the leakage current is controlled below 0.05 microamps. In high-temperature operating environments, the voltage automatically adjusts to 0.78V, and the leakage current still does not exceed the preset threshold, ensuring no loss of critical data throughout the process.

[0028] In the terminal sleep state, the preprocessing module continuously monitors the signal of the external interrupt input pin and uses a sliding window level detection mechanism to filter noise. Only when the input signal maintains a stable level within multiple consecutive detection windows and the duration exceeds the effective trigger duration is it determined to be a valid wake-up trigger signal. At the same time, edge shaping processing is performed on the signal to convert irregular signals into standard digital edge signals that meet the interrupt trigger requirements of the Cortex-M33 core, effectively filtering out invalid trigger signals such as environmental electromagnetic interference and signal glitches.

[0029] Upon receiving a valid wake-up trigger signal, the clock bypass module directly calls the previous kernel clock calibration value stored in the pre-calibration parameter storage unit and outputs a clock start command to the Cortex-M33 core, completely skipping the full calibration and stability testing steps of the system clock phase-locked loop, allowing the kernel clock to start rapidly. After the kernel completes startup and enters the initialization state, the clock bypass module immediately triggers cyclic redundancy check (CRC) of the critical data storage area. In this application, the check result is completely consistent with the baseline check value pre-stored before hibernation, and a valid data signal is sent to the kernel. The system does not need to perform a data recovery process and directly enters the normal operating state.

[0030] The hibernation power supply module collects the on / off status of each power supply branch, the power supply voltage of the key data storage area, and the kernel clock running status in real time throughout the process. It encodes the above information into a serial feedback signal and outputs it to the external device interface. The external debugging equipment can accurately determine the current hibernation depth and wake-up ready status of the terminal through this signal.

[0031] After this terminal is equipped with this system, the power consumption of the whole machine in deep sleep mode is reduced to 0.8 microamps, and the total wake-up response time is only 4.2 microseconds, which fully meets the design specifications; the battery life of button battery reaches 14 months, key data remains stable and without loss during long-term sleep, and there are no abnormalities after wake-up. It can quickly perform temperature and humidity sampling and data upload operations, and is well adapted to the application needs of portable low-power acquisition devices for the Internet of Things.

[0032] In summary, the system in the above embodiments effectively reduces the overall power consumption during the system's sleep phase by implementing differentiated partitioned power supply management for the on-chip RAM, cutting off power supply to non-critical storage areas and providing maintenance power to critical storage areas during deep sleep. It also dynamically adjusts the power supply to critical storage areas to the minimum threshold required for data retention and suppresses branch leakage current, further compressing sleep energy consumption. Level shaping and noise filtering are performed on external wake-up input signals to improve the effectiveness and stability of the wake-up trigger signal. During the wake-up phase, the core clock is directly started, skipping the entire system clock calibration process, further shortening the system wake-up response time. A phase-complementary power supply switching curve is used to keep the power bus current within a stable fluctuation range, avoiding voltage anomalies caused by power supply switching. After wake-up, critical data verification is completed to ensure data integrity and reliability. Overall, the system balances low power consumption and fast wake-up performance, adapting to low-power application scenarios of Cortex-M33 core MCUs and improving device endurance and operational stability.

[0033] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions will not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A low-power MCU deep sleep and fast wake-up system for Cortex-M33 cores, comprising a Cortex-M33 core, on-chip RAM, power supply circuitry, and external interrupt input pins, characterized in that, Also includes: The partitioning module is used to divide the on-chip RAM into independent critical data storage areas and non-critical data storage areas according to preset address mapping rules. The power supply mapping module is used to establish a one-to-one mapping relationship between critical data storage areas, non-critical data storage areas and corresponding power supply branches in the power supply circuit, and to store the on / off control parameters of each power supply branch. The hibernation power supply module is used to cut off all power supply to non-critical data storage areas and simultaneously turn on the power supply branch for critical data storage areas when the system enters deep hibernation state, based on the mapping relationship and control parameters stored in the power supply mapping module. The regulation module is used to dynamically adjust the output voltage of the power supply branch to the minimum threshold required for data retention during the period when the power supply branch in the critical data storage area is on, and to suppress the leakage current of the branch. The preprocessing module is used to continuously monitor the external interrupt input pin, perform level shaping and noise filtering on the input signal, and output a valid wake-up trigger signal that meets the trigger conditions. The clock bypass module is used to directly output the kernel clock start instruction to the Cortex-M33 core when a valid wake-up trigger signal is received from the preprocessing module, skipping the entire system clock calibration process.

2. The low-power MCU deep sleep fast wake-up system for Cortex-M33 core according to claim 1, characterized in that, The preset address mapping rules in the partitioning module are as follows: The partitioning module divides the on-chip RAM into data blocks of fixed granularity, calculates the energy gain coefficient K for each data block, and then completes the region partitioning based on the comparison result of the energy gain coefficient K and the preset energy gain threshold. ； In the formula: This represents the total energy required for the system to return to normal operation after a power outage and loss of data blocks. The power consumption for maintaining power supply to this data block throughout the entire sleep cycle; When K is greater than the preset energy gain threshold, the continuous address range corresponding to the data block is assigned to the critical data storage area; otherwise, it is assigned to the non-critical data storage area.

3. The low-power MCU deep sleep fast wake-up system for Cortex-M33 core according to claim 2, characterized in that, The ; In the formula: The number of kernel clock cycles consumed during the recovery process; This is the core operating voltage; This refers to the kernel's operating frequency. The duration of a single kernel clock cycle; Power is transferred via the bus from external non-volatile memory to on-chip RAM. The ; In the formula: Maintain power consumption per unit for a single data block; This represents the number of storage units contained in the data block. The preset duration for this hibernation.

4. The low-power MCU deep sleep fast wake-up system for Cortex-M33 core according to claim 2, characterized in that, After establishing the mapping relationship, the power supply mapping module automatically generates the on / off control parameters corresponding to each power supply branch. The on / off control parameters include branch conduction delay, branch cut-off delay, and holding current reference value. The power supply mapping module simultaneously performs mutual exclusion and integrity checks on the generated mapping relationship, ensuring that any address range of the on-chip RAM uniquely corresponds to only one power supply branch and that all address ranges are covered. After the check passes, the mapping relationship and on / off control parameters are written into the on-chip non-volatile control register.

5. The low-power MCU deep sleep fast wake-up system for Cortex-M33 core according to claim 1, characterized in that, When the dormant power supply module performs a power switching operation, it adopts an adaptive S-shaped voltage switching curve, and its instantaneous switching slope S(t) satisfies: ； In the formula: The maximum safe switching slope allowed by the power bus; The target output voltage for the power supply branch; The real-time output voltage of the power supply branch at time t; This is the preset voltage reference value; This is the inherent time constant of the power bus; The power supply cut-off curve of the non-critical data storage area and the power supply conduction curve of the critical data storage area adopt a phase-complementary S-shaped curve, so that the total current of the power bus remains within the preset current fluctuation range during the switching process.

6. The low-power MCU deep sleep fast wake-up system for Cortex-M33 core according to claim 1, characterized in that, When the adjustment module dynamically adjusts the output voltage of the power supply branch for maintaining the critical data storage area, it collects the ambient temperature in real time. Real-time leakage current of storage unit The time interval between the last time data was written and the current time. The minimum reliable holding voltage under the current operating conditions is calculated. ; In the formula: Standard temperature The reference holding voltage for newly written data; The voltage temperature coefficient of the storage cell; This is the charge decay compensation coefficient; The charge retention time constant of the storage cell; This is the leakage current compensation coefficient; This is the reference leakage current value at standard temperature; The adjustment module maintains a stable output voltage of the power supply branch through closed-loop negative feedback. And limit the leakage current of the branch to within the preset leakage current threshold.

7. The low-power MCU deep sleep fast wake-up system for Cortex-M33 core according to claim 1, characterized in that, The preprocessing module uses a sliding window level detection mechanism to filter noise. Only when the input signal maintains a stable level within a preset number of consecutive detection windows and the duration exceeds the preset effective trigger duration is it determined to be a valid wake-up trigger signal. During the operation of the preprocessing module, edge shaping processing is performed on the input signal synchronously, converting non-rectangular edges into standard digital edge signals whose rising and falling edge slopes meet the interrupt triggering requirements of the Cortex-M33 core.

8. The low-power MCU deep sleep fast wake-up system for Cortex-M33 core according to claim 1, characterized in that, The clock bypass module integrates a pre-calibration parameter storage unit, which is used to store the kernel clock frequency calibration value collected and locked before the end of the last normal operation of the system. When the clock bypass module receives a valid wake-up trigger signal, it directly loads the calibration value from the pre-calibration parameter storage unit and starts the kernel clock, skipping the full-process frequency calibration and stability detection steps of the system master clock phase-locked loop.

9. The low-power MCU deep sleep fast wake-up system for Cortex-M33 core according to claim 1, characterized in that, After outputting the kernel clock start command to the Cortex-M33 core, the clock bypass module is also used to trigger cyclic redundancy check of all data in the critical data storage area when the Cortex-M33 core completes startup and enters the initialization state; if the check passes, a data valid signal is sent to the kernel and the system enters normal operation state. If the verification fails, a preset data recovery process is triggered to load the pre-backed-up critical data from an external non-volatile storage device. The hibernation power supply module is also used to collect the on / off status of each power supply branch and the power supply voltage status of the key data storage area in real time, and to obtain the operating status of the kernel clock from the clock bypass module; the above status information is encoded into a serial feedback signal of a preset format and output to the external device interface, so that the external device can determine the current hibernation depth or wake-up ready state based on the serial feedback signal.

10. The low-power MCU deep sleep fast wake-up system for Cortex-M33 core according to claim 1, characterized in that, The output signal of the partitioning module is connected to the input signal of the power supply mapping module. The output signal of the power supply mapping module is connected to the input signal of the sleep power supply module. The control output of the sleep power supply module is electrically connected to the power supply branch of the non-critical data storage area, the hold power supply branch of the critical data storage area, and the enable terminal of the adjustment module. The output of the adjustment module is electrically connected to the hold power supply branch of the critical data storage area. The first output signal of the preprocessing module is connected to the trigger input of the clock bypass module. The second output signal of the preprocessing module is connected to the reset terminal of the adjustment module. The output signal of the clock bypass module is connected to the clock control terminal of the Cortex-M33 core.

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