Control method of power chip and power chip

Abstract

The application provides a control method of a power chip and the power chip. The method comprises the following steps: for each IP core, after the calculation task in the current sampling period is completed and before the sampling data in the next sampling period arrives, pre-calculation irrelevant to the sampling data in the next sampling period is performed based on historical sampling data to obtain a pre-calculation result; in response to the arrival of the sampling data in the next sampling period, the processor core writes the sampling data in the next sampling period into the corresponding IP core, the corresponding IP core performs incremental calculation related to the sampling data in the next sampling period based on the pre-calculation result to obtain a final calculation result, the processor core acquires the final calculation result from the corresponding IP core, and outputs a control signal based on the final calculation result to control a power electronic device. The real-time response capability of power closed-loop control is greatly improved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design technology, and in particular to a control method for a power chip and a power chip. Background Technology

[0002] The real-time control system of power electronic devices, such as three-phase AC systems like motor drives, grid-connected inverters, energy storage converters, and charging piles, directly depends on the computing power and response speed of digital control chips for its closed-loop control performance. With the widespread application of wide-bandgap semiconductor devices such as silicon carbide and gallium nitride, the switching frequency of power electronic devices is constantly increasing, and the control cycle is shortening from hundreds of microseconds to tens of microseconds or even microseconds. This places extremely high demands on the real-time computing power of control chips.

[0003] Currently, closed-loop control algorithms are typically implemented in pure software using general-purpose processor chips (such as digital signal processors and advanced reduced instruction set machine architecture microcontrollers). Within a complete control cycle, several computationally intensive modules need to be executed sequentially, including: Fast Fourier Transform (FFT) for harmonic analysis; digital filters for signal conditioning; coordinate transformations (including Clarke and Park transforms) for decoupling control; Space Vector Generation (SVGEN) for inverter drive; Proportional-Integral-Derivative (PID) controllers for error regulation; Phase-Locked Loop (PLL) for grid synchronization; and RMS calculation for electrical quantity monitoring.

[0004] However, the processor core must sequentially complete the computation process of all the aforementioned algorithm modules within the same control cycle. Due to data dependencies between the algorithm modules, subsequent modules must wait for the previous module to finish executing completely before they can begin computation, resulting in the processor core being exclusively occupied throughout the entire control cycle. Each module's computation involves a complete instruction pipeline of data reading, arithmetic and logical operations, and result writing back; modules cannot overlap in execution. This serial, cumulative execution method causes the computation time of each algorithm module to add up, resulting in a linear increase in the total computation time within a single control cycle with the number of algorithm modules. This extends the delay from sampling to control output, reducing the dynamic response speed of the control system. Summary of the Invention

[0005] The purpose of this application is to provide a control method for a power chip and a power chip, so as to improve the real-time response capability of power closed-loop control, reduce computational latency, and on this basis reduce system power consumption and achieve the ability to independently replace high-performance general-purpose processor cores.

[0006] To address the aforementioned technical problems, this application provides the following technical solutions: The first aspect of this application provides a control method for a power chip. The method is applied to a power chip, which includes a processor core and multiple intellectual property (IP) cores. The IP cores are electrically connected to the processor core, and each IP core is used to perform a power control operation. The method includes: for each IP core, after the calculation task of the current sampling period is completed and before the sampling data of the next sampling period arrives, performing a pre-calculation based on historical sampling data that is unrelated to the sampling data of the next sampling period to obtain a pre-calculation result; in response to the arrival of the sampling data of the next sampling period, the processor core writes the sampling data of the next sampling period into the corresponding IP core, and the corresponding IP core performs an incremental calculation related to the sampling data of the next sampling period based on the pre-calculation result to obtain a final calculation result; the processor core obtains the final calculation result from the corresponding IP core and outputs a control signal based on the final calculation result to control a power electronic device.

[0007] Compared to existing technologies, the power chip control method provided in the first aspect of this application performs pre-calculations based on historical sampling data during the idle period between the completion of the calculation task of the current sampling cycle of each IP core and the arrival of the data of the next sampling cycle. This pre-calculations are unrelated to the data of the next cycle. When the new data arrives, only incremental calculations are performed. This reduces the computational latency caused by the serial execution of all algorithm modules in the traditional architecture from linearly accumulating with the number of modules to a fixed small number of clock cycles that depend only on the incremental calculations. This significantly improves the real-time response capability of power closed-loop control and compresses the lower limit of the control cycle. At the same time, since the processor core only needs to perform data writing and result reading without participating in intensive calculations, it can significantly reduce the core load and system power consumption, reduce the dependence on high-performance general-purpose processor cores, and improve the autonomy and controllability of the chip architecture.

[0008] In other embodiments provided in this application, after the computation task of the current sampling period is completed, each IP core is triggered to enter the pre-computation preparation state; before the sampling data of the next sampling period arrives, each IP core performs pre-computation in parallel based on its stored historical sampling data, which is unrelated to the sampling data of the next sampling period.

[0009] By having each IP core execute its own pre-computation in parallel, the pre-computation stages of multiple algorithm modules are overlapped on the time axis, so that the total pre-computation time no longer increases linearly with the number of IP cores, further compressing the bottleneck of idle period utilization and providing additional time margin for shortening the overall control cycle.

[0010] In other embodiments provided in this application, each IP core performs pre-computation unrelated to the sampling data of the next sampling period in parallel based on its own stored historical sampling data. This includes: determining the order of the start times of the pre-computation of each IP core according to the historical pre-computation time and / or real-time priority of the algorithm corresponding to each IP core; wherein, the IP core with longer pre-computation time or higher real-time priority is ranked earlier in the order, and the pre-computation of each IP core is partially overlapped on the time axis; and performing pre-computation unrelated to the sampling data of the next sampling period in sequence based on its own stored historical sampling data.

[0011] By determining the pre-computation start order based on the historical pre-computation time and / or real-time priority of each IP core, IP cores with longer or higher time consumption are started earlier and partially overlapped in execution on the timeline. This can prioritize the completion window of pre-computation for long-duration and high-real-time tasks under the constraints of limited bus bandwidth or shared resource conflicts, avoid delays in critical path pre-computation due to resource contention, and thus improve the overall timing determinism in multi-IP core scenarios.

[0012] In other embodiments provided in this application, before performing pre-calculations based on historical sampling data that are unrelated to the sampling data of the next sampling period, the method further includes: obtaining feature parameters of historical sampling data; dynamically configuring the depth of the sliding window according to the feature parameters; and performing pre-calculations based on historical sampling data that are unrelated to the sampling data of the next sampling period, including: using historical data collected by the sliding window with dynamically configured depth to perform pre-calculations unrelated to the sampling data of the next sampling period.

[0013] By acquiring the feature parameters of historical sampling data and dynamically configuring the depth of the sliding window based on these feature parameters, the system can collect historical data for pre-calculation using the dynamically configured sliding window. This allows for adaptive adjustment of the amount of historical data required for pre-calculation based on signal fluctuations or sampling characteristics. This avoids redundant storage and computational overhead while ensuring the accuracy of pre-calculation, thereby improving the utilization efficiency of pre-calculation resources under different operating conditions.

[0014] In other embodiments provided in this application, the feature parameters include fluctuation feature parameters and sampling feature parameters; dynamically configuring the depth of the sliding window according to the feature parameters includes: increasing the depth of the sliding window in response to an increase in the fluctuation feature parameters; and increasing the depth of the sliding window in response to an increase in the sampling feature parameters.

[0015] By increasing the sliding window depth when the fluctuation characteristic parameter or the sampling characteristic parameter increases, the historical data coverage can be automatically expanded to smooth the pre-calculation error when the signal fluctuation is severe or the sampling rate is increased. When the fluctuation is gentle or the sampling rate is reduced, the window can be automatically shrunk to reduce redundant calculations, thereby improving the reliability of the pre-calculation results under different operating conditions.

[0016] In other embodiments provided in this application, before performing pre-calculations based on historical sampling data that are unrelated to the sampling data of the next sampling period, the method further includes: dynamically reconstructing the internal data path of the IP core according to the current working mode; wherein, in response to being in the pre-calculation mode, the internal data path is reconstructed to connect only the historical sampling data path and the pre-calculation operation path; in response to being in the incremental calculation mode, the internal data path is reconstructed to connect the new sampling data path, the pre-calculation result path, and the incremental calculation operation path simultaneously.

[0017] By dynamically reconstructing the internal data path of the IP core according to the pre-computation mode or the incremental computation mode, only the historical data path and the pre-computation operation path are connected in the pre-computation mode, while the new data path, the pre-computation result path and the incremental computation operation path are connected at the same time in the incremental computation mode. This enables time-sharing multiplexing of computing resources within the same hardware IP core and avoids additional clock overhead or data pollution when switching between unrelated paths, thereby improving the execution efficiency and reliability of the IP core between the two working states of pre-computation and incremental computation.

[0018] In other embodiments provided in this application, the IP core includes a validity flag bit, which is used to indicate whether the pre-calculation result stored locally has been used for incremental calculation; before dynamically reconstructing the internal data path of the IP core according to the current working mode, the method further includes: in response to the validity flag bit indicating that it has been used for incremental calculation, determining the current working mode as a pre-calculation mode; in response to the validity flag bit indicating that it has not been used for incremental calculation, determining the current working mode as an incremental calculation mode, and updating the validity flag bit to indicate that it has been used for incremental calculation after the incremental calculation is completed.

[0019] By using a validity flag to indicate whether the local pre-computation result has been used for incremental computation, and determining the current working mode accordingly, and updating the flag after the incremental computation is completed, the IP core can autonomously identify the consumption status of the pre-computation result and automatically complete the mode switching without relying on an external processor or additional timing logic. This avoids logical errors caused by repeated pre-computation or missed incremental computation, and improves the robustness of multi-cycle pipelined operations.

[0020] In other embodiments provided in this application, the IP core includes a data storage module and a bus interface module. The bus interface module includes an output register. The data storage module and the output register are independent storage spaces that support parallel read and write operations. The method also includes: storing the pre-calculated result into the data storage module; and storing the final calculation result into the output register for the processor core to read.

[0021] By storing the pre-calculation results in the data storage module and the final calculation results in a separate output register, and making both independent storage spaces that support parallel read and write operations, the processor core can read the final calculation results of the previous cycle from the output register in parallel while the IP core performs the next round of pre-calculation and writes to the data storage module. This eliminates the mutual exclusion wait between result reading and pre-calculation, and further improves pipeline throughput.

[0022] In other embodiments provided in this application, the data storage module includes a public pre-computation area and a dedicated pre-computation area. The public pre-computation area is used to store pre-computation results that are shared and accessed by multiple IP cores, and the dedicated pre-computation area is used to store pre-computation results that are used only by this IP core. After obtaining the pre-computation results, the method further includes: in response to the fact that the pre-computation results of the first IP core are dependent on the calculation of the second IP core, the first IP core stores its own pre-computation results in the public pre-computation area and sets a sharing identifier for the second IP core; the second IP core obtains the pre-computation results of the first IP core from the public pre-computation area according to the sharing identifier and performs calculations.

[0023] By dividing the data storage module into a common pre-computation area and a dedicated pre-computation area, when the pre-computation result of the first IP core is dependent on the second IP core, it is stored in the common area and a shared identifier is set. The second IP core retrieves the result from the common area based on the identifier and performs the calculation. This can avoid repeatedly pre-computing the same intermediate result in a multi-algorithm pipeline with data dependencies and reduce inter-core communication latency, thereby reducing the overall redundant computation and improving the system throughput.

[0024] A second aspect of this application provides a power chip, which includes a processor core and multiple IP cores. The IP cores are electrically connected to the processor core, and each IP core is used to perform a power control operation. Each IP core is used to perform a pre-calculation based on historical sampling data, which is unrelated to the sampling data of the next sampling period, after the calculation task of the current sampling period is completed and before the sampling data of the next sampling period arrives, to obtain a pre-calculation result. The processor core is used to write the sampling data of the next sampling period into the corresponding IP core in response to the arrival of the sampling data of the next sampling period. The corresponding IP core is used to perform an incremental calculation related to the sampling data of the next sampling period based on the pre-calculation result to obtain a final calculation result. The processor core is used to obtain the final calculation result from the corresponding IP core and output a control signal based on the final calculation result to control a power electronic device.

[0025] The power chip provided in the second aspect of this application has the same or similar beneficial effects as the control method of the power chip provided in the first aspect. Attached Figure Description

[0026] The above and other objects, features, and advantages of exemplary embodiments of this application will become readily understood by reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of this application are illustrated by way of example and not limitation, with the same or corresponding reference numerals denoteing the same or corresponding parts, wherein: Figure 1 This is a schematic diagram of the power chip structure in the embodiments of this application. Figure 1 ; Figure 2 This is a flowchart illustrating the control method of the power chip in the embodiments of this application. Figure 1 ; Figure 3 This is a flowchart illustrating the control method of the power chip in the embodiments of this application. Figure 2 ; Figure 4 This is a schematic diagram of the power chip structure in the embodiments of this application. Figure 2 ; Figure 5 This is a schematic diagram of the structure of the power-specific algorithm IP core in the embodiments of this application; Figure 6 This is a schematic diagram comparing the power chip and the general-purpose processor in the closed-loop algorithm execution flow in the embodiments of this application. Detailed Implementation

[0027] Exemplary embodiments of this application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of this application are shown in the drawings, it should be understood that this application may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of this application and to fully convey the scope of this application to those skilled in the art.

[0028] It should be noted that, unless otherwise stated, the technical or scientific terms used in this application shall have the ordinary meaning as understood by one of ordinary skill in the art to which this application pertains.

[0029] It should be noted that the user data, data acquisition, and / or use involved in the embodiments of this application strictly comply with the laws, regulations, and industry standards of relevant countries and regions. The collection and acquisition of data involved in the embodiments of this application are all done in advance by actively prompting or prominently displaying information to inform users and obtaining authorization, or by obtaining full authorization from all parties. The processing, manipulation, forwarding, and use of data involved in the embodiments of this application are all carried out on the premise that the user or relevant party is fully informed and authorized. In implementing the various embodiments of this application, the types of data or information, scope of use, and usage scenarios that may be involved are informed to users or relevant parties and authorization is obtained through appropriate means. The specific methods of notification and authorization may vary according to the actual situation, and this application is not limited in this regard. The processing of personal information involved in the embodiments of this application is carried out under the premise of having a legal basis (such as obtaining the consent of the personal information subject or being necessary for the performance of a contract), and is only processed within the prescribed or agreed scope. Sensitive personal information such as biometric information, medical and health information, financial account information, and precise location information involved in the embodiments of this application are all processed under the premise of having a specific purpose and sufficient necessity, and with the separate authorization and consent of the user or relevant party. In some embodiments of this application, if the user or related party refuses to process personal information other than the information necessary for the basic functions, it will not affect the use of the basic functions of the embodiments of this application.

[0030] Currently, general-purpose processor chips are used to execute all algorithm modules in power closed-loop control serially in a purely software manner. However, the serial execution of each algorithm module causes the total computation time to accumulate linearly with the number of modules, making it difficult to meet the real-time requirements of the control cycle.

[0031] In view of this, embodiments of this application provide a control method and a power chip for a power chip, decomposing the serial execution mode in the traditional architecture, which requires complete recalculation of all algorithm modules in each control cycle, into a two-stage pipelined mode of pre-calculation during idle periods + incremental calculation after the arrival of new data. Specifically, each dedicated algorithm IP core performs pre-calculation based on stored historical sampling data during its inherent idle gap between the completion of the calculation task in the current sampling cycle and the arrival of sampling data in the next sampling cycle. When the new sampling data arrives, the processor core only needs to write the new data to the corresponding IP core, which can then combine the previously completed pre-calculation results to complete the remaining incremental calculation and output the final result within a very short fixed clock cycle. In this way, the overall computational latency of the algorithm is decoupled from being linearly related to the algorithm complexity and the number of modules to "only depending on a fixed small number of clock cycles of incremental calculation", so that the lower limit of the control cycle is no longer constrained by the total time consumption of each algorithm module, ultimately achieving deterministic microsecond-level real-time response.

[0032] First, the control method for the power chip provided in the embodiments of this application will be described.

[0033] The control methods for power chips are applied to power chips. Figure 1 This is a schematic diagram of the power chip structure in the embodiments of this application. Figure 1 See Figure 1 As shown, the power chip 10 includes a processor core 11 and multiple IP cores 12. The IP cores 12 are electrically connected to the processor core 11. Each IP core 12 is used to perform a power control operation.

[0034] The power chip 10 is suitable for high-frequency real-time power control scenarios such as motor drive, grid-connected inverter, energy storage converter and charging pile. It is a system-on-chip (SoC) chip that integrates a processor core 11 and multiple dedicated algorithm IP cores 12 and supports pre-computation pipeline mechanism. For example, it is a dedicated control chip for implementing vector control of three-phase AC motor.

[0035] Processor core 11 is a central processing unit used to execute control instructions, schedule tasks, and manage data writing and result reading, such as a processor core based on the open-source Reduced Instruction Set Computing Version Five (RISC-V) architecture.

[0036] IP core 12 is a hardware-implemented intellectual property core used to independently complete a specific algorithm function in the field of power control, such as a Fast Fourier Transform (FFT) IP core, a coordinate transformation IP core, or a Proportional-Integral-Derivative (PID) IP core.

[0037] The number of IP cores 12 is determined based on the number of dedicated algorithm modules that need to be offloaded from processor core 11 in the power control algorithm. Each key algorithm module is configured with an independent hardware IP core 12. Specifically, it may include an FFT IP core, a digital filter IP core, a coordinate transformation IP core, an SVGEN IP core, a PID IP core, a PLL IP core, and a true RMS (Root Mean Square, RMS) calculation IP core.

[0038] Figure 2 This is a flowchart illustrating the control method of the power chip in the embodiments of this application. Figure 1 See Figure 2 As shown, the method may include: S21: For each IP core, after the computation task of the current sampling period is completed and before the sampling data of the next sampling period arrives, perform pre-computation based on historical sampling data that is unrelated to the sampling data of the next sampling period, and obtain the pre-computation result.

[0039] After the sampled data arrives in each sampling period, the processor core writes the current sampled data to the corresponding IP core, triggering the IP core to execute the computational task related to the sampled data in order to produce the final computational result of the current period.

[0040] The computational task here refers to the complete calculation process by which an IP core, after receiving the sampled data of the current sampling period, performs incremental calculations based on the pre-calculated results already completed within the IP core to produce the final result. For example, after receiving the error value of the current period, the proportional-integral-derivative IP core, combined with the pre-calculated integral accumulation term and historical deviation term, completes the control output calculation within several clock cycles.

[0041] The sampling period refers to the fixed time interval between two consecutive samples in a real-time power control system. The current sampling period refers to the sampling period in progress, where the sampled data has just been written into the IP core by the processor core to perform incremental calculations and generate the current output result.

[0042] After the calculation task of the current sampling period is completed and before the sampling data of the next sampling period arrives, there is an inherent idle period in which the IP core has just completed the final calculation result based on the current sampling data, but the timing sampling interval before the next sampling time has not yet ended. For example, in a motor drive system with a control cycle of 10 microseconds, after the calculation output is completed in the 5th microsecond of the current cycle, there is a 5-microsecond idle period that can be used for pre-calculation before the new sampling data arrives in the 10th microsecond of the next cycle.

[0043] In the pre-calculation, historical sampling data is a series of past sampling values ​​that have been stored before the current sampling period and do not include data for the current sampling period or future sampling periods. For example, in proportional-integral-derivative control, the current or voltage feedback values ​​collected in the first N control cycles.

[0044] Pre-computation independent of the sampling data in the next sampling period refers to the IP core performing calculations that do not depend on the values ​​of future new sampling points using only historical sampling data. For example, in a Fast Fourier Transform IP core, intermediate results of butterfly operations for twitch factors and historical data windows are pre-calculated and stored.

[0045] S22: In response to the arrival of the sampling data in the next sampling period, the processor core writes the sampling data of the next sampling period into the corresponding IP core. The corresponding IP core performs incremental calculations related to the sampling data of the next sampling period based on the pre-calculation results to obtain the final calculation results. The processor core obtains the final calculation results from the corresponding IP core and outputs control signals based on the final calculation results to control the power electronic device.

[0046] Once the analog-to-digital converter (ADC) completes the acquisition of the electrical signal for the next moment and generates new sampled data, the processor core directly transmits the new sampled data to the input register inside the corresponding IP core via the system bus, thereby triggering the IP core to perform incremental calculations based on the pre-calculated results.

[0047] When determining the corresponding IP core, the processor core can parse the data type tag carried by the newly sampled data and directly route it to the corresponding IP core based on the matching relationship between the data type tag and the IP core function identifier. For example, when the new sampled data is voltage phase angle data and carries a phase-locked loop (PLL) type tag, the processor core directly writes the data to the PLL core. When the new sampled data is an error signal and carries a proportional-integral-derivative (PI-DE) type tag, it directly routes to the PI-DE IP core. This eliminates the clock overhead of mapping table lookups, achieves zero-latency data distribution within a single cycle, and further improves real-time response speed.

[0048] Of course, the processor core can also determine the IP core corresponding to the newly sampled data by querying a preset algorithm-core mapping table, based on the algorithm chain configuration required for the current control cycle. This enables flexible configuration of the algorithm chain, allowing it to adapt to different power control application scenarios without modifying the hardware.

[0049] Upon receiving new sampled data, the IP core does not re-execute the complete algorithm. Instead, it only calculates the parts that depend on the new sampled data and directly reuses the pre-calculated results based on historical data, quickly combining the two to obtain the final output. For example, in the Fast Fourier Transform IP core, the pre-calculated twitch factor and the intermediate results of the butterfly operation of the historical data window are stored in the internal cache. When new sampled data arrives, the IP core only needs to substitute the new data into the last stage of the butterfly operation and perform complex multiplication and addition operations with the pre-calculated previous stage results to output the updated frequency domain result within a fixed two clock cycles, without having to re-execute the complete FFT pipeline.

[0050] The IP core uses two preset calculation formulas in its internal timing control module. The pre-calculation formula uses only historical sampled data as input variables, while the incremental calculation formula uses new sampled data and pre-calculation results as joint input variables. During runtime, the corresponding formula is automatically selected and called to perform the calculation based on the current working mode.

[0051] After the IP core completes the incremental calculation, it stores the final result in the output register of the bus interface module.

[0052] After the processor core reads the final calculation result from the output register through the system bus, it outputs a control signal based on the final calculation result to adjust the operating state of the power electronic device, so as to execute the corresponding power closed-loop control operation.

[0053] The following explanation uses a motor vector control scenario as an example. Assume the current control system contains three cascaded algorithmic components: PLL, PID, and SVGEN, each independently executed by its corresponding IP core. The pre-calculation of the PLL IP core can be based on historical phase information to pre-calculate the phase increment or synchronization angular velocity required for the next cycle. The incremental calculation combines the voltage phase observation of the current sampling cycle with the pre-calculated phase increment to obtain the precise synchronization phase angle and output it. After completing the incremental calculation of the PLL for the current sampling cycle, the processor core transmits the synchronization phase angle obtained by the PLL to the PID control IP core (e.g., for decoupling control used for coordinate transformation), triggering the PID control IP core to start incremental calculation (substituting the current cycle error into the PID formula to obtain the control quantity). Simultaneously, after completing the output of the current sampling cycle, the PLL IP core immediately enters an idle period and starts the pre-calculation for the next sampling cycle (pre-calculating the phase increment or synchronization angular velocity required for the next cycle). Subsequently, after completing the incremental calculation, the PID control IP core transmits its final control quantity to the SVGEN IP core to trigger the SVGEN's incremental calculation (modulating the control quantity into the final inverter switching signal). Simultaneously, the PID control IP core also initiates the next round of pre-calculation (pre-accumulating historical error integral terms). Similarly, after completing the incremental calculation and outputting the switching signal, the SVGEN IP core immediately initiates its next round of pre-calculation (pre-calculating the reference values ​​for the duty cycle of each phase voltage). In this way, the incremental calculation link of each IP core in the current sampling period and the pre-calculation preparation for the next sampling period overlap and run in parallel on the time axis. The minimum control cycle is determined by the greater of the total time consumed by the incremental calculation link and the time consumed by each pre-calculation. By decomposing the traditional serial complete calculation into a two-stage pipelined mode of pre-calculation during idle periods plus incremental calculation after new data arrives, the real-time response capability is improved.

[0054] After reading the final calculation result from the output register via the system bus, the processor core outputs control signals to regulate the operating state of power electronic devices based on the final calculation result. Power electronic devices encompass high-frequency real-time power control scenarios such as motor drive systems, grid-connected inverters, energy storage converters, and charging piles. Accordingly, the output control signals manifest as different physical execution actions in different application scenarios: in motor drives, they are space vector modulation signals that determine the conduction sequence of inverter switching devices; in grid-connected inverters, they are phase-locked signals and modulation wave signals that maintain grid synchronization; in energy storage converters, they are duty cycle control signals that regulate charging and discharging power; and in charging piles, they are feedback regulation signals that adjust output voltage and current. Regardless of the scenario, the control signals all originate from the final calculation result obtained by each IP core performing incremental calculations based on pre-calculated results. It is precisely by changing the way the final calculation result is produced that the real-time response capability is improved.

[0055] As can be seen from the above, the power chip control method provided in this application reduces the computational latency caused by the serial execution of all algorithm modules in the traditional architecture from linearly accumulating with the number of modules to a fixed small number of clock cycles that depend only on the incremental calculation during the idle period after the calculation task of the current sampling cycle of each IP core is completed and before the data of the next sampling cycle arrives. This significantly improves the real-time response capability of power closed-loop control and compresses the lower limit of the control cycle. At the same time, since the processor core only needs to perform data writing and result reading without participating in intensive calculations, it can significantly reduce the core load and system power consumption, reduce the dependence on high-performance general-purpose processor cores, and improve the autonomy and controllability of the chip architecture.

[0056] Furthermore, as a response to Figure 2 In a refinement and extension of the method shown, this application also provides a control method for a power chip.

[0057] Figure 3 This is a flowchart illustrating the control method of the power chip in the embodiments of this application. Figure 2 See Figure 3 As shown, the method may include: S31: Obtain the feature parameters of historical sampling data; dynamically configure the depth of the sliding window based on the feature parameters.

[0058] Historical sampling data refers to a series of past sampled values ​​stored prior to the current sampling period. Feature parameters are statistical quantities used to characterize the features of this historical sampling data.

[0059] The IP core continuously stores and updates historical sampling data through a sliding window or buffer queue, while the IP core calculates the feature parameters within the historical data window during verification.

[0060] By dynamically configuring the depth of the sliding window based on characteristic parameters, the IP core can adaptively adjust the scale of historical data required for pre-computation according to the actual signal characteristics, thereby achieving the optimal balance between computational accuracy and resource consumption under different operating conditions. This dynamic configuration allows the IP core to autonomously adapt to changes in operating conditions without relying on the intervention of an external processor, avoiding the shortcomings of a fixed window depth in unsuitable scenarios, which result in either insufficient accuracy or wasted resources.

[0061] It should be noted that the depth of the sliding window refers to the number of historical sampling data points that the window contains, i.e., the number of historical data points that each pre-calculation relies on.

[0062] In practical applications, the window depth can be set according to different types of feature parameters.

[0063] The characteristic parameters can include fluctuation characteristic parameters and sampling characteristic parameters.

[0064] Fluctuation characteristic parameters are quantitative indicators used to characterize the dispersion or drastic changes of historical sampled data sequences, reflecting the fluctuation of the controlled electrical quantity on the time axis. Examples include the cumulative sum of the absolute values ​​of the differences between adjacent sampling points within a historical data window, the variance, or the rate of change of amplitude.

[0065] Sampling characteristic parameters are quantitative indicators used to characterize the density of sampled data acquisition, and are usually directly related to the sampling frequency. For example, the sampling period value obtained by reading the system configuration register.

[0066] Specifically, step S31 above may include: S31a: In response to an increase in the fluctuation characteristic parameter, increase the depth of the sliding window.

[0067] The increase in the fluctuation characteristic parameter means that the dispersion of the historical sampling data sequence is aggravated, the signal fluctuation is more violent, and the controlled electrical quantity is in a non-stationary or strongly disturbed state. At this time, relying on only a small amount of historical data is easily affected by short-term spikes or random noise, which will lead to the distortion of the pre-calculation results. Therefore, it is necessary to increase the sliding window depth.

[0068] S31b: In response to an increase in the sampling feature parameters, increase the depth of the sliding window.

[0069] An increase in sampling characteristic parameters implies a higher sampling frequency, a shorter time interval between adjacent samples, and an increase in the number of data points collected per unit time. If the depth of the sliding window remains constant, the actual physical time span covered by the window will be correspondingly shortened (e.g., when the sampling frequency increases from 10kHz to 100kHz, the time span covered by the fixed 32-point window decreases from 3.2 milliseconds to 0.32 milliseconds). This results in the historical data used for pre-calculation being insufficient to reflect the changing trends of electrical quantities over a sufficiently long time scale. Therefore, it is necessary to increase the depth of the sliding window.

[0070] The increase here can refer to either a rise in the value of the fluctuation characteristic parameter or the sampling characteristic parameter relative to the previous moment or the initial value, or it can refer to the parameter exceeding a certain preset threshold.

[0071] When increasing the depth, the current fluctuation characteristic parameter can be compared with preset multi-level thresholds. When the parameter exceeds a certain threshold, the depth of the sliding window increases incrementally by a preset step size. For example, let the low threshold be 100, the medium threshold be 300, and the high threshold be 600. When the calculated fluctuation characteristic parameter is 250, it exceeds the low threshold but not the medium threshold, so the sliding window depth is increased from the default 32 points to 64 points. If the parameter reaches 450, exceeding the medium threshold, it is further increased to 128 points. If the parameter reaches 800, exceeding the high threshold, it is increased to 256 points.

[0072] Alternatively, the window depth can be continuously adjusted using a linear or nonlinear mapping function based on the magnitude of the fluctuation characteristic parameter. For example, suppose the relationship between the window depth D and the fluctuation characteristic parameter P is a linear function D=D min +k×P. D min The minimum depth is 32 points, and k is a preset coefficient. When P=100, D=32+0.2×100=52 points. When P=500, D=32+0.2×500=132 points, achieving a smooth and continuous change in window depth with the degree of fluctuation.

[0073] As the window depth increases, the data storage module automatically expands the storage space or uses a circular buffer to include more historical sampling points in subsequent pre-calculation, thereby providing more sufficient historical statistical information to smooth the pre-calculation results when the signal changes drastically.

[0074] When the fluctuation characteristic parameter decreases, it means the signal is becoming more stable and the disturbance is weakening. At this point, a deeper historical window is no longer necessary, and appropriately reducing the sliding window depth can save storage resources and pre-computation overhead. When the sampling characteristic parameter decreases, it means the sampling frequency is reduced and the interval between adjacent samples is increased. The physical time span covered by the fixed-depth window is sufficient or even too long. Continuing to maintain a deeper window may cause the data used for pre-computation to span too long a time interval, introducing outdated information, which will reduce the sensitivity of pre-computation to the current operating conditions. In this case, the sliding window depth should also be reduced accordingly.

[0075] The criteria for determining a decrease in the two feature parameters mentioned above are the same as those for determining an increase in the two feature parameters mentioned above. Furthermore, the method for decreasing the sliding window depth here corresponds to the method for increasing the sliding window depth mentioned above; please refer to the relevant explanations above, which will not be repeated here.

[0076] By actively reducing the window depth when the fluctuation characteristic parameter or sampling characteristic parameter decreases, the IP core can avoid redundant calculation and storage waste when the signal is flat or the sampling is sparse, and adjust to the appropriate depth in time during recovery, thus realizing bidirectional adaptive adjustment of the window depth.

[0077] Within each adjustment cycle, it can be first determined whether the fluctuation characteristic parameter or the sampling characteristic parameter has increased. If so, the depth of the sliding window is increased. If the characteristic parameter has not increased, or has decreased, no operation is performed, and the sliding window continues to maintain its current depth.

[0078] This method of prioritizing adjustments ensures that the window depth can only increase initially, and can only be gradually reduced after the operating conditions stabilize or improve. This avoids incorrectly performing reduction operations due to instantaneous fluctuations in characteristic parameters before the depth has increased, thereby improving the stability and resistance to transient interference in sliding window depth adjustment, and preventing the pre-calculation accuracy from deteriorating due to frequent erroneous depth reductions.

[0079] S32: Based on the current working mode, dynamically reconstruct the internal data path of the IP core; wherein, in response to being in pre-computation mode, the internal data path is reconstructed to connect only the historical sampling data path and the pre-computation operation path; in response to being in incremental computation mode, the internal data path is reconstructed to connect the new sampling data path, the pre-computation result path, and the incremental computation operation path simultaneously.

[0080] By dynamically reconstructing the internal data paths of the IP core according to the pre-computation mode and the incremental computation mode, the same hardware resource can activate only the required data paths in different working modes, thereby avoiding the dynamic power consumption waste caused by the signal flipping of irrelevant paths and ensuring that the operation path in each mode has the shortest data transmission latency.

[0081] The internal data path of an IP core refers to the set of physical signal connection paths between its various functional modules (including data storage module, arithmetic logic unit in core computing module, register array and bus interface module) for transmitting sampled data, pre-calculation results, configuration parameters and final output results. This path can selectively connect or disconnect the connection between different data sources and computing units according to the working mode.

[0082] In response to being in pre-computation mode, the timing control module switches the multiplexer in the internal data path to the output of the historical sampling data memory, so that the historical sampling data flows directly into the arithmetic logic unit corresponding to the pre-computation operation path, while disconnecting the new sampling data input from the incremental calculation operation unit.

[0083] In response to being in incremental calculation mode, the timing control module simultaneously connects the input terminal of the new sampled data and the output terminal of the pre-calculation result buffer to the multiplexer, so that both are fed into the arithmetic logic unit of the incremental calculation operation path and participate in the combined calculation of the final result.

[0084] Determining the current operating mode can be achieved using a state machine-based timing-driven strategy. This involves the IP core automatically switching to incremental calculation mode each time new sampled data arrives and automatically returning to pre-calculation mode after calculation. Alternatively, the current operating mode can be determined based on configuration bits in a dedicated mode control register written by the processor core through the bus interface module.

[0085] To enable the IP core to autonomously identify the consumption status of the current pre-computation results and automatically switch modes without processor kernel intervention, a validity flag can be used to indicate whether the pre-computation results stored locally have been used for incremental computation. When the flag indicates that the results have been used, the system enters the pre-computation mode; when it indicates that the results have not been used, the system enters the incremental computation mode and updates the flag after computation is completed.

[0086] Specifically, the IP core contains a validity flag, which indicates whether the pre-computed results stored locally have been used for incremental computation.

[0087] The validity flag is a single-bit register maintained internally by the IP core. Its initial value of 0 indicates that the pre-calculated result has not been used. After the incremental calculation is completed, the IP core automatically sets this bit to 1 to indicate that it has been used. It will be cleared to zero again when the next round of pre-calculation generates a new pre-calculation result.

[0088] Prior to step S32 above, the method may further include: S3201: In response to the validity flag indicating that it has been used for incremental calculation, determine that the current working mode is pre-calculation mode.

[0089] For example, suppose the validity flag inside a Fast Fourier Transform (FFT) IP core is currently set to 1, indicating that the pre-calculation result generated based on historical data has already been used in the incremental calculation step and the final result has been output. At this time, the timing control module of the IP core reads that the flag is 1, determines that a new round of pre-calculation has not yet started, and therefore sets the operating mode to pre-calculation mode. Based on the latest stored historical sampling data, it begins performing pre-calculation unrelated to the next sampling period, generating new pre-calculation results which are then temporarily stored in the internal cache.

[0090] S3202: In response to the validity flag indicating that it has not been used for incremental calculation, determine that the current working mode is incremental calculation mode, and update the validity flag to indicate that it has been used for incremental calculation after the incremental calculation is completed.

[0091] Continuing the example above, when new sampled data arrives but the IP core has not yet completed a new round of pre-calculation, the validity flag is still 0 (because the new pre-calculation result has just been generated but has not yet been used by incremental calculation). At this time, the timing control module reads that the flag is 0, determines that incremental calculation needs to be performed, and therefore switches the working mode to incremental calculation mode, sending the new sampled data and the generated pre-calculation result into the incremental calculation operation path. The final calculation is completed and the result is output within several clock cycles. After the output is completed, the IP core automatically updates the validity flag to 1, indicating that the pre-calculation result has been used, thereby triggering a new round of pre-calculation in the next idle period.

[0092] It should be noted that steps S31 and S32 can be executed simultaneously or asynchronously. When executed asynchronously, step S31 is executed first, followed by step S32. This avoids the need to reconfigure the reconstructed data path due to window depth adjustments, thereby reducing the number of path reconstructions and the risk of timing conflicts.

[0093] S33: For each IP core, after the calculation task of the current sampling period is completed and before the sampling data of the next sampling period arrives, historical data collected by a sliding window with dynamically configured depth is used to perform pre-calculation that is unrelated to the sampling data of the next sampling period, and the pre-calculation results are obtained.

[0094] Here, historical data can be collected based on a sliding window. Specifically, the data storage module inside the IP core maintains a fixed-depth circular sliding window, which stores the N most recent historical sampled data in chronological order. Each time new sampled data arrives and incremental calculation is completed, the new data is written to the window, overwriting the oldest data, thus achieving a rolling update of the window content. During the pre-computation phase, the core calculation module directly reads all N historical data sequentially from this sliding window and performs pre-computation according to the algorithm logic.

[0095] Furthermore, historical data can be collected based on a buffer queue. Specifically, the data storage module inside the IP core maintains a buffer queue with dynamically adjustable depth. The tail of the queue continuously receives and stores each newly arrived sampled data, while the head retains the oldest historical data. At the start of pre-computation, the core computing module reads historical data within a set depth range sequentially from the head of the queue without overwriting or moving other data in the queue.

[0096] To further improve the utilization efficiency of pre-computation resources during idle periods and shorten the overall pre-computation time in multi-algorithm scenarios, each IP core can be triggered to enter the pre-computation preparation state after the current sampling period is completed, and each IP core can execute its own pre-computation in parallel during the idle period before the next sampling data arrives.

[0097] Specifically, step S33 above may include: S33a: After the computation task of the current sampling period is completed, each IP core is triggered to enter the pre-computation preparation state.

[0098] After each IP core completes the incremental calculation and output of the result for the current sampling cycle, the timing control module or processor core sends a pre-computation trigger signal to all IP cores, causing them to transition from the idle or waiting state to the pre-computation preparation state. The pre-computation preparation state refers to a specific preparatory stage where the IP core has cleared the temporary intermediate values ​​from the previous cycle, prepared historical sampling data at the output of the data storage module, and activated the arithmetic logic unit corresponding to the pre-computation operation path, awaiting the start of the pre-computation operation.

[0099] S33b: Before the sampling data for the next sampling period arrives, each IP core performs pre-computations in parallel based on its stored historical sampling data, which are independent of the sampling data for the next sampling period.

[0100] During the idle period before the analog-to-digital converter completes the acquisition of the electrical signal for the next moment and generates new sampled data, multiple IP cores independently perform pre-computations unrelated to the new data in the next cycle, based on the historical sampled data stored in their internal data storage modules. Parallelism here means that the pre-computation operations of each IP core are executed completely overlappingly on the time axis, without waiting for or blocking each other. Each IP core independently occupies its internal arithmetic logic unit and data path, and the total pre-computation time depends on the pre-computation time of the single IP core with the longest execution time.

[0101] To further improve the timing determinism of parallel pre-computation of multiple IP cores under the constraints of limited bus bandwidth or shared memory resources, and to prioritize the completion window of pre-computation for critical path tasks, IP cores with longer execution times or higher priorities can be started earlier, and the pre-computation of each IP core can be partially overlapped on the time axis.

[0102] Specifically, step S33b above may include: S33b1: Determine the order of the pre-computation start times for each IP core based on the historical pre-computation time and / or real-time priority of the algorithm corresponding to each IP core. Among them, the IP core with longer pre-computation time or higher real-time priority is ranked earlier in the order, and the pre-computation of each IP core partially overlaps on the time axis.

[0103] Historical pre-computation time refers to the average number of clock cycles or time required for an IP core to complete a full pre-computation that is independent of the data from the next sampling cycle during its historical operation.

[0104] Real-time priority refers to the response urgency level pre-assigned to each IP core based on the timing constraints of the power control algorithm link.

[0105] In specific determination, the order can be based solely on historical pre-computation time or real-time priority. Taking historical pre-computation time as an example, the IP cores are sorted from largest to smallest according to the historical pre-computation time of their corresponding algorithms. The IP core with the longest pre-computation time starts pre-computation first, followed by the IP core with the second longest time, which starts after a preset time interval, and so on. This creates a partially overlapping pipeline execution pattern for the pre-computation of each IP core on the time axis. For example, if the historical pre-computation time of the Fast Fourier Transform (FFT) IP core is 120 clock cycles, the coordinate transformation IP core is 40 clock cycles, and the proportional-integral-differential (PI-DE) IP core is 20 clock cycles, then the startup order is as follows: the FFT IP core starts first, the coordinate transformation IP core starts 80 clock cycles after the FFT starts (at which point the remaining 40 cycles of the FFT overlap with the 40 cycles of the coordinate transformation), and the PI-DE IP core starts 20 clock cycles after the coordinate transformation starts.

[0106] Alternatively, the order can be determined by combining historical pre-calculation time and real-time priority. Specifically, a comprehensive scheduling weight is calculated for each IP core. This weight is determined by both historical pre-calculation time and real-time priority. IP cores with longer pre-calculation times and higher real-time priority receive higher scheduling weights, and the startup order is determined according to the weights from highest to lowest. For example, a phase-locked loop (PLL) IP core may have the highest real-time priority but a medium pre-calculation time (60 cycles), while a fast Fourier transform (FFT) IP core may have a very long pre-calculation time (120 cycles) but a lower priority. After comprehensive evaluation, the PLL IP core can still be started before the FFT IP core to ensure that the pre-calculation results of high real-time tasks can be completed as early as possible, avoiding high-priority tasks missing the pre-calculation window due to waiting for long-timed IP cores.

[0107] S33b2: Perform pre-calculations based on the historical sampling data stored in each sample period in chronological order, without regard to the sampling data of the next sampling period.

[0108] According to the determined IP core startup order, the scheduling control module sequentially triggers each IP core to start its own pre-computation operation on the time axis. When the start time of each IP core is triggered, it immediately starts pre-computation based on the historical sampling data stored in its internal storage, which is unrelated to the new data of the next cycle.

[0109] S34: In response to the arrival of the sampled data in the next sampling period, the processor core writes the sampled data of the next sampling period into the corresponding IP core. The corresponding IP core performs incremental calculations related to the sampled data of the next sampling period based on the pre-calculation results to obtain the final calculation results.

[0110] Step S34 here is implemented in the same way as step S22 in the previous embodiment. Please refer to the relevant description in the previous embodiment. It will not be repeated here.

[0111] After each IP core completes incremental computation and outputs the final result, in order to further improve the pipeline parallelism of the IP core in the two stages of pre-computation and result output, and to avoid mutual exclusion waiting between the processor core reading the result and the IP core executing the next round of pre-computation, the internal storage structure of the IP core can be optimized as follows.

[0112] The IP core includes a data storage module and a bus interface module. The bus interface module includes an output register. The data storage module and the output register are independent storage spaces that support parallel read and write operations.

[0113] The data storage module inside the IP core (used to store historical sampled data, pre-calculated results, and intermediate state variables) and the output register in the bus interface module (used to temporarily store the final calculation results for the processor core to read) are independent of each other in terms of physical address space and read / write control logic. This allows the processor core to read the calculation results of the previous cycle from the output register in parallel while the IP core performs pre-calculation and writes to the data storage module, without the two blocking each other.

[0114] S35: Store the pre-calculated results into the data storage module.

[0115] The pre-calculation results are immediately stored in the dedicated pre-calculation area or public pre-calculation area in the data storage module after the pre-calculation stage is completed.

[0116] To further improve the efficiency of reusing pre-computation results and reduce redundant computation in multi-IP core scenarios with data dependencies, the data storage module can be divided into a common pre-computation area and a dedicated pre-computation area.

[0117] Specifically, step S35 above may include: S351: In response to the fact that the pre-computation result of the first IP core is relied upon by the computation of the second IP core, the first IP core stores its own pre-computation result in the common pre-computation area and sets a shared identifier for the second IP core.

[0118] The pre-calculation results of the first IP core are relied upon by the calculations of the second IP core. This means that when the second IP core performs its own incremental calculations, it needs to directly use the pre-calculation results already completed by the first IP core as part of its input data. For example, the pre-calculation results of the coordinate transformation IP core (such as the trigonometric function values ​​corresponding to the rotation angle required for the Park transformation) are relied upon by the subsequent proportional-integral-differential IP core in its incremental calculations. The proportional-integral-differential IP core needs this angle information to correctly calculate the decoupled current error control quantity.

[0119] In response to the fact that the pre-calculation result of the first IP core is dependent on the calculation of the second IP core, after the first IP core completes its own pre-calculation, it writes its pre-calculation result into the common pre-calculation area in the data storage module through the internal data bus. At the same time, it sets a shared identifier pointing to the second IP core in the shared identifier register corresponding to the common pre-calculation area (for example, writing the number or mask of the target IP core into the identifier bit to indicate that the pre-calculation result is allowed to be accessed by the second IP core).

[0120] The shared identifier can be in the form of a bitmap, with each bit corresponding to an IP core. The first IP core sets the bit corresponding to the second IP core to 1, while keeping the remaining bits 0, thereby realizing targeted shared access control.

[0121] S352: The second IP core obtains the pre-computation result of the first IP core from the public pre-computation area based on the shared identifier and performs calculations.

[0122] Before starting its own incremental computation, the second IP core first reads the shared identifier in the public pre-computation area to determine whether the identifier contains an access permission pointing to itself. If the bit corresponding to the second IP core in the shared identifier is 1, the second IP core reads the pre-computation result stored by the first IP core from the public pre-computation area through the system bus or internal dedicated data channel, and uses it as part of the input data for its own incremental computation, participating in the calculation together with its own newly sampled data and other intermediate variables.

[0123] After reading, the second IP core can choose to clear its own access permission bit from the corresponding shared identifier to improve the management accuracy and resource reclamation efficiency of the shared identifier, and avoid redundant judgment overhead caused by the same pre-calculated result being read repeatedly by the same IP core. Alternatively, it can retain the identifier for subsequent reading by other IP cores, realizing one-to-many broadcast sharing and reuse.

[0124] S36: The final calculation result is stored in the output register. The processor core obtains the final calculation result from the corresponding IP core and outputs a control signal based on the final calculation result to control the power electronic device.

[0125] The final calculation result is stored in the output register immediately after the incremental calculation is completed. The pre-calculation result and the final calculation result are stored in different time windows and use independent storage spaces.

[0126] The processor core then reads the final calculation result from the output register via the system bus and uses it for subsequent control decisions. For example, it updates the pulse width modulation (PWM) duty cycle or uses it as a reference input for the next control cycle.

[0127] To more clearly illustrate the hardware foundation upon which the above method embodiments rely, as well as the connection relationships and functional divisions between the constituent units, the basic framework of the power chip architecture and the dedicated algorithm IP cores contained therein, provided in the embodiments of this application, will be explained again.

[0128] Figure 4 This is a schematic diagram of the power chip structure in the embodiments of this application. Figure 2 See Figure 4 As shown, the power chip includes a processor core, multiple power-specific algorithm IP cores, and multiple general-purpose peripherals.

[0129] The processor core is based on a reduced instruction set architecture and is used to execute control instructions and schedule tasks. Power-specific algorithm IP cores are connected to the processor core via the system bus. Each power-specific algorithm IP core performs a specific power control operation. These IP cores include one or more of the following: FFT IP core, digital filter IP core, coordinate transformation IP core, SVGEN IP core, PID IP core, PLL IP core, and RMS calculation IP core.

[0130] General-purpose peripherals are connected to the processor core via the system bus and are used to perform data acquisition and communication functions. General-purpose peripherals include one or more of the following: ADC, Inter-Integrated Circuit (I2C) interface, Universal Asynchronous Receiver / Transmitter (UART), PWM module, Controller Area Network (CAN) interface, Watchdog Timer (WDT), and Input / Output (IO) interface.

[0131] Among them, the ADC is used to collect electrical signals of power electronic devices to generate sampling data, the PWM module is used to generate switching signals to drive power electronic devices according to the control signals output by the processor core, the CAN interface is used to transmit control commands and operating status data, the WDT is used to monitor the system operating status and output a reset signal in case of abnormality, and the IO interface is used to collect external signals and output control signals.

[0132] Figure 5 This is a schematic diagram of the structure of the power-specific algorithm IP core in the embodiments of this application. See also: Figure 5 As shown, the specific framework of this power-specific algorithm IP core includes: The bus interface module is used to receive standard format data and configuration instructions from the processor core, parse and convert them into internal computing tasks, and package the internal calculation results back to the processor core according to the standard bus protocol.

[0133] The core computing module is used to perform arithmetic and logical operations for corresponding power-specific algorithms (such as fast Fourier transform, digital filtering, coordinate transformation, proportional-integral-derivative control, etc.).

[0134] The data storage module is used to store historical data and intermediate state variables required during the operation of this IP core in the form of a sliding window or a buffer queue.

[0135] The timing control module is used to schedule and prioritize historical data budgeting, current data increment calculation, and result output, and dynamically reconstruct the internal data path according to the current working mode.

[0136] To more clearly illustrate the execution speed advantage brought about by the above method embodiments, Figure 6 This is a schematic diagram comparing the power chip and the general-purpose processor in the closed-loop algorithm execution flow in the embodiments of this application. See [link / reference]. Figure 6 As shown, taking a closed-loop algorithm consisting of three sub-algorithms as an example, A', B', and C' are the pre-calculation processes related to historical data in each sub-algorithm, and A, B, and C are the incremental calculation processes related to new data at the current sampling point in each sub-algorithm. Figure 6 The upper part illustrates the computational flow of a general-purpose processor. Within a single control cycle, all operations need to be computed sequentially (i.e., A, B, C, and the necessary complete operations within each algorithm are executed in order). The minimum control cycle of the entire chip is equal to the total time required to execute all algorithms. Figure 6 The lower half illustrates the calculation process of an embodiment of this application. After completing the incremental calculations (A, B, C) related to the current sampling point, the data pre-calculation (A', B', C') for the next sampling point is immediately started during the idle period.

[0137] In practical applications, processes A, B, and C are extremely short, typically completed within one to several clock cycles, while processes A', B', and C' can be performed independently without interference. The minimum control cycle of the entire chip is determined by the greater of the sum of the incremental calculation times of each sub-algorithm and the maximum value of the pre-calculation times of each sub-algorithm. In typical power control scenarios, since pre-calculation only involves offline processing of historical data, its single-step time is usually less than the cumulative time of multiple incremental calculation stages. Figure 6 As can be seen, the embodiments of this application can achieve a shorter control cycle and a significant improvement compared to general processor architectures. At the same time, it can minimize the chip's dependence on high-performance processor cores and achieve higher control performance with lower-performance cores.

[0138] This concludes the description of the control method for the power chip provided in the embodiments of this application.

[0139] Based on the same inventive concept, this application also provides a power chip.

[0140] See also Figure 1 As shown, the power chip 10 may include a processor core 11 and multiple IP cores 12. The IP cores 12 are electrically connected to the processor core 11, and each IP core 12 is used to perform a power control operation.

[0141] Each IP core has 12 cores and is used to perform pre-calculations based on historical sampling data, which are unrelated to the sampling data of the next sampling period, after the calculation task of the current sampling period is completed and before the sampling data of the next sampling period arrives, to obtain the pre-calculation results.

[0142] Processor core 11 is used to write the sampled data of the next sampling period to the corresponding IP core 12 in response to the arrival of the sampled data of the next sampling period.

[0143] The corresponding IP core 12 is used to perform incremental calculations related to the sampling data of the next sampling period based on the pre-calculation results, and obtain the final calculation results.

[0144] The processor core 11 is used to obtain the final calculation result from the corresponding IP core 12 and output control signals based on the final calculation result to control the power electronic device.

[0145] Furthermore, each IP core 12 is used to trigger each IP core 12 to enter the pre-computation preparation state after the computation task of the current sampling period is completed; before the sampling data of the next sampling period arrives, each IP core 12 performs pre-computation in parallel based on its own stored historical sampling data, which is unrelated to the sampling data of the next sampling period.

[0146] Furthermore, each IP core 12 is used to determine the order of the start time of the pre-computation of each IP core 12 based on the historical pre-computation time and / or real-time priority of the algorithm corresponding to each IP core 12; wherein, the IP core 12 with longer pre-computation time or higher real-time priority is ranked earlier in the order, and the pre-computation of each IP core 12 is partially overlapped on the time axis; according to the order, pre-computation unrelated to the sampling data of the next sampling period is performed sequentially based on the historical sampling data stored by each IP core 12.

[0147] Furthermore, each IP core 12 is used to acquire feature parameters of historical sampling data; dynamically configure the depth of the sliding window according to the feature parameters; and use the historical data acquired by the sliding window with the dynamically configured depth to perform pre-calculations that are unrelated to the sampling data of the next sampling period.

[0148] Furthermore, the feature parameters include fluctuation feature parameters and sampling feature parameters; each IP core 12 is used to increase the depth of the sliding window in response to an increase in the fluctuation feature parameters; and to increase the depth of the sliding window in response to an increase in the sampling feature parameters.

[0149] Furthermore, each IP core 12 is used to dynamically reconstruct the internal data path of the IP core 12 according to the current working mode; wherein, in response to being in the pre-computation mode, the internal data path is reconstructed to connect only the historical sampling data path and the pre-computation operation path; in response to being in the incremental computation mode, the internal data path is reconstructed to connect the new sampling data path, the pre-computation result path and the incremental computation operation path simultaneously.

[0150] Furthermore, IP core 12 includes a validity flag bit, which is used to indicate whether the pre-calculation result stored locally has been used for incremental calculation. Each IP core 12 is used to determine the current working mode as pre-calculation mode in response to the validity flag bit indicating that it has been used for incremental calculation; and to determine the current working mode as incremental calculation mode in response to the validity flag bit indicating that it has not been used for incremental calculation, and to update the validity flag bit to indicate that it has been used for incremental calculation after the incremental calculation is completed.

[0151] Furthermore, IP core 12 includes a data storage module and a bus interface module. The bus interface module includes an output register. The data storage module and the output register are independent storage spaces that support parallel read and write operations. Each IP core 12 is used to store the pre-calculated results into the data storage module and store the final calculation results into the output register for the processor core 11 to read.

[0152] Furthermore, the data storage module includes a public pre-computation area and a dedicated pre-computation area. The public pre-computation area is used to store pre-computation results that are shared and accessed by multiple IP cores 12, while the dedicated pre-computation area is used to store pre-computation results that are only used by this IP core 12. Each IP core 12 is configured to store its own pre-computation results in the public pre-computation area and set a sharing identifier for the second IP core 12 when the pre-computation results of the first IP core 12 are dependent on the calculation of the second IP core 12. The second IP core 12 then retrieves the pre-computation results of the first IP core 12 from the public pre-computation area based on the sharing identifier and performs calculations.

[0153] It should be noted that the description of the chip embodiments above is similar to the description of the method embodiments above, and has similar beneficial effects. For technical details not disclosed in the chip embodiments of this application, please refer to the description of the method embodiments of this application for understanding.

[0154] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A control method for a power chip, characterized in that, The method is applied to a power chip, the power chip including a processor core and multiple intellectual property (IP) cores, the IP cores being electrically connected to the processor core, and each IP core being used to perform a power control operation; the method includes: For each IP core, after the computation task of the current sampling period is completed and before the sampling data of the next sampling period arrives, a pre-computation is performed based on the historical sampling data, which is unrelated to the sampling data of the next sampling period, to obtain the pre-computation result; In response to the arrival of sampled data in the next sampling period, the processor core writes the sampled data of the next sampling period into the corresponding IP core. The corresponding IP core performs incremental calculations related to the sampled data of the next sampling period based on the pre-calculation result to obtain the final calculation result. The processor core obtains the final calculation result from the corresponding IP core and outputs a control signal based on the final calculation result to control the power electronic device.

2. The method according to claim 1, characterized in that, For each IP core, after the computation task of the current sampling period is completed and before the sampling data of the next sampling period arrives, a pre-computation unrelated to the sampling data of the next sampling period is performed based on historical sampling data, including: After the computation task of the current sampling period is completed, each of the IP cores is triggered to enter the pre-computation preparation state; Before the sampling data for the next sampling period arrives, each of the IP cores performs pre-calculations in parallel based on its stored historical sampling data, which are independent of the sampling data for the next sampling period.

3. The method according to claim 2, characterized in that, Each of the IP cores performs pre-calculations in parallel based on its stored historical sampling data, independent of the sampling data for the next sampling period, including: Based on the historical pre-computation time and / or real-time priority of the algorithm corresponding to each IP core, the order of the pre-computation start time of each IP core is determined; wherein, the IP core with longer pre-computation time or higher real-time priority is ranked earlier in the order, and the pre-computation of each IP core is partially overlapped on the time axis. In the aforementioned order, pre-calculations unrelated to the sampling data of the next sampling period are performed sequentially based on the historical sampling data stored in each period.

4. The method according to claim 1, characterized in that, Before performing pre-calculations based on historical sampling data that are unrelated to the sampling data of the next sampling period, the method further includes: Obtain the feature parameters of the historical sampling data; The depth of the sliding window is dynamically configured based on the aforementioned feature parameters; The pre-calculation based on historical sampling data, which is independent of the sampling data of the next sampling period, includes: Historical data collected using a sliding window with dynamically configured depth is used for pre-calculation that is independent of the sampling data in the next sampling period.

5. The method according to claim 4, characterized in that, The feature parameters include fluctuation feature parameters and sampling feature parameters; the step of dynamically configuring the depth of the sliding window based on the feature parameters includes: In response to an increase in the fluctuation characteristic parameter, the depth of the sliding window is increased; In response to an increase in the sampling feature parameters, the depth of the sliding window is increased.

6. The method according to claim 1, characterized in that, Before performing pre-calculations based on historical sampling data that are unrelated to the sampling data of the next sampling period, the method further includes: Based on the current working mode, the internal data path of the IP core is dynamically reconstructed; wherein, in response to being in pre-computation mode, the internal data path is reconstructed to connect only the historical sampling data path and the pre-computation operation path; in response to being in incremental computation mode, the internal data path is reconstructed to connect the new sampling data path, the pre-computation result path, and the incremental computation operation path simultaneously.

7. The method according to claim 6, characterized in that, The IP core includes a validity flag, which indicates whether the pre-calculated results stored locally have been used for incremental computation. Before dynamically reconstructing the internal data path of the IP core according to the current operating mode, the method further includes: In response to the validity flag indicating that it has been used for incremental calculation, the current working mode is determined to be the pre-calculation mode; In response to the validity flag indicating that it has not been used for incremental calculation, the current working mode is determined to be incremental calculation mode, and after the incremental calculation is completed, the validity flag is updated to indicate that it has been used for incremental calculation.

8. The method according to any one of claims 1 to 7, characterized in that, The IP core includes a data storage module and a bus interface module. The bus interface module includes an output register. The data storage module and the output register are independent storage spaces that support parallel read and write operations. The method further includes: The pre-calculation results are stored in the data storage module; The final calculation result is stored in the output register for the processor core to read.

9. The method according to claim 8, characterized in that, The data storage module includes a public pre-computation area and a dedicated pre-computation area. The public pre-computation area is used to store pre-computation results that are shared and accessed by multiple IP cores, while the dedicated pre-computation area is used to store pre-computation results that are only used by this IP core. After obtaining the pre-calculated results, the method further includes: In response to the fact that the pre-computation result of the first IP core is dependent on the computation of the second IP core, the first IP core stores its own pre-computation result in the public pre-computation area and sets a shared identifier for the second IP core; The second IP core performs calculations based on the shared identifier, obtaining the pre-calculation result of the first IP core from the public pre-calculation area.

10. A power chip, characterized in that, The power chip includes a processor core and multiple intellectual property (IP) cores, the IP cores being electrically connected to the processor core, and each IP core being used to perform a power control operation. Each of the IP cores is used to perform pre-calculations based on historical sampling data, which are unrelated to the sampling data of the next sampling period, after the calculation task of the current sampling period is completed and before the sampling data of the next sampling period arrives, to obtain the pre-calculation results; The processor core is configured to write the sampled data of the next sampling period into the corresponding IP core in response to the arrival of the sampled data of the next sampling period; The corresponding IP core is used to perform incremental calculations related to the sampling data of the next sampling period based on the pre-calculation results, so as to obtain the final calculation results; The processor core is used to obtain the final calculation result from the corresponding IP core and output a control signal based on the final calculation result to control the power electronic device.

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