Dynamic hybrid access memory and reconfigurable computing system

Abstract

The application relates to a dynamic hybrid access memory and a reconfigurable computing system; the dynamic hybrid access memory is used for obtaining a target access mode indicated by an access mode configuration instruction, configuring a storage area in the dynamic hybrid access memory according to the target access mode, and performing data access on the storage area in the dynamic hybrid access memory according to the target access mode in the case that an access request corresponding to the access mode configuration instruction is received; the dynamic hybrid access memory comprises at least two storage areas; the dynamic hybrid access memory is configured according to a target access mode indicated by a mode configuration instruction, and subsequent data access on the storage area is performed according to the target access mode, so that on-demand switching of different access modes is realized, different application requirements are adapted, data access is matched with application requirements, bandwidth utilization is improved, and memory access delay is reduced.

Description

Technical Field

[0001] This application relates to the field of reconfigurable computing technology, and in particular to dynamic hybrid access memory and reconfigurable computing systems. Background Technology

[0002] Coarse-Grained Reconfigurable Architecture (CGRA) is a heterogeneous acceleration architecture that lies between application-specific integrated circuits (ASICs) and general-purpose processors. It can perform a variety of data processing tasks such as matrix computation, graph processing, and data stream processing.

[0003] As the core hub for data interaction in the CGRA system, the shared memory's memory access mechanism directly determines the overall system efficiency.

[0004] In related technologies, the shared memory in CGRA systems typically adopts a uniform random access method, which has poor adaptability to different data processing tasks, resulting in low bandwidth utilization and high memory access latency, thereby limiting system performance. Summary of the Invention

[0005] Therefore, it is necessary to provide a dynamic hybrid access memory and a reconfigurable computing system to address the aforementioned technical problems.

[0006] In a first aspect, this application provides a dynamic hybrid access memory for:

[0007] Retrieve the target access mode indicated by the access mode configuration directive;

[0008] The memory regions in the dynamic hybrid access memory are configured according to the target access mode; the dynamic hybrid access memory includes at least two memory regions.

[0009] Upon receiving an access request corresponding to an access mode configuration instruction, data access is performed on the storage area in the dynamic hybrid access memory according to the target access mode.

[0010] In one embodiment, when the target access mode is a double-buffered mode, configuring the storage regions in the dynamic hybrid access memory according to the target access mode includes:

[0011] A first buffer and a second buffer are defined in a dynamic hybrid access memory; both the first buffer and the second buffer include at least one storage area.

[0012] Configure the first buffer and the second buffer for data writing and data reading, respectively.

[0013] In one embodiment, data access to a storage region in a dynamic hybrid access memory is performed according to a target access mode, including:

[0014] If an access request indicates that data should be written, a write buffer configured for data writing is determined in the first buffer and the second buffer, and data is written in the write buffer.

[0015] If an access request indicates that data should be read, a read buffer configured for data reading is determined in the first buffer and the second buffer, and data is read from the read buffer.

[0016] The configurations of the first and second buffers are periodically switched.

[0017] In one embodiment, when the target access mode is a single-instruction multi-threaded mode, the storage regions in the dynamic hybrid access memory are configured according to the target access mode, including:

[0018] A multi-threaded buffer is defined in a dynamically mixed access memory; the multi-threaded buffer includes at least one storage region;

[0019] The configuration information for the corresponding target access mode is stored in the storage area of ​​the multi-threaded buffer.

[0020] In one embodiment, data access to a storage region in a dynamic hybrid access memory is performed according to a target access mode, including:

[0021] In response to the configuration transfer request from the data controller, the configuration information is sent to the data control module. The configuration information includes at least one piece of configuration data and its corresponding quantity. The data control module is used to copy each piece of configuration data into the corresponding quantity of configuration data through the data copying unit and send it to the corresponding processing unit in the processing unit array.

[0022] In response to access requests sent by each processing unit based on configuration data, data access is performed on the storage area in the multi-threaded buffer.

[0023] In one embodiment, when the target access mode is a streaming first-in-first-out mode, configuring the storage regions in the dynamic hybrid access memory according to the target access mode includes:

[0024] A streaming buffer is defined in a dynamically mixed access memory; the streaming buffer includes at least one storage region;

[0025] Configure write pointers and read pointers for each storage area in the streaming buffer; the write pointer is used to point to the data writing position, and the read pointer is used to point to the data reading position.

[0026] In one embodiment, data access to a storage region in a dynamic hybrid access memory is performed according to a target access mode, including:

[0027] If an access request indicates that data should be written to a storage area in the streaming buffer, read the data write position pointed to by the write pointer of the indicated storage area, write the data at the data write position, and update the data write position pointed to by the write pointer.

[0028] When an access request indicates that data should be read from a storage area in the streaming buffer, the system reads the data read position pointed to by the read pointer of the indicated storage area, reads the data at the data read position, and updates the data read position pointed to by the read pointer.

[0029] In one embodiment, when the target access mode is a row-buffered mode, configuring the storage regions in the dynamic hybrid access memory according to the target access mode includes:

[0030] In a dynamically mixed access memory, a row buffer is defined; the row buffer includes at least one storage region.

[0031] Configure write pointers and read pointers for each storage area in the row buffer; the write pointer is used to point to the data writing position, and the read pointer is used to point to the data reading position.

[0032] Configure the row buffer as a contiguous storage area to store consecutive rows of data.

[0033] In one embodiment, data access to a storage region in a dynamic hybrid access memory is performed according to a target access mode, including:

[0034] When an access request indicates that data should be written to the storage area of ​​the row buffer, consecutive rows of data in the required row data group are written to consecutive storage areas in the row buffer.

[0035] When writing data to any storage area in the row buffer, read the data write position pointed to by the write pointer of the storage area, write the data at the data write position, and update the data write position pointed to by the write pointer.

[0036] If an access request indicates that data should be read from the storage area of ​​the row buffer, the target row data should be read from the storage area where the target row data is stored after the target row data has been written.

[0037] When reading data from any storage area in the row buffer, the data is read from the data read position pointed to by the read pointer of the storage area, the data is read from the data read position, and the data read position pointed to by the read pointer is updated.

[0038] In a second aspect, this application also provides a reconfigurable computing system, comprising: at least one processing unit array and at least one dynamic hybrid access memory as described in the first aspect; any processing unit in the processing unit array can be used to access data in a storage region of the dynamic hybrid access memory.

[0039] In the aforementioned dynamic hybrid access memory and reconfigurable computing system, the target access mode indicated by the access mode configuration instruction is obtained, the storage area in the dynamic hybrid access memory is configured according to the target access mode, and upon receiving an access request corresponding to the access mode configuration instruction, data access is performed on the storage area in the dynamic hybrid access memory according to the target access mode. The dynamic hybrid access memory includes at least two storage areas. The aforementioned dynamic hybrid access memory configures the storage areas in the dynamic hybrid access memory according to the target access mode indicated by the mode configuration instruction, and subsequently performs data access on the storage areas according to the target access mode, so as to realize on-demand switching of different access modes, adapt to different application requirements, achieve matching between data access and application requirements, thereby improving bandwidth utilization, reducing memory access latency, and improving system operating performance. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a schematic diagram of the structure of a reconfigurable computing system in one embodiment;

[0042] Figure 2 This is a flowchart illustrating a data access control method in one embodiment;

[0043] Figure 3 This is a flowchart illustrating the configuration of a storage area in one embodiment;

[0044] Figure 4 This is a schematic diagram of the configuration corresponding to the double buffering mode in one embodiment;

[0045] Figure 5 This is a schematic diagram of the data access process to the storage area in one embodiment;

[0046] Figure 6 This is a flowchart illustrating the configuration of a storage area in another embodiment;

[0047] Figure 7This is a configuration diagram of a single instruction multithreaded mode in one embodiment;

[0048] Figure 8 This is a schematic diagram of the data access process to the storage area in another embodiment;

[0049] Figure 9 This is a flowchart illustrating the configuration of a storage area in another embodiment;

[0050] Figure 10 This is a schematic diagram of the configuration of a corresponding streaming first-in-first-out mode in one embodiment;

[0051] Figure 11 This is a schematic diagram of the data access process to the storage area in another embodiment;

[0052] Figure 12 This is a flowchart illustrating the configuration of a storage area in another embodiment;

[0053] Figure 13 This is a schematic diagram illustrating the configuration of the corresponding row buffer mode in one embodiment;

[0054] Figure 14 This is a schematic diagram of the data access process to the storage area in another embodiment;

[0055] Figure 15 This is a flowchart illustrating the data access control method in another embodiment;

[0056] Figure 16 This is a structural block diagram of a data access control device in one embodiment. Detailed Implementation

[0057] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0058] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.

[0059] The dynamic hybrid access memory provided in this application embodiment can be applied to, for example... Figure 1The reconfigurable computing system shown is a CGRA system, which includes at least one Processing Element Array (PEA), at least one Dynamic Hybrid Access Memory (DHMemory), and a Data Control module. The Processing Element (PE) is the basic execution unit within the PEA, capable of accessing data in the DHMemory to perform data processing tasks.

[0060] In this embodiment, the dynamic hybrid access memory can also be referred to as shared memory (SM). SM includes multiple physical storage areas (banks), also known as storage volumes, used to store data.

[0061] The data control module is used to uniformly schedule access requests from PEA, SM, and external Direct Memory Access (DMA) controllers, and to sort and distribute multi-source requests through a round-robin arbiter. All data reads and writes to the SM in the CGRA system must pass through the data control module.

[0062] For example, the PE in PEA can include various types. For example, the PE can be a Load / Store Unit (LSU) or an Arithmetic Logic Unit (ALU).

[0063] SM supports multiple access modes and allows flexible switching between them based on application requirements. It also allows different banks to be configured with independent access modes, thus supporting mixed access within the same hardware architecture. Furthermore, different banks within SM can be configured with different access modes to achieve mixed access.

[0064] The SM may include a first buffer and a second buffer for implementing a double-buffered mode. Both the first and second buffers include at least one bank. One of the first and second buffers is configured for data writing, and the other is configured for data reading, with the functions switching periodically. The buffer configured for data writing is used to write data, and the buffer configured for data reading is used to read data.

[0065] The SM may also include a multi-threaded buffer for implementing a single-instruction multi-threaded mode. This multi-threaded buffer includes at least one Bank. The Bank in the multi-threaded buffer can be used to store configuration information for the PEs in the PEA to execute multi-threaded parallel tasks, and to send this configuration information to the data copying unit in the data control module to copy the configuration data in the configuration information as needed, and then send the copied configuration data to the corresponding PEs.

[0066] The Streaming Module (SM) may also include a streaming buffer for implementing a streaming first-in-first-out (FIFO) mode. This streaming buffer includes at least one Bank. Each Bank in the streaming buffer is configured with independent write and read pointers. The write pointer points to a data write position, and the read pointer points to a data read position. For any Bank in the streaming buffer, the SM can read the data write position pointed to by the write pointer of that Bank to write the received data stream at that position, and automatically increment the write pointer after the write is complete to update the data write position pointed to by the write pointer. The SM can also read the data write position pointed to by the write pointer of that Bank to write the received data stream at that position, and automatically increment the write pointer after the write is complete to update the data write position pointed to by the write pointer.

[0067] The SM may also include a row buffer for implementing a row-buffered mode, which comprises at least two banks. Similar to the streaming buffer described above, each bank in this row buffer is configured with independent write and read pointers, and consecutive adjacent banks in the row buffer are used to store consecutive rows of data. Once a row of data in any bank of the row buffer has been completely written, that row of data can be read, and new row data can be written simultaneously.

[0068] In one exemplary embodiment, such as Figure 2 As shown, a dynamic hybrid access memory (SM) is provided, which can implement a data access control method, including the following steps:

[0069] S210. Obtain the target access mode indicated by the access mode configuration instruction.

[0070] The target access mode is one of the data access modes supported by SM. For example, the target access mode can be any of the following: Double Buffer mode, Single Configuration Multi-Thread (SCMT) mode, Streaming FIFO mode, and Line-Buffer mode.

[0071] Optionally, the SM can receive access mode configuration instructions sent by the upper-level controller through the data control module, and parse the access mode configuration instructions to obtain the target access mode indicated by the access mode configuration instructions.

[0072] For example, the upper-level controller can be a CPU.

[0073] S220. Configure the storage regions in the dynamic hybrid access memory according to the target access mode; the dynamic hybrid access memory includes at least two storage regions.

[0074] In this context, a Bank is a physical storage area defined in SM. Each Bank can be configured with an access mode independently. The access modes configured for different Banks can be the same or different.

[0075] Optionally, the SM can configure the Bank according to the target access mode, and the configured Bank will subsequently implement data reading and writing according to the data access method corresponding to the target access mode.

[0076] For example, SM can configure the Bank using the Bank Mode module based on the target access mode.

[0077] S230. Upon receiving an access request corresponding to the access mode configuration instruction, perform data access on the storage area in the dynamic hybrid access memory according to the target access mode.

[0078] It should be noted that when the data control module sends the access mode configuration command to the SM, it will also send the access mode configuration command to the PEA, so that the PE can initiate the access request corresponding to the access mode configuration command to the SM.

[0079] Optionally, the SM receives the access request corresponding to the access mode configuration instruction sent by the PE, so as to access the Bank in the SM according to the data access method corresponding to the target access mode.

[0080] In this embodiment, the provided dynamic hybrid access memory is used to obtain the target access mode indicated by the access mode configuration instruction, configure the storage area in the dynamic hybrid access memory according to the target access mode, and, upon receiving an access request corresponding to the access mode configuration instruction, access the storage area in the dynamic hybrid access memory according to the target access mode. The dynamic hybrid access memory includes at least two storage areas. In the aforementioned dynamic hybrid access memory, the storage area in the dynamic hybrid access memory is configured according to the target access mode indicated by the mode configuration instruction, and subsequently, the storage area is accessed according to the target access mode. This enables on-demand switching of different access modes to adapt to different application requirements, achieve matching between data access and application requirements, thereby improving bandwidth utilization, reducing memory access latency, and improving system performance.

[0081] Double buffering is suitable for applications that require simultaneous computation and loading of large amounts of data, such as matrix calculations. In one embodiment where the target access mode is double buffering, for example... Figure 3 As shown, the configuration of the storage region in the dynamic hybrid access memory according to the target access mode in S220 includes:

[0082] S310. Determine a first buffer and a second buffer in the dynamic mixed access memory; both the first buffer and the second buffer include at least one storage area.

[0083] The first buffer and the second buffer are two sets of equivalent logical buffers. Each set of buffers includes several banks and provides a unified address access interface.

[0084] Optionally, when the target access mode is a double buffer mode, the SM can divide a first buffer including at least one Bank and a second buffer including at least one Bank.

[0085] For example, such as Figure 4 As shown, Bank0 to Bank3 can be divided into the first buffer (Ping Buffer), and Bank4 to Bank7 can be divided into the second buffer (Pong Buffer).

[0086] S320. Configure the first buffer and the second buffer for data writing and data reading, respectively.

[0087] The buffer configured for data writing is used to receive incoming data input, enabling data writing. The buffer configured for data reading is used to provide data externally, enabling data reading.

[0088] Optionally, after determining the first buffer and the second buffer, the SM can write the function configuration data of one of the first buffer and the second buffer, and configure the function of the other buffer to read data.

[0089] When the target access mode is double-buffered, correspondingly, such as Figure 5 As shown, the data access in S230 above, which involves accessing the storage area in the dynamic hybrid access memory according to the target access mode, includes:

[0090] S510. When an access request indicates that data should be written, determine the write buffer configured for data writing in the first buffer and the second buffer, and write the data in the write buffer.

[0091] Optionally, if the SM determines that the access request indicates that data should be written, it determines the write buffer configured for data writing in the first buffer and the second buffer, and writes the data from the outside (such as DMA) to the write buffer in response to the data write request.

[0092] S520: When an access request indicates that data should be read, a read buffer configured for data reading is determined in the first buffer and the second buffer, and data is read in the read buffer.

[0093] Optionally, if the SM determines that the access request indicates that data should be read, it determines a read buffer configured for data reading in the first buffer and the second buffer, and reads data in the read buffer in response to the data read request for transmission to an external source (such as a PEA).

[0094] S530: Periodically switch the configuration of the first buffer and the second buffer alternately.

[0095] Optionally, SM can periodically switch the configuration of the first and second buffers alternately using control signals, causing the buffer that was originally writing data to become reading data, and the buffer that was originally reading data to become writing data, thus realizing the read / write switching between the first and second buffers. Throughout the process, the external address remains consistent, thereby ensuring the continuity of the programming model.

[0096] For example, such as Figure 4 As shown, for the current block of data, the first buffer is configured for data writing (Store) and the second buffer is configured for data reading (Load). After the read / write switch, for the next block of data, the first buffer is configured for data reading and the second buffer is configured for data writing.

[0097] In this embodiment, when the target access mode is a double-buffered mode, a first buffer and a second buffer are determined in the dynamic hybrid access memory, and the first buffer and the second buffer are respectively configured for data writing and data reading; both the first buffer and the second buffer include at least one storage area. Based on this, when an access request indicates that data should be written, a write buffer configured for data writing is determined in the first buffer and the second buffer, and data is written in the write buffer; when an access request indicates that data should be read, a read buffer configured for data reading is determined in the first buffer and the second buffer, and data is read in the read buffer, and the configuration of the first buffer and the second buffer is periodically switched alternately. The aforementioned dynamic hybrid access memory can meet the application requirements for processing block data based on the double-buffered mode, allowing the computation process (data reading) and the data transfer process (data writing) to overlap in time, reducing the time the processing unit waits for data, thereby improving computational efficiency and bandwidth utilization.

[0098] Single-instruction multithreaded mode is suitable for applications requiring multithreaded parallelism and irregular access, as shown in the diagram. In one embodiment where the target access mode is single-instruction multithreaded mode, such as... Figure 6 As shown, the configuration of the storage region in the dynamic hybrid access memory according to the target access mode in S220 includes:

[0099] S610. Determine a multi-threaded buffer in a dynamic mixed access memory; the multi-threaded buffer includes at least one storage area.

[0100] Optionally, when the target access mode is a single instruction multi-threaded mode, the SM can divide a buffer that includes at least one Bank, denoted as a multi-threaded buffer.

[0101] For example, such as Figure 7 As shown, Bank0 to Bank3 can be divided into multi-threaded buffers.

[0102] S620. Store the configuration information corresponding to the target access mode into the storage area of ​​the target buffer.

[0103] The configuration information corresponding to the target access mode includes the information required for the PE in the PEA to initiate an access request to the multi-threaded buffer in the SM.

[0104] Optionally, the SM can store the configuration information of the corresponding target access mode sent by the CPU through the data control module into the storage area of ​​the target buffer, and the number of storage areas occupied can be determined according to the size of the configuration information.

[0105] When the target access mode is a single-instruction multi-threaded mode, correspondingly, such as Figure 8 As shown, the data access in S230 above, which involves accessing the storage area in the dynamic hybrid access memory according to the target access mode, includes:

[0106] S810, in response to the configuration transfer request sent by the data controller, sends configuration information to the data control module; the configuration information includes at least one piece of configuration data and the corresponding quantity, and the data control module is used to copy each piece of configuration data into the corresponding quantity of configuration data through the data copying unit and send it to the corresponding processing unit in the processing unit array.

[0107] The CUP can send a configuration transfer request to the data control module, which then sends the configuration transfer request to the SM.

[0108] Optionally, the SM responds to the configuration transfer request sent by the data control module by retrieving configuration information from the multi-threaded buffer and sending it to the data control module.

[0109] The configuration information includes at least one piece of configuration data and the corresponding quantity of that configuration data. The data control module copies each piece of configuration data into the corresponding quantity of configuration data through the data copying unit, and broadcasts it to the corresponding processing unit in the processing unit array through the internal data path.

[0110] For example, such as Figure 7 As shown, the SM stores the received configuration information (including three configuration data items Configuration0-3 and the corresponding quantity of each configuration data item) into a multi-threaded buffer (Bank0~Bank3). In response to the configuration transfer request, the SM sends the configuration information to the data copy unit in the data control module to copy Configuration0-3 into the corresponding quantities. For example, Configuration0 is copied into 4 copies, Configuration1 is kept as 1 copy, Configuration2 is kept as 1 copy, and Configuration3 is copied into 2 copies. The configuration data items are then broadcast to the corresponding processing units.

[0111] S820: In response to access requests sent by each processing unit based on configuration data, access data in the storage area of ​​the multi-threaded buffer.

[0112] The processing unit that receives the configuration data sends an access request to the SM based on the configuration data.

[0113] Optionally, the SM responds to access requests sent by each processing unit based on configuration data to access the storage area in the multi-threaded buffer.

[0114] In this embodiment, when the target access mode is a single-instruction multi-threaded mode, a multi-threaded buffer is determined in the dynamic hybrid access memory to store the configuration information corresponding to the target access mode into the storage area of ​​the multi-threaded buffer; the multi-threaded buffer includes at least one storage area. Based on this, in response to the configuration transfer request from the data controller, configuration information is sent to the data control module; the configuration information includes at least one configuration data item and its corresponding quantity. The data control module is used to copy each configuration data item into the corresponding quantity of configuration data through the data copying unit and send it to the corresponding processing unit in the processing unit array; in response to the access requests sent by each processing unit based on the configuration data, data access is performed on the storage area in the multi-threaded buffer; the aforementioned dynamic hybrid access memory can meet the application requirements of multi-threaded task processing based on the single-instruction multi-threaded mode. Multiple processing units can perform consistent operations under the same instruction control, but can access different data addresses, without needing to store configuration separately for each processing unit, thereby improving the utilization rate of the dynamic hybrid access memory space and simplifying the configuration process.

[0115] Streaming FIFO mode is suitable for applications that process data streams, such as video streaming. In one embodiment where the target access mode is streaming FIFO, such as... Figure 9 As shown, the configuration of the storage region in the dynamic hybrid access memory according to the target access mode in S220 includes:

[0116] S910. Determine a streaming buffer in a dynamic hybrid access memory; the streaming buffer includes at least one storage region.

[0117] Optionally, when the target access mode is a streaming first-in-first-out mode, the SM can divide a buffer that includes at least one Bank, denoted as a streaming buffer.

[0118] For example, such as Figure 10 As shown, Bank0 to Bank3 can be divided into streaming buffers.

[0119] S920: Configure write pointers and read pointers for each storage area in the streaming buffer; the write pointer is used to point to the data writing position, and the read pointer is used to point to the data reading position.

[0120] Optionally, after determining the streaming buffer, SM can configure write pointers and read pointers for each Bank in the streaming buffer to store the data stream sequentially in the order of writing and output it sequentially in the order of reading.

[0121] For example, such as Figure 10As shown, independent write pointers (WritePtr) and read pointers (ReadPtr) can be configured for Bank0 to Bank3 respectively.

[0122] When the target access mode is a streaming first-in-first-out (FIFO) mode, correspondingly, such as Figure 11 As shown, the data access in S230 above, which involves accessing the storage area in the dynamic hybrid access memory according to the target access mode, includes:

[0123] S1110. If an access request indicates that data should be written to a storage area in the streaming buffer, read the data write position pointed to by the write pointer of the indicated storage area, write the data at the data write position, and update the data write position pointed to by the write pointer.

[0124] Optionally, the SM can parse the received access request, and if the access request indicates that data is to be written to a storage area in the streaming buffer, determine the storage area indicated by the access request, read the data write position pointed to by the write pointer of the storage area, write the received data stream at the data write position, and automatically increment the write pointer after the write is completed to update the data write position pointed to by the write pointer.

[0125] S1120. If an access request indicates that data should be read from a storage area in the streaming buffer, read the data read position pointed to by the read pointer of the indicated storage area, read the data at the data read position, and update the data read position pointed to by the read pointer.

[0126] Optionally, the SM can parse the received access request, and if the access request indicates that data is to be read from a storage area in the streaming buffer, determine the storage area indicated by the access request, read the data read position pointed to by the read pointer of the storage area, read the data stream at the data read position, and automatically increment the read pointer after reading to update the data read position pointed to by the read pointer.

[0127] For example, such as Figure 10 As shown, the LSU in PEA0 can write data streams to the data write positions pointed to by the write pointers of Bank0 / 1 / 2 / 3 in the streaming buffer, while the LSU in PEA1 can read data streams to the data read positions pointed to by the read pointers of Bank0 / 1 / 2 / 3 in the streaming buffer.

[0128] In an optional embodiment, to ensure data consistency, SM also configures an empty / full detection mechanism for each Bank in the streaming buffer. For each Bank, the data write position pointed to by the write pointer and the data read position pointed to by the read pointer can be read separately to determine the empty / full storage state of the Bank based on the data write position and data read position. When the empty / full storage state is empty, data reading is prohibited, and when the empty / full storage state is full, data writing is prohibited, thereby avoiding data corruption.

[0129] In an optional embodiment, for a Bank in the streaming buffer where data is being read, the SM can prepare the target data to be read into the corresponding register according to the read pointer for subsequent direct reading, thereby reducing address decoding and access latency during read operations and further improving data stream processing efficiency.

[0130] In this embodiment, when the target access mode is a streaming FIFO mode, a streaming buffer is determined in the dynamic hybrid access memory, and write pointers and read pointers are configured for each storage area in the streaming buffer. The write pointer is used to point to the data write position, and the read pointer is used to point to the data read position. Based on this, when an access request indicates that data is written to a storage area in the streaming buffer, the data write position pointed to by the write pointer of the indicated storage area is read, data is written at the data write position, and the data write position pointed to by the write pointer is updated. When an access request indicates that data is read from a storage area in the streaming buffer, the data read position pointed to by the read pointer of the indicated storage area is read, data is read at the data read position, and the data read position pointed to by the read pointer is updated. The aforementioned dynamic hybrid access memory can meet the application requirements for processing data streams based on the streaming FIFO mode, and can perform read and write operations on the data stream simultaneously, reducing the control overhead and access latency of sequential data stream access and improving the efficiency of streaming data processing.

[0131] Line-buffered mode is suitable for applications requiring the reuse of neighboring data, such as image convolution. In one embodiment, when the target access mode is line-buffered mode, such as... Figure 12 As shown, the configuration of the storage region in the dynamic hybrid access memory according to the target access mode in S220 includes:

[0132] S1210. Determine a row buffer in the dynamic mixed access memory; the row buffer includes at least two storage areas.

[0133] Optionally, when the target access mode is row buffer mode, the SM can divide a buffer consisting of at least two banks, denoted as the row buffer.

[0134] For example, such as Figure 13The four banks in the code form the row buffers.

[0135] S1220. Configure write pointers and read pointers for each storage area in the row buffer; the write pointer is used to point to the data writing position, and the read pointer is used to point to the data reading position.

[0136] Optionally, after determining the line buffer, SM can configure write pointers and read pointers for each Bank in the line buffer.

[0137] For example, such as Figure 13 As shown, independent write pointers (WritePtr) and read pointers (ReadPtr) can be configured for each of the four banks.

[0138] S1230. Configure the row buffer as a contiguous storage area to store contiguous row data.

[0139] Here, contiguous storage areas refer to consecutively adjacent storage areas, and contiguous row data correspondingly refers to consecutively adjacent rows of data. For example, row data refers to the row data in an image. Figure 13 As shown, the image contains four consecutive rows of data: Line 0 to Line 3 form one group, Line 4 to Line 7 form another group, Line 8 to Line 11 form a third group, and Line 12 to Line 15 form a fourth group.

[0140] Optionally, the SM can configure the row buffer as a contiguous storage area to store consecutive row data, so as to support the parallel reading of historical row data and the writing of new row data while ensuring the integrity of the current row data, thereby providing row-level data reuse capability for the processing unit.

[0141] When the target access mode is row-buffered mode, correspondingly, such as Figure 14 As shown, the data access in S230 above, which involves accessing the storage area in the dynamic hybrid access memory according to the target access mode, includes:

[0142] S1410. When an access request indicates that data should be written to the storage area of ​​the row buffer, the consecutive rows of data in the row data group to be written are written to the consecutive storage areas of the row buffer.

[0143] The group of rows to be written consists of consecutive rows of data. For example, such as... Figure 13 As shown, Line 0 to Line 3 form one group of line data, Line 4 to Line 7 form another group of line data, Line 8 to Line 11 form yet another group of line data, and Line 12 to Line 15 form yet another group of line data.

[0144] Optionally, the SM can parse the received access request, and if the access request indicates that data should be written to the storage area of ​​the row buffer, then the received row data group to be written is written to the consecutive storage areas in the row buffer line by line.

[0145] For example, such as Figure 13 As shown, for the row data group including Line0 to Line3, Line0 to Line3 are written to four consecutive storage areas.

[0146] S1420. When writing data to any storage area in the row buffer, read the data write position pointed to by the write pointer of the storage area, write data at the data write position, and update the data write position pointed to by the write pointer.

[0147] Optionally, when writing data to any storage area in the row buffer, the SM can read the data write position pointed to by the write pointer of that storage area, write the corresponding row data at that data write position, and automatically increment the write pointer after writing is completed to update the data write position pointed to by the write pointer.

[0148] S1430. If the access request indicates that data should be read from the storage area of ​​the row buffer, after determining that the target row data to be read has been written, the target row data should be read from the storage area where the target row data is stored.

[0149] Optionally, the SM can parse the received access request, and if the access request indicates that data should be read from the storage area of ​​the row buffer, determine the target row data to be read, so as to read the target row data from the storage area where the target row data is stored after the target row data has been written.

[0150] For example, such as Figure 13 As shown, the four banks in the row buffer receive row data blocks Line0~Line3 sent by the DMA and write them into these four consecutive banks accordingly. Then, the next set of row data blocks Line4~Line7 are written into these four consecutive banks in sequence. When the PEA initiates the reading of the target row data Line1, the SM determines whether the target row data Line1 has been written completely. After determining that the target row data Line1 has been written completely, the SM reads the target row data Line1 from the bank where it is stored.

[0151] S1440. When reading data from any storage area in the row buffer, read the data read position pointed to by the read pointer of the storage area, read the data at the data read position, and update the data read position pointed to by the read pointer.

[0152] Optionally, when reading data from any storage area in the row buffer, the SM can read the data read position pointed to by the read pointer of that storage area to read the corresponding row data at that data read position, and automatically increment the read pointer after reading to update the data read position pointed to by the read pointer.

[0153] In this embodiment, when the target access mode is row buffer mode, a row buffer is determined in the dynamic hybrid access memory, and write pointers and read pointers are configured for each storage area in the row buffer, and the row buffer is configured as a contiguous storage area to store contiguous row data; the row buffer includes at least one storage area; the write pointer is used to point to the data write position, and the read pointer is used to point to the data read position; the above-mentioned dynamic hybrid access memory can realize the application requirements for neighborhood data reuse based on the row buffer mode, improve the integrity and order of data, support the processing unit to perform row-based neighborhood data access, reduce repeated memory access in sliding window calculation, thereby improving bandwidth utilization and reducing memory access latency.

[0154] To facilitate understanding by those skilled in the art, the data access control method provided in this application is described in detail below, such as... Figure 15 As shown, this method is applied to dynamically hybrid access memory and includes:

[0155] S1501. Obtain the target access mode indicated by the access mode configuration instruction;

[0156] S1502. When the target access mode is a double-buffered mode, a first buffer and a second buffer are determined in the dynamic hybrid access memory; both the first buffer and the second buffer include at least one storage area, and the first buffer and the second buffer are respectively configured for data writing and data reading.

[0157] S1503. When an access request indicates that data should be written, determine a write buffer configured for writing data in the first buffer and the second buffer, and write data in the write buffer; when an access request indicates that data should be read, determine a read buffer configured for reading data in the first buffer and the second buffer, and read data in the read buffer; and periodically switch the configuration of the first buffer and the second buffer alternately.

[0158] S1504. When the target access mode is single instruction multi-threaded mode, determine a multi-threaded buffer in the dynamic hybrid access memory; the multi-threaded buffer includes at least one storage area; store the configuration information corresponding to the target access mode into the storage area in the multi-threaded buffer;

[0159] S1505, In response to the configuration transfer request from the data controller, the configuration information is sent to the data control module; the configuration information includes at least one piece of configuration data and the corresponding quantity, and the data control module is used to copy each piece of configuration data into the corresponding quantity of configuration data through the data copying unit and send it to the corresponding processing unit in the processing unit array; in response to the access request sent by each processing unit based on the configuration data, the storage area in the multi-threaded buffer is accessed.

[0160] S1506. When the target access mode is a streaming first-in-first-out mode, a streaming buffer is determined in the dynamic hybrid access memory; the streaming buffer includes at least one storage area; write pointers and read pointers are configured for each storage area in the streaming buffer; the write pointer is used to point to the data write position, and the read pointer is used to point to the data read position.

[0161] S1507. If an access request indicates that data is written to a storage area in the streaming buffer, read the data write position pointed to by the write pointer of the indicated storage area, write data at the data write position, and update the data write position pointed to by the write pointer; if an access request indicates that data is read from a storage area in the streaming buffer, read the data read position pointed to by the read pointer of the indicated storage area, read data at the data read position, and update the data read position pointed to by the read pointer.

[0162] S1508. When the target access mode is row buffer mode, determine a row buffer in the dynamic mixed access memory; the row buffer includes at least one storage area; configure write pointers and read pointers for each storage area in the row buffer respectively; configure the row buffer as a contiguous storage area to store contiguous row data;

[0163] S1509. When an access request indicates that data should be written to the storage area of ​​the row buffer, the consecutive rows of data in the row data group to be written should be written to the consecutive storage areas in the row buffer. When data is written to any storage area in the row buffer, the data write position pointed to by the write pointer of the storage area should be read, the data should be written at the data write position, and the data write position pointed to by the write pointer should be updated.

[0164] S1510. If the access request indicates that data should be read from the storage area of ​​the row buffer, after the target row data to be read has been written, the target row data should be read from the storage area where the target row data is stored. If data is read from any storage area in the row buffer, the data read position pointed to by the read pointer of the storage area should be read, the data should be read from the data read position, and the data read position pointed to by the read pointer should be updated.

[0165] It should be noted that the descriptions in S1501-S1510 above can be found in the relevant descriptions in the above embodiments, and their effects are similar, so they will not be repeated here.

[0166] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0167] Based on the same inventive concept, this application also provides a data access control device for implementing the data access control method described above. The solution provided by this device is similar to the implementation described in the above method; therefore, the specific limitations in one or more data access control device embodiments provided below can be found in the limitations of the data access control method described above, and will not be repeated here.

[0168] In one exemplary embodiment, such as Figure 16 As shown, a data access control device is provided, including: a mode determination module 1601, a storage configuration module 1602, and an access response module 1603, wherein:

[0169] The mode determination module 1601 is used to obtain the target access mode indicated by the access mode configuration instruction;

[0170] The storage configuration module 1602 is used to configure the storage regions in the dynamic hybrid access memory according to the target access mode; the dynamic hybrid access memory includes at least two storage regions;

[0171] The access response module 1603 is used to access the storage area in the dynamic hybrid access memory according to the target access mode when it receives an access request corresponding to the access mode configuration instruction.

[0172] Each module in the aforementioned data access control device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0173] In one exemplary embodiment, a reconfigurable computing system is provided, such as Figure 1 As shown, the reconfigurable computing system includes: at least one processing unit array and at least one of the above-mentioned dynamic hybrid access memories; any processing unit in the processing unit array can be used to access data in the storage area of ​​the dynamic hybrid access memory.

[0174] Those skilled in the art will understand that Figure 1 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0175] In one exemplary embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of any of the data access control methods described above.

[0176] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps of any of the above data access control methods.

[0177] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps of any of the data access control methods described above.

[0178] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0179] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0180] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A dynamic hybrid access memory, characterized in that, The dynamic hybrid access memory is used for: Retrieve the target access mode indicated by the access mode configuration directive; The storage regions in the dynamic hybrid access memory are configured according to the target access mode; the dynamic hybrid access memory includes at least two storage regions. Upon receiving an access request corresponding to the access mode configuration instruction, data access is performed on the storage area in the dynamic hybrid access memory according to the target access mode.

2. The dynamic hybrid access memory according to claim 1, characterized in that, When the target access mode is a double-buffered mode, configuring the storage regions in the dynamic hybrid access memory according to the target access mode includes: A first buffer and a second buffer are defined in the dynamic hybrid access memory; both the first buffer and the second buffer include at least one storage area. Configure the first buffer and the second buffer for data writing and data reading, respectively.

3. The dynamic hybrid access memory according to claim 2, characterized in that, The step of accessing data in the storage area of ​​the dynamic hybrid access memory according to the target access mode includes: If the access request indicates that data should be written, a write buffer configured for data writing is determined in the first buffer and the second buffer, and data is written in the write buffer. If the access request indicates that data should be read, a read buffer configured for data reading is determined in the first buffer and the second buffer, and data is read in the read buffer. The configurations of the first buffer and the second buffer are periodically switched alternately.

4. The dynamic hybrid access memory according to claim 1, characterized in that, When the target access mode is a single-instruction multi-threaded mode, configuring the storage region in the dynamic hybrid access memory according to the target access mode includes: A multi-threaded buffer is defined in the dynamic hybrid access memory; the multi-threaded buffer includes at least one storage area; The configuration information corresponding to the target access mode is stored in the storage area of ​​the multi-threaded buffer.

5. The dynamic hybrid access memory according to claim 4, characterized in that, The step of accessing data in the storage area of ​​the dynamic hybrid access memory according to the target access mode includes: In response to the configuration transfer request from the data controller, the configuration information is sent to the data control module; the configuration information includes at least one piece of configuration data and the corresponding quantity, and the data control module is used to copy each piece of configuration data into the corresponding quantity of configuration data through the data copying unit, and send it to the corresponding processing unit in the processing unit array; In response to the access requests sent by each of the processing units based on the configuration data, data access is performed on the storage area in the multi-threaded buffer.

6. The dynamic hybrid access memory according to claim 1, characterized in that, When the target access mode is a streaming first-in-first-out (FIFO) mode, configuring the storage regions in the dynamic hybrid access memory according to the target access mode includes: A streaming buffer is defined in the dynamic hybrid access memory; the streaming buffer includes at least one storage area; Each storage area in the streaming buffer is configured with a write pointer and a read pointer; the write pointer is used to point to the data writing position, and the read pointer is used to point to the data reading position.

7. The dynamic hybrid access memory according to claim 6, characterized in that, The step of accessing data in the storage area of ​​the dynamic hybrid access memory according to the target access mode includes: If the access request indicates that data should be written to the storage area in the streaming buffer, the data write position pointed to by the write pointer of the indicated storage area is read, data is written to the data write position, and the data write position pointed to by the write pointer is updated. If the access request indicates that data should be read from the storage area in the streaming buffer, the data read position pointed to by the read pointer of the indicated storage area is read, data is read from the data read position, and the data read position pointed to by the read pointer is updated.

8. The dynamic hybrid access memory according to claim 1, characterized in that, When the target access mode is a row-buffered mode, configuring the storage region in the dynamic hybrid access memory according to the target access mode includes: A row buffer is defined in the dynamic hybrid access memory; the row buffer includes at least one storage area. Write pointers and read pointers are configured for each storage area in the row buffer; the write pointer is used to point to the data write position, and the read pointer is used to point to the data read position. Configure the row buffer as a contiguous storage area to store consecutive rows of data.

9. The dynamic hybrid access memory according to claim 8, characterized in that, The step of accessing data in the storage area of ​​the dynamic hybrid access memory according to the target access mode includes: When the access request indicates that data should be written to the storage area of ​​the row buffer, consecutive rows of data in the required row data group are written to consecutive storage areas in the row buffer. When writing data to any storage area in the row buffer, read the data write position pointed to by the write pointer of the storage area, write data at the data write position, and update the data write position pointed to by the write pointer. If the access request indicates that data should be read from the storage area of ​​the row buffer, after the target row data to be read has been written, the target row data is read from the storage area where the target row data is stored. When reading data from any storage area in the row buffer, the data read position pointed to by the read pointer of the storage area is read, data is read from the data read position, and the data read position pointed to by the read pointer is updated.

10. A reconfigurable computing system, characterized in that, The reconfigurable computing system includes: at least one processing unit array and at least one dynamic hybrid access memory according to any one of claims 1 to 9; any processing unit in the processing unit array can be used to access data in the storage area of ​​the dynamic hybrid access memory.

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