A method and device for floating-point number value self-checking and a computer storage medium

Abstract

The application provides a floating-point number value self-checking method, device and computer storage medium, and relates to the technical field of data processing. The method divides the mantissa bits of a floating-point number into load bits and check information bearing bits, splices the sign bits, the exponent bits, the load bits and a first context containing target slot bit information of the floating-point number into a first bit string in a set order, calculates and writes check information into the check information bearing bits according to a predetermined check algorithm, and constructs a self-check floating-point number; after receiving or reading the self-check floating-point number, the written check information is extracted, a second context and a second bit string are constructed according to actual read or effective slot bit information, and read check information is calculated according to the same algorithm; by comparing the written check information with the read check information, if the two are inconsistent, it is judged that the self-check floating-point number or its slot mapping has an abnormality. The application can detect value bit errors and abnormal slot errors without increasing the total bit width of floating-point data.

Description

Technical Field

[0001] This application relates to the field of data processing technology, and to a floating-point number self-verification method, apparatus, and computer storage medium. Background Technology

[0002] Floating-point numbers are an approximate representation of real numbers in computers and a core means of processing continuous data in modern digital systems. Currently, the industry widely uses the IEEE 754 binary floating-point standard to encode floating-point numbers, describing the value through a combination of a sign bit, an exponent, and a fractional / mantissa. Taking the most widely used format as an example, 32-bit single-precision (float) consists of 1 sign bit, 8 exponent bits, and 23 explicit mantissa bits, while 64-bit double-precision (double) consists of 1 sign bit, 11 exponent bits, and 52 explicit mantissa bits.

[0003] In applications with high reliability requirements, such as rail transit control, industrial automation, and embedded real-time systems, the system often needs to frequently adjust control parameters online, issue calibration tables, or persist and exchange parameters through computer storage media such as network transmission, shared memory interaction, Flash storage, and file reading and writing. These floating-point parameters, which carry critical control logic, will undergo multiple copies, forwards, and storage throughout their lifecycle, and may even involve manual copying and modification.

[0004] However, existing data transmission and storage verification technologies have significant limitations. In practical engineering applications, if problems such as bit flips, reassembly errors due to lost communication frames, misaligned memory copies, incorrect addresses or indexes, or incorrect parameter mapping occur during parameter processing, the control system may very well operate with incorrect parameters without its knowledge.

[0005] In particular, traditional verification methods are ineffective in handling special error scenarios such as "incorrectly written parameter slots but the value itself is valid." For example, when a valid floating-point number is incorrectly written to an adjacent parameter slot, or a line mapping error occurs during reloading after offline editing, the value remains valid at the binary level, conforming to the IEEE 754 standard. In such cases, traditional frame-level cyclic redundancy check (CRC) or file-level checksums often fail to cover these errors because they typically occur during the internal write / mapping phase after frame-level checksums have passed, or during offline processing when the data is outside the scope of checksum protection. Due to the lack of effective detection mechanisms for parameter semantics and position validity, these hidden parameter errors can easily lead to system control anomalies and even serious security incidents. Summary of the Invention

[0006] The purpose of this application is to solve one of the above-mentioned technical problems by providing a floating-point number self-verification method, apparatus and computer storage medium.

[0007] To achieve the above objectives, the technical solution adopted in this application is as follows: The first aspect of this application provides a method for self-verification of floating-point numbers, including: The mantissa of the floating-point number is divided into a payload bit and a parity information carrying bit. A first context is constructed according to the target slot information of the floating-point number. The sign bit, exponent bit, payload bit of the floating-point number and the first context are concatenated into a first bit string according to a set concatenation order. According to the predetermined verification algorithm, the written verification information is calculated based on the first bit string, and the written verification information is written into the verification information bearer bit to construct a self-test floating-point number; After receiving or reading the self-test floating-point number, the write verification information is extracted from the verification information bearer bit, and a second context is constructed according to the slot information that the self-test floating-point number is actually read or effective; the sign bit, exponent bit, payload bit of the self-test floating-point number and the second context are concatenated into a second bit string according to the concatenation order. According to the predetermined verification algorithm, the verification information is calculated and read based on the second bit string; Compare the write verification information and the read verification information. If the write verification information and the read verification information are inconsistent, it is determined that the self-test floating-point number or its slot mapping is abnormal.

[0008] In conjunction with the first aspect, in some embodiments of the first aspect of this application, the predetermined verification algorithm is a CRC remainder algorithm, the verification information bearer is a CRC remainder bearer, and the method further includes: The mantissa of the floating-point number is divided into a payload bit and a CRC remainder bit. The payload bit is used to store the payload data, and the CRC remainder bit is used to store the CRC remainder. A CRC remainder algorithm is defined, which is used to calculate the CRC remainder based on the bit string to be calculated; The step of calculating and writing verification information based on the first bit string includes: Based on the first bit string, calculate the first CRC remainder and write the first CRC remainder into the CRC remainder bearer bit to construct a self-checking floating-point number; the first CRC remainder is the written verification information; The step of calculating and reading the verification information based on the second bit string includes: Based on the second bit string received or read from the self-test floating-point number, the CRC remainder algorithm is executed to calculate the second CRC remainder; the second CRC remainder is the read verification information.

[0009] In conjunction with the first aspect, in some embodiments of the first aspect of this application, a number of bits k is set, and the lowest k bits of the mantissa of the floating-point number are taken as the CRC remainder bearer bits.

[0010] In conjunction with the first aspect, in some embodiments of the first aspect of this application, the self-verification method further includes: setting the number of bits k according to the tolerance requirements of the parameter represented by the floating-point number, wherein the number of bits k corresponding to the strict tolerance parameter is less than the number of bits k corresponding to the tolerance parameter.

[0011] In conjunction with the first aspect, in some embodiments of the first aspect of this application, both the first context and the second context are fixed-length context bit strings, and their field sets, field widths, encoding methods, and concatenation orders are the same.

[0012] In conjunction with the first aspect, in some embodiments of the first aspect of this application, the method further includes, when it is determined that there is an anomaly in the self-test floating-point number or its slot mapping, determining and performing corresponding anomaly handling operations based on the characteristics of the parameter represented by the floating-point number; The characteristics of the parameter include, but are not limited to: the importance level of the parameter, the number of exceptions, and the current operating stage of the system in which the floating-point number is applied.

[0013] A second aspect of this application provides a floating-point number self-verification device, comprising: a transmitting end and a receiving end; The sending end includes: Quantization trimming module: used to divide the mantissa of a floating-point number into payload bits and check information carrying bits; Context binding module: Constructs a first context based on the target slot information of the floating-point number, and concatenates the sign bit, exponent bit, payload bit of the floating-point number and the first context into a first bit string according to a set concatenation order; First calculation module: used to calculate and write verification information based on the first bit string according to a predetermined verification algorithm; Reassembly module: used to write the written verification information into the verification information bearer bit to construct a self-test floating-point number; The receiving end includes: The second calculation module is used to calculate and read verification information based on the second bit string according to the predetermined verification algorithm. Verification Extraction and Verification Module: This module is used to extract the write verification information from the verification information bearer bits of the received or read self-test floating-point number, construct a second context based on the slot information of the self-test floating-point number that is actually read or effective, concatenate the sign bit, exponent bit, payload bit of the self-test floating-point number and the second context into a second bit string according to the concatenation order, and compare the write verification information with the read verification information. If the two are inconsistent, it generates floating-point number or slot mapping abnormal information.

[0014] In conjunction with the second aspect, in some embodiments of the second aspect of this application, the predetermined verification algorithm is a CRC remainder algorithm, the verification information bearer is a CRC remainder bearer, the written verification information is a first CRC remainder, and the read verification information is a second CRC remainder; The quantization trimming module is used to divide the mantissa of the floating-point number into a payload bit and a CRC remainder carry bit; the first calculation module is used to calculate a first CRC remainder based on the CRC remainder algorithm and the first bit string; the reassembly module is used to write the first CRC remainder into the CRC remainder carry bit to construct a self-test floating-point number. The second calculation module is used to calculate the second CRC remainder based on the second bit string using the CRC remainder algorithm. The verification extraction and validation module is used to compare the first CRC remainder with the second CRC remainder, and generate floating-point error information when the first CRC remainder and the second CRC remainder are inconsistent.

[0015] A third aspect of this application provides a computer storage medium for storing a computer program, which, when executed, implements the floating-point number self-verification method described above.

[0016] Compared with the prior art, the beneficial effects of the technical solution of this application include at least the following: 1. This application breaks through the limitations of traditional verification schemes that rely on adding independent fields or extending the protocol structure. By cleverly embedding verification information (such as CRC remainder) into the least significant bits of the floating-point number mantissa, the built-in verification function of data is achieved without increasing the protocol length, changing the structure size, or occupying additional bus bandwidth.

[0017] 2. This innovative approach incorporates context (including slot information, index, address, etc.) into the calculation process of verification information, establishing a strong binding relationship between "value" and "storage location." Unlike traditional schemes that only verify the value itself, this application can not only detect bit-flipping errors that occur during transmission or storage, but also effectively identify hidden engineering faults such as "valid value but incorrect position" (e.g., incorrect slot writing, incorrect index reference, incorrect row mapping, etc.). This mechanism can improve the system's ability to perceive complex logical errors.

[0018] 3. This application supports an integrated design of quantization and verification embedding, allowing flexible configuration of verification strategies based on parameter tolerance requirements. For parameters with high tolerance, more mantissa bits can be allocated for verification to achieve stronger error detection capabilities; for parameters with high tolerance, fewer mantissa bits can be allocated to retain higher precision, or double-precision floating-point numbers can be used to balance numerical accuracy and error detection capabilities. This flexible and configurable feature enables this application to adapt to the needs of different scenarios, from low-power embedded devices to high-performance computing platforms, achieving a balance between computational accuracy and data reliability.

[0019] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application, it can be implemented according to the contents of the specification. In order to make the above and other objects, features and advantages of this application more apparent, specific embodiments of this application are given below. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of a floating-point number structure according to an embodiment of this application.

[0022] Figure 2 This is a schematic diagram of a floating-point number structure according to another embodiment of this application.

[0023] Figure 3 This is a schematic diagram of the implementation context configuration structure for this application.

[0024] Figure 4 This is a schematic diagram of the bit string structure implemented in this application.

[0025] Figure 5 The flowchart illustrates the floating-point number self-verification method implemented in this application.

[0026] Figure 6Diagram illustrating the anomaly handling strategy for this application.

[0027] Figure 7 This is a schematic diagram of the floating-point number self-verification device proposed in an embodiment of this application. Detailed Implementation

[0028] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0029] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0030] In this application, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0031] The terms "first" and "second" are used only to describe the purpose and are not used to imply relative importance.

[0032] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. In the description of the embodiments of this application, unless otherwise stated, " / " means "or," for example, A / B can mean A or B; the term "and / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone.

[0033] In the embodiments provided in this application, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0034] In existing rail transit, industrial automation, and embedded control systems, the integrity and accuracy of parameter data are the cornerstones for ensuring the safe operation of the system. Currently, existing technologies mainly employ two conventional methods to verify parameters during transmission, storage, and processing: one is to add an additional Cyclic Redundancy Check (CRC) field or checksum to each individual parameter (such as float or double type); the other is to perform overall verification calculations at the communication frame, data packet, or file level.

[0035] However, the aforementioned existing technical solutions have significant defects and shortcomings in practical engineering applications.

[0036] First, the drawback of adding a separate CRC field for each parameter is that it significantly increases system overhead and complexity. In large-scale parameter tables or high-frequency communication scenarios, additional check fields directly lead to protocol field bloat, significantly consuming communication bandwidth and storage space. More seriously, such modifications often have far-reaching consequences, forcing developers to make extensive modifications and adaptations to existing data structure definitions, serialization / deserialization interfaces, and underlying drivers, greatly increasing development costs and maintenance difficulty.

[0037] Secondly, overall verification schemes at the communication frame or file level have significant limitations in their protection scope. This type of verification typically only covers the integrity of a single transmission process or a single file generation, making it a "one-off" protection mechanism. Once the data passes verification and is unpacked and written to memory, or undergoes multiple memory copies, address remappings, offline editing, and reloading within the system, the protective effect of the overall verification immediately fails. This means that if an error occurs during the internal writing stage after frame verification (such as writing the wrong address or index offset), current technologies cannot detect it, and the system will load erroneous parameters without warning.

[0038] Furthermore, considering the characteristics of the data itself, existing technologies often overlook the issue of "precision redundancy" when processing floating-point numbers. In practical control engineering, the control precision of physical quantities is usually limited by factors such as sensor noise and actuator resolution. The ultra-high precision provided by the least significant bits of the mantissa in the IEEE 754 standard (such as a dozen or so decimal places) often does not significantly benefit the actual control effect. However, existing technologies still rigidly retain all bit widths for numerical representation, failing to utilize these redundant bits to assist in data integrity protection, resulting in a hidden waste of storage resources.

[0039] In summary, how to solve the problems of parameter misalignment and abnormal modification during multiple data transfers, mappings, and offline processing without excessively increasing protocol overhead or disrupting the existing interface architecture, and how to leverage the precision redundancy of floating-point numbers to achieve efficient anomaly verification, are technical problems that urgently need to be solved by those skilled in the art.

[0040] To address the above issues, this application proposes a floating-point number self-verification method, apparatus, and computer storage medium. Without increasing the width of float / double data or changing the existing interface, it provides continuously verifiable data integrity and slot consistency guarantees for each parameter value, and prevents erroneous parameters from entering the system when verification fails, thus avoiding the spread of misoperation and hidden errors.

[0041] The first embodiment of this application proposes a floating-point number self-verification method, which includes the following steps.

[0042] S1: Divide the mantissa of the floating-point number into payload bits and parity information carrying bits, construct the first context according to the target slot information, and concatenate the sign bit, exponent bit, payload bit and the first context into the first bit string according to the set concatenation order. S2: Calculate the written verification information based on the first bit string according to the predetermined verification algorithm, and write the written verification information into the verification information bearer bit to construct a self-test floating-point number; S3: After receiving or reading the self-test floating-point number, extract and write the verification information from the verification information bearer bit, and construct a second context according to the slot information that the self-test floating-point number is actually read or effective, and concatenate the sign bit, exponent bit, payload bit of the self-test floating-point number and the second context into a second bit string according to the concatenation order. S4: Calculate and read the verification information based on the second bit string according to the predetermined verification algorithm; S5: Compare the written verification information and the read verification information. If the written verification information and the read verification information are inconsistent, it is determined that there is an anomaly in the self-test floating-point number or its slot mapping.

[0043] There are multiple methods for calculating verification information, and it is necessary to ensure that the calculation methods for writing and reading verification information are the same. These methods include, but are not limited to, the following.

[0044] Cyclic Redundancy Check (CRC) method. The bit string is treated as a dividend, and zeros of the same length as the check bits are added to the end. Then, a modulo-2 division operation is performed with a predetermined generator polynomial (such as CRC-8, CRC-16, etc.) as the divisor, and the remainder is used as the check information.

[0045] Parity check calculation method. Count the total number of binary "1"s in the first bit string. If even parity is used, the check information is recorded as "1" when the number of "1"s is odd and as "0" when it is even; if odd parity is used, the opposite is true. Use the generated check bit as the written check information.

[0046] In a preferred embodiment of this application, to improve the data anomaly detection capability, the method for calculating the verification information is Cyclic Redundancy Check (CRC). In other alternative embodiments, if the system has extremely stringent requirements for computing resources, parity check or summation method can also be used to generate the verification information; this application does not impose absolute limitations on this.

[0047] Specifically, the floating-point number self-verification method based on Cyclic Redundancy Check (CRC) includes the following steps.

[0048] S1': Parse the floating-point number X, dividing the mantissa of X into payload bits and CRC remainder bits. The CRC remainder bits serve as the verification information bearer, the payload bits store the payload data, and the CRC remainder bits store the CRC remainder. Specifically, the lowest k bits of the mantissa of the floating-point number X are used as the CRC remainder bits.

[0049] In the IEEE 754 standard, the mantissa of a floating-point number typically has m bits (e.g., 23 bits for float and 52 bits for double). This application splits the m-bit mantissa into two parts, where: height m k bits: This is F_payload. It represents the main numerical information of the floating-point number.

[0050] The low k bits are released and are no longer used to carry the original numerical information. Instead, they are used to store the calculated CRC check remainder.

[0051] It should be understood that in industrial control, the accuracy of physical quantities (such as speed, temperature, and pressure) is often limited by sensors and actuators. Minor changes in the few least significant digits (e.g., the 6th decimal place and beyond) have no substantial significance for actual control. Therefore, this "accuracy redundancy" is trimmed (through rounding or truncation) and converted into "reliability redundancy" (used to store CRC remainders) to meet engineering control requirements.

[0052] refer to Figure 1 This is a schematic diagram of the floating-point number X structure after re-dividing the CRC remainder carry bits in one embodiment. In this embodiment, taking float as an example, the original 23-bit mantissa is divided into two parts: a 15-bit payload and an 8-bit CRC remainder carry bit.

[0053] refer to Figure 2 This is a schematic diagram of the floating-point number X structure after re-dividing the CRC remainder bearer bits in another embodiment. In this embodiment, taking double as an example, the original 52-bit explicit mantissa field is divided into two parts: a 36-bit payload bit and a 16-bit CRC remainder bearer bit.

[0054] Since the lowest k bits of the mantissa no longer carry the original numerical information, the effective precision of the value is equivalent to reducing it by k bits. By truncating or rounding the lower bits of the mantissa before embedding CRC, the introduced error can be constrained to within the acceptable range for engineering applications. In practical applications, the value of k is determined based on the parameter tolerance grading.

[0055] In a preferred embodiment of this application, a differentiated verification strategy based on parameter tolerance grading is proposed.

[0056] Specifically, since using the lowest k bits of the mantissa X as the remainder area for cyclic redundancy check (CRC) would reduce the effective precision of the floating-point number by k bits, the system establishes a parameter tolerance grading mechanism based on the physical properties of the parameters and control requirements: For low-sensitivity parameters (tolerance parameters: such as non-critical status indicators and auxiliary control quantities with wide tolerance ranges), the system allocates a larger bit width k. Although this sacrifices some low-bit precision, since this precision is already within the noise range allowed by engineering tolerances, it can significantly improve error detection capability and data reliability.

[0057] For highly sensitive parameters (strict tolerance parameters, such as high-precision position loop feedback and small gain coefficients), the system allocates a smaller bit width k, or adopts a precision extension strategy, that is, upgrades the parameter to a 64-bit double-precision floating-point number and uses the rich mantissa redundancy bits in the double-precision format to configure a larger parity bit width k.

[0058] Through the above-mentioned hierarchical configuration, this application can improve the parameter anomaly detection capability by utilizing the precision redundancy of floating-point numbers while keeping the introduced quantization error within the engineering allowable range corresponding to each parameter.

[0059] S2': Concatenate the sign bit, exponent bit, payload bit, and first context of the floating-point number into a first bit string according to the set concatenation order; wherein, the first context includes the floating-point number target slot information.

[0060] In this embodiment, the floating-point number is concatenated into a first bit string in the order of sign bit S, exponent bit E, payload bit F, and first context (ContextC). (See reference) Figure 5 The first bit string is in the form of: B=[S||E||F_payload||C]; Figure 5 The "mantissa" in the second step refers to the aforementioned payload bits.

[0061] Context C is a fixed-length context bit string generated according to the product specifications, used to prove that "this parameter is correct in this position" as an identity label or environmental information. The set of fields, the bit width of each field, the encoding method, and the concatenation order of context C should be fixed in advance in the system specifications.

[0062] Context C typically contains one or more of the following information. In this embodiment, the C output by the context binding module is a bitwise concatenation of a fixed set of fields. (See reference) Figure 3 This is a diagram illustrating the concatenation of context-bound fields. Fields may include, but are not limited to: ParamID: Parameter identifier, a unique ID or name for the parameter. Used to clearly identify the specific physical quantity or control logic represented by the current floating-point number. For example, it can be a string (such as "Motor_Speed") or a globally unique numeric code (such as 0x001A). This prevents different types of parameters from being confused.

[0063] SlotIndex: Parameter slot index. This is the specific position number of the parameter within the parameter table (array or memory block), for example, "this is the speed parameter for motor number 10". A "slot" is an entry in the parameter table, calibration table, or address map where a logical parameter is written and takes effect. This is directly used to prevent problems with incorrect parameter mapping or copying—even if the value itself is valid, if it is written to the wrong slot, the SlotIndex will not match expectations, and the CRC check will fail.

[0064] TableVersion: Version information for the entire calibration table or parameter configuration file (e.g., "Calibration Table V2.0" or a timestamp). Used to prevent version mismatch issues when reloading after offline editing. Ensures that the currently loaded parameters are compatible with the currently running control program, avoiding loading older or incorrect versions of parameter sets.

[0065] ChannelID: Channel identifier, the number of a communication channel or hardware module. In multi-channel systems (such as multi-axis motor control and multi-sensor acquisition), it is used to distinguish the physical channel to which a parameter belongs. It prevents parameters from channel A from being incorrectly written into the control slot of channel B.

[0066] AddressTag: An address tag that specifies the absolute / relative physical address of the parameter in memory or Flash. For example, "data at memory address 0x80004000". This provides the lowest-level memory binding. If an out-of-bounds memory write or pointer offset results in a "wrong address write", AddressTag will directly expose this low-level memory operation error.

[0067] For example, it is stipulated that: C = [ParamID(8bit)||SlotIndex(8bit)||TableVersion(8bit)||ChannelID(8bit)], all encoded as unsigned integers, MSB-first. For ParamID=0x2A, SlotIndex=0x03, TableVersion=0x01, and ChannelID=0x00, C = 0x2A030100. In this example, 0x03 is the slot index; the entire C is the normalized context including the slot identity.

[0068] refer to Figure 4 This is a diagram showing the arrangement of the first bit string in a specific instance.

[0069] S3': Calculate the first CRC remainder R based on the first bit string, and write the first CRC remainder R into the CRC remainder bearer bit to construct a self-test floating-point number. In this embodiment, the self-test floating-point number is defined as X'.

[0070] Specifically, the calculated first CRC remainder is written into the lowest k bits of the mantissa.

[0071] The CRC algorithm is not a fixed mathematical formula; it is a "parameterized" algorithm. If the parameters are not fixed, even if the sending and receiving ends use the same name (e.g., both are called CRC-8), the calculated results may be completely different, causing the verification to fail indefinitely.

[0072] In order to achieve accurate remainder calculation, in addition to standardizing the bit string concatenation order, other CRC algorithm configuration items also need to be standardized in this embodiment, including but not limited to: bit order (MSB-first or LSB-first), CRC polynomial, initial value, final XOR value, whether reflection is used, etc.

[0073] Concatenation order: Indicates the concatenation order of each field, such as the sign bit, exponent bit, payload bit, and context C, and which is placed first and which is placed last.

[0074] Bit order: Indicates whether the most significant bit (MSB-first) or the least significant bit (LSB-first) is sent first when transmitting data.

[0075] CRC polynomial: The divisor used in division operations (e.g., the polynomial for CRC-8 is 0x07).

[0076] Initial value (Init): What value is initially stored in the CRC register before the calculation begins (e.g., all 0s, all 1s, or 0xFF).

[0077] Final XOR value (XorOut): After the final step of the calculation, should the result be XORed with a fixed value?

[0078] Whether to reflect (RefIn / RefOut): Whether to reverse the bit order of each byte before or after the calculation.

[0079] Different products can uniformly select a single parameter setting format. In order to reduce R&D costs and facilitate code and hardware logic reuse, different products can uniformly adopt the same standard configuration (such as uniformly using CRC-8 / ATM) for easy management.

[0080] Specifically, a CRC remainder algorithm can be configured, which is used to calculate the CRC remainder based on the bit string to be calculated. This CRC remainder algorithm can be used in the remainder calculation of each bit string in the embodiments of this application.

[0081] S4': After receiving or reading the self-test floating-point number, extract the first CRC remainder R_recv from the self-test floating-point number. Construct the second context based on the slot information actually read or effective from the self-test floating-point number, and calculate the second CRC remainder R_calc. It should be noted that the first CRC remainder R is the original remainder R calculated and written by the sending end; the first CRC remainder R_recv specifically refers to the remainder extracted by the receiving end from the self-test floating-point number. The normal relationship should be R = R_recv, and when the floating-point number is correct, R = R_recv = R_calc.

[0082] S5': If the first CRC remainder R_recv and the second CRC remainder R_calc are inconsistent, then it is determined that the floating-point number or its slot information is abnormal.

[0083] In industrial control and high-reliability systems, a blanket shutdown strategy cannot be adopted when the receiving end detects a floating-point parameter verification failure (i.e., R_calc and R_recv are inconsistent). Different exception handling conditions and methods can be set for different types of parameters. For example, different exception handling methods can be configured based on the parameter's importance level, the number of exceptions, and the current stage of system operation.

[0084] Table 1 Examples of Floating-Point Number Exception Handling

[0085] For example, refer to Table 1 and Figure 6 The system categorizes parameters into three levels—general, critical, and security critical—based on their impact on overall business operations, and matches them with different fault tolerance strategies. General parameters (such as non-core status variables and auxiliary display data): Single failure: A brief absence of this type of parameter will not cause the system to malfunction. The system only needs to trigger an alarm to notify the maintenance personnel and refuse to update the current parameter value (i.e., keep the original valid value in memory unchanged). This ensures data continuity and avoids corrupted parameters from contaminating the system.

[0086] Key parameters (such as PID gain of conventional control loop, target speed): Single failure: This type of parameter directly affects control quality. In addition to alarms and refusing updates, the system must also actively roll back to the last known good value. This ensures seamless control logic and avoids severe jitter or overshoot in the actuator due to sudden parameter changes.

[0087] Safety-critical parameters (such as emergency stop threshold, overcurrent protection limit, and safety boundary coordinates): Single failure: Any uncertainty in such parameters could lead to catastrophic consequences. The system must take the highest level of protection: issue an alarm, roll back to the previous valid value, and force entry into Safe Mode. In Safe Mode, the system typically cuts off power output or limits its operating range, awaiting manual intervention in a "fail-safe" manner.

[0088] This tiered anomaly handling mechanism can adopt a fault-tolerant strategy that balances benefits and risks based on the business impact of parameters, the persistence of the fault, and the stage of the system's life cycle.

[0089] This application provides a complete anomaly handling mechanism, changing the passive situation of traditional verification which can only "report errors" but cannot "stop the damage." When inconsistent verification information is detected, the system can controllably block the erroneous parameters from taking effect and automatically execute defensive actions such as alarms, rejection of updates, state rollback, or request for retransmission. This proactive defense mechanism can prevent detected erroneous data from entering the core control logic, maintain the system in a safe state, and significantly reduce the risk of security incidents caused by parameter anomalies.

[0090] The following will use a specific application example to fully illustrate the implementation process of the floating-point number self-verification method proposed in this application.

[0091] Step 1: Parameter Configuration and Bit Width Allocation The default floating-point number standard format and the total number of bits for the mantissa are set to m. Based on the engineering tolerance and precision sensitivity of the parameters, the minimum mantissa bit width k used to carry the cyclic redundancy check (CRC) remainder is determined. Simultaneously, the configuration parameters of the CRC algorithm are determined, including the CRC polynomial, initial value, final XOR value, bit order, and reflection rules.

[0092] For example, using IEEE 754 binary32 (float), the explicit mantissa bits m=23, and k=8; the CRC uses a polynomial: (Hexadecimal 0x07), initial value 0x00, final XOR value 0x00, no reflection in input / output, processed bit by bit according to MSB-first. C is constructed according to the aforementioned format.

[0093] Step 2: Extract the mantissa payload and trim the precision to obtain the original floating-point bit field and release the CRC remainder carry bits.

[0094] Obtain the raw floating-point number to be transmitted or stored, and extract its sign bit S, exponent E, and complete m-bit mantissa F. Perform truncation or rounding operations on the mantissa F, releasing its lowest k bits and retaining the high m bits. k bits are used as the effective numerical payload F_payload.

[0095] For example, suppose the 32-bit encoding of the original parameter X is 0x414800C8, corresponding to the decimal constraint 12.500190734863281. Decomposing this gives S=0, E=10000010b (0x82), and a 23-bit mantissa F=10010000000000011001000b (0x4800C8). Pruning the lowest 8 bits of the mantissa, 11001000b, leaves the highest 15 bits, F_payload=1001000000000000b (0x4800). At this point, [S||E||F_payload] is exactly 24 bits, i.e., 0x414800.

[0096] Step 3: Context metadata construction, constructing the send / write side context.

[0097] Obtain the context binding information C of the floating-point number in the current system environment. The context C includes, but is not limited to, metadata fields such as parameter identifier (ParamID), slot index (SlotIndex), version information (TableVersion), or channel identifier (ChannelID), and concatenates them into a fixed-length bit string C_enc according to a predetermined rule.

[0098] For example, if the target is ParamID=0x2A, SlotIndex=0x03, TableVersion=0x01, ChannelID=0x00, then C_enc=0x2A030100.

[0099] Step 4: Verify the concatenated input bit string to obtain the concatenated CRC input.

[0100] Following the system-defined concatenation order, the sign bit S, exponent bit E, effective value payload F_payload, and context bit string C_enc are concatenated bit by bit to generate the input bit string B used for CRC calculation.

[0101] For example, B=[S||E||F_payload||C_enc]=0x4148002A030100; represented by bytes as 4148 00 2A 03 01 00 (56 bits in total).

[0102] Step 5: CRC remainder calculation.

[0103] Based on the preset CRC algorithm configuration parameters, CRC calculation is performed on the input bit string B to obtain the CRC remainder R with a bit width of k.

[0104] For example, a byte-by-byte shift-and-XOR method can be used to calculate the CRC remainder. The CRC register is initially set to 0x00. The above 7 bytes are processed sequentially: 41 48 00 2A 03 01 00. Each byte is XORed with the CRC register, and the register is shifted left by one bit each time. If the most significant bit (MSB) before shifting out is 1: after shifting left, the register is XORed with the polynomial 0x07; if the most significant bit (MSB) before shifting out is 0: only left shift, no XOR. The register states are C0, B1, 1E, 8C, A4, 72, 59, therefore R = 0x59 = 01011001b. Equivalently (another equivalent calculation method), B can be padded with 8 zeros and divided modulo 2 by G(x), resulting in an 8-bit remainder of 0x59.

[0105] Step 6: Embedding the check bit and reassembling the data.

[0106] The calculated CRC remainder R is written into the least k bits of the released mantissa F of the original floating-point number, replacing the original numerical bits, thereby reconstructing a new floating-point value X′ carrying the check information. This X′ still conforms to the original floating-point number format standard, and the total bit width remains unchanged.

[0107] For example, writing R into the lowest 8 bits of the original floating-point mantissa yields the 32-bit encoding of X′: 0x41480059, which is 0|10000010|100100000000000|01011001, corresponding to the decimal constraint 12.50008487701416. X′ remains a valid binary32, and the data width remains 32 bits.

[0108] Step 7: Receiver Context Reconstruction and Verification At the receiving or data reading end, the CRC remainder R_recv and the valid numerical payload F_payload are extracted from the received floating-point value X′. Simultaneously, based on the physical / logical slot where the current data is actually written or activated, the context bit string C_ver of the current environment is reconstructed in real time. The verification bit string B_ver is generated according to the same concatenation rules, and the CRC remainder R_calc is recalculated.

[0109] For example, the receiving end extracts R_recv=0x59 and F_payload=0x4800 from X′, and reconstructs C_ver=0x2A030100 based on the actual effective slot 0x03. It then recalculates B_ver=0x4148002A030100, obtaining R_calc=0x59; since R_calc=R_recv, the verification passes. This is the same slot identity as in the previous steps.

[0110] Step 8: Anomaly Detection and Data Cleaning Compare R_calc and R_recv: If the two values ​​match, it is determined that no parameter value or slot abnormality was detected, and the verification passes. The system can set the lowest k position of the mantissa of X′ to zero and output the cleaned floating-point value X_clean for subsequent control logic. If the two values ​​do not match, it is determined that a data abnormality or parameter misalignment has occurred (such as writing to the wrong slot), the verification fails, the system triggers the exception handling mechanism, and refuses to use the parameter.

[0111] For example, if the same X′ is mistakenly written to SlotIndex=0x04, the receiving end reconstructs C_ver=0x2A040100 and B_ver=0x4148002A040100 according to the actual slot, and recalculates to obtain R_calc=0x4F; which is not equal to R_recv=0x59 in X′, so the verification fails and enters the exception handling stage. This difference can expose the fault situation of writing to the wrong slot.

[0112] Compared to schemes that only perform verification at the data frame transmission or file storage level, this application implements fine-grained verification for individual floating-point numbers. Because the verification information is integrated with the floating-point number itself, the data carries verification capability regardless of whether it is in memory, registers, or persistently stored on disk. This means that data can still be verified when it is read after it has been stored, improving the anomaly detection capability throughout the data's lifecycle and reducing the system risk caused by silent data corruption.

[0113] A second aspect of this application provides a floating-point number self-verification device, referencing... Figure 7 The self-verification device includes a transmitter and a receiver. The sending end includes: Quantization trimming module: used to divide the mantissa of a floating-point number into payload bits and check information carrying bits; Context binding module: Constructs a first context based on the target slot information of the floating-point number, and concatenates the sign bit, exponent bit, payload bit of the floating-point number and the first context into a first bit string according to the set concatenation order; First calculation module: used to calculate and write verification information based on the first bit string according to a predetermined verification algorithm; Reassembly module: Used to write the written verification information into the verification information bearer bit and construct a self-test floating-point number; The receiving end includes: The second calculation module is used to calculate and read the verification information based on the second bit string according to a predetermined verification algorithm. Verification Extraction and Verification Module: This module is used to extract the written verification information from the verification information bearer bits of the received or read self-test floating-point number, construct a second context based on the slot information of the self-test floating-point number that is actually read or effective, concatenate the sign bit, exponent bit, payload bit of the self-test floating-point number and the second context into a second bit string according to the concatenation order, and compare the written verification information with the read verification information. If the two are inconsistent, it generates floating-point number or slot mapping abnormal information.

[0114] In conjunction with the second aspect, in some embodiments of the second aspect of this application: The predetermined verification algorithm is the CRC remainder algorithm, the verification information bearer is the CRC remainder bearer, the written verification information is the first CRC remainder, and the read verification information is the second CRC remainder; The quantization trimming module is used to divide the mantissa of the floating-point number into a payload bit and a CRC remainder carrying bit; the first calculation module is used to calculate the first CRC remainder based on the CRC remainder algorithm and the first bit string; the reassembly module is used to write the first CRC remainder into the CRC remainder carrying bit to construct a self-test floating-point number. The second calculation module is used to calculate the second CRC remainder based on the second bit string using the CRC remainder algorithm. Verification and extraction module: used to compare the first CRC remainder with the second CRC remainder, and generate floating-point error information when the first CRC remainder and the second CRC remainder are inconsistent.

[0115] This application also provides a computer-readable storage medium storing program code that is executed by one or more processors. When the program code runs on the processor, it causes a device including one or more processors to perform the floating-point number self-verification method described in the above embodiments.

[0116] It should be understood that when the modules or units described herein are implemented using software, they can be implemented in whole or in part as a computer program product. A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, they produce, in whole or in part, the processes or functions described in the embodiments of this application. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., a solid-state disk (SSD)).

[0117] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for self-verification of floating-point numbers, characterized in that, include: The mantissa of the floating-point number is divided into a payload bit and a parity information carrying bit. A first context is constructed according to the target slot information of the floating-point number. The sign bit, exponent bit, payload bit of the floating-point number and the first context are concatenated into a first bit string according to a set concatenation order. According to the predetermined verification algorithm, the written verification information is calculated based on the first bit string, and the written verification information is written into the verification information bearer bit to construct a self-test floating-point number; After receiving or reading the self-test floating-point number, the write verification information is extracted from the verification information bearer bit, and a second context is constructed according to the slot information that the self-test floating-point number is actually read or effective; the sign bit, exponent bit, payload bit of the self-test floating-point number and the second context are concatenated into a second bit string according to the concatenation order. According to the predetermined verification algorithm, the verification information is calculated and read based on the second bit string; Compare the write verification information and the read verification information. If the write verification information and the read verification information are inconsistent, it is determined that the self-test floating-point number or its slot mapping is abnormal.

2. The floating-point number self-verification method according to claim 1, characterized in that, The predetermined verification algorithm is the CRC remainder algorithm, the verification information bearer is the CRC remainder bearer, and the method further includes: The mantissa of the floating-point number is divided into a payload bit and a CRC remainder bit. The payload bit is used to store the payload data, and the CRC remainder bit is used to store the CRC remainder. A CRC remainder algorithm is defined, which is used to calculate the CRC remainder based on the bit string to be calculated; The step of calculating and writing verification information based on the first bit string includes: Based on the first bit string, calculate the first CRC remainder and write the first CRC remainder into the CRC remainder bearer bit to construct a self-checking floating-point number; the first CRC remainder is the written verification information; The step of calculating and reading the verification information based on the second bit string includes: Based on the second bit string received or read from the self-test floating-point number, the CRC remainder algorithm is executed to calculate the second CRC remainder; the second CRC remainder is the read verification information.

3. The floating-point number self-verification method according to claim 2, characterized in that, Set the number of bits k, and take the lowest k bits of the mantissa of the floating-point number as the CRC remainder bit.

4. The floating-point number self-verification method according to claim 3, characterized in that, The self-verification method further includes: setting the number of bits k according to the tolerance requirements of the parameters represented by the floating-point number, wherein the number of bits k corresponding to the strict tolerance parameter is less than the number of bits k corresponding to the tolerance parameter.

5. The floating-point number self-verification method according to claim 1, characterized in that, Both the first context and the second context are fixed-length context bit strings, and they have the same field set, field width, encoding method, and concatenation order.

6. The floating-point number self-verification method according to claim 1, characterized in that, The method further includes, when it is determined that there is an anomaly in the self-test floating-point number or its slot mapping, determining and executing the corresponding anomaly handling operation based on the characteristics of the parameter represented by the floating-point number; The characteristics of the parameter include, but are not limited to: the importance level of the parameter, the number of exceptions, and the current operating stage of the system in which the floating-point number is applied.

7. A floating-point number self-verification device, characterized in that, include: Sender and receiver; The sending end includes: Quantization trimming module: used to divide the mantissa of a floating-point number into payload bits and check information carrying bits; Context binding module: Constructs a first context based on the target slot information of the floating-point number, and concatenates the sign bit, exponent bit, payload bit of the floating-point number and the first context into a first bit string according to a set concatenation order; First calculation module: used to calculate and write verification information based on the first bit string according to a predetermined verification algorithm; Reassembly module: used to write the written verification information into the verification information bearer bit to construct a self-test floating-point number; The receiving end includes: The second calculation module is used to calculate and read the verification information based on the second bit string according to the predetermined verification algorithm. Verification Extraction and Verification Module: This module is used to extract the write verification information from the verification information bearer bits of the received or read self-test floating-point number, construct a second context based on the slot information of the self-test floating-point number that is actually read or effective, concatenate the sign bit, exponent bit, payload bit of the self-test floating-point number and the second context into a second bit string according to the concatenation order, and compare the write verification information with the read verification information. If the two are inconsistent, it generates floating-point number or slot mapping abnormal information.

8. The floating-point number self-verification device according to claim 7, characterized in that, The predetermined verification algorithm is the CRC remainder algorithm, the verification information carrying bit is the CRC remainder carrying bit, the written verification information is the first CRC remainder, and the read verification information is the second CRC remainder; The quantization trimming module is used to divide the mantissa of a floating-point number into a payload bit and a CRC remainder carry bit. The first calculation module is used to calculate a first CRC remainder based on the first bit string using the CRC remainder algorithm; the reassembly module is used to write the first CRC remainder into the CRC remainder carrying bit to construct a self-test floating-point number. The second calculation module is used to calculate the second CRC remainder based on the second bit string using the CRC remainder algorithm. The verification extraction and validation module is used to compare the first CRC remainder with the second CRC remainder, and generate floating-point error information when the first CRC remainder and the second CRC remainder are inconsistent.

9. A computer storage medium, characterized in that, The computer storage medium is used to store a computer program, which, when executed, implements the floating-point number self-verification method as described in any one of claims 1-6.

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