Q-format data conversion apparatus and conversion method

Abstract

The application discloses a kind of Q format data conversion device, including pre-processing module for receiving at least two Qm format fixed-point number to be converted, obtain the bit width information of target conversion format Qn for the determination of conversion scene and output path selection signal, while according to demand, complete the original code operation of signed number complement, output the standardized data and original cache data after original complement conversion.Q format data conversion processing module is connected with pre-processing module, for receiving the path selection signal, standardized data and original cache data output by pre-processing module, according to path selection signal, one-way conduction bit width bit clipping hardware path or bit width extension hardware path is selected, receives external operation mode instruction, completes the one-way conduction of zero-order homogeneity operation and non-zero-order homogeneity operation, according to selection path, executes rounding, bit clipping and extension processing to the converted number, finally output the converted Qn format fixed-point number.The application has the advantages of high speed, low delay and deterministic timing.

Description

Technical Field

[0001] This invention relates to the field of digital signal processing technology, and more specifically to a Q-format data conversion device and method for embedded systems and digital signal processing systems. Background Technology

[0002] In the field of digital signal processing, fixed-point number format (Q format) is a data format for representing and processing rational numbers on integer hardware. Q format defines the precision and range of values ​​through a pre-defined bit width. Complex digital systems often rely on Q format data with different precisions and ranges to work together, making the conversion between Q format data a necessary and frequent core operation. In existing technologies, Q format data conversion mainly employs the following two implementation methods: The first implementation is a software-based conversion scheme using a general-purpose CPU. This scheme completes the shifting, rounding, and truncation operations of Q-format data by executing multiple instructions. However, this purely software implementation has the following inherent drawbacks when facing next-generation high-performance applications such as 5G communication, real-time image processing, and high-precision industrial control: (1) Real-time bottleneck: The software conversion process requires the execution of multiple instructions, which has inherent hardware processing delay. When faced with high-speed, continuous data streams, the CPU's processing throughput becomes a bottleneck, making it difficult to meet the real-time processing requirements in high-performance scenarios. (2) Timing uncertainty: In complex embedded multitasking environments, the software conversion process is easily interrupted by system interruptions, introducing unpredictable delays and disrupting the deterministic timing of the system, which may lead to serious consequences in control systems with strict real-time requirements. (3) High resource utilization: Complex Q format conversion will continuously consume a large number of CPU calculation cycles, which not only increases the overall power consumption of the system, but also squeezes out a large amount of CPU resources, resulting in a decline in the overall performance of the system.

[0003] The second implementation is based on a hardware conversion scheme. This scheme uses shifting, comparison, addition, and logical operations to convert between different Q-format data: expanding the bits when converting to a larger data format, and truncating the bits when converting to a smaller data format. However, this hardware scheme has a technical flaw: blindly truncating the bit width can result in significant loss of data precision, and in more serious cases, it can violate some basic principles of subsequent critical mathematical operations, thus causing functional errors at the system level. Specifically, a 32-bit Q32 format non-zero number 'a', with its high 24 bits all being 0, will trigger a division-by-zero exception when the conversion result is used as a divisor in a division operation because the lower eight bits are truncated during the conversion to Q24 format. The root cause of this problem is that when the bit width is reduced, the low-bit precision of the operands participating in zero homogeneous operations is not preserved, causing the truncation to completely reduce the data to 0 when the data is extremely small.

[0004] Therefore, existing technologies lack a Q-format data conversion solution that can guarantee high throughput, low latency, deterministic timing, and maintain the mathematical integrity of zero-order homogeneous operations. Summary of the Invention

[0005] The summary of this invention introduces a series of simplified concepts, all of which are simplifications of existing technologies in the field, and will be further explained in detail in the detailed description section. This summary is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0006] The technical problem to be solved by the present invention is to provide a Q-format data conversion device and conversion method that can guarantee high throughput, low latency, deterministic timing, and maintain the mathematical integrity of zero homogeneous operations, in order to address the shortcomings of the existing technology.

[0007] To solve the above-mentioned technical problems, the present invention provides a Q-format data conversion device, comprising: a preprocessing module and a Q-format data conversion processing module; The preprocessing module is used to receive at least two Qm format fixed-point numbers to be converted (data bit width m, Qm[m-1,0]), obtain the bit width information of the target conversion format Qn (data bit width n, Qn[n-1,0]) for determining the conversion scenario and outputting the path selection signal. At the same time, it performs the sign number two's complement to original code operation as required, and outputs the standardized data after the original two's complement conversion and the original buffered data. The Q-format data conversion and processing module, connected to the preprocessing module, receives the path selection signal, normalized data, and raw buffered data output from the preprocessing module. Based on the path selection signal, it selects either a truncated or extended hardware path. It also receives external operation mode instructions and further selects the truncated hardware path based on these instructions, choosing between operations with zero homogeneity and those without. The Q-format data conversion and processing module performs rounding, truncating, or extending operations on the converted number based on the selected path, ultimately outputting the converted Qn format fixed-point number.

[0008] Preferably, in a further improvement to the Q-format data conversion device, the preprocessing module includes: The bit width conversion judgment unit is used to receive and buffer the output first Qm format fixed point number and second Qm format fixed point number, as well as receive and buffer the current format bit width m and target format bit width n signals, and output a path selection signal according to the relationship between m and n to indicate whether the subsequent operation selects the bit width truncation hardware path or the bit width expansion hardware path. True form and complement conversion unit, connected to the bit width conversion judgment unit, and configured to perform a complement-to-true form operation on the signed first Qm format fixed-point number and the second Qm format fixed-point number when m is greater than n; Data cache register, connected to the bit width conversion judgment unit and the true form and complement conversion unit, and configured to cache the sign judgment processing results of the first Qm format fixed-point number and the second Qm format fixed-point number when m is greater than n, and output standardized data.

[0009] Preferably, the Q format data conversion apparatus is further improved, and the Q format data conversion processing module comprises: A first conversion link, applicable to the case where m>n and the subsequent operation involving the converted and output Qn format data has no zero-degree homogeneity characteristic, comprising: A first hardware rounding unit, configured to perform rounding processing on the output data of the data cache register to obtain first intermediate data and second intermediate data; A hardware truncation unit, connected to the first hardware rounding unit, and configured to truncate bits (m-n) to m of the data, and output a truncated first Qn format fixed-point number and a truncated second Qn format fixed-point number; A second conversion link, applicable to the case where m>n and the subsequent operation involving the converted and output Qn format data has a zero-degree homogeneity characteristic, comprising: Left shift bit width judgment unit, connected to the left shift unit, and configured to receive the first standardized data and the second standardized data cached by the preprocessing module, and determine a unified left shift width q according to the distribution of significant bits of the first standardized data and the second standardized data; Left shift unit, connected to the left shift bit width judgment unit, and configured to perform a q-time left shift operation on the first standardized data and the second standardized data (discarding the high q bits and padding q zeros at the low bits), and output first left-shifted data and second left-shifted data; A second hardware rounding unit, connected to the left shift unit, and configured to perform rounding processing on the first left-shifted data and the second left-shifted data after the left shift to obtain first rounded data and second rounded data; A hardware truncation unit, connected to the second hardware rounding unit, and configured to truncate bits (m-n) to m of the first rounded data and the second rounded data, and output a truncated first Qn format fixed-point number and a truncated second Qn format fixed-point number; A third conversion link, applicable to a conversion mode where m<n, comprising: A hardware bit extension unit, configured to perform bit extension on the first Qm format fixed-point number and the second Qm format fixed-point number, and output a first Qn format fixed-point number and a second Qn format fixed-point number; The data gating unit is connected to the hardware truncation unit of the first and second conversion links and the hardware expansion unit of the third conversion link, and is used to gating the first Qn format fixed-point number and the second Qn format fixed-point number of the first and second conversion links and the third conversion link.

[0010] Preferably, in a further improvement to the Q-format data conversion device, the left shift width determination unit includes: The bit OR operation module is used to perform bit OR logical operations on the first standardized data and the second standardized data. The bit OR range of the signed number is the second highest (mn) bit excluding the highest sign bit, and the bit OR range of the unsigned number is the highest (mn) bit. The judgment module, connected to the bitwise OR operation module, is used to determine the left shift width. The bitwise OR operation is performed bit by bit from the high bit to the low bit. If all bitwise OR results are 0, then the left shift width q = (mn). If the bitwise OR operation result from the high bit to the low bit is 1, then the bitwise OR judgment stops. The left shift width q is the number of bitwise OR results that are 0.

[0011] Preferably, in a further improvement to the Q-format data conversion device, the first hardware rounding unit includes: The bit detection module is used to detect the (mn-1)th bit of the input data; An addition and overflow detection module, connected to the bit detection module, is used to add 1 to the (mn-1)th bit of the input data as a whole when the (mn-1)th bit is 1 and the high n bits of the input data, i.e. the (mn)th to (m-1)th bits, are not all 1s. Preferably, the Q-format data conversion device is further improved, and the second hardware rounding unit includes: The bit detection module is used to detect the (mn-1)th bit of the input data; An addition and overflow detection module, connected to the bit detection module, is used to add 1 to the (mn-1)th bit of the input data as a whole when the (mn-1)th bit is 1 and the high n bits of the input data, i.e. the (mn)th to (m-1)th bits, are not all 1.

[0012] Preferably, in a further improvement to the Q-format data conversion device, the symbol processing module includes: The sign determination unit is used to detect the sign bit of the input data; The original complement conversion unit is connected to the sign determination unit and is used to convert signed numbers from two's complement to original complement. The data buffer register is connected to the sign determination unit and the original two's complement conversion unit. When the input data is a signed number, it receives and buffers the output data of the original two's complement conversion unit. When the input data is an unsigned number, it receives and buffers the original input data.

[0013] To solve the above-mentioned technical problems, the present invention provides a Q-format data conversion method, comprising the following steps: S1: Receive a first Qm format fixed-point number, a second Qm format fixed-point number, bit width information of m and n, and an external operation mode instruction. The external operation mode instruction is used to indicate whether the subsequent operation has a zero-order homogeneity requirement. S2: Determine the relationship between the target format bit width n and the current format bit width m, and select different conversion paths to execute based on the external operation mode instructions.

[0014] Preferably, the Q-format data conversion method is further improved.

[0015] When m > n and subsequent operations do not require zero-order homogeneity, execute the first transformation mode, which includes the following sub-steps: S201: Perform sign determination on the first Qm format fixed-point number and the second Qm format fixed-point number. When the data is a signed number, perform original two's complement conversion and cache the result in the data cache register. When the input data is an unsigned number, cache it directly in the data cache register to obtain the first cached data and the second cached data. S202: The first cached data and the second cached data are output to the first hardware rounding unit after the operation mode is determined, and rounding is performed respectively to obtain the first intermediate data and the second intermediate data. S203: The low (mn) bits of the first intermediate data and the second intermediate data are truncated and discarded, while the remaining high bits are retained. The first Qn format fixed-point number and the second Qn format fixed-point number are then output through the data gating unit. When m > n and subsequent operations have a zero-order homogeneity requirement, execute the second conversion mode, which includes the following sub-steps: S204: Perform sign determination on the first Qm format fixed-point number and the second Qm format fixed-point number. When the data is a signed number, perform original two's complement conversion and cache the result in the data cache register. When the input data is an unsigned number, cache it directly in the data cache register to obtain the first cached data and the second cached data. S205: The first and second buffered data are output to the left shift unit after the operation mode is determined, and the left shift width q is determined according to the left shift width determination unit to complete the left shift operation of the input data and obtain the first left shift data and the second left shift data. S206: inputting the first left-shifted data and the second left-shifted data into a second hardware rounding unit, and respectively performing rounding processing to obtain first rounded data and second rounded data; S207: truncating and discarding the lower (m-n) bits of the first rounded data and the second rounded data, retaining the remaining higher bits, and outputting a first Qn format fixed-point number and a second Qn format fixed-point number via a data gating unit; When m<n, a third conversion mode is executed, which includes the following sub-steps: S208: extending the low bits of the first Qm format fixed-point number and the second Qm format fixed-point number, shifting left by (n-m) bits and padding zeros at the low bits, to output the first Qn format fixed-point number and the second Qn format fixed-point number.

[0016] Compared with the prior art, the present invention has the following beneficial effects: (1) Since the present invention uses a dedicated hardware circuit instead of CPU software for execution, instruction execution overhead and interrupt latency are eliminated, conversion is completed in a single clock cycle or a fixed number of clock cycles, and timing determinism is ensured. The conversion of Q format data implemented by the hardware circuit has the advantages of high conversion speed and low resource consumption, can effectively improve the conversion efficiency of Q format data, overcomes the processing delay bottleneck of the software conversion solution in the prior art, and achieves the technical effects of high throughput, low latency and deterministic timing.

[0017] (2) In the prior art, either all implementations are based on software which cannot guarantee real-time performance, or a fixed hardware structure is adopted which cannot adapt to the requirements of different operation scenarios.

[0018] According to whether the target Q format data participates in zero-degree homogeneous operation, the present invention automatically switches the hardware conversion strategy, and can intelligently switch between "efficiency" and "correctness" according to application scenarios. A simple and efficient conventional rounding method is adopted for scenarios with no zero-degree homogeneity requirement, and a cooperative scaling algorithm is adopted for scenarios with zero-degree homogeneity requirement, so as to realize optimal configuration of hardware resources.

[0019] (3) Through the cooperative scaling algorithm, the present invention uniformly determines the left shift bits for a plurality of associated operands and performs left shift synchronously, fundamentally maintains the mathematical integrity of the zero-degree homogeneous operation, and completely solves the system errors (such as division by zero exception) caused by excessive loss of data precision due to the static truncation strategy in the existing hardware solutions. Specifically, by uniformly analyzing the effective bit distribution of the associated operands, the maximum left shift width that can keep the relative proportional relationship between the two unchanged is determined, the two operands are synchronously amplified by the same multiple and then truncated, which ensures that the mathematical operation relationship remains unchanged after conversion, and avoids the risk that the data are simultaneously zeroed due to truncation in the prior art.

[0020] (4) This invention can be widely applied in fields with high precision and high performance requirements such as motor control, 5G communication, and real-time image processing, significantly improving the reliability and performance of the system. In particular, in closed-loop control systems that require zero homogeneous operations such as division and comparison, this invention can ensure the correctness of system functions and avoid control failure or system crash due to data conversion errors. Attached Figure Description

[0021] The accompanying drawings are intended to illustrate the general characteristics of the methods, structures, and / or materials used in specific exemplary embodiments of the invention, supplementing the description in the specification. However, the drawings are schematic diagrams not drawn to scale and may not accurately reflect the precise structural or performance characteristics of any of the given embodiments. The drawings should not be construed as limiting or restricting the range of numerical values ​​or properties covered by exemplary embodiments of the invention. The invention will now be described in further detail with reference to the accompanying drawings and specific embodiments: Figure 1 This is a schematic diagram of the overall structure of the Q-format data conversion device of the present invention. Detailed Implementation

[0022] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can fully understand other advantages and technical effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through different specific embodiments, and various details in this specification can also be applied based on different viewpoints, with various modifications or changes made without departing from the overall design concept of the invention. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. The following exemplary embodiments of the present invention can be implemented in many different forms and should not be construed as being limited to the specific embodiments set forth herein. It should be understood that these embodiments are provided so that the disclosure of the present invention is thorough and complete, and that the technical solutions of these exemplary embodiments are fully conveyed to those skilled in the art. It should be understood that when an element is referred to as "connected" or "combined" to another element, the element can be directly connected or combined to the other element, or there may be intermediate elements. The difference is that when an element is referred to as "directly connected" or "directly combined" to another element, there are no intermediate elements. Throughout the drawings, the same reference numerals always denote the same elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0023] First embodiment; This invention provides a Q-format data conversion device, comprising: a preprocessing module and a Q-format data conversion processing module; The preprocessing module is used to receive at least two Qm format associated fixed-point numbers to be converted, obtain the operation mode instructions from external input and the bit width information of the target conversion format Qn, complete the determination of the conversion scenario and output the path selection signal, and at the same time perform sign bit judgment and original code conversion standardization processing on the data to be converted that participate in the zero homogeneity operation, and output standardized data and original buffer data. The Q-format data conversion and processing module, connected to the preprocessing module, receives the path selection signal, standardized data, and raw buffered data output by the preprocessing module. Based on the path selection signal, it selects one of the hardware paths for conventional rounding conversion, zero-order homogeneity guaranteed conversion, and bit-width expansion conversion, and performs corresponding shift, rounding, and truncation processing on the associated operands to achieve coordinated conversion of multiple associated operands and outputs the converted Qn format fixed-point number.

[0024] Second embodiment; First, it should be noted that the second embodiment of the present invention is a preferred implementation based on the overall design concept of the first embodiment described above. Those skilled in the art should also consider that adding or replacing hardware units based on the overall design concept of the present invention falls within the protection scope of the present invention.

[0025] refer to Figure 1 As shown, the preprocessing module of the Q-format data conversion device includes: The bit width conversion judgment unit is used to receive and buffer the output first Qm format fixed point number and second Qm format fixed point number, as well as receive and buffer the current format bit width m and target format bit width n signals, and output a path selection signal according to the relationship between m and n to indicate whether the subsequent operation selects the bit width truncation hardware path or the bit width expansion hardware path. The original two's complement conversion unit is connected to the bit width conversion judgment unit. When m is greater than n, it is used to perform two's complement to original code conversion on signed first Qm format fixed-point numbers and second Qm format fixed-point numbers. Preferably, the sign processing module includes a sign determination unit for detecting the sign bit of the input data, a two's complement conversion unit connected to the sign determination unit for converting signed numbers from two's complement to original code, and a data buffer register connected to the sign determination unit and the two's complement conversion unit, which receives and buffers the output data of the two's complement conversion unit when the input data is a signed number, and directly buffers the input data when the input data is an unsigned number.

[0026] The Q format data conversion processing module of the Q format data conversion device includes: The first transformation chain, applicable when m>n and subsequent operations involving the transformed output Qn format data do not exhibit zero-order homogeneity, includes: The first hardware rounding unit is used to round the output data x1 and y1 of the data buffer register to obtain the first intermediate data x2 and the second intermediate data y2. Specifically, the hardware rounding unit detects the (mn-1)th bit (i.e., the most significant bit of the truncated part) of the input data, as well as bits from the most significant bit to the (mn)th bit. If bit (mn-1) is 1, and bits from the most significant bit to the (mn)th bit are not all 1, then the entire data from the most significant bit to the (mn)th bit is incremented by 1 to achieve "rounding"; otherwise, the data remains unchanged. After rounding, the first intermediate data x2 and the second intermediate data y2 are obtained. The hardware truncation unit, connected to the first hardware rounding unit, is used to truncate the data from (mn) to m bits and output the truncated data x5 and y5. After passing through the data gating unit, the final output is the first Qn format fixed-point number xout and the second Qn format fixed-point number yout.

[0027] The second conversion link is applicable when m>n and the subsequent operations involving the converted Qn format data have zero homogeneity, including: The left shift width determination unit, connected to the left shift unit, is used to receive the first normalized data x1 and the second normalized data y1 cached by the preprocessing module, and determine the uniform left shift width q according to the effective bit distribution of the first normalized data and the second normalized data. The left shift unit, connected to the left shift width determination unit, is used to perform left shift q times on the first normalized data x1 and the second normalized data y1 (discarding the high q bits and adding q zeros to the low bits), and output the first left shift data x3 and the second left shift data y3. Preferably, the left shift width determination unit includes a bitwise OR operation module and a determination module. The bitwise OR operation module is used to perform a bitwise OR logical operation on the first and second standardized data. The bitwise OR range for signed numbers is the second highest (mn) bits excluding the highest sign bit, and the bitwise OR range for unsigned numbers is the highest (mn) bits. The determination module is connected to the bitwise OR operation module and is used to determine the left shift width. The bitwise OR operation is performed bit by bit from the highest bit to the lowest bit. If all bitwise OR results are 0, then the left shift width q = (mn). If the bitwise OR operation result from the highest bit to the lowest bit is 1, then the bitwise OR operation stops, and the left shift width q is the number of bitwise OR results that are 0.

[0028] This mode aims to shift the data to the left to the greatest extent through unified control of the left shift width, so as to raise the significant bits to the highest bit of the target format, ensure that the maximum number of significant bits can be retained during subsequent truncation, thereby retaining the precision of the original data to the maximum extent and realizing conversion with minimum precision loss. The converted data is amplified by 2^q times. In the subsequent zero-degree homogeneous operation, since the operands are synchronously amplified by the same multiple, the operation results (such as the ratio) are consistent with those before the conversion, fundamentally avoiding system errors such as division-by-zero exceptions.

[0029] a second hardware rounding unit, connected to the left shift unit, configured to perform rounding processing on the first left-shifted data and the second left-shifted data after left shifting to obtain first rounded data x4 and second rounded data y4; Preferably, the second hardware rounding unit comprises a bit detection module and an addition and overflow detection module. The bit detection module is configured to detect the (m-n-1)th bit of the input data. The addition and overflow detection module is configured to, when the (m-n-1)th bit of the input data is 1 and the high n bits of the input data, i.e., the (m-n)th to (m-1)th bits, are not all 1, add 1 to the entire (m-n)th to (m-1)th bits of the input data, so as to realize "rounding off"; otherwise, the data remains unchanged. After the rounding processing, the first rounded data x4 and the second rounded data y4 are obtained; a hardware truncation unit, connected to the second hardware rounding unit, configured to truncate the (m-n)th to m-th bits of the first rounded data x4 and the second rounded data y4, output the truncated data x5 and y5, and finally output a first Qn format fixed-point number xout and a second Qn format fixed-point number yout through a data strobe unit. a third conversion link, capable of executing a third conversion mode, which is applicable to a conversion mode where m<n, comprising: a hardware bit extension unit, configured to perform bit extension on the first Qm format fixed-point number and the second Qm format fixed-point number, output extended data x6 and y6, and finally output a first Qn format fixed-point number xout and a second Qn format fixed-point number yout through a data strobe unit.

[0030] This mode realizes lossless bit width extension, and the bit extension operation does not introduce any precision error, which is very efficient.

[0031] Furthermore, it should be understood that although the terms "first," "second," etc., may be used herein to describe different elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, without departing from the teachings of exemplary embodiments according to the present invention, the first element, component, region, layer, or portion discussed below may also be referred to as the second element, component, region, layer, or portion.

[0032] Third embodiment; This invention provides a Q-format data conversion method, which can be implemented in hardware at least through the second embodiment described above, and includes the following steps: S1: Receive a first Qm format fixed-point number x0, a second Qm format fixed-point number y0, and an operation mode input signal. The operation mode input signal is used to indicate whether the subsequent operation has a zero-order homogeneity requirement. S2: Determine the relationship between the target format bit width n and the current format bit width m, and select to perform different conversions based on the operation mode input signal.

[0033] Based on the main design concept of the third embodiment described above, the specific execution process is as follows; When m > n and subsequent operations do not require zero-order homogeneity, execute the first transformation mode, which includes the following sub-steps: S201: Perform sign determination on the first Qm format fixed-point number x0 and the second Qm format fixed-point number y0 respectively. The signed number is cached in the data cache register after the two's complement to original code conversion operation, and the unsigned number is directly cached in the data cache register to obtain the first intermediate data x1 and the second intermediate data y1. S202: Round the first intermediate data x1 and the second intermediate data y1 respectively to obtain the first intermediate data x2 and the second intermediate data y2; S203: Hardware truncation is performed on the first intermediate data x2 and the second intermediate data y2 to obtain the first intermediate data x5 and the second intermediate data y5, and the first Qn format fixed-point number xout and the second Qn format fixed-point number yout are output through the data gating unit. When m > n and subsequent operations have a zero-order homogeneity requirement, execute the second conversion mode, which includes the following sub-steps: S204: Perform sign determination on the first Qm format fixed-point number x0 and the second Qm format fixed-point number y0 respectively. The signed number is cached in the data cache register after the two's complement to original code conversion operation, and the unsigned number is directly cached in the data cache register to obtain the first intermediate data x1 and the second intermediate data y1. S205: Determine a unified left shift width q according to the distribution of significant bits of the first intermediate data x1 and the second intermediate data y1; S206: Perform left shift processing on the first intermediate data x1 and the second intermediate data y1 according to the left shift width q, to obtain first left-shifted data x3 and second left-shifted data y3; S207: Perform rounding processing on the first left-shifted data x3 and the second left-shifted data y3, to obtain first rounded data x4 and second rounded data y4; S208: Perform hardware truncation on the first rounded data x4 and the second rounded data y4, to obtain first intermediate data x5 and second intermediate data y5, and output a first Qn format fixed-point number xout and a second Qn format fixed-point number yout via a data strobe unit; When m<n, a third conversion mode is executed, which includes the following sub-steps: S209: Perform bit extension on the first Qm format fixed-point number x0 and the second Qm format fixed-point number y0, output first extended data x6 and second extended data y6, and obtain a first Qn format fixed-point number xout and a second Qn format fixed-point number yout via output through the data strobe unit.

[0034] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. It shall also be understood that terms such as those defined in commonly used dictionaries shall be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0035] The present invention is described in detail above through specific embodiments and examples, but these do not constitute a limitation to the present invention. Without departing from the principle of the present invention, those skilled in the art may make many modifications and improvements, which shall also be regarded as falling within the protection scope of the present invention.

Claims

1. A Q-format data conversion device, characterized in that, include: Preprocessing module and Q-format data conversion processing module; The preprocessing module is used to receive at least two Qm format fixed-point numbers to be converted, obtain the bit width information of the target conversion format Qn, determine the conversion scenario and output the path selection signal, and at the same time complete the two's complement to original code conversion of signed numbers as required, and output the standardized data after the original two's complement conversion and the original buffer data. The Q-format data conversion and processing module, connected to the preprocessing module, receives the path selection signal, normalized data, and raw buffered data output by the preprocessing module. Based on the path selection signal, it selects and activates either a truncated or extended bit-width hardware path. It also receives external operation mode instructions and further selects the truncated bit-width hardware path based on these instructions, enabling the selection of either a path with zero-order homogeneity or one without. The Q-format data conversion and processing module performs rounding, truncating, or extending operations on the converted number based on the selected path, ultimately outputting the converted Qn format fixed-point number.

2. The Q-format data conversion device as described in claim 1, characterized in that, The preprocessing module includes: The bit width conversion judgment unit is used to receive and buffer the output first Qm format fixed point number and second Qm format fixed point number, as well as receive and buffer the current format bit width m and target format bit width n signals, and output a path selection signal according to the relationship between m and n to indicate whether the subsequent operation selects the bit width truncation hardware path or the bit width expansion hardware path. The original two's complement conversion unit is connected to the bit width conversion judgment unit. When m is greater than n, it is used to perform two's complement to original code conversion on signed first Qm format fixed-point numbers and second Qm format fixed-point numbers. The data buffer register is connected to the bit width conversion judgment unit and the original two's complement conversion unit. When m is greater than n, it buffers the sign judgment and processing results of the first Qm format fixed-point number and the second Qm format fixed-point number, and outputs standardized data.

3. The Q-format data conversion device as described in claim 2, characterized in that, The Q format data conversion and processing module includes: The first transformation chain, applicable when m>n and subsequent operations involving the transformed output Qn format data have no zero-order homogeneity, includes: The first hardware rounding unit is used to round the output data of the data buffer register to obtain the first intermediate data and the second intermediate data. The hardware truncation unit, connected to the first hardware rounding unit, is used to truncate the data from (mn) to m bits and output the truncated first Qn format fixed-point number and second Qn format fixed-point number. The second conversion link is applicable when m>n and the subsequent operations involving the converted Qn format data have zero homogeneity, including: The left shift width determination unit, connected to the left shift unit, is used to receive the first and second normalized data cached by the preprocessing module, and determine the uniform left shift width q based on the effective bit distribution of the first and second normalized data. The left shift unit, connected to the left shift width determination unit, is used to perform left shift q times on the first normalized data and the second normalized data (discarding the high q bits and adding q zeros to the low bits), and output the first left shift data and the second left shift data. a second hardware rounding unit, connected to the left shift unit, configured to perform rounding processing on the first left-shifted data and the second left-shifted data after left shifting, to obtain first rounded data and second rounded data; a hardware truncation unit, connected to the second hardware rounding unit, configured to truncate bits (m-n) to m of the first rounded data and the second rounded data, and output the truncated first Qn format fixed-point number and second Qn format fixed-point number; a third conversion link, adapted to a conversion mode where m<n, comprising: a hardware bit expansion unit, configured to perform bit expansion on the first Qm format fixed-point number and the second Qm format fixed-point number, and output a first Qn format fixed-point number and a second Qn format fixed-point number; a data gating unit, connected to the hardware truncation units of the first and second conversion links and the hardware bit expansion unit of the third conversion link, configured to gate the first Qn format fixed-point number and the second Qn format fixed-point number from the first and second conversion links and the third conversion link.

4. The Q-format data conversion device according to claim 3, characterized in that, The left shift width judgment unit comprises: a bitwise OR operation module, configured to perform a bitwise OR logic operation on the first normalized data and the second normalized data, wherein the bitwise OR range for signed numbers is the next highest (m-n) bits excluding the highest sign bit, and the bitwise OR range for unsigned numbers is the high (m-n) bits; a judgment module, connected to the bitwise OR operation module, configured to judge the left shift width, wherein the judgment of the bitwise OR operation is performed bit by bit from the high bit to the low bit; if all bitwise OR results are 0, the left shift width q=(m-n); if a 1 appears in the bitwise OR operation result from the high bit to the low bit, the bitwise OR judgment stops, and the left shift width q is the number of bits whose bitwise OR result is 0.

5. The Q-format data conversion device according to claim 3, characterized in that, The first hardware rounding unit comprises: a bit detection module, configured to detect the (m-n-1)th bit of input data; an addition and overflow detection module, connected to the bit detection module, configured to, when the (m-n-1)th bit of the input data is 1 and the high n bits of the input data, i.e., the (m-n)th to (m-1)th bits, are not all 1, add 1 to the (m-n)th to (m-1)th bits of the input data as a whole.

6. The Q-format data conversion device according to claim 3, characterized in that, The second hardware rounding unit comprises: a bit detection module, configured to detect the (m-n-1)th bit of input data; an addition and overflow detection module, connected to the bit detection module, configured to, when the (m-n-1)th bit of the input data is 1 and the high n bits of the input data, i.e., the (m-n)th to (m-1)th bits, are not all 1, add 1 to the (m-n)th to (m-1)th bits of the input data as a whole.

7. The Q-format data conversion device according to claim 3, characterized in that, The sign processing module comprises: a sign judgment unit, configured to detect the sign bit of input data; a one's complement and original code conversion unit, connected to the sign judgment unit, configured to perform two's complement to original code conversion on signed numbers; a data cache register, connected to the sign judgment unit and the one's complement and original code conversion unit, configured to receive output data from the one's complement and original code conversion unit when the input data is a signed number, and keep the received data unchanged when the input data is an unsigned number.

8. A method for converting Q-format data, characterized in that, comprising the following steps: S1: Receive a first Qm format fixed-point number, a second Qm format fixed-point number, bit width information of m and n, and an external operation mode instruction, where the external operation mode instruction is used to indicate whether subsequent operations have a zero-degree homogeneity requirement; S2: Determine the relationship between the target format bit width n and the current format bit width m, and select to execute different conversion paths in combination with the external operation mode instruction.

9. The Q-format data conversion method according to claim 8, characterized in that: When m>n and the subsequent operations have no zero-degree homogeneity requirement, a first conversion mode is executed, which includes the following sub-steps: S201: Perform sign judgment on the first Qm format fixed-point number and the second Qm format fixed-point number, perform original-complement code conversion when the data is a signed number and store the result in the data cache register, keep the data unchanged and store it in the data cache register when the input data is an unsigned number, so as to obtain first cached data and second cached data; S202: Output the first cached data and the second cached data to a first hardware rounding unit after operation mode judgment, and perform rounding processing respectively to obtain first intermediate data and second intermediate data; S203: Truncate and discard the low (m-n) bits of the first intermediate data and the second intermediate data, retain the remaining high bits, and output a first Qn format fixed-point number and a second Qn format fixed-point number through the data gating unit; When m>n and the subsequent operations have a zero-degree homogeneity requirement, a second conversion mode is executed, which includes the following sub-steps: S204: Perform sign judgment on the first Qm format fixed-point number and the second Qm format fixed-point number, perform original-complement code conversion when the data is a signed number and store the result in the data cache register, keep the data unchanged and store it in the data cache register when the input data is an unsigned number, so as to obtain first cached data and second cached data; S205: Output the first cached data and the second cached data to a left shift unit after operation mode judgment, determine a left shift width q according to a left shift width judgment unit, complete the left shift operation on the input data, and obtain first left-shifted data and second left-shifted data; S206: Input the first left-shifted data and the second left-shifted data into a second hardware rounding unit, and perform rounding processing respectively to obtain first rounded data and second rounded data; S207: Truncate and discard the low (m-n) bits of the first rounded data and the second rounded data, retain the remaining high bits, and output a first Qn format fixed-point number and a second Qn format fixed-point number through the data gating unit; When m<n, a third conversion mode is executed, which includes the following sub-steps: S208: Expand the low bits of the first Qm format fixed-point number and the second Qm format fixed-point number, shift left by (n-m) bits and fill zeros in the low bits, so as to output a first Qn format fixed-point number and a second Qn format fixed-point number.

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