Bit-level dissipative chaos-based state generation method

Abstract

The application relates to the technical field of electric digital data processing, and discloses a state generation method based on bit-level dissipative chaos, which comprises the following steps: acquiring branch signals by a data bus and inputting the branch signals into an exclusive or reduction tree to extract characteristic marks; injecting a compensation mask into coincident components according to the characteristic marks to output modulation components; modulating the bit stream state of the modulation components by adjusting the shift step of the current stage according to the intermediate state data of the previous stage to output secondary modulation components; outputting shift features by left shifting the non-identical differential features by using a hardwired structure; coupling the shift features with the secondary modulation components by bit level by using a single-layer exclusive or gate array; outputting intermediate state data and constructing a three-value logic state matrix, the application adjusts the data bit stream topology, eliminates the convergence collapse of the state, and long-term maintains the random discrete distribution of the output sequence.

Description

Technical Field

[0001] This invention belongs to the field of electrical digital data processing technology, and particularly relates to a state generation method based on bit-level dissipative chaos. Background Technology

[0002] Currently, in data processing architectures, general-purpose chips commonly employ instruction-driven multiply-accumulate topologies. These chips carry out matrix transformations of discrete signals through deterministic register state configurations and fixed logic gate timing relationships. While maintaining deterministic pipeline flow, these chips exhibit stable clock efficiency and meet the high predictability requirements of conventional computing. However, when digital circuits perform state derivation tasks under finite bit width constraints, bit-level nonlinear operations contain irreversible information dissipation properties. When branch state signals are sent to the bus and overlapped components are extracted through a bitwise AND gate array, inconsistent bit information is lost, causing a monotonous contraction of the migration trajectory within the information space. As the cascaded series progresses, this cumulative dissipation effect causes the evolution trajectory to collapse rapidly, resulting in the output sequence being fixed within all-zero, all-one, or short-period cyclic attractors, making it impossible to maintain the random discrete distribution characteristics of the output sequence.

[0003] In low-power edge scenarios, conventional solutions typically employ periodic external seed injection or expand the physical bit width of registers. However, frequent seed injection requires high-frequency intervention from external control flow, increasing bus communication frequency and memory access power consumption. Expanding the physical bit width leads to an increase in logic gate size, increasing chip area and leakage current overhead. These linear stacking methods at the hardware or control level not only fail to escape the constraints of fixed circuit mechanisms, but also have shortcomings in existing internal control methods and generation logic. For example, Chinese invention patent CN110795064B discloses a high-speed real-time physical random number generation method and apparatus at the Gbps level, utilizing… The fixed-cascade autonomous Boolean network generates chaotic signals. The control method is entirely based on preset static hardware interconnection and fixed device delay. Under non-ideal operating conditions such as temperature drift or voltage fluctuation in edge computing units, it lacks real-time feature perception and in-situ balancing mechanism for bit-level information dissipation. The fixed Boolean transformation logic is prone to monotonically shrinking evolution trajectory and sliding into deadlock state. The solution relies heavily on peripheral parallel multi-channel post-processing circuits to implement debiasing and decorrelation, resulting in an expansion of gate circuit size. It cannot meet the original requirements of edge deployment for low power consumption and long-period divergent state matrix construction. The stacking and mismatch methods at the hardware or control level cannot get rid of the fixed track constraint in the circuit mechanism, and it also creates technical conflicts with the strict energy efficiency boundary of edge computing units.

[0004] Therefore, the technical problem to be solved by this invention is how to establish a state matrix generation method that takes into account both low logic gate overhead and long-period evolution characteristics, and eliminate state deadlock collapse caused by bit-level dissipation. Summary of the Invention

[0005] The present invention aims to solve the problems of state space degradation and collapse caused by irreversible information dissipation due to bit-level operations in pure digital circuits under limited bit width constraints, as well as the heavy external control overhead.

[0006] In this technical solution, a state generation method based on bit-level dissipative chaos includes the following steps: Step S101, obtain data from the data bus with... A single-path branch signal with a fixed bit width is input into an XOR-reduced tree, and state feature flags characterizing the bit-level distribution density of the single-path branch signal are extracted in parallel. Step S102: Dynamically change the data bit stream topology of the hardware bus according to the state feature flag, so as to construct and inject the interleaved state compensation mask into the overlapping component generated by the bitwise AND logic operation on the single branch signal, and output the modulated overlapping component. Step S103: Dynamically modulate the current stage's cyclic shift step size based on the intermediate state data generated by the previous stage operation to introduce nonlinear modulation parameters, and use the nonlinear modulation parameters as a feedback loop constraint to adjust the bit stream state of the modulated overlapping components, output the overlapping components after secondary modulation, and form a double nonlinear constraint with the interleaved state compensation mask injection to jointly maintain the steady-state balance of bit stream evolution. Step S104: Perform a bitwise XOR operation between the single branch signal and its own cyclically shifted signal to extract the non-common differential feature that represents the nonlinear difference. Use a preset hard-wired logic structure to cyclically shift the non-common differential feature 1 bit to the left within the current bit width to output the shifted differential feature. Step S105: Using a single-layer XOR gate array, the shifted differential features and the double-modulated overlapping components are coupled at the final bit level, resulting in the final output of the current-level operation unit in the cascaded sequence. The intermediate state data is used to construct a three-valued logic state matrix by combining the intermediate state data of each level in parallel.

[0007] Preferably, in step S101, the single-branch signal is directly transmitted to the XOR reduction tree via a hardwired connection; the XOR reduction tree calculates in parallel the number of low-level distributions and the number of high-level distributions of the single-branch signal in the current clock cycle based on the transient level transitions of the single-branch signal on the time axis, and determines the state feature flag based on the ratio of the number of low-level distributions to the number of high-level distributions.

[0008] Preferably, in step S102, when the state feature flag presents a consecutive preset number of the same logic level, the interleaved state compensation mask is injected in place into the overlapping component to stabilize the output of the modulated overlapping component.

[0009] Preferably, step S102 is explicitly decomposed, which includes the following sub-steps: step S1021, applying bitwise AND logic to the single-branch signal to output the overlapping component; step S1022, performing a bitwise XOR operation between the interleaving state compensation mask and the overlapping component to output the modulated overlapping component; step S1023, dynamically adjusting the injection ratio of the interleaving state compensation mask when the low-level distribution ratio of the modulated overlapping component deviates from a set threshold.

[0010] Preferably, in step S103, the bidirectional interlocking data dependency relationship is established through the following path: the step size control signal output by the intermediate state data generated by the previous stage operation directly controls the enable state of the feedback state parameter, while the feedback state parameter is used to constrain the fluctuation range of the cyclic shift step size in real time, and the nonlinear adjustment state of the operation logic is maintained by the bidirectional feedback interaction between the two.

[0011] Preferably, the bit-level transformation of each level in the cascaded architecture is composed of a combination of bitwise AND logic, XOR logic and data shifting network, and the output data stream of each level is directly transmitted unidirectionally between adjacent levels.

[0012] Preferably, the method further includes the following steps: Step S106, continuously recording the state feature sequence data of the ternary logic state matrix as it evolves with the recursive clock cycle; Step S107, calculating the bit imbalance rate flag representing the high-low level ratio offset rate of the ternary logic state matrix from the state feature sequence data; Step S108, when the bit imbalance rate flag reaches a preset threshold, outputting a state reset command to the data bus to reset the multi-level cascaded accumulation network to its initial configuration state.

[0013] Preferably, in step S104, the non-common differential features are directly cyclically shifted left by 1 bit through a hard-wired network; the size of the single-layer XOR gate array is limited to 200,000 logic gates, and the dynamic power consumption of the operation circuit under 28nm semiconductor process is constrained to within 100mW.

[0014] Preferably, the generated ternary logic state matrix is ​​directly used as the parallel control mask output of the digital logic circuit, and is used to provide a state data source for encryption, data pseudo-randomization processing, or artificial intelligence inference sampling and agent decision search.

[0015] Preferably, a state generation circuit based on bit-level dissipative chaos includes: The feature extraction module is used to acquire N-bit fixed-width single-path branch signals and extract state feature flags that characterize the bit-level distribution density of the signal in parallel. The mask modulation module is used to construct and inject the interleaved state compensation mask into the coincident component based on the state feature flag, and output the modulated coincident component. The dynamic shift module is used to dynamically modulate the current stage cyclic shift step size according to the intermediate state data of the previous stage, introduce nonlinear modulation parameter constraints to adjust the bit stream state of the overlapping components, and output the overlapping components after secondary modulation. Together with the interleaved state compensation mask injection, it forms a double nonlinear constraint to maintain the steady-state balance of bit stream evolution. The differential extraction module is used to perform a bitwise XOR operation between the single-branch signal and its own cyclically shifted signal to extract the non-common differential features and complete the shift output. The bit-level coupling module is used to couple the shifted differential features with the second-modulated component bit levels, output the current stage intermediate state data, and combine the outputs of each stage to construct a ternary logic state matrix. Compared with existing technologies, the state generation method based on bit-level dissipative chaos in this invention has the following advantages: 1. In the state generation of bit-level dissipative chaos, the multi-bit state signals of the preceding stage directly control the shift step size of the subsequent stage data, so that the bit-level perturbation network between cascaded stages is dynamically reconstructed as the data flow changes. This bidirectional dependency mechanism between topological state and data characteristics can eliminate the monotonic evolution path of fixed mapping functions in digital circuits. Within the finite register bit width space, the dynamic state transition relationship is used to spontaneously guide the data flow to deviate from the deterministic isolated trajectory. Through the nonlinear synergistic effect between cascades, the state transition process has a highly divergent spatial distribution characteristic, thereby avoiding the system from spontaneously falling into a fixed cycle or a low-entropy quiescent state in multiple rounds of recursive evolution, and maintaining the random discrete distribution characteristics of the output sequence for a long time.

[0016] 2. The single-branch signal output from the split operation is directly fed into the XOR reduction tree via the data bus. The level flag representing the local geometric sparsity of the current data space is extracted in parallel, and the interleaved state compensation mask is triggered in real time. In conjunction with the XOR logic gate array, the mask is injected in place into the overlapping components generated by the bitwise AND logic. The constructed heterogeneous perturbation balances the inherent information dissipation loss of the digital circuit. This dynamic feedback closed loop of state recognition and in-place balancing can cut off the path of data to spontaneous degradation to the all-zero or all-one deadlock state from the hardware structure, solve the technical problem that pure digital dissipative systems are prone to convergence to trivial attractors, and keep the Shannon entropy value of the long-term recursive state matrix stable.

[0017] 3. The dynamic step size mapping unit and the bit density offset feedback unit establish a bidirectional interlocked data dependency at the bus level. Removing the dynamic step size controller will cause the subsequent topology to degenerate into deterministic linear logic, causing the data density feedback unit to fail due to the lack of nonlinear sources. Removing the mask offset loop will cause the system to fall into the all-zero dead zone after several rounds of recursion due to the accumulation of dissipation, resulting in logic collapse. Therefore, this deep interlocking topology of the hardware circuit can provide a high-density logic coupling boundary, blocking the path of reverse deduction through single module disassembly or linear sensitivity analysis. While ensuring the normal operation of the circuit, it spontaneously enhances the system's protection performance against probe physical tampering.

[0018] 4. This solution can be adapted to emerging scenarios such as generative artificial intelligence inference sampling control, agent multi-path decision search, and evolutionary computing acceleration, providing them with low power consumption, long cycle, and high stability state sequence support. It is compatible with various deployment environments at the edge and in data centers, expanding the application boundaries of bit-level chaotic state generation. Attached Figure Description

[0019] Figure 1 This is a flowchart illustrating the steps of extracting state feature flags and constructing a ternary logic state matrix in this invention. Figure 2 This is a diagram showing the generation result of extracting the feature markers of the present invention to the state reset control. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0021] A state generation method based on bit-level dissipative chaos includes the following steps: Step S101, obtain data from the data bus with... A single-path branch signal with a fixed bit width is input into an XOR-reduced tree, and state feature flags characterizing the bit-level distribution density of the single-path branch signal are extracted in parallel. Step S102: Dynamically change the data bit stream topology of the hardware bus according to the state feature flag, so as to construct and inject the interleaved state compensation mask into the overlapping component generated by the bitwise AND logic operation on the single branch signal, and output the modulated overlapping component. Step S103: Dynamically modulate the current stage's cyclic shift step size based on the intermediate state data generated by the previous stage operation to introduce nonlinear modulation parameters, and use the nonlinear modulation parameters as a feedback loop constraint to adjust the bit stream state of the modulated overlapping components, output the overlapping components after secondary modulation, and form a double nonlinear constraint with the interleaved state compensation mask injection to jointly maintain the steady-state balance of bit stream evolution. Step S104: Perform a bitwise XOR operation between the single branch signal and its own cyclically shifted signal to extract the non-common differential feature that represents the nonlinear difference. Use a preset hard-wired logic structure to cyclically shift the non-common differential feature 1 bit to the left within the current bit width to output the shifted differential feature. Step S105: Using a single-layer XOR gate array, the shifted differential features and the double-modulated overlapping components are coupled at the final bit level, resulting in the final output of the current-level operation unit in the cascaded sequence. The intermediate state data is used to construct a three-valued logic state matrix by combining the intermediate state data of each level in parallel.

[0022] Preferably, in step S101, the single-branch signal is directly transmitted to the XOR reduction tree via a hardwired connection; the XOR reduction tree calculates in parallel the number of low-level distributions and the number of high-level distributions of the single-branch signal in the current clock cycle based on the transient level transitions of the single-branch signal on the time axis, and determines the state feature flag based on the ratio of the number of low-level distributions to the number of high-level distributions.

[0023] Preferably, in step S102, when the state feature flag presents a consecutive preset number of the same logic level, the interleaved state compensation mask is injected in place into the overlapping component to stabilize the output of the modulated overlapping component.

[0024] Preferably, step S102 is explicitly decomposed, which includes the following sub-steps: step S1021, applying bitwise AND logic to the single-branch signal to output the overlapping component; step S1022, performing a bitwise XOR operation between the interleaving state compensation mask and the overlapping component to output the modulated overlapping component; step S1023, dynamically adjusting the injection ratio of the interleaving state compensation mask when the low-level distribution ratio of the modulated overlapping component deviates from a set threshold.

[0025] Preferably, in step S103, the bidirectional interlocking data dependency relationship is established through the following path: the step size control signal output by the intermediate state data generated by the previous stage operation directly controls the enable state of the feedback state parameter, while the feedback state parameter is used to constrain the fluctuation range of the cyclic shift step size in real time, and the nonlinear adjustment state of the operation logic is maintained by the bidirectional feedback interaction between the two.

[0026] Preferably, the bit-level transformation of each level in the cascaded architecture is composed of a combination of bitwise AND logic, XOR logic and data shifting network, and the output data stream of each level is directly transmitted unidirectionally between adjacent levels.

[0027] Preferably, the method further includes the following steps: Step S106, continuously recording the state feature sequence data of the ternary logic state matrix as it evolves with the recursive clock cycle; Step S107, calculating the bit imbalance rate flag representing the high-low level ratio offset rate of the ternary logic state matrix from the state feature sequence data; Step S108, when the bit imbalance rate flag reaches a preset threshold, outputting a state reset command to the data bus to reset the multi-level cascaded accumulation network to its initial configuration state.

[0028] Preferably, in step S104, the non-common differential features are directly cyclically shifted left by 1 bit through a hard-wired network; the size of the single-layer XOR gate array is limited to 200,000 logic gates, and the dynamic power consumption of the operation circuit under 28nm semiconductor process is constrained to within 100mW.

[0029] Preferably, the generated ternary logic state matrix is ​​directly used as the parallel control mask output of the digital logic circuit, and is used to provide a state data source for encryption, data pseudo-randomization processing, or artificial intelligence inference sampling and agent decision search.

[0030] Preferably, a state generation circuit based on bit-level dissipative chaos includes: The feature extraction module is used to acquire N-bit fixed-width single-path branch signals and extract state feature flags that characterize the bit-level distribution density of the signal in parallel. The mask modulation module is used to construct and inject the interleaved state compensation mask into the coincident component based on the state feature flag, and output the modulated coincident component. The dynamic shift module is used to dynamically modulate the current stage cyclic shift step size according to the intermediate state data of the previous stage, introduce nonlinear modulation parameter constraints to adjust the bit stream state of the overlapping components, and output the overlapping components after secondary modulation. Together with the interleaved state compensation mask injection, it forms a double nonlinear constraint to maintain the steady-state balance of bit stream evolution. The differential extraction module is used to perform a bitwise XOR operation between the single-branch signal and its own cyclically shifted signal to extract the non-common differential features and complete the shift output. The bit-level coupling module is used to couple the shifted differential features with the second-modulated component bit level, output the current level intermediate state data, and combine the outputs of each level to construct a three-valued logic state matrix.

[0031] Example 1: The data processing terminal operates under the condition of withstanding physical tampering of the bus level and maintaining the stability of the Shannon entropy value of the long-term recursive state matrix. The internal hardware consists of shift registers and logic gate arrays. When the data stream undergoes continuous recursive iteration between each evolution level and the transformation logic remains constant, the dissipation of bit-level information causes the migration trajectory to contract monotonically, resulting in the solidification of data output and the loss of discrete random characteristics.

[0032] The data bus acquires a single-branch signal with a fixed 64-bit width and transmits it directly to the XOR reduction tree. The XOR reduction tree extracts state feature flags in parallel, representing the bit-level distribution density of the single-branch signal. Specifically, it calculates the number of low-level and high-level distributions of the single-branch signal in parallel during the current clock cycle and determines the state feature flag based on the ratio of low-level to high-level distributions. To convert the calculated ratio into binary logic levels usable for logical judgment, this invention establishes a clear threshold reduction rule. A numerical comparator is placed after the output of the XOR reduction tree, internally containing a balance threshold range. When the ratio of low-level to high-level distributions calculated within a single clock cycle falls within a preset range of 0.85 to 1.15, it indicates that the data stream distribution is in a highly uniform, low-dissipation state, and the numerical comparator outputs a low level to the state feature flag. However, if this ratio exceeds the above range, whether it's a significant excess of low levels or high levels, it indicates... The signal space faces the risk of collapse, and the numerical comparator will immediately switch to outputting a high level. Through this mapping of multidimensional proportional features to scalar level states, the state feature flag is based on a definite binary attribute, thus enabling it to directly participate in the counting flow of the subsequent four consecutive clock cycles of high-level judgment logic. When the state feature flag presents a logic state of outputting a high level for four consecutive clock cycles, the data bit stream topology of the hardware bus changes. A 64-bit interleaved state compensation mask is constructed in place on the hardware bus, with odd-numbered bits set to high level and even-numbered bits set to low level. A bitwise AND gate array operates on the single-branch signal to output a coincident component. An XOR gate array performs a bitwise XOR operation on the interleaved state compensation mask and the coincident component, injects the interleaved state compensation mask in place into the coincident component, and outputs the modulated coincident component. When the low-level distribution ratio of the modulated coincident component deviates from the 50% threshold, the injection ratio of the interleaved state compensation mask dynamically increases or decreases to complete the adaptive balancing of information dissipation.

[0033] The intermediate state data generated by the previous stage operation is used to modulate the cyclic shift step size of the current stage. Specifically, the lowest 6 bits of the low-order bitstream of the 64-bit intermediate state data from the previous stage are extracted as the dynamic shift control factor. The real-time value of the dynamic shift control factor is directly used as the cyclic shift step size of the current stage split operation, thereby controlling the enable state of the feedback state parameter. The fluctuation range of the cyclic shift step size is constrained by the feedback state parameter, and the bitstream state of the modulated coincident component is adjusted to output the coincident component after secondary modulation. The single-branch signal outputs a non-common differential feature representing nonlinear differences through its own bitwise XOR operation. The preset hard-wired logic structure with a fixed shift path cyclically shifts the non-common differential feature one bit to the left within the 64-bit width to output the shifted differential feature. The aforementioned 200000 The upper limit of the number of logic gates and the dynamic power consumption constraint of 100 milliwatts were determined based on the standard delay and power consumption model of the standard component library at the 28-nanometer process node. Since the present invention abandons the high-power multiply-accumulator array throughout the entire path and only uses basic bitwise AND gates, XOR gates and hard-wired shift networks, the number of logic gates required for a single 64-bit operation level is only 1250 according to engineering calculations. The total scale of multi-level cascading is far lower than the chip area limit of 200,000 logic gates. At a working frequency of 100 MHz and a standard core voltage of 0.9 volts, the gate-level netlist was simulated for extreme flip-flop rate using a full dynamic power consumption simulation tool. The maximum dynamic current was measured to be 98 mA, and the corresponding dynamic power consumption was stabilized at 88.2 milliwatts, successfully closing within the 100 milliwatt power consumption boundary.

[0034] If the gate size exceeds 200,000, it will lead to excessive parasitic capacitance overhead and increased leakage current, breaking the energy efficiency boundary of edge computing power. If the dynamic power consumption exceeds 100 milliwatts, it cannot remain constantly on in maintenance-free battery-powered edge conditions. A single-layer XOR gate array with a size limited to 200,000 logic gates completes bit-level coupling between the shifted differential features and the overlapping components after secondary modulation, outputting the final 64-bit intermediate state data of the current level operation unit in the cascaded sequence. The intermediate state data output by each level is directly transmitted unidirectionally between adjacent levels and combined in parallel through parallel lines to construct a ternary logic state matrix containing multi-level evolution states. Specifically, the construction of the ternary logic state matrix is ​​achieved by grouping the 64-bit intermediate state data output by each level through logic mapping. In the 64-bit data stream output by each level The hard-wired logic divides the data into basic mapping units of 2 bits each, forming 32 data pairs. For each data pair, there are four possible logical combinations of the 2-bit binary code: double low level, low high level, high low level, and double high level. The physical mapping network of this invention directly maps double low level to the first state value of the state matrix, maps low high level and high low level to the second state value of the state matrix, and directly maps double high level to the third state value of the state matrix. Thus, in a pure digital circuit, the traditional binary information flow is converted into a tri-state matrix feature flow containing three independent logical states. The component vectors containing 32 tri-state elements generated by each level of the operation unit are arranged in parallel in space and finally combined into a multi-dimensional tri-valued logic state matrix to provide a mask source with high distribution complexity.

[0035] The system continuously records the state characteristic sequence data of the ternary logic state matrix as it evolves with the recursive clock cycle, and calculates the bit imbalance rate flag, which characterizes the offset rate of the high and low level ratio of the ternary logic state matrix, based on the state characteristic sequence data. When the bit imbalance rate flag reaches the 10% critical threshold, the system outputs a state reset command to the data bus, and the multi-level cascaded accumulation network and each level register are reset to the preset initial reset state, clearing the cumulative degradation caused by bit-level dissipation. The ternary logic state matrix is ​​output as a parallel control mask of the digital logic circuit to the data encryption module and the randomization processing unit. The interlocking structure of the hardware circuit blocks the reverse deduction path executed by single module disassembly or linear sensitivity analysis, and the dynamic power consumption of the arithmetic circuit under the 28nm semiconductor process is kept within 100mW. The data processing terminal maintains the random discrete distribution characteristics of the output sequence under the condition of no external control flow intervention. Although this embodiment uses the 28nm semiconductor process and 100mW dynamic power consumption constraint as an example for illustration, those skilled in the art will know that this method is also applicable to other semiconductor process technologies and power consumption levels.

[0036] Example 2: In a continuously running edge computing data security protection scenario, to verify the technical performance of the bit-level dissipative chaos-based state generation method in suppressing data space degradation and resisting interference, the experimental platform adopts a pure digital hardware simulation verification system with time performance analysis function. The system clock frequency of the simulation verification system is set to 100MHz, and the time measurement resolution is 1.0ns, which is used to capture and record the changing state of the bus signal. The input data source is the level sequence of the analog hardware bus under electromagnetic radiation interference of different intensities. The level sequence is superimposed with Gaussian white noise with a signal-to-noise ratio of 20.5dB and power frequency interference harmonics with a frequency of 50Hz. The voltage fluctuation rate of the hardware bus, as the core variable parameter characterizing the severity of the current situation, is set to three fluctuation levels with independent gradients of 5.3%, 14.8%, and 29.4%, respectively, to examine the data output characteristics of the system under different voltage fluctuation states.

[0037] In the experimental design, a preset clock cycle threshold is set for the continuous high-level output trigger condition of the state characteristic flag. This is to balance the causal relationship between the suppression speed of state space collapse and the in-situ injection frequency of the state compensation mask. If the preset clock cycle threshold is set too small, the system will frequently inject interleaved state compensation masks, causing redundant flips in the data bit stream topology of the hardware bus and increasing the flip power consumption of the shift register. If the preset clock cycle threshold is set too large, information dissipation accumulates in the shift transformation network, causing the single-branch signal to fall into the trivial cyclic attractor before the compensation mechanism is triggered, resulting in state space deadlock. According to the above correspondence, when the level offset rate characterizing the bit-level distribution density of the single-branch signal increases, in order to ensure that the data stream deviates from the monotonic evolution path in time, the preset clock cycle threshold has a deterministic tendency to approach the lower limit of its value range in the control logic. Under the current operating conditions, for the hardware bus subject to electromagnetic pulse radiation interference, the preset clock cycle threshold is selected as 4 clock cycles to balance the power consumption and dissipation offset speed.

[0038] The experiment established a multi-dimensional control system to measure the technical performance of different feature combinations. The control system included the sample group of this invention, the control group using existing technology, the first missing control group with in-situ injected features after removing the interleaved state compensation mask, and the second missing control group with a fixed cyclic shift step size. Under low gradient interference conditions with a hardware bus voltage fluctuation rate of 5.3%, the discrete features of the output data of the control group using existing technology converged after 42.3 ms of continuous operation, and the Shannon entropy value of the generated sequence decreased to 1.15. The first missing control group solidified its output state matrix to all zero levels after 125.6 ms of continuous operation. The Shannon entropy value of the second missing control group monotonically decreased from 5.84 to 2.31 within 300.0 ms of operation. In contrast, the sample group of this invention output the sequence after 1000.0 s of continuous operation under the same conditions. The Shannon entropy value remained stable at 7.92, and the spatial bit distribution exhibited uniform discrete characteristics. When the core variable parameter increased to a medium gradient interference state of 14.8%, the degradation speed of the control group using the existing technology and the first missing type control group accelerated, and the data output solidification state appeared at 12.8ms and 35.4ms respectively. The bit distribution non-uniformity of the second missing type control group increased to 42.5%. However, the sample group of this invention was triggered by the logic of outputting a high level for four consecutive clock cycles through the state feature flag, dynamically constructing an interleaved state compensation mask and injecting it in situ. The low level distribution ratio of the modulated overlapping components converged to 50.2% after fluctuation. The Shannon entropy value of the final 64-bit intermediate state data remained at 7.89, which confirmed the causal relationship between the XOR reduction tree and the adaptive topology reconstruction network in eliminating Gaussian white noise interference.

[0039] To determine the rationality of the numerical range boundary, an out-of-range control group with altered critical thresholds for the bit imbalance rate flag was introduced to examine the nonlinear effects and performance inflection points after deviating from the preset range. When the critical threshold for the bit imbalance rate flag was set to 2.1% below the lower limit, the system became overly sensitive to minute noise, causing the trigger frequency of state reset commands to surge from 1.2 times per hour under normal operating conditions to 58.4 times per second. This high-frequency reset caused frequent clearing of the accumulation network, resulting in a sharp drop in the effective throughput of the arithmetic circuit from 98.4 Mbps to 3.1 Mbps. This indicated that the system's effective processing capacity was nearing exhaustion and an overload saturation effect was occurring; further lowering the threshold would not produce a gain commensurate with the processing overhead. Conversely, when the critical threshold for the bit imbalance rate flag was set to 25.4% above the upper limit, under high-gradient interference conditions with a hardware bus voltage fluctuation rate of 29.4%, the judgment condition was too lenient. The final 64-bit intermediate state data of the arithmetic unit in the cascaded sequence slipped into a short-cycle loop after 54.2 ms due to bit-level dissipation. The bit imbalance rate flag locks up after diverging to 18.6%, preventing the system from outputting state reset instructions to guide the data stream away from the deterministic trajectory. This results in the loss of richness in the ternary logic state matrix, indicating a sharp decline in the dynamic impedance matching capability of the pure digital hardware circuit system after exceeding the upper limit. This confirms the technical basis of using the 10% critical threshold as the boundary of the optimal working window in the method of this invention. After being verified by high-gradient electromagnetic pulse radiation interference and long-term continuous cyclic iteration, the sample of this invention, through dynamic adaptive adjustment of the hardware bus data bit stream topology and nonlinear feedback control of the shift step size of the multi-level cascaded network, avoids the information dissipation and stagnation of pure digital circuits under limited bit width constraints while maintaining a low logic gate overhead architecture. The ternary logic state matrix continuously outputs a pseudo-random control mask stream with high uniformity and long period. The parallel control mask at the output end is fully aligned with the interface data format of the downstream encryption processing unit. The hardware bus does not detect state deadlock caused by level space convergence, and the overall operation circuit maintains a stable operating state with low power dissipation and chaotic operation.

[0040] Example 3: This example combines Figures 1 to 2 The method for generating states based on bit-level dissipative chaos is explained, as follows: Figure 1As shown, in step S101, a single-branch signal with a fixed width of N bits is acquired from the data bus and input into the XOR reduction tree, and the state feature flag representing the bit-level distribution density of the single-branch signal is extracted in parallel; in step S102, the data bit stream topology of the hardware bus is dynamically changed according to the state feature flag to construct and inject an interleaved state compensation mask into the coincident component generated by the bitwise AND logic operation on the single-branch signal, and the modulated coincident component is output; in step S103, the cyclic shift step size of the current stage is dynamically modulated according to the intermediate state data generated by the previous stage operation to introduce nonlinear modulation parameters, and the nonlinear modulation parameters are used as feedback loop constraints to adjust the modulation. The bitstream state of the overlapping components is then output, followed by the second-modulated overlapping components. In step S104, a bitwise XOR operation is performed between the single-path branch signal and its own cyclically shifted signal to extract the non-common differential features that characterize the nonlinear differences. The non-common differential features are then cyclically shifted left by 1 bit within the current bit width using a preset hard-wired logic structure to output the shifted differential features. In step S105, a single-layer XOR gate array is used to complete the final bit-level coupling between the shifted differential features and the second-modulated overlapping components, outputting the final N-bit intermediate state data of the current level operation unit in the cascaded sequence. The intermediate state data output from each level are then combined in parallel to construct a ternary logic state matrix.

[0041] like Figure 2 As shown, in feature extraction, the system inputs a single-path branch signal with a fixed N-bit width to an XOR reduction tree to extract state feature flags in parallel. In topology dynamic reconstruction, the system generates overlapping components through bitwise AND logic operations and injects interleaved state compensation masks into the overlapping components. In nonlinear feedback modulation, the system feeds back intermediate state data generated by the previous stage operation to dynamically modulate the cyclic shift step size of the current stage. In differential feature shift, the system extracts non-common differential features based on its own bitwise XOR operation and shifts them left within the current bit width using a hard-wired logic structure. In bit-level coupling output, the system uses a single-layer XOR gate array to complete the final bit-level coupling and constructs a state matrix through parallel combination of cascaded sequences. In state reset control, the system calculates the bit imbalance rate flag of the matrix sequence and outputs a state reset command to reset the multi-level network. The three-valued logic state matrix finally coordinates with the output state generation results to construct a three-valued logic state matrix and maintains the random discrete distribution of the output sequence for a long time.

[0042] Example 4: The data processing terminal operates in a permanent field data acquisition environment facing high-frequency thermal drift and large-scale disordered fluctuations in power supply levels. Due to temperature changes in local hardware units of the register, the signal fluctuations of the single-branch signal cause the bit imbalance rate flag to deviate from the normal distribution during the cascaded sequence transmission of the data stream, resulting in low-entropy loops in the shift register. The data bus acquires the single-branch signal with a fixed 64-bit width and transmits it directly to the XOR reduction tree. The XOR reduction tree extracts the state feature flags that characterize the bit-level distribution density of the single-branch signal in parallel. That is, it calculates the number of low-level distributions and the number of high-level distributions of the single-branch signal in parallel during the current clock cycle, and determines the state feature flags based on the ratio of the number of low-level distributions to the number of high-level distributions.

[0043] When the status flag displays a logic state where it outputs a high level for four consecutive clock cycles, the data bit stream topology of the hardware bus changes. A 64-bit interleaved state compensation mask is constructed in-situ on the hardware bus, with odd-numbered bits set to high and even-numbered bits set to low. A bitwise AND gate array operates on the single-branch signal to output the overlapping component. An XOR gate array performs a bitwise XOR operation between the interleaved state compensation mask and the overlapping component, injects the interleaved state compensation mask into the overlapping component in-situ, and outputs the modulated overlapping component. When the low level of the modulated overlapping component... When the flat distribution ratio deviates from the 50% threshold, the number of changes in the state characteristic flag is accumulated by an internal counter with a sampling frequency of 100MHz. When the accumulated value monotonically increases within 10 consecutive sampling windows, the injection ratio of the feedback adjustment interleaved state compensation mask is increased by 2% to complete the adaptive balancing of local data dissipation of the signal. According to the Boolean algebra law of large numbers and the principle of statistical stationarity of random signals, the level distribution of the pseudo-random binary data stream tends to be uniform and equal in probability under long-term operation. The signal collapse caused by local nonlinear dissipation is manifested as a deviation of the low or high level probability from the equilibrium point.

[0044] To eliminate interference from system hardware temperature drift thermal noise and power supply voltage oscillations on injection accuracy, the controller employs an initial reference calibration and sliding window low-pass filtering algorithm. During circuit startup, a constant low level is applied to the data bus input. The sampling circuit continuously acquires data for 1000 clock cycles at a 100MHz clock frequency to determine the initial residual bias of the system. During subsequent state deduction, the internal counter uses 10 clock cycles as independent sliding sampling windows, accumulating the frequency of state characteristic flag changes within the window in real time. When the low-level ratio deviates from the reference drift plus a 5% safety redundancy zone for three consecutive sliding sampling windows, the hardware bus is determined to be in a nonlinear degradation condition. The control logic corrects the timing controller output parameters, changes the duty cycle of the interleaved state compensation mask time axis enable, adjusts the original 50% initial clock cycle coverage to 52%, and increases the mask XOR injection time to eliminate local data space dissipation loss in a time-division multiplexing manner. During this process, the dynamic change of the hardware bus data bitstream topology is achieved through... The switching of the multiplexer array configured in the online network is achieved. When the trigger condition is met, the control logic sends a high-level switching signal to the selection terminal of the multiplexer array, switching the original straight-through bus route to a cross-connection route, thereby spontaneously changing the physical flow of the bit stream. The injection ratio feedback adjustment of the interleaving state compensation mask is specifically implemented by changing the enable duty cycle of the mask on the time axis. Under normal operating conditions, the interleaving state compensation mask is injected into the overlapping components with an initial clock cycle coverage of 50%. When the counter detects a deviation and triggers the instruction to increase by 2%, the internal timing control logic adjusts the output parameters of the pulse width modulator, precisely increasing the effective enable duty cycle of the interleaving state compensation mask from 50% to 52%. This means that in the subsequent 100 operation clock cycles, 52 cycles will perform mask XOR injection, and the remaining 48 cycles will maintain the original signal pass-through. Thus, the precise offsetting and balancing of local dissipation in the information space is achieved through the adjustment of the time-division multiplexing ratio.

[0045] It utilizes a cascaded architecture with bidirectional feedback between adjacent stages. The lowest 6 bits of the low-order bitstream of the 64-bit intermediate data from the previous stage drive the cyclic shift step size of the splitting operation in the current stage. The fluctuation range of the cyclic shift step size is constrained to between 2 and 8 bits through feedback state parameters, adjusting the bitstream state of the modulated overlapping components to output the double-modulated overlapping components. The feedback state parameter is essentially a hardware state register operating in the feedback loop, used to cache the feature weight scalars generated by the current level in the previous recursive cycle. Specifically, this loop includes a 6-bit wide limiting comparator and a preset sliding boundary storage unit. When the real-time value of the dynamic shift control factor changes... When a value is input, the feedback state parameter generates a dynamic upper limit and a dynamic lower limit based on the normal average value recorded in the storage unit. If the current cyclic shift step size exceeds the 2-8 bit range defined by the feedback state parameter, the limiting comparator will forcibly intercept the shift step size, locking it directly at the boundary extreme value. Simultaneously, a periodic level adjustment increment is fed back to the aforementioned dynamic shift control terminal. This bidirectional interlocked hardware negative feedback control circuit ensures that the cyclic shift step size always fluctuates within the preset nonlinear divergence range, preventing degradation of the shift transformation network due to excessively large or small step sizes. The single-branch signal is output after a bitwise XOR operation with its own cyclically shifted signal. The non-common differential feature, representing nonlinear differences, is output by a hard-wired logic structure with a fixed shift path that cyclically shifts the non-common differential feature one bit to the left within a 64-bit width. More specifically, the bitwise XOR operation here does not refer to performing a logical operation between each bit of the signal and its corresponding bit, but rather to a staggered XOR operation between different bits within a single-path branch signal. Specifically, in a 64-bit fixed-width single-path branch signal network, the network topology splits the 64-bit data into two internal parallel paths. The first path maintains the original bit order, while the second path cyclically shifts the overall bit order one bit to the right through hardware routing. A single-layer XOR gate array then performs an XOR operation between each current bit of the first path and... The second path performs a bitwise XOR operation on the misaligned data at the corresponding position. Since the data already has discrete randomness due to the preceding cascaded modulation during bus flow, this internal misaligned XOR between adjacent bits can effectively extract the level jump characteristics of adjacent spatial nodes in the signal flow. Thus, without relying on external input, it purifies and outputs non-common differential features that can characterize the nonlinear differences in the internal spatial structure of the data flow. A single-layer XOR gate array with a scale limited to 200,000 logic gates completes bit-level coupling between the shifted differential features and the overlapping components after secondary modulation, outputting the final 64-bit intermediate state data of the current level operation unit in the cascaded sequence, clearing the cumulative degradation caused by level fluctuations.Furthermore, the dynamic power consumption of the arithmetic circuit under 28nm semiconductor technology remains within 100mW, ensuring that the ternary logic state matrix maintains its random discrete distribution characteristics without relying on high-energy-consuming external control flow intervention.

[0046] Example 5: In a continuously running edge computing data security protection scenario, when the data processing terminal is deployed for the first time, transistor threshold voltage mismatch occurs due to process deviation, causing the XOR reduction tree output to have a non-zero state characteristic flag, resulting in an initial state shift of the overlapping components. The system establishes a benchmark through a pre-calibration procedure, connects the single-branch signal input terminal to a constant low level, and collects the output results of 1000 sampling cycles at a clock frequency of 100MHz to determine the residual bias. When the residual bias is greater than the 1% threshold, a static balancing code is loaded in situ on the hardware bus and injected into the output terminal to pull the initial characteristic output back to the symmetry center point, thereby ensuring that the operation circuit starts the cyclic generation of the state matrix in an environment free from residual interference.

[0047] When the data processing terminal faces transistor temperature drift interference caused by the ambient temperature rising from 25℃ to 85℃ over time, the multi-stage cascaded registers experience nonlinear drift, leading to inter-stage thermal residual error propagation in the arithmetic unit and inducing state space collapse. To suppress temperature drift interference, the system performs in-situ compensation on the cyclic shift step size through an online calibration procedure. Specifically, it uses an internal temperature sensing unit to obtain the operating temperature value and calculates the shift step size correction operator every 5℃ change in temperature. The control parameters are adjusted to reduce the clock reversal frequency to offset the conducted lead, keeping the thermal residual error within the 5% limit. This allows the arithmetic circuit to maintain the random discrete distribution characteristics of the output sequence in an outdoor environment subject to temperature disturbances.

[0048] The embodiments of this application have been described above with reference to the accompanying drawings. Unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other. This application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit of this application and the scope of protection of this invention, and all of these forms are within the protection scope of this application.

Claims

1. A state generation method based on bit-level dissipative chaos, characterized in that, Includes the following steps: Step S101, obtain data from the data bus with... A single-path branch signal with a fixed bit width is input into an XOR-reduced tree, and state feature flags characterizing the bit-level distribution density of the single-path branch signal are extracted in parallel. Step S102: Dynamically change the data bit stream topology of the hardware bus according to the state feature flag, so as to construct and inject the interleaved state compensation mask into the overlapping component generated by the bitwise AND logic operation on the single branch signal, and output the modulated overlapping component. Step S103: Dynamically modulate the current stage's cyclic shift step size based on the intermediate state data generated by the previous stage operation to introduce nonlinear modulation parameters, and use the nonlinear modulation parameters as a feedback loop constraint to adjust the bit stream state of the modulated overlapping components, output the overlapping components after secondary modulation, and form a double nonlinear constraint with the interleaved state compensation mask injection to jointly maintain the steady-state balance of bit stream evolution. Step S104: Perform a bitwise XOR operation between the single branch signal and its own cyclically shifted signal to extract the non-common differential feature that represents the nonlinear difference. Use a preset hard-wired logic structure to cyclically shift the non-common differential feature 1 bit to the left within the current bit width to output the shifted differential feature. Step S105: Using a single-layer XOR gate array, the shifted differential features and the overlapping components after secondary modulation are coupled to achieve the final bit-level coupling, outputting the final output of the current-level operation unit in the cascaded sequence. The intermediate state data is used to construct a three-valued logic state matrix by combining the intermediate state data of each level in parallel.

2. The state generation method based on bit-level dissipative chaos according to claim 1, characterized in that, In step S101, the single-branch signal is directly transmitted to the XOR reduction tree via hardwire; The XOR reduced tree calculates the number of low-level distributions and the number of high-level distributions of a single branch signal in the current clock cycle in parallel based on the transient level transitions of the single branch signal on the time axis, and determines the state feature flag based on the ratio of the number of low-level distributions to the number of high-level distributions.

3. The state generation method based on bit-level dissipative chaos according to claim 1, characterized in that, In step S102, when the state feature flag presents a consecutive preset number of the same logic level, the interleaved state compensation mask is injected in place into the overlapping component to stabilize the output of the modulated overlapping component.

4. The state generation method based on bit-level dissipative chaos according to claim 1, characterized in that, The explicit breakdown of step S102 includes the following sub-steps: Step S1021, applying bitwise AND logic to the single-branch signal to output the overlapping component; Step S1022, performing a bitwise XOR operation between the interleaving state compensation mask and the overlapping component to output the modulated overlapping component; Step S1023, dynamically adjusting the injection ratio of the interleaving state compensation mask when the low-level distribution ratio of the modulated overlapping component deviates from the set threshold.

5. The state generation method based on bit-level dissipative chaos according to claim 1, characterized in that, In step S103, the bidirectional interlocking data dependency relationship is established through the following path: the step size control signal output by the intermediate state data generated by the previous stage operation directly controls the enable state of the feedback state parameter, and at the same time, the feedback state parameter is used to constrain the fluctuation range of the cyclic shift step size in real time, and the nonlinear adjustment state of the operation logic is maintained by the bidirectional feedback interaction between the two.

6. The state generation method based on bit-level dissipative chaos according to claim 1, characterized in that, In the cascaded architecture, the bit-level transformation of each level is composed of a combination of bitwise AND logic, XOR logic and data shifting network, and the output data stream of each level is directly transmitted unidirectionally between adjacent levels.

7. The state generation method based on bit-level dissipative chaos according to claim 1, characterized in that, The method also includes the following steps: Step S106, continuously recording the state feature sequence data of the three-valued logic state matrix as it evolves with the recursive clock cycle; Step S107, calculating the bit imbalance rate flag representing the high-low level ratio offset rate of the three-valued logic state matrix from the state feature sequence data; Step S108, when the bit imbalance rate flag reaches a preset threshold, outputting a state reset command to the data bus to reset the multi-level cascaded accumulation network to its initial configuration state.

8. The state generation method based on bit-level dissipative chaos according to claim 1, characterized in that, In step S104, the non-common differential features are directly cyclically shifted left by 1 bit through a hard-wired network; the size of the single-layer XOR gate array is limited to 200,000 logic gates, and the dynamic power consumption of the operation circuit under the 28nm semiconductor process is constrained to within 100mW.

9. The state generation method based on bit-level dissipative chaos according to claim 1, characterized in that, The generated ternary logic state matrix is ​​directly used as the parallel control mask output of digital logic circuits, serving as a state data source for encryption, data pseudo-randomization processing, or artificial intelligence inference sampling and agent decision search.

10. A state generation circuit based on bit-level dissipative chaos, characterized in that, include: The feature extraction module is used to acquire N-bit fixed-width single-path branch signals and extract state feature flags that characterize the bit-level distribution density of the signal in parallel. The mask modulation module is used to construct and inject the interleaved state compensation mask into the coincident component based on the state feature flag, and output the modulated coincident component. The dynamic shift module is used to dynamically modulate the current stage cyclic shift step size according to the intermediate state data of the previous stage, introduce nonlinear modulation parameter constraints to adjust the bit stream state of the overlapping components, and output the overlapping components after secondary modulation. Together with the interleaved state compensation mask injection, it forms a double nonlinear constraint to maintain the steady-state balance of bit stream evolution. The differential extraction module is used to perform a bitwise XOR operation between the single-branch signal and its own cyclically shifted signal to extract the non-common differential features and complete the shift output. The bit-level coupling module is used to couple the shifted differential features with the second-modulated component bit level, output the current level intermediate state data, and combine the outputs of each level to construct a three-valued logic state matrix.

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