Redundancy information elimination method and device, electronic equipment, medium and program product

Abstract

Embodiments of the present disclosure disclose a redundancy information elimination method, device, electronic equipment, medium and program product. A specific implementation of the method comprises: obtaining code intermediate representation information generated by a target compiler; determining a set of hybrid base expressions in the code intermediate representation information; determining variable domain value information corresponding to each hybrid base expression in the set of hybrid base expressions to obtain a set of variable domain value information; filtering at least one hybrid base expression supporting expression redundancy elimination from the set of hybrid base expressions according to the set of variable domain value information; and performing redundancy elimination on at least one hybrid base expression in the code intermediate representation information to obtain post-elimination intermediate representation information for use by a target graphics processor. The implementation is related to AI code compilation, and through expression redundancy elimination, the number of instruction calculations can be reduced and the conflict rate of a vector register file can be reduced.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of artificial intelligence technology, and specifically to methods, apparatus, electronic devices, computer-readable media, and program products for eliminating redundant information. Background Technology

[0002] Currently, Triton is a high-performance AI compiler for GPU / DSA accelerators. When front-end frameworks such as PyTorch Inductor generate kernel code for Triton, they mechanically derive multi-dimensional coordinates from flattened linear subscripts (xindex), producing multi-level mixed-radix subscript expressions. However, multi-level mixed-radix subscript expressions may generate multiple interdependent instruction sequences, causing excessively high vector register file conflict rates and redundant instruction computations on AI accelerator hardware. Summary of the Invention

[0003] The summary portion of this disclosure is intended to provide a brief overview of the concepts, which will be described in detail in the detailed description portion. This summary portion is not intended to identify key or essential features of the claimed technical solutions, nor is it intended to limit the scope of the claimed technical solutions.

[0004] Some embodiments of this disclosure provide methods, apparatuses, electronic devices, computer-readable media, and program products for eliminating redundant information to address the technical problems mentioned in the background section above.

[0005] In a first aspect, some embodiments of this disclosure provide a method for eliminating redundant information, including: obtaining intermediate code representation information generated by a target compiler; determining a set of mixed base expressions in the intermediate code representation information; determining variable field value information corresponding to each mixed base expression in the mixed base expression set to obtain a set of variable field value information; selecting at least one mixed base expression that supports expression redundancy elimination from the mixed base expression set based on the variable field value information set; and performing redundancy elimination on at least one mixed base expression in the intermediate code representation information to obtain eliminated intermediate representation information for use by a target graphics processor.

[0006] Optionally, after determining the mixed base expression set in the intermediate code representation information, the method further includes: obtaining pre-set expression simplification rule information; and simplifying the mixed base expressions in the mixed base expression set according to each expression simplification rule in the expression simplification rule information to obtain a simplified mixed base expression set as the mixed base expression set.

[0007] Optionally, the above-mentioned determination of the variable domain value information corresponding to each mixed basis expression in the mixed basis expression set to obtain the variable domain value information set includes: in response to performing domain value analysis using the target solver, obtaining the program computation logic diagram corresponding to the above-mentioned intermediate code representation information; converting the above-mentioned program computation logic diagram into various arithmetic expressions under the above-mentioned target solver; and determining the variable domain value information corresponding to each of the above-mentioned arithmetic expressions based on the obtained variable constraint information set, as the variable domain value information set.

[0008] Optionally, determining the variable domain value information corresponding to each of the above arithmetic expressions, based on the obtained variable constraint information set, as the variable domain value information set, includes: selecting arithmetic expressions that perform modulo and integer division calculations from the above arithmetic expressions to obtain an arithmetic expression set; for the target arithmetic expression in the above arithmetic expression set, performing the following generation steps: generating a domain value query based on the variable constraint information subset corresponding to the target arithmetic expression; using the above target solver to generate the query result corresponding to the above domain value query; and generating the variable domain value information corresponding to the above target arithmetic expression based on the query result.

[0009] Optionally, after generating the variable field value information corresponding to the target arithmetic expression based on the query results, the method further includes: caching the variable field value information and the variable information corresponding to the target arithmetic expression; and the method further includes: in response to performing a field value query for the next arithmetic expression corresponding to the target arithmetic expression, determining whether the variable information corresponding to the next arithmetic expression exists in the cache; and in response to determining that it exists, determining the variable field value information corresponding to the next arithmetic expression based on the variable information corresponding to the cached variable information.

[0010] Optionally, after selecting arithmetic expressions that perform modulo and divisibility operations from the aforementioned arithmetic expressions to obtain a set of arithmetic expressions, the method further includes: removing arithmetic expressions whose modulo or divisibility operations satisfy simple logical reasoning conditions from the set of arithmetic expressions to obtain a set of arithmetic expressions after removal; and determining the set of arithmetic expressions after removal as the set of arithmetic expressions.

[0011] Optionally, the above-mentioned redundancy elimination of at least one mixed base expression in the above-mentioned intermediate code representation information to obtain the eliminated intermediate representation information includes: performing redundancy elimination on at least one mixed base expression in the above-mentioned intermediate code representation information to obtain at least one eliminated expression; simplifying the expressions in the at least one eliminated expression according to the expression simplification rules of the expression simplification rule information to obtain a set of simplified expressions; and generating the above-mentioned eliminated intermediate representation information according to the set of simplified expressions.

[0012] Secondly, some embodiments of this disclosure provide a redundancy elimination apparatus, comprising: an acquisition unit configured to acquire intermediate code representation information generated by a target compiler; a first determination unit configured to determine a set of mixed base expressions in the intermediate code representation information; a second determination unit configured to determine variable field value information corresponding to each mixed base expression in the mixed base expression set, thereby obtaining a set of variable field value information; a filtering unit configured to filter at least one mixed base expression that supports expression redundancy elimination from the mixed base expression set based on the set of variable field value information; and an elimination unit configured to perform redundancy elimination on at least one mixed base expression in the intermediate code representation information, thereby obtaining eliminated intermediate representation information for use by a target graphics processor.

[0013] Optionally, the apparatus further includes: acquiring pre-set expression simplification rule information; and simplifying the mixed base expressions in the mixed base expression set according to each expression simplification rule in the expression simplification rule information to obtain a simplified mixed base expression set, which is used as the mixed base expression set.

[0014] Optionally, the second determining unit can be configured to: in response to performing domain value analysis using the target solver, obtain the program computation logic diagram corresponding to the intermediate representation information of the code; convert the program computation logic diagram into various arithmetic expressions under the target solver; and determine the domain value information of each variable corresponding to each arithmetic expression based on the obtained variable constraint information set, as a variable domain value information set.

[0015] Optionally, the second determining unit can be configured to: select arithmetic expressions for modulo and integer division calculations from the above arithmetic expressions to obtain an arithmetic expression set; for the target arithmetic expression in the above arithmetic expression set, perform the following generation steps: generate a domain value query based on the subset of variable constraint information corresponding to the above target arithmetic expression; generate the query result corresponding to the above domain value query using the above target solver; and generate variable domain value information corresponding to the above target arithmetic expression based on the query result.

[0016] Optionally, the second determining unit can be configured to: cache the aforementioned variable field value information and the variable information corresponding to the aforementioned target arithmetic expression. The apparatus further includes: in response to performing a field value query for the next arithmetic expression corresponding to the aforementioned target arithmetic expression, determining whether the variable information corresponding to the next arithmetic expression exists in the cache; and in response to determining its existence, determining the variable field value information corresponding to the next arithmetic expression based on the aforementioned variable information correspondence information in the cache.

[0017] Optionally, the second determining unit can be configured to: remove arithmetic expressions that satisfy simple logical reasoning conditions from the above set of arithmetic expressions, thereby obtaining a set of arithmetic expressions after removal; and determine the set of arithmetic expressions after removal as the set of arithmetic expressions.

[0018] Optionally, the elimination unit can be configured to: perform redundancy elimination on at least one mixed base expression in the above-mentioned intermediate code representation information to obtain at least one eliminated expression; simplify the expressions in the at least one eliminated expression according to the expression simplification rules of the expression simplification rule information to obtain a set of simplified expressions; and generate the above-mentioned intermediate representation information after elimination according to the set of simplified expressions.

[0019] Thirdly, some embodiments of this disclosure provide an electronic device, including: one or more processors; and a storage device having one or more programs stored thereon, such that when the one or more programs are executed by the one or more processors, the one or more processors implement the method as described in any implementation of the first aspect.

[0020] Fourthly, some embodiments of this disclosure provide a computer-readable medium having a computer program stored thereon, wherein the program, when executed by a processor, implements the method as described in any implementation of the first aspect.

[0021] Fifthly, some embodiments of this disclosure provide a computer program product, including a computer program that, when executed by a processor, implements the method described in any of the implementations of the first aspect above.

[0022] The above embodiments of this disclosure have the following beneficial effects: By using the redundancy elimination method of some embodiments of this disclosure, the number of instruction calculations can be reduced and the conflict rate of the vector register file can be lowered through expression redundancy elimination. Specifically, the reason for the large number of related instruction calculations and the high conflict rate of the vector register file is that multi-level mixed-base table expressions may generate multiple interdependent instruction sequences, causing excessively high vector register file conflict rates and instruction calculation redundancy for AI accelerator hardware. Based on this, the redundancy elimination method of some embodiments of this disclosure first obtains the intermediate code representation information generated by the target compiler to eliminate redundancy in each included mixed-base expression, simplifying the intermediate code representation information and improving execution efficiency. Then, the set of mixed-base expressions in the intermediate code representation information is determined to facilitate subsequent redundancy elimination. Next, the variable field value information corresponding to each mixed-base expression in the mixed-base expression set is determined to obtain a variable field value information set, so as to determine whether to perform redundancy elimination processing on the mixed-base expression from the perspective of variable value range, thereby ensuring the accuracy of the mixed-base expression. Secondly, based on the aforementioned variable field value information set, at least one mixed-base expression supporting expression redundancy elimination can be accurately selected from the mixed-base expression set for subsequent expression simplification and redundancy elimination processing. Finally, redundancy elimination is performed on at least one mixed-base expression in the aforementioned intermediate code representation information to obtain the eliminated intermediate representation information for use by the target graphics processor. In summary, determining the mixed-base expression supporting expression redundancy elimination through variable field value information ensures the accuracy of the intermediate code representation information during redundancy elimination, avoiding logical problems in the intermediate code information caused by redundancy elimination. Furthermore, expression redundancy elimination reduces the number of instruction calculations and lowers the conflict rate of vector register files. Attached Figure Description

[0023] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and elements are not necessarily drawn to scale.

[0024] Figure 1 This is a schematic diagram of an application scenario of a redundant information elimination method according to some embodiments of the present disclosure; Figure 2 This is a flowchart of some embodiments of the redundant information elimination method according to this disclosure; Figure 3 These are flowcharts of some other embodiments of the redundant information elimination method according to this disclosure; Figure 4These are schematic diagrams illustrating the structure of some embodiments of the redundant information elimination device according to this disclosure; Figure 5 This is a schematic diagram of the structure of an electronic device suitable for implementing some embodiments of the present disclosure. Detailed Implementation

[0025] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0026] It should also be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings. Unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other.

[0027] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are used only to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or their interdependencies.

[0028] It should be noted that the terms "a" and "a plurality of" used in this disclosure are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0029] The names of messages or information exchanged between multiple devices in the embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of such messages or information.

[0030] Before performing any of the operations involving the collection, storage, or use of personal information (e.g., information represented by codes) disclosed in this disclosure, the relevant organizations or individuals shall fulfill their obligations, including conducting personal information security impact assessments, informing personal information subjects, and obtaining prior authorization and consent from personal information subjects.

[0031] This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0032] Figure 1 This is a schematic diagram illustrating an application scenario of a method for eliminating redundant information according to some embodiments of the present disclosure.

[0033] exist Figure 1In this application scenario, firstly, the electronic device 101 can acquire the intermediate code representation information 103 generated by the target compiler 102. In this application scenario, the target compiler 102 can be an AI compiler. The intermediate code representation information 103 can be "Triton MLIR IR data". Then, the electronic device 101 can determine the set of mixed base expressions 104 in the intermediate code representation information 103. Next, the electronic device 101 can determine the variable domain value information corresponding to each mixed base expression in the mixed base expression set 104, obtaining a set of variable domain value information 105. Furthermore, the electronic device 101 can filter out at least one mixed base expression 106 that supports expression redundancy elimination from the mixed base expression set 105 based on the variable domain value information set 105. Finally, the electronic device 101 can perform redundancy elimination on at least one mixed base expression 106 in the intermediate code representation information 103, obtaining the eliminated intermediate representation information 107 for use by the target graphics processor 108. In this application scenario, the eliminated intermediate representation information 107 can be "Triton MLIR IR eliminated data". The target graphics processor 108 can be graphics processor A.

[0034] It should be noted that the aforementioned electronic device 101 can be either hardware or software. When the electronic device is hardware, it can be implemented as a distributed cluster consisting of multiple servers or terminal devices, or as a single server or a single terminal device. When the electronic device is software, it can be installed in the hardware devices listed above. It can be implemented as, for example, multiple software programs or software modules used to provide distributed services, or as a single software program or software module. No specific limitations are made here.

[0035] It should be understood that Figure 1 The number of electronic devices shown is merely illustrative. Any number of electronic devices can be used depending on the implementation requirements.

[0036] Continue to refer to Figure 2 The diagram illustrates a flow 200 of some embodiments of a redundancy elimination method according to the present disclosure. The redundancy elimination method includes the following steps: Step 201: Obtain the intermediate representation information of the code generated by the target compiler.

[0037] In some embodiments, the entity executing the above-described redundant information elimination method (e.g.) Figure 1The electronic device 101 shown can acquire intermediate representation information of the code generated by the target compiler via a wired or wireless connection. The target compiler can be a compiler currently in use to simplify AI operators on high-performance GPUs (Graphics Processing Units) and DSA (Domain Specific Architecture) accelerators. The target compiler can generate corresponding hardware-optimized code (e.g., machine code that the GPU can recognize and execute) based on the front-end development code, solving the problems of low development efficiency and difficulty in cross-hardware adaptation in traditional GPU programming. The intermediate representation information can be Triton MLIR IR. Triton MLIR IR can be an internal structured code generated by the Triton compiler based on the MLIR (Multi-Level Intermediate Representation) framework when processing code. Triton MLIR IR can be the structured intermediate representation content transformed from the front-end code. Triton MLIR IR allows the target compiler to perform global analysis and layout planning at this level (e.g., deciding how data is distributed across threads). Therefore, the intermediate representation information can be the intermediate representation content of the target front-end AI code after transformation in the target compiler.

[0038] Step 202: Determine the set of mixed base expressions in the intermediate representation information of the above code.

[0039] In some embodiments, the execution entity can determine the set of mixed-radix expressions in the intermediate code representation information. In the target compiler, a mixed-radix expression can be a numerical or address calculation logic that simultaneously includes operations with multiple different "radixes" or "modulos". For example, for a multi-level mixed-radix subscript expression generated by the target compiler, the multi-level mixed-radix subscript expression can be decomposed to obtain the mixed-radix expression. For example, the multi-level mixed-radix subscript expression is "addr=x0+512*(tmp4%614400) + 1228800*((x0+512*(tmp4%2400) / / 1228800)", and the corresponding mixed-radix expression can be either "tmp4%614400" or "tmp4%2400".

[0040] As an example, the aforementioned execution entity can leverage MLIR's powerful graph traversal and pattern matching capabilities to extract specific arithmetic operations from the compiler's SSA (Static Single Assignment) graph. Specifically, in MLIR, mixed base expressions (e.g., tmp4%614400) are represented in the IR content as a series of nested arithmetic operation nodes (e.g., arith.remsi or arith.remui). An MLIR Pass can be written that uses the PatternRewriter or walk function to traverse the SSA graph and match specific operation tree structures to obtain the set of mixed base expressions.

[0041] In some optional implementations of certain embodiments, after step 201, the steps further include: The first step is to obtain pre-set expression simplification rule information. This information describes how expressions are simplified. In practice, this information includes multiple pre-set rules. Each rule describes the simplification logic for simplifying the corresponding expression. For example, a rule might simplify the expression "(x % N) / / N" to "0". This is because the result of (x % N) / / N is 0 by default. The specific mathematical basis is: x % N ∈ [0, N-1], integer division by N always equals 0, and this holds true for any integer x and positive constant N, without the need for threshold constraints. If subsequent calculations involve performing modulo operations followed by integer division, it increases the number of instructions and the conflict rate in the vector register file. Therefore, directly simplifying "(x % N) / / N" to "0" reduces instruction calculations and lowers the conflict rate in the vector register file while maintaining accuracy. For example, an expression simplification rule could reduce the expression "(a%M)+M*((a / / M)%N)" to "a%(M*N)". Specifically, this involves decomposing mixed-base identities, folding a two-level modulo / division chain into a single-level modulo operation. For instance, (xindex%512)+512*((xindex / / 512)%2400) can be simplified to "xindex%1228800". This rule handles the commutative properties of both addition and multiplication, and uses stripTypeCasts to penetrate type conversion operations such as extsi / trunci / index_cast to identify the same dividend across types.

[0042] It should be noted that the various expression simplification rules in the expression simplification rule information can be generated based on computational experience.

[0043] The second step is to simplify the mixed base expressions in the mixed base expression set according to the expression simplification rules in the above expression simplification rule information, and obtain the simplified mixed base expression set as the mixed base expression set.

[0044] Step 203: Determine the variable domain value information corresponding to each mixed base expression in the above mixed base expression set to obtain the variable domain value information set.

[0045] In some embodiments, the execution entity can determine the variable domain value information corresponding to each mixed base expression in the mixed base expression set, thereby obtaining a variable domain value information set. The variable domain value information can be the domain value range of the variables in the mixed base expression. For example, for the mixed base expression "tmp4%2400", the corresponding variable can be "tmp4", and the corresponding variable domain value information can be the domain value range of "tmp4".

[0046] As an example, for each mixed-base expression, the aforementioned execution entity can obtain the set of constraints related to the variables in the mixed-base expression. Then, based on the set of constraints, it integrates the range of values ​​corresponding to the variables in the mixed-base expression as variable domain information.

[0047] Step 204: Based on the above variable domain value information set, select at least one mixed base expression from the above mixed base expression set that supports expression redundancy elimination.

[0048] In some embodiments, the execution entity may, based on the variable field value information set, select at least one mixed base expression from the mixed base expression set that supports expression redundancy elimination. Wherein, the mixed base expression in the at least one mixed base expression is an expression whose redundancy elimination can be performed under the verification of the corresponding variable field value information.

[0049] As an example, the aforementioned execution entity can query the expression redundancy table to obtain at least one mixed base expression by performing redundancy elimination under variable domain value information. The expression redundancy table can store redundancy records indicating whether the mixed base expression is valid (i.e., whether it is redundant) across various domain value ranges.

[0050] Step 205: Redundancy elimination is performed on at least one mixed base expression in the above code intermediate representation information to obtain the eliminated intermediate representation information for use by the target graphics processor.

[0051] In some embodiments, the execution entity may perform redundancy elimination on at least one mixed base expression in the intermediate code representation information to obtain redundancy-eliminated intermediate representation information for use by the target graphics processor. Redundancy elimination of at least one mixed base expression may include... In some optional implementations of certain embodiments, the execution entity may perform redundancy elimination on at least one mixed base expression in the intermediate code representation information to obtain the eliminated intermediate representation information, including the following steps: The first step is to perform redundancy elimination on at least one mixed base expression in the intermediate representation information of the above code to obtain at least one eliminated expression.

[0052] The second step involves simplifying the expressions in at least one of the eliminated expressions according to the expression simplification rules in the expression simplification rule information, thereby obtaining a set of simplified expressions. The specific implementation details are not elaborated here.

[0053] The third step is to generate the eliminated intermediate representation information based on the simplified expression set.

[0054] In summary, after redundancy elimination, some expressions that require simplification may be revealed. Therefore, further redundancy processing of the expressions is needed by utilizing the various expression simplification rules within the expression simplification rule information.

[0055] The above embodiments of this disclosure have the following beneficial effects: By using the redundancy elimination method of some embodiments of this disclosure, the number of instruction calculations can be reduced and the conflict rate of the vector register file can be lowered through expression redundancy elimination. Specifically, the reason for the large number of related instruction calculations and the high conflict rate of the vector register file is that multi-level mixed-base table expressions may generate multiple interdependent instruction sequences, causing excessively high vector register file conflict rates and instruction calculation redundancy for AI accelerator hardware. Based on this, the redundancy elimination method of some embodiments of this disclosure first obtains the intermediate code representation information generated by the target compiler to eliminate redundancy in each included mixed-base expression, simplifying the intermediate code representation information and improving execution efficiency. Then, the set of mixed-base expressions in the intermediate code representation information is determined to facilitate subsequent redundancy elimination. Next, the variable field value information corresponding to each mixed-base expression in the mixed-base expression set is determined to obtain a variable field value information set, so as to determine whether to perform redundancy elimination processing on the mixed-base expression from the perspective of variable value range, thereby ensuring the accuracy of the mixed-base expression. Secondly, based on the aforementioned variable field value information set, at least one mixed-base expression supporting expression redundancy elimination can be accurately selected from the mixed-base expression set for subsequent expression simplification and redundancy elimination processing. Finally, redundancy elimination is performed on at least one mixed-base expression in the aforementioned intermediate code representation information to obtain the eliminated intermediate representation information for use by the target graphics processor. In summary, determining the mixed-base expression supporting expression redundancy elimination through variable field value information ensures the accuracy of the intermediate code representation information during redundancy elimination, avoiding logical problems in the intermediate code information caused by redundancy elimination. Furthermore, expression redundancy elimination reduces the number of instruction calculations and lowers the conflict rate of vector register files.

[0056] Further reference Figure 3 The diagram illustrates a flow 300 of another embodiment of the redundancy elimination method according to the present disclosure. This redundancy elimination method includes the following steps: Step 301: Obtain the intermediate representation information of the code generated by the target compiler.

[0057] Step 302: Determine the set of mixed base expressions in the intermediate representation information of the above code.

[0058] Step 303: In response to performing domain value analysis using the target solver, obtain the program computation logic diagram corresponding to the intermediate representation information of the above code.

[0059] In some embodiments, in response to performing threshold analysis using a target solver, the execution entity (e.g. Figure 1The electronic device 101 shown can acquire the program computation logic diagram corresponding to the intermediate representation information of the above code. The target solver can be a solver used for domain value analysis. In practice, the target solver can be a Z3 SMT solver. The program computation logic diagram can be a graph representing the program computation logic. In practice, the program computation logic diagram can be an MLIR SSA diagram.

[0060] Step 304: Convert the above program calculation logic diagram into various arithmetic expressions under the above target solver.

[0061] In some embodiments, the execution entity can convert the program computation logic diagram into various arithmetic expressions under the target solver. These arithmetic expressions can be Z3 integer arithmetic expressions.

[0062] Here, the Z3IndexProver module can be built to translate MLIR SSA graphs into Z3 integer arithmetic expressions.

[0063] Step 305: Based on the obtained variable constraint information set, determine the variable domain value information corresponding to each of the above arithmetic expressions, and use it as the variable domain value information set.

[0064] In some embodiments, the aforementioned execution entity can determine the variable domain value information corresponding to each of the arithmetic expressions based on the acquired variable constraint information set, as a variable domain value information set. The variable constraint information can be the constraint content of the variable at runtime. In practice, the entire MLIR module is traversed, and runtime constraints are extracted from Triton-specific operations such as `tt.make_range`, `tt.get_program_id`, `arith.cmpi slt`, `arith.remsi`, and `scf.for` to form a variable constraint information set. The arithmetic expression contains at least one corresponding variable. The variable has corresponding variable domain value information (i.e., the range of variable values).

[0065] As an example, for each variable corresponding to each arithmetic expression, firstly, determine the subset of variable constraint information corresponding to the above variables. Then, summarize the constraint content of the subset of variable constraint information (i.e., take the intersection) to generate variable domain value information, thus obtaining the variable domain value information set.

[0066] In some optional implementations of certain embodiments, the execution entity can determine the variable domain value information corresponding to each of the arithmetic expressions based on the acquired variable constraint information set, as the variable domain value information set, including the following steps: In the first step, arithmetic expressions that are remainder calculation and integer division calculation are screened out from the above respective arithmetic expressions to obtain an arithmetic expression set. The arithmetic expressions in the arithmetic expression set are remainder expressions or integer division expressions.

[0067] As an example, the arithmetic expressions that are remainder calculation and integer division calculation may be screened out from the above respective arithmetic expressions based on the arith.divsi and arith.remsi instructions to obtain the arithmetic expression set.

[0068] In the second step, the following generation step is performed for a target arithmetic expression in the above arithmetic expression set: Substep 1: generating a domain value query according to the variable constraint information subset corresponding to the above target arithmetic expression. The domain value query may be configured to query and determine whether a domain value interval corresponding to the target arithmetic expression under the constraint of the variable constraint information subset is not within a determined value interval. That is, by generating the domain value query, it is tested whether the target arithmetic expression can be simplified. For example, the domain value query may be " Is v: constraints ∧ ¬(lo ≤ v<hi) satisfiable? If UNSAT, then v∈[lo, hi) is always true, divsi is replaced with 0, and remsi is replaced with the dividend itself. Use the QF_LIA theory, set a 500ms timeout". Here, constraints may be the corresponding variable constraint information subset. v∈[lo, hi) may be the determined value interval of the variable v. Specifically, this may be explained as: when program analysis finds that a variable v always falls within a certain interval [lo, hi), tentative simplification optimization may be performed on division and remainder operations involving v.

[0069] Specifically, after it is determined that v is always in the [lo, hi) interval (that is, the above logical problem is UNSAT), the compiler may perform specific optimization on the program. Two key operations are involved here: 1. Replace divsi with 0: This usually occurs in a case where the range of the interval [lo, hi) is very small, or the divisor is a known large constant, such that the result of v divided by the number is always 0. Since the result is determined to be 0, the compiler may directly replace the entire division operation with the constant 0, eliminating the runtime calculation overhead.

[0070] 2. Replace remsi with the dividend itself: This usually occurs in a case where the divisor is greater than the maximum possible value hi of v. According to the definition of the remainder operation, if the dividend is less than the divisor, the remainder is the dividend itself. Therefore, the compiler may safely replace v % divisor (where divisor >= hi) directly with v, which also avoids runtime remainder calculation.

[0071] As an example, the aforementioned execution entity can substitute the variable-related information (e.g., variables and the determined value range) and a subset of variable constraint information corresponding to the target arithmetic expression into the domain value query template to obtain the domain value query.

[0072] Sub-step 2 involves using the aforementioned objective solver to generate the query results corresponding to the domain value query. These query results can indicate whether the assumptions made in the domain value query are true or false.

[0073] As an example, the aforementioned execution entity can substitute the aforementioned domain value query into the target solver to generate query results.

[0074] Sub-step 3: Based on the above query results, generate the variable domain value information corresponding to the above target arithmetic expression.

[0075] As an example, the aforementioned execution entity can adaptively adjust the original value range of the variable corresponding to the target arithmetic expression based on whether the query result is assumed to be successful, thereby obtaining variable domain value information.

[0076] In some optional implementations of certain embodiments, after generating the variable domain value information corresponding to the target arithmetic expression based on the query results, the method further includes: The variable field value information and the corresponding variable information of the target arithmetic expression are associated and cached. In practice, the Z3 query results can be cached using the triplet (Value pointer, lo, hi) as the key to avoid repeated calls to the solver.

[0077] Optionally, the steps also include: The first step is to perform a field value lookup for the next arithmetic expression corresponding to the target arithmetic expression to determine whether the variable information corresponding to the next arithmetic expression exists in the cache.

[0078] The second step, in response to the confirmed existence, is to determine the variable field value information corresponding to the next arithmetic expression based on the associated information of the aforementioned variables in the cache. Here, caching avoids reusing the solver multiple times, reducing resource waste.

[0079] In some optional implementations of certain embodiments, after selecting arithmetic expressions for modulo and integer division calculations from the aforementioned arithmetic expressions to obtain a set of arithmetic expressions, the method further includes: The first step is to remove arithmetic expressions from the above set of arithmetic expressions that satisfy the condition of simple logical reasoning by performing modulo or divisibility operations, resulting in a set of arithmetic expressions after the removal. The condition of simple logical reasoning can be defined by the level of difficulty of the logical reasoning corresponding to the modulo or divisibility operation. For example, a condition of simple logical reasoning can be an arithmetic expression where the modulo or divisibility operation is a single-step simple logical reasoning.

[0080] For example, if the remsi result is naturally in the range [0, N), return true directly for such a query, skipping the Z3 solver call.

[0081] The second step is to determine the set of arithmetic expressions after the removal as the set of arithmetic expressions.

[0082] Step 306: Based on the above variable domain value information set, select at least one mixed base expression from the above mixed base expression set that supports expression redundancy elimination.

[0083] Step 307: Redundancy elimination is performed on at least one mixed base expression in the above code intermediate representation information to obtain the eliminated intermediate representation information for use by the target graphics processor.

[0084] In some embodiments, the specific implementation of steps 301-302 and 306-307 and their resulting technical effects can be found in [reference needed]. Figure 2 Steps 201-202 and 204-205 in the corresponding embodiments will not be repeated here.

[0085] from Figure 3 It can be seen from this that, with Figure 2 Compared to the description of some corresponding embodiments, Figure 3 In some corresponding embodiments, the process 300 of the redundant information elimination method uses the objective solver to perform domain value analysis and, based on the corresponding variable constraint information set, can accurately and quickly determine the domain value information of the corresponding variables, so as to accurately select the mixed basis expression subsequently.

[0086] Further reference Figure 4 As an implementation of the methods shown in the above figures, this disclosure provides some embodiments of a redundant information elimination device, which are similar to... Figure 2 Corresponding to the method embodiments shown, this redundant information elimination device can be specifically applied to various electronic devices.

[0087] like Figure 4As shown, a redundancy elimination device 400 includes: an acquisition unit 401, a first determination unit 402, a second determination unit 403, a filtering unit 404, and an elimination unit 405. The acquisition unit is configured to acquire intermediate code representation information generated by a target compiler; the first determination unit 401 is configured to determine a set of mixed base expressions in the intermediate code representation information; the second determination unit 402 is configured to determine variable field value information corresponding to each mixed base expression in the mixed base expression set, thereby obtaining a variable field value information set; the filtering unit 403 is configured to filter at least one mixed base expression that supports expression redundancy elimination from the mixed base expression set based on the variable field value information set; and the elimination unit 404 is configured to perform redundancy elimination on at least one mixed base expression in the intermediate code representation information, obtaining eliminated intermediate representation information for use by a target graphics processor.

[0088] In some optional implementations of certain embodiments, the apparatus 400 further includes an information acquisition unit and a simplification unit (not shown in the figure). The information acquisition unit can be configured to acquire pre-set expression simplification rule information. The simplification unit can be configured to simplify the mixed base expressions in the mixed base expression set according to the expression simplification rules in the expression simplification rule information, obtaining a simplified mixed base expression set as the mixed base expression set.

[0089] In some optional implementations of certain embodiments, the second determining unit 402 may be further configured to: in response to performing domain value analysis using the target solver, obtain the program computation logic diagram corresponding to the intermediate code representation information; convert the program computation logic diagram into various arithmetic expressions under the target solver; and determine the domain value information of each variable corresponding to each arithmetic expression based on the obtained variable constraint information set, as a variable domain value information set.

[0090] In some optional implementations of certain embodiments, the second determining unit 402 may be further configured to: filter out arithmetic expressions for modulo and integer division calculations from the aforementioned arithmetic expressions to obtain an arithmetic expression set; for the target arithmetic expression in the aforementioned arithmetic expression set, perform the following generation steps: generate a domain value query based on the subset of variable constraint information corresponding to the aforementioned target arithmetic expression; generate the query result corresponding to the aforementioned domain value query using the aforementioned target solver; and generate variable domain value information corresponding to the aforementioned target arithmetic expression based on the aforementioned query result.

[0091] In some optional implementations of certain embodiments, the second determining unit 402 may be further configured to: perform a corresponding association cache of the aforementioned variable field value information and the variable information corresponding to the aforementioned target arithmetic expression. The apparatus 400 further includes: in response to performing a field value query for the next arithmetic expression corresponding to the aforementioned target arithmetic expression, determining whether the variable information corresponding to the next arithmetic expression exists in the cache; and in response to determining its existence, determining the variable field value information corresponding to the next arithmetic expression based on the aforementioned variable information correspondence information in the cache.

[0092] In some optional implementations of some embodiments, the second determining unit 402 may be further configured to: remove arithmetic expressions that satisfy simple logical reasoning conditions from the above set of arithmetic expressions, to obtain a set of arithmetic expressions after removal; and determine the set of arithmetic expressions after removal as the set of arithmetic expressions.

[0093] In some optional implementations of certain embodiments, the elimination unit 405 may be further configured to: perform redundancy elimination on at least one mixed base expression in the above-mentioned intermediate code representation information to obtain at least one eliminated expression; simplify the expressions in the at least one eliminated expression according to the expression simplification rules of the expression simplification rule information to obtain a set of simplified expressions; and generate the above-mentioned intermediate representation information after elimination according to the set of simplified expressions.

[0094] It is understandable that the units described in the redundant information elimination device 400 are related to the reference. Figure 2 The steps in the described method correspond to each other. Therefore, the operations, features, and beneficial effects described above for the method also apply to the redundant information elimination device 400 and the units contained therein, and will not be repeated here.

[0095] The following is for reference. Figure 5 It illustrates electronic devices suitable for implementing some embodiments of this disclosure (e.g., Figure 1 A schematic diagram of the structure of electronic device 101)500. Figure 5 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments of this disclosure.

[0096] like Figure 5As shown, the electronic device 500 may include a processing unit (e.g., a central processing unit, a graphics processing unit, etc.) 501, which can perform various appropriate actions and processes according to a program stored in a read-only memory 502 or a program loaded from a storage device 508 into a random access memory 503. The random access memory 503 also stores various programs and data required for the operation of the electronic device 500. The processing unit 501, the read-only memory 502, and the random access memory 503 are interconnected via a bus 504. An input / output interface 505 is also connected to the bus 504.

[0097] Typically, the following devices can be connected to the input / output interface 505: input devices 506 including, for example, a touchscreen, touchpad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; output devices 507 including, for example, a liquid crystal display (LCD), speaker, vibrator, etc.; storage devices 508 including, for example, magnetic tape, hard disk, etc.; and communication devices 509. Communication device 509 allows electronic device 500 to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 5 An electronic device 500 with various devices is shown; however, it should be understood that it is not required to implement or possess all of the devices shown. More or fewer devices may be implemented or possessed alternatively. Figure 5 Each box shown can represent a device or multiple devices as needed.

[0098] In particular, according to some embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, some embodiments of this disclosure include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device 509, or installed from a storage device 508, or installed from a read-only memory 502. When the computer program is executed by the processing device 501, it performs the functions defined above in the methods of some embodiments of this disclosure.

[0099] It should be noted that, in some embodiments of this disclosure, the computer-readable medium described above may be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium may be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In some embodiments of this disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In some embodiments of this disclosure, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (radio frequency), etc., or any suitable combination thereof.

[0100] In some implementations, clients and servers can communicate using any currently known or future-developed network protocol such as HTTP (Hypertext Transfer Protocol) and can interconnect with digital data communication (e.g., communication networks) of any form or medium. Examples of communication networks include local area networks (“LANs”), wide area networks (“WANs”), the Internet (e.g., the Internet of Things), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks), as well as any currently known or future-developed networks.

[0101] The aforementioned computer-readable medium may be included in the aforementioned electronic device; or it may exist independently and not assembled into the electronic device. The aforementioned computer-readable medium carries one or more programs that, when executed by the electronic device, cause the electronic device to: acquire intermediate code representation information generated by the target compiler; determine a set of mixed-base expressions in the intermediate code representation information; determine variable field value information corresponding to each mixed-base expression in the mixed-base expression set, obtaining a set of variable field value information; based on the set of variable field value information, select at least one mixed-base expression from the mixed-base expression set that supports expression redundancy elimination; and perform redundancy elimination on at least one mixed-base expression in the intermediate code representation information to obtain eliminated intermediate representation information for use by the target graphics processor.

[0102] Computer program code for performing operations of some embodiments of this disclosure can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0103] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0104] The units described in some embodiments of this disclosure can be implemented in software or hardware. The described units can also be located in a processor; for example, a processor can be described as including an acquisition unit, a first determination unit, a second determination unit, a filtering unit, and an elimination unit. The names of these units do not necessarily limit the unit itself; for example, the acquisition unit can also be described as "a unit that acquires intermediate representation information of the code generated by the target compiler."

[0105] The functions described above in this document can be performed at least in part by one or more hardware logic components. For example, exemplary types of hardware logic components that can be used, without limitation, include: field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), system-on-a-chip (SoCs), complex programmable logic devices (CPLDs), and so on.

[0106] Some embodiments of this disclosure also provide a computer program product, including a computer program that, when executed by a processor, implements any of the above-described methods for eliminating redundant information.

[0107] The above description is merely a selection of preferred embodiments of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in the embodiments of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in the embodiments of this disclosure.

Claims

1. A method for eliminating redundant information, comprising: Obtain intermediate representation information of the code generated by the target compiler; Determine the set of mixed base expressions in the intermediate representation information of the code; Determine the variable domain value information corresponding to each mixed base expression in the mixed base expression set to obtain the variable domain value information set; Based on the variable domain value information set, at least one mixed base expression that supports expression redundancy elimination is selected from the mixed base expression set; Redundancy removal is performed on at least one mixed base expression in the intermediate representation information of the code to obtain the removed intermediate representation information for use by the target graphics processor.

2. The method according to claim 1, wherein, After determining the set of mixed base expressions in the intermediate code representation information, the method further includes: Retrieve pre-defined expression simplification rule information; Based on the expression simplification rules in the expression simplification rule information, the mixed base expressions in the mixed base expression set are simplified to obtain a simplified mixed base expression set, which serves as the mixed base expression set.

3. The method according to claim 1, wherein, The step of determining the variable domain value information corresponding to each mixed base expression in the mixed base expression set, to obtain a variable domain value information set, includes: In response to performing domain value analysis using the target solver, the program computation logic diagram corresponding to the intermediate representation information of the code is obtained; The program computation logic diagram is converted into various arithmetic expressions under the target solver; Based on the acquired set of variable constraint information, the domain value information of each variable corresponding to each arithmetic expression is determined, which is then used as the set of variable domain value information.

4. The method according to claim 3, wherein, The step of determining the variable domain value information corresponding to each arithmetic expression based on the acquired variable constraint information set, as the variable domain value information set, includes: From the various arithmetic expressions, arithmetic expressions for modulo and integer division are selected to obtain a set of arithmetic expressions; For the target arithmetic expression in the set of arithmetic expressions, perform the following generation steps: Generate a domain value query based on the subset of variable constraint information corresponding to the target arithmetic expression; Using the target solver, the query results corresponding to the domain value query are generated; Based on the query results, the variable field value information corresponding to the target arithmetic expression is generated.

5. The method according to claim 4, wherein, After generating the variable domain value information corresponding to the target arithmetic expression based on the query result, the method further includes: The variable field value information and the corresponding variable information of the target arithmetic expression are associated and cached accordingly; and The method further includes: In response to performing a field value lookup of the next arithmetic expression corresponding to the target arithmetic expression, determine whether the variable information corresponding to the next arithmetic expression exists in the cache; In response to the determination of existence, the variable field value information corresponding to the next arithmetic expression is determined based on the associated information of the variable information in the cache.

6. The method according to claim 4, wherein, After selecting arithmetic expressions for modulo and divisibility calculations from the various arithmetic expressions to obtain a set of arithmetic expressions, the method further includes: Remove arithmetic expressions from the set of arithmetic expressions that satisfy simple logical reasoning conditions for modulo or integer division calculations to obtain the set of arithmetic expressions after removal; The set of arithmetic expressions after removal is determined as the set of arithmetic expressions.

7. The method according to claim 1, wherein, The process of redundancy elimination of at least one mixed base expression in the intermediate code representation information to obtain the eliminated intermediate representation information includes: Redundancy elimination is performed on at least one mixed base expression in the intermediate representation information of the code to obtain at least one eliminated expression; Based on the expression simplification rules in the expression simplification rule information, the expressions in the at least one eliminated expression are simplified to obtain a set of simplified expressions. The eliminated intermediate representation information is generated based on the simplified expression set.

8. A redundant information elimination device, comprising: The acquisition unit is configured to acquire intermediate representation information of the code generated by the target compiler. The first determining unit is configured to determine the set of mixed base expressions in the intermediate code representation information; The second determining unit is configured to determine the variable domain value information corresponding to each mixed base expression in the mixed base expression set, thereby obtaining a variable domain value information set. The filtering unit is configured to filter at least one mixed base expression that supports expression redundancy elimination from the mixed base expression set based on the variable domain value information set. The elimination unit is configured to perform redundancy elimination on at least one mixed base expression in the intermediate representation information of the code to obtain eliminated intermediate representation information for use by the target graphics processor.

9. An electronic device, comprising: One or more processors; Storage device, on which one or more programs are stored, When the one or more programs are executed by the one or more processors, the one or more processors implement the method as described in any one of claims 1-7.

10. A computer-readable medium having a computer program stored thereon, wherein, When the computer program is executed by a processor, it implements the method as described in any one of claims 1-7.

11. A computer program product comprising a computer program that, when executed by a processor, implements the method according to any one of claims 1-7.

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